VOLTAGE, SKEW, PCI-X CLOCK GENERATOR Fully integrated LVCMOS/LVTT

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VOLTAGE, SKEW, PCI-X CLOCK GENERATOR Fully integrated LVCMOS/LVTT

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ICS8761
VOLTAGE, SKEW, PCI-X CLOCK GENERATOR
Fully integrated LVCMOS/LVTTL outputs, typical output impedance Selectable crystal oscillator interface LVCMOS/LVTTL REF_CLK Maximum output frequency: 166.67MHz Maximum crystal input frequency: 38MHz Maximum REF_CLK input frequency: 83.33MHz Individual banks with selectable output dividers generating 33.333MHz, 66.66MHz, 100MHz 133.333MHz simultaneously Separate feedback control generating PCI-X frequencies from 20MHz 25MHz crystal 33.333MHz 66.666MHz reference frequency Cycle-to-cycle jitter: 70ps (maximum) Period jitter, RMS: 17ps (maximum) Output skew: 230ps (maximum) Bank skew: 40ps (maximum) Static phase offset: 150ps (maximum)
GENERAL DESCRIPTION
ICS8761 voltage, skew PCI-X Clock Generator member HiPerClockSHiPerClockSfamily High Performance Clock Solutions from ICS. ICS8761 selectable REF_CLK crystal input. REF_CLK input accepts LVCMOS LVTTL input levels. ICS8761 fully integrated along with frequency configurable clock feedback outputs multiplying regenerating clocks with "zero delay". Using 20MHz 25MHz crystal 33.333MHz 66.666MHz reference frequency, ICS8761 will generate output frequencies 33.333MHz, 66.666MHz, 100MHz 133.333MHz simultaneously.
impedance LVCMOS/LVTTL outputs ICS8761 designed drive series parallel terminated transmission lines.
BLOCK DIAGRAM
D_SELA0 D_SELA1 REF_CLK XTAL1
Full 3.3V 3.3V core, 2.5V multiple output supply modes 85°C ambient operating temperature Lead-Free package available
ASSIGNMENT
VDDOC VDDOC VDDOD VDDOD
REF_CLK
XTAL2 XTAL_SEL FB_IN PLL_SEL D_SELB1 D_SELB0
FB_OUT VDDOFB FB_IN FBDIV_SEL0 FBDIV_SEL1 D_SELD0 D_SELD1 D_SELB0 D_SELB1
XTAL1 XTAL2 XTAL_SEL PLL_SEL VDDA
ICS8761
D_SELC1 D_SELC0
D_SELC0 D_SELC1
D_SELA0 D_SELA1
VDDOA VDDOA VDDOB VDDOB
D_SELD1 D_SELD0
FB_OUT
FBDIV_SEL1 FBDIV_SEL0
8761CY
64-Lead LQFP 10mm 10mm 1.4mm package body package View
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ICS8761
VOLTAGE, SKEW, PCI-X CLOCK GENERATOR
Type Input Power Description
TABLE DESCRIPTIONS
Number Name REF_CLK XTAL1, XTAL2 XTAL_SEL PLL_SEL VDDA D_SELC0, D_SELC1 D_SELA0, D_SELA1 QA0, QA1, QA2, VDDOA QB0, QB1, QB2, VDDOB D_SELB1, D_SELB0 D_SELD1, D_SELD0
Pulldown Reference clock input. LVCMOS LVTTL interface levels. Power supply ground.
Input Power Input Input Power Input Input Input Input Output Power Output Power Input Input Input Input Pulldown Pullup Pullup Pulldown Pulldown Pullup Pullup Pulldown Pullup Pullup
Crystal oscillator interface. XTAL1 input. XTAL2 output. Core supply pins. Selects between crystal oscillator reference clock reference source. Selects XTAL inputs when HIGH. Selects REF_CLK when LOW. LVCMOS LVTTL interface levels. Selects between bypass mode. When HIGH, selects PLL. When LOW, selects reference clock. LVCMOS LVTTL interface levels. Analog supply pin. Applications Note filtering. Selects divide value Bank outputs described Table LVCMOS LVTTL interface levels. Determines state Bank outputs. When HIGH, outputs enabled. When LOW, outputs disabled. LVCMOS LVTTL interface levels. Determines state Bank outputs. When HIGH, outputs enabled. When LOW, outputs disabled. LVCMOS LVTTL interface levels. Selects divider value Bank outputs described Table LVCMOS LVTTL interface levels. Bank clock outputs. typical output impedance. LVCMOS LVTTL interface levels. Output supply pins Bank outputs. Bank clock outputs. typical output impedance. LVCMOS LVTTL interface levels. Output supply pins Bank outputs. Selects divider value Bank outputs described Table LVCMOS LVTTL interface levels. Determines state Bank outputs. When HIGH, outputs enabled. When LOW, outputs disabled. LVCMOS LVTTL interface levels. Determines state Bank outputs. When HIGH, outputs enabled. When LOW, outputs disabled. LVCMOS LVTTL interface levels. Selects divider value Bank outputs described Table LVCMOS LVTTL interface levels. Active HIGH Master reset. When logic HIGH, internal dividers reset causing outputs low. When logic LOW, internal dividers outputs enabled. LVCMOS LVTTL interface levels. Selects divider value bank feedback output described Table LVCMOS LVTTL interface levels. Selects divider value bank feedback output described Table LVCMOS LVTTL interface levels. Feedback input phase detector generating clocks with "zero delay". LVCMOS LVTTL interface levels.
Input
Pulldown
FBDIV_SEL1 FBDIV_SEL0 FB_IN
Input Input Input
Pulldown Pullup Pulldown
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ICS8761
VOLTAGE, SKEW, PCI-X CLOCK GENERATOR
Type Power Output Output Power Output Power Description Output supply FB_Out output. Feedback output. Connect FB_IN. typical output impedance. LVCMOS LVTTL interface levels. Bank clock outputs. typical output impedance. LVCMOS LVTTL interface levels. Output supply pins Bank outputs. Bank clock outputs. typical output impedance. LVCMOS LVTTL interface levels. Output supply pins Bank outputs.
Number
Name VDDOFB FB_OUT QD3, QD2, QD1, VDDOD QC3, QC2, QC1, VDDOC
NOTE: Pullup Pulldown refer internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output); NOTE Output Impedance VDD, VDDA 3.465V; VDDOx 3.465V VDD, VDDA 3.465V; VDDOx 2.625V Test Conditions Minimum Typical Maximum Units
NOTE VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOD, VDDOFB.
TABLE OUTPUT CONTROL FUNCTION TABLE
Inputs QA0:QA3 Active Active Outputs QB0:QB3 QC0:QC3 Active QD0:QD3 Active
TABLE OPERATING MODE FUNCTION TABLE
Inputs PLL_SEL Operating Mode Bypass
TABLE INPUT FUNCTION TABLE
Inputs XTAL_SEL Input REF_CLK XTAL Oscillator
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TABLE CONTROL FUNCTION TABLE
Inputs Reference Frequency Range (MHz) 41.6 83.33 20.83 41.67 15.62 31.25 12.5 41.6 83.33 20.83 41.67 15.62 31.25 12.5 41.6 83.33 20.83 41.67 15.62 31.25 12.5 41.6 83.33 20.83 41.67 15.62 31.25
ICS8761
VOLTAGE, SKEW, PCI-X CLOCK GENERATOR
Outputs PLL_SEL QX0:QX3 5.33 6.67 2.67 3.33 1.33 Frequency QX0:QX3 (MHz) 83.33 166.67 83.33 166.67 83.33 166.67 83.33 166.67 62.4 62.4 62.4 62.4 41.6 83.33 41.6 83.33 41.6 83.33 41.6 83.33 20.8 41.67 20.8 41.67 20.8 41.67 FB_OUT (MHz) 41.6 83.33 20.83 41.67 15.62 31.25 12.5 41.6 83.33 20.83 41.67 15.62 31.25 12.5 41.6 83.33 20.83 41.67 15.62 31.25 12.5 41.6 83.33 20.83 41.67 15.62 31.25
D_SELx1
D_SELx0
FBDIV_SEL1 FBDIV_SEL0
12.5 1.67 20.8 41.67 12.5 NOTE: D_SELX1 denotes D_SELA1, D_SELB1, D_SELC1, D_SELD1. D_SELX0 denotes D_SELA0, D_SELB0, D_SELC0, D_SELD0. QX0:QX3 denotes QA0:QA3, QB0:QB3, QC0:QC3, QD0:QD3.
TABLE CONTROL FUNCTION TABLE (PCI CONFIGURATION)
Inputs D_SELx1 D_SELx0 FBDIV_SEL1 FBDIV_SEL0 Reference Frequency (MHz) 66.67 33.33 66.67 33.33 66.67 33.33 66.67 33.33 Outputs PLL_SEL QX0:QX3 5.33 6.67 2.67 3.33 1.33 Frequency QX0:QX3 FB_OUT (MHz) (MHz) 66.67 66.67 66.67 66.67 66.67 33.33 33.33 33.33 33.33 66.67 33.33 66.67 33.33 66.67 33.33
1.67 33.33 NOTE: D_SELx1 denotes D_SELA1, D_SELB1, D_SELC1, D_SELD1. D_SELx0 denotes D_SELA0, D_SELB0, D_SELC0, D_SELD0. QX0:QX3 denotes QA0:QA3, QB0:QB3, QC0:QC3, QD0:QD3.
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, Package Thermal Impedance, Storage Temperature, TSTG 4.6V -0.5V -0.5V VDDOx 0.5V 41.1°C/W lfpm) -65°C 150°C
ICS8761
VOLTAGE, SKEW, PCI-X CLOCK GENERATOR
NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
TABLE POWER SUPPLY CHARACTERISTICS, VDDA VDDOX 3.3V±5%, 85°C
Symbol VDDA VDDOx IDDA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage; NOTE Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical Maximum 3.465 3.465 3.465 Units
Output Supply Current; NOTE IDDOx NOTE VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOD, VDDOFB. NOTE IDDOx denotes IDDOA, IDDOB, IDDOC, IDDOD, IDDOFB.
TABLE LVCMOS/LVTTL CHARACTERISTICS, VDDA VDDOX 3.3V±5%, 85°C
Symbol Parameter OEA:OED, XTAL_SEL, D_SELA0:D_SELD0, FB_IN, Input D_SELA1:D_SELD1, PLL_SEL, High Voltage FBDIV_SEL0, FBDIV_SEL1 REF_CLK OEA:OED, XTAL_SEL, D_SELA0:D_SELD0, FB_IN, Input Voltage D_SELA1, D_SELD1, PLL_SEL REF_CLK D_SELA0:D_SELD0, FB_IN, D_SELA1:D_SELD1, REF_CLK, Input FBDIV_SEL1 High Current XTAL_SEL, PLL_SEL, FBDIV_SEL0, OEA:OED D_SELA0:D_SELD0, FB_IN, D_SELA1:D_SELD1, REF_CLK, Input FBDIV_SEL1 Current XTAL_SEL, PLL_SEL, FBDIV_SEL0, OEA:OED Output High Voltage; NOTE Output Voltage; NOTE Output Tristate Current Test Conditions Minimum -0.3 -0.3 3.465V 3.465V 3.465V, 3.465V, -150 Typical Maximum Units
IOZL
IOZH Output Tristate Current High NOTE Outputs terminated with VDDOx/2. Parameter Measurement Information section, "3.3V Output Load Test Circuit".
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ICS8761
VOLTAGE, SKEW, PCI-X CLOCK GENERATOR
Test Conditions 50MHz Minimum -150 Typical Maximum 166.67 50MHz; NOTE 25MHz XTAL, 133.3MHz Units
TABLE CHARACTERISTICS, VDDA VDDOX 3.3V±5%, 85°C
Symbol fMAX Parameter Output Frequency Static Phase Offset; NOTE Bank Skew; NOTE Output Skew; NOTE Cycle-to-Cycle Jitter; Period Jitter, RMS; NOTE Lock Time Output Rise Time Output Fall Time
sk(b) sk(o) tjit(cc) tjit(per)
Output Duty Cycle; NOTE NOTE Defined time difference between input reference clock average feedback input signal when locked input reference frequency stable. Measured from VDD/2 input VDDOx/2 output. NOTE Defined skew within bank outputs same voltages with equal load conditions. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured VDDOx/2. NOTE Jitter performance using LVCMOS inputs. NOTE Measured using REF_CLK. XTAL input, refer Application Note. NOTE This parameter defined accordance with JEDEC Standard NOTE Tested with D_SELXX (divide FBDIV_SEL (divide NOTE This parameter defined value.
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ICS8761
VOLTAGE, SKEW, PCI-X CLOCK GENERATOR
TABLE POWER SUPPLY CHARACTERISTICS, VDDA 3.3V±5%, VDDO 2.5V±5%, 85°C
Symbol VDDA VDDOx IDDA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage; NOTE Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 2.375 Typical Maximum 3.465 3.465 2.625 Units
Output Supply Current; NOTE IDDOx NOTE VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOD, VDDOFB. NOTE IDDOx denotes IDDOA, IDDOB, IDDOC, IDDOD, IDDOFB.
TABLE LVCMOS/LVTTL CHARACTERISTICS, VDDA 3.3V±5%, VDDO 2.5V±5%, 85°C
Symbol
Parameter OEA:OED, XTAL_SEL, D_SELA0:D_SELD0, FB_IN, Input D_SELA1:D_SELD1, PLL_SEL, High Voltage FBDIV_SEL0, FBDIV_SEL1 REF_CLK OEA:OED, XTAL_SEL, D_SELA0:D_SELD0, FB_IN, Input D_SELA1:D_SELD1, PLL_SEL, Voltage FBDIV_SEL0, FBDIV_SEL1 REF_CLK D_SELA0:D_SELD0, FB_IN, D_SELA1:D_SELD1, REF_CLK, Input FBDIV_SEL1 High Current XTAL_SEL, PLL_SEL, FBDIV_SEL0, OEA:OED D_SELA0:D_SELD0, FB_IN, D_SELA1:D_SELD1, REF_CLK, Input FBDIV_SEL1 Current XTAL_SEL, PLL_SEL, FBDIV_SEL0, OEA:OED Output High Voltage; NOTE Output Voltage; NOTE Output Tristate Current
Test Conditions
Minimum -0.3 -0.3
Typical
Maximum
Units
3.465V 3.465V 3.465V, 3.465V, -150
IOZL
IOZH Output Tristate Current High NOTE Outputs terminated with VDDOx/2. Parameter Measurement Information section, "3.3V/2.5V Output Load Test Circuit".
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VOLTAGE, SKEW, PCI-X CLOCK GENERATOR
TABLE CHARACTERISTICS, VDDA 3.3V±5%, VDDO 2.5V±5%, 85°C
Symbol fMAX Parameter Output Frequency Static Phase Offset; NOTE Bank Skew; NOTE Output Skew; NOTE Cycle-to-Cycle Jitter; NOTE Period Jitter, RMS; NOTE Lock Time Output Rise Time Output Fall Time 50MHz; NOTE 25MHz XTAL, 133.3MHz 50MHz -350 Test Conditions Minimum Typical Maximum 166.67 Units
sk(b) sk(o) tjit(cc) tjit(per)
Output Duty Cycle; NOTE NOTE Defined time difference between input reference clock average feedback input signal when locked input reference frequency stable. Measured from VDD/2 input VDDOX/2 output. NOTE Defined skew within bank outputs same voltages with equal load conditions. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured VDDOx/2. NOTE Jitter performance using LVCMOS inputs. NOTE Measured using REF_CLK. XTAL input, refer Application Note. NOTE This parameter defined accordance with JEDEC Standard NOTE Tested with D_SELXX (divide FBDIV_SEL (divide NOTE This parameter defined value
TABLE CRYSTAL CHARACTERISTICS
Parameter Mode Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Test Conditions Minimum Typical Maximum Units Fundamental
TABLE INPUT REFERENCE CHARACTERISTICS, VDDA VDDO 3.3V±5%, 85°C
Symbol fREF
Parameter Reference Frequency
Test Conditions
Minimum
Typical
Maximum 83.33
Units
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ICS8761
VOLTAGE, SKEW, PCI-X CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V±5% 2.05V±5% 1.25V±5%
VDD, VDDA, VDDOx
SCOPE
VDD, VDDA
SCOPE
VDDOx
LVCMOS
LVCMOS
-1.165V±5%
-1.25V±5%
3.3V OUTPUT LOAD TEST CIRCUIT
3.3V/2.5V OUTPUT LOAD TEST CIRCUIT
DDOX
VDDO
DDOX
sk(o)
sk(o)
VDDO
OUTPUT SKEW
BANK SKEW (Where denotes outputs same Bank)
DDOX
DDOX
DDOX
tcycle
1000 Cycles
CYCLE-TO-CYCLE JITTER
VDDOX PERIOD
STATIC PHASE OFFSET
VDDOX
VDDOX
QAx, QBx, QCx, QDx, FB_OUT
Clock Outputs
PERIOD
tPERIOD
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OUTPUT RISE/FALL TIME
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jit(cc) tcycle -tcycle
QAx, QBx, QCx,
REF_CL:K
tcycle
FB_IN
ICS8761
VOLTAGE, SKEW, PCI-X CLOCK GENERATOR APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS8761 provides separate power supplies isolate high switching noise from outputs internal PLL. VDD, VDDA, VDDOx should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with 10µF .01µF bypass capacitor should connected each VDDA.
3.3V .01µF VDDA .01µF
FIGURE POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
ICS8761 crystal interface shown Figure While layout Board, recommended provide spare footprints frequency fine tuning. 18pF parallel resonant crystal, expected ~10pF ~5pF respectively.
XTAL2
SPARE
18pF Parallel stal
XTAL1
SPARE
FIGURE CRYSTAL INPUT INTERFACE
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ICS8761
VOLTAGE, SKEW, PCI-X CLOCK GENERATOR
near power pin. ICS8761, unused clock outputs left floating. optional spare footprints frequency fine tuning.
SCHEMATIC EXAMPLE
Figure shows schematic example ICS8761. this example, input driven HiPerClockS LVHSTL driver. decoupling capacitors should physically located
VDDO
Receiv
VDDOC VDDOC VDDOD VDDOD
Receiv
25MHz,18pF
0.1u
REF_CLK XTAL1 XTAL2 XTAL_SEL PLL_SEL VDDA D_SELC0 D_SELC1 D_SELA0 D_SELA1
FB_OUT VDDOFB FB_IN FBDIV_SEL0 FBDIV_SEL1 D_SELD0 D_SELD1 D_SELB0 D_SELB1
VDDO
Receiv
Spare, Install
ICS8761
VDDO
VDDOA VDDOA VDDOB VDDOB
Logic Input Examples
(U1,5)
(U1,9)
(U1,40)
(U1,44)
Logic Input
Logic Input
0.1u
0.1u
0.1u
0.1u
VDD=3.3V
VDDO=3.3V
Receiv
Logic Input pins
Logic Input pins
(U1,23) (U1,19) VDDO
0.1u
(U1,27)
(U1,31)
(U1,50)
(U1,54)
(U1,58)
(U1,62)
(U1,46)
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
FIGURE ICS8761 CLOCK GENERATOR SCHEMATIC EXAMPLE
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ICS8761
VOLTAGE, SKEW, PCI-X CLOCK GENERATOR RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE
LEAD TSSOP
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 58.8°C/W 41.1°C/W
48.5°C/W 35.8°C/W
43.2°C/W 33.6°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS8761 6040
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ICS8761
VOLTAGE, SKEW, PCI-X CLOCK GENERATOR
LEAD TSSOP
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL 0.45 -0.05 1.35 0.17 0.09 MINIMUM NOMINAL -1.40 -12.00 BASIC 10.00 BASIC 7.50 Ref. 12.00 BASIC 10.00 BASIC 7.50 Ref. 0.50 BASIC -0.75 0.08 1.60 0.15 1.45 0.27 0.20 MAXIMUM
Reference Document: JEDEC Publication MS-026
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ICS8761
VOLTAGE, SKEW, PCI-X CLOCK GENERATOR
Marking ICS8761CY ICS8761CY ICS8761CYLN ICS8761CYLN ICS8761CYLF ICS8761CYLF Package Lead LQFP Lead LQFP Tape Reel Lead "Lead-Free/Annealed" LQFP Lead "Lead-Free/Annealed" LQFP Tape Reel Lead "Lead-Free" LQFP Lead "Lead-Free" LQFP Tape Reel Count tray tray tray Temperature 85°C 85°C 85°C 85°C 85°C 85°C
TABLE ORDERING INFORMATION
Part/Order Number ICS8761CY ICS8761CYT ICS8761CYLN ICS8761CYLNT ICS8761CYLF ICS8761CYLFT
aforementioned trademark, HiPerClockSis trademark Integrated Circuit Systems, Inc. subsidiaries United States and/or other countries. While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 8761CY
REV. SEPTEMBER 2004
ICS8761
VOLTAGE, SKEW, PCI-X CLOCK GENERATOR
REVISION HISTORY SHEET Description Change Description Table, revised Master Reset description. Description Table, should labeled PULL-UP instead PULL-DOWN. LVCMOS Characteristics table rows, FBDIV_SEL0 deleted from "pulldown" added "pullup" row. Features section, changed max. output frequency from 200MHz 183.3MHz, max. REF_CLK input frequency from 100MHz 91.6MHz. Control Function Table revised Reference Frequency Range column Frequency columns reflect output frequency change. Characteristics tables changed Output Frequency from 200MHz max. 183.3MHz max. Description Table, revised ystal description. Characteristics tables changed Period Jitter measurement Period Jitter, added NOTE Added ystal information. Added Schematic Example Application Information Section. Description Table revised description. Power Supply Tables changed parameter read "Core Supply Voltage" from "Positive Supply Voltage". Deleted ystal Input Interface section. Updated Schematic Example diagram. Updated Features reflect 3.3V Characteristics (see below). Adjusted Ref. Frequency Range Frequency columns. Changed max. from 150mA 175mA, IDDA max. from 50mA 55mA, IDDO max. from 330mA 25mA. Changed fMAX from 183.3MHz max. 166.67MHz max. Changed tjit(per) from 20ps max. 17ps max. Features Section added Lead-Free bullet. Added ystal Section. Ordering Information Table added Lead-Free/Annealed Number. Ordering Information Table added Lead-Free Number. 4/10/03 1/20/03 Date 8/15/02 11/05/02
Table T4B,
Page
T5A, T5A,
11/06/02
T4A,
3/25/03
8/2/04 8/7/04
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VOLTAGE, SKEW, PCI-X CLOCK GENERATOR Fully integrated LVCMOS/LVTT

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