Skew Output Buffer ICS9112-16 high performance, skew, jitter cloc
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ICS9112-16
Skew Output Buffer
ICS9112-16 high performance, skew, jitter clock driver. uses phase lock loop (PLL) technology align, both phase frequency, input with CLKOUT signal. designed distribute high speed clocks systems operating speeds from MHz. ICS9112-16 zero delay buffer that provides synchronization between input output. synchronization established CLKOUT feed back input PLL. Since skew between input output less than part acts zero delay buffer. ICS9112-16 comes eight SOIC TSSOP package. five output clocks. absence input, will power down mode. this mode, turned output buffers pulled low. Power down mode provides lowest power consumption standby condition.
Features
Zero input output delay Frequency range (3.3V) High loop filter bandwidth ideal Spread Spectrum applications. Less than Jitter between outputs Skew controlled outputs Skew less than between outputs Available SOIC TSSOP package. 3.3V ±10% operation
Block Diagram
Configuration
SOIC, TSSOP
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ICS9112-16
Descriptions
NUMBER NAME
TYPE Input reference frequency. Buffered clock output Buffered clock output Ground Buffered clock output Power Supply (3.3V) Buffered clock output
DESCRIPTION
CLK2
CLK13 CLK33 CLK4
CLKOUT
Buffered clock output. Internal feedback this
Notes: Guaranteed design characterization. subject 100% test. Weak pull-down Weak pull-down outputs
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ICS9112-16
Absolute Maximum Ratings
Supply Voltage Logic Inputs -0.5 +0.5 Ambient Operating Temperature +70°C Storage Temperature -65°C +150°C Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only functional operation device these other conditions above those listed operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
Electrical Characteristics 3.3V
unless otherwise stated
Characteristics PARAMETER Input Voltage Input High Voltage Input Current Input High Current Output Voltage1 SYMBOL VIN=0V VIN=VDD 25mA 25mA Unloaded oututs 66.66 inputs 0.10 0.25 30.0 50.0 40.0 50.0 100.0 TEST CONDITIONS UNITS
Output High Voltage1 Power Down Supply Current Supply Current
Notes: Guaranteed design characterization. subject 100% test. Skew specifications mesured with transmission line, load teminated with 1.4V. Duty cycle measured 1.4V. Skew measured 1.4V rising edges. Loading must equal outputs.
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ICS9112-16
Switching Characteristics
PARAMETER Output period Input period Duty Cycle1 Duty Cycle1 Rise Time1 Fall Time1 Delay, Rising Edge CLKOUT Rising Edge1, Output Output Skew1 Device Device Skew1 Cycle Cycle Jitter1 Lock Time1 Jitter Absolute Jitter1 Jitter Sigma1 SYMBOL Tskew Tdsk-Tdsk Tcyc-Tcyc tLOCK Tjabs Tj1s CONDITION With CL=30pF With CL=30pF Measured 1.4V; CL=30pF Measured VDD/2 Fout <66.6MHz Measured between 0.8V 2.0V: CL=30pF Measured between 2.0V 0.8V; CL=30pF Measured 1.4V outputs equally loaded, CL=20pF Measured VDD/2 CLKOUT pins devices Measured 66.66 MHz, loaded outputs Stable power supply, valid clock presented 10,000 cycles CL=30pF 10,000 cycles CL=30pF -100 40.00 (25) 40.00 (25) 40.0 (133) (133) ±350 UNITS (MHz) (MHz)
Notes: Guaranteed design characterization. subject 100% test. input threshold voltage 1.4V parameters expected with loaded outputs
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ICS9112-16
Output Output Skew
skew between CLKOUT CLK(1-4) outputs dynamically adjusted PLL. Since CLKOUT inputs PLL, zero phase difference maintained from CLKOUT. outputs equally loaded, zero phase difference will maintained from outputs. applications requiring zero output-output skew, outputs must equally loaded. CLK(1-4) outputs less loaded than CLKOUT, CLK(1-4) outputs will lead CLK(1-4) more loaded than CLKOUT, CLK(1-4) will CLKOUT. Since CLKOUT CLK(1-4) outputs identical, they start same time, different loads cause them have different rise times different times crossing measurement thresholds.
input outputs loaded Equally
input CLK(1-4) outputs loaded equally, with CLKOUT loaded More.
input CLK(1_4) outputs loaded equally, with CLKOUT loaded Less.
Timing diagrams with different loading configurations
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ICS9112-16
INDEX AREA
SEATING PLANE (.004)
Millimeters Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS 1.35 1.75 .0532 .0688 0.10 0.25 .0040 .0098 0.33 0.51 .013 .020 0.19 0.25 .0075 .0098 VARIATIONS VARIATIONS 3.80 4.00 .1497 .1574 0.050 BASIC 1.27 BASIC 5.80 6.20 .2284 .2440 0.25 0.50 .010 .020 0.40 1.27 .016 .050 VARIATIONS VARIATIONS VARIATIONS
10-0030
4.80 5.00
(inch) .1890 .1968
Reference Doc.: JEDEC Publication MS-012
(Narrow Body) SOIC
Ordering Information
ICS9112yM-16LF-T
Example:
XXXX
Designation tape reel packaging Lead Free (Optional) Pattern Number digit number parts with code patterns) Package Type SOIC Revision Designator (will correlate with datasheet revision) Device Type Prefix Standard Device
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ICS9112-16
INDEX AREA
Millimeters SYMBOL COMMON DIMENSIONS -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 VARIATIONS 6.40 BASIC 4.30 4.50 0.65 BASIC 0.45 0.75 VARIATIONS -0.10 VARIATIONS 2.90 3.10
Inches COMMON DIMENSIONS -.047 .002 .006 .032 .041 .007 .012 .0035 .008 VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 VARIATIONS -.004
(inch) .114 .122
SEATING PLANE
10-0035
Reference Doc.: JEDEC Publication MO-153
4.40 Body, 0.65 pitch TSSOP (0.0256 Inch) (173 mil)
Ordering Information
ICS9112yG-16LF-T
Example:
XXXX
Designation tape reel packaging Lead Free (Optional) Pattern Number digit number parts with code patterns) Package Type TSSOP Revision Designator (will correlate with datasheet revision) Device Type Prefix Standard Device
0047H-09/01/04
ICS9112-16
Revision History
Rev. Issue Date Description 9/1/2004 Updated Lead Free information Page
0047H-09/01/04
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