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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION LIFE SUPPO


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PI7C7300A 3-PORT PCI-to-PCI BRIDGE
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
LIFE SUPPORT POLICY Pericom Semiconductor Corporation's products authorized critical components life support devices systems unless specific written agreement pertaining such intended executed between manufacturer officer PSC. Life support devices systems devices systems which: intended surgical implant into body support sustain life whose failure perform, when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness. Pericom Semiconductor Corporation reserves right make changes products specifications time, without notice, order improve design performance supply best possible product. Pericom Semiconductor does assume responsibility circuitry described other than circuitry embodied Pericom Semiconductor product. Company makes representations that circuitry described herein free from patent infringement other rights third parties which result from use. license granted implication otherwise under patent, patent rights other rights, Pericom Semiconductor Corporation. other trademarks their respective companies.
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
REVISION HISTORY
Revision 1.01 Date 9/25/01 Description Corrected description bits both Configuration register configuration register offset (Diagnostic/ Chip Control Register). controls memory read flow-through bits reserved. Updated jumper setting/descriptions Evaluation Board User's Manual. Updated Sheet schematics. 1.02 1.03 10/25/01 10/29/01 Added more description Primary Reset. Replaced Preliminary Information with Advanced Information. Corrected Secondary Status Register read Received instead Signaled Changed email address from nolimits@pericom.com solutions@pericom.com. 1.04 1.05 1.06 11/12/01 12/19/01 06/04/02 Corrected PBGA List (S2_AD[28], S1_CLKOUT[7:0] S2_CLKOUT[7:0] incorrect) Corrected P_AD[27,26] section P_AD[27] should instead P_AD[26] should instead references TDELAY sections 17.4 17.5 removed. references removed power consumption supply current section 17.6. Ambient temperature corrected section (maximum ratings) 1.07 08/22/02 Revised TSKEW section 17.4 17.5 Added reference Thermal Characteristics section 1.08 1.09 09/09/03 09/25/03 Corrected part number references from PI7C7300 PI7C7300A. Added back signal type description section
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
TABLE CONTENTS
INTRODUCTION BLOCK DIAGRAM. SIGNAL DEFINITIONS SIGNAL TYPES PRIMARY INTERFACE SIGNALS SECONDARY INTERFACE SIGNALS. CLOCK SIGNALS. MISCELLANEOUS SIGNALS COMPACT HOT-SWAP SIGNALS. JTAG BOUNDARY SCAN SIGNALS. POWER GROUND. PI7C7300A PBGA LIST
OPERATION TYPES TRANSACTIONS. SINGLE ADDRESS PHASE DUAL ADDRESS PHASE. DEVICE SELECT (DEVSEL#) GENERATION. DATA PHASE WRITE TRANSACTIONS 4.6.1 MEMORY WRITE TRANSACTIONS. 4.6.2 MEMORY WRITE INVALIDATE TRANSACTIONS. 4.6.3 DELAYED WRITE TRANSACTIONS 4.6.4 WRITE TRANSACTION ADDRESS BOUNDARIES 4.6.5 BUFFERING MULTIPLE WRITE TRANSACTIONS. 4.6.6 FAST BACK-TO-BACK WRITE TRANSACTIONS READ TRANSACTIONS 4.7.1 PREFETCHABLE READ TRANSACTIONS. 4.7.2 NON-PREFETCHABLE READ TRANSACTIONS 4.7.3 READ PREFETCH ADDRESS BOUNDARIES. 4.7.4 DELAYED READ REQUESTS 4.7.5 DELAYED READ COMPLETION WITH TARGET 4.7.6 DELAYED READ COMPLETION INITIATOR BUS. 4.7.7 FAST BACK-TO-BACK READ TRANSACTION. CONFIGURATION TRANSACTIONS 4.8.1 TYPE ACCESS PI7C7300A. 4.8.2 TYPE TYPE CONVERSION 4.8.3 TYPE TYPE FORWARDING. 4.8.4 SPECIAL CYCLES TRANSACTION TERMINATION 4.9.1 MASTER TERMINATION INITIATED PI7C7300A 4.9.2 MASTER ABORT RECEIVED PI7C7300A 4.9.3 TARGET TERMINATION RECEIVED PI7C7300A
4.9.3.1 4.9.3.2 4.9.3.3 DELAYED WRITE TARGET TERMINATION RESPONSE. POSTED WRITE TARGET TERMINATION RESPONSE DELAYED READ TARGET TERMINATION RESPONSE
4.9.4
4.9.4.1 4.9.4.2 4.9.4.3
TARGET TERMINATION INITIATED PI7C7300A
TARGET RETRY. TARGET DISCONNECT. TARGET ABORT
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 4.10 CONCURRENT MODE OPERATION
ADDRESS DECODING ADDRESS RANGES ADDRESS DECODING 5.2.1 BASE LIMIT ADDRESS REGISTER. 5.2.2 MODE. MEMORY ADDRESS DECODING. 5.3.1 MEMORY-MAPPED BASE LIMIT ADDRESS REGISTERS 5.3.2 PREFETCHABLE MEMORY BASE LIMIT ADDRESS REGISTERS SUPPORT 5.4.1 MODE. 5.4.2 SNOOP MODE
TRANSACTION ORDERING. TRANSACTIONS GOVERNED ORDERING RULES. GENERAL ORDERING GUIDELINES. ORDERING RULES DATA SYNCHRONIZATION
ERROR HANDLING. ADDRESS PARITY ERRORS DATA PARITY ERRORS 7.2.1 CONFIGURATION WRITE TRANSACTIONS CONFIGURATION SPACE 7.2.2 READ TRANSACTIONS 7.2.3 DELAYED WRITE TRANSACTIONS 7.2.4 POSTED WRITE TRANSACTIONS. DATA PARITY ERROR REPORTING SUMMARY SYSTEM ERROR (SERR#) REPORTING.
EXCLUSIVE ACCESS. CONCURRENT LOCKS ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C7300A. 8.2.1 LOCKED TRANSACTIONS DOWSTREAM DIRECTION. 8.2.2 LOCKED TRANSACTION UPSTREAM DIRECTION. ENDING EXCLUSIVE ACCESS
ARBITRATION. PRIMARY ARBITRATION. SECONDARY ARBITRATION 9.2.1 SECONDARY BUSARBITRATION USING INTERNAL ARBITER 9.2.2 PREEMPTION 9.2.3 SECONDARY ARBITRATION USING EXTERNAL ARBITER. 9.2.4 PARKING.
11.1 11.2 12.1 12.2
COMPACT SWAP CLOCKS PRIMARY CLOCK INPUTS. SECONDARY CLOCK OUTPUTS. RESET. PRIMARY INTERFACE RESET SECONDARY INTERFACE RESET Page 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 13.1 13.2 SUPPORTED COMMANDS PRIMARY INTERFACE SECONDARY INTERFACE CONFIGURATION REGISTERS
14.1 CONFIGURATION REGISTER 14.1.1 VENDOR REGISTER OFFSET 00h. 14.1.2 DEVICE REGISTER OFFSET 14.1.3 COMMAND REGISTER OFFSET 14.1.4 STATUS REGISTER OFFSET 04h. 14.1.5 REVISION REGISTER OFFSET 08h. 14.1.6 CLASS CODE REGISTER OFFEST 14.1.7 CACHE LINE SIZE REGISTER OFFSET 14.1.8 PRIMARY LATENCY TIMER REGISTER OFFSET 0Ch. 14.1.9 HEADER TYPE REGISTER OFFSET 14.1.10 PRIMARY NUMBER REGISTER OFFSET 14.1.11 SECONDARY NUMBER REGISTER OFFSET 14.1.12 SUBORDINATE NUMBER REGISTER OFFSET 14.1.13 SECONDARY LATENCY TIMER REGISTER OFFSET 14.1.14 BASE REGISTER OFFSET 14.1.15 LIMIT REGISTER OFFSET 14.1.16 SECONDARY STATUS REGISTER OFFSET 1Ch. 14.1.17 MEMORY BASE REGISTER OFFSET 20h. 14.1.18 MEMORY LIMIT REGISTER OFFSET 20h. 14.1.19 PREFETCHABLE MEMORY BASE REGISTER OFFSET 14.1.20 PREFETCHABLE MEMORY LIMIT REGISTER OFFSET 14.1.21 PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER OFFSET 14.1.22 PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER OFFSET 14.1.23 BASE ADDRESS UPPER 16-BITS REGISTER Offset 30h. 14.1.24 LIMIT ADDRESS UPPER 16-BITS REGISTER OFFSET 30h. 14.1.25 POINTER REGISTER OFFSET 34h. 14.1.26 BRIDGE CONTROL REGISTER OFFSET 3Ch. 14.1.27 DIAGNOSTIC CHIP CONTROL REGISTER OFFSET 14.1.28 ARBITER CONTROL REGISTER OFFSET 40h. 14.1.29 UPSTREAM MEMORY CONTROL REGISTER OFFSET 48h. 14.1.30 SWAP SWITCH TIME SLOT REGISTER OFFSET 4Ch. 14.1.31 UPSTREAM MEMORY BASE REGISTER OFFSET 50h. 14.1.32 UPSTREAM MEMORY LIMIT REGISTER OFFSET 50h. 14.1.33 UPSTREAM MEMORY BASE UPPER 32-BITS REGISTER OFFSET 14.1.34 UPSTREAM MEMORY LIMIT UPPER BITS REGISTER OFFSET 14.1.35 P_SERR# EVENT DISABLE REGISTER OFFSET 14.1.36 SECONDARY CLOCK CONTROL REGISTER OFFSET 14.1.37 PORT OPTION REGISTER OFFSET 14.1.38 MASTER TIMEOUT COUNTER REGISTER OFFSET 14.1.39 RETRY COUNTER REGISTER OFFSET 78h. 14.1.40 SAMPLING TIMER REGISTER OFFSET 7Ch. 14.1.41 SECONDARY SUCCESSFUL READ COUNTER REGISTER OFFSET 14.1.42 SECONDARY SUCCESSFUL WRITE COUNTER REGISTER OFFSET 84h. 14.1.43 SECONDARY SUCCESSFUL MEMORY READ COUNTER REGISTER Offset 88h. Page 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 14.1.44 14.1.45 14.1.46 14.1.47 14.1.48 14.1.49 14.1.50 14.1.51 14.1.52 14.1.53 14.1.54 14.1.55 SECONDARY SUCCESSFUL MEMORY WRITE COUNTER REGISTER OFFSET PRIMARY SUCCESSFUL READ COUNTER REGISTER OFFSET PRIMARY SUCCESSFUL WRITE COUNTER REGISTER OFFSET 94h. PRIMARY SUCCESSFUL MEMORY READ COUNTER REGISTER OFFSET PRIMARY SUCCESSFUL MEMORY WRITE COUNTER REGISTER OFFSET 9Ch. CAPABILITY REGISTER OFFSET NEXT POINTER REGISTER OFFSET SLOT NUMBER REGISTER OFFSET B0h. CHASSIS NUMBER REGISTER OFFSET B0h. CAPABILITY REGISTER OFFSET NEXT POINTER REGISTER OFFSET C0h. SWAP CONTROL STATUS REGISTER OFFSET
BRIDGE BEHAVIOR.
15.1 BRIDGE ACTIONS VARIOUS CYCLE TYPES 15.2 TRANSACTION ORDERING 15.3 ABNORMAL TERMINATION (INITIATED BRIDGE MASTER). 15.3.1 MASTER ABORT. 15.3.2 PARITY ERROR REPORTING. 15.3.3 REPORTING PARITY ERRORS. 15.3.4 SECONDARY IDSEL MAPPING IEEE 1149.1 COMPATIBLE JTAG CONTROLLER 16.1 BOUNDARY SCAN ARCHITECTURE. 16.1.1 PINS. 16.1.2 INSTRUCTION REGISTER. 16.2 BOUNDARY-SCAN INSTRUCTION 16.3 TEST DATA REGISTERS 16.4 BYPASS REGISTER 16.5 BOUNDARY-SCAN REGISTER. 16.6 CONTROLLER 17.1 17.2 17.3 17.4 17.5 17.6 18.1 ELECTRICAL TIMING SPECIFICATIONS. MAXIMUM RATINGS 3.3V SPECIFICATIONS 3.3V SPECIFICATIONS PRIMARY SECONDARY BUSES 66MHZ CLOCK TIMING PRIMARY SECONDARY BUSES 33MHZ CLOCK TIMING POWER CONSUMPTION 272-PIN PBGA PACKAGE FIGURE PART NUMBER ORDERING INFORMATION
APPENDIX PI7C7300A EVALUATION BOARD USER'S MANUAL. FREQUENTLY ASKED QUESTIONS
LIST TABLES
TABLE TABLE TABLE TABLE TRANSACTIONS WRITE TRANSACTION FORWARDING WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES. READ PREFETCH ADDRESS BOUNDARIES. Page 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION TABLE READ TRANSACTION PREFETCHING TABLE DEVICE NUMBER IDSEL S1_AD S2_AD MAPPING TABLE DELAYED WRITE TARGET TERMINATION RESPONSE. TABLE RESPONSE POSTED WRITE TARGET TERMINATION TABLE RESPONSE DELAYED READ TARGET TERMINATION TABLE SUMMARY TRANSACTION ORDERING. TABLE SETTING PRIMARY INTERFACE DETECTED PARITY ERROR TABLE SETTING SECONDARY INTERFACE DETECTED PARITY ERROR TABLE SETTING PRIMARY INTERFACE DATA PARITY ERROR DETECTED BIT. TABLE SETTING SECONDARY INTERFACE DATA PARITY ERROR DETECTED TABLE ASSERTION P_PERR#. TABLE ASSERTION S_PERR#. TABLE ASSERTION P_SERR# DATA PARITY ERRORS TABLE 16-1 PINS TABLE 16-2 JTAG BOUNDARY REGISTER ORDER
LIST FIGURES
FIGURE SECONDARY ARBITER EXAMPLE. FIGURE 16-1 TEST ACCESS PORT BLOCK DIAGRAM. FIGURE 17-1 SIGNAL TIMING MEASUREMENT CONDITIONS FIGURE 18-1 272-PIN PBGA PACKAGE
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
INTRODUCTION
PRODUCT DESCRIPTION
PI7C7300A Pericom Semiconductor's second-generation PCI-PCI Bridge. designed fully compliant with 32-bit, 66MHz implementation Local Specification, Revision 2.2. PI7C7300A supports only synchronous transactions between devices Primary running 33MHz 66MHz Secondary Buses operating either 33MHz 66MHz. Primary Secondary Buses also operate concurrent mode, resulting added increase system performance. Concurrent operation off-loads isolates unnecessary traffic from Primary Bus; thereby enabling master target device same Secondary communicate even while Primary busy. addition, Secondary Buses have load balancing capability, allowing faster devices isolated away from slower devices. Among other features supported PI7C7300A are: support devices Secondary Buses, Compact Swap (PICMG 2.1, R1.0) Friendly Support Dual Addressing Cycle.
PRODUCT FEATURES
32-bit Primary Secondary Ports 66MHz ports compliant with Local Specification, Revision Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 1.1. memory commands Type Type configuration conversion Type Type configuration forwarding Type configuration write special cycle conversion Concurrent Primary Secondary operation independent intra-Secondary Port channel reduce traffic Primary Port Provides internal arbitration eight secondary masters bus) seven (eight Swap disable)secondary masters bus) Programmable 2-level priority arbiter Disable control external arbiter Supports posted write buffers directions Three byte FIFO's delay transactions Three byte FIFO's posted memory transactions Enhanced address decoding 32-bit address range 32-bit memory-mapped address range addressing palette snooping ISA-aware mode legacy support first 64KB address range Dual Addressing cycle (64-bit) Interrupt handling interrupts routed through external interrupt concentrator Supports system transaction ordering rules Tri-state control output buffers secondary buses Compact Swap (PICMG 2.1, R1.0) Friendly Support Industrial Temperature range -40°C 85°C IEEE 1149.1 JTAG interface support 3.3V core; 3.3V interface with tolerance 272-pin plastic package
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
BLOCK DIAGRAM
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
SIGNAL DEFINITIONS
SIGNAL TYPES
Signal Type PSTS Description input (3.3V, tolerant) input (3.3V, tolerant) with weak pull-up input (3.3V, tolerant) with weak pull-down output (3.3V) tri-state bidirectional (3.3V, tolerant) sustained tri-state bi-directional (Active signal which must driven inactive cycle before being tri-stated ensure HIGH performance shared signal line) tri-state output output which either drives (active state) tri-state
PRIMARY INTERFACE SIGNALS
Name P_AD[31:0] W10, V10, Y11, V11, U11, Y12, W12, V12, V16, W16, Y16, W17, Y17, U18, W18, Y18, U19, W19, Y19, U20, V20, Y20, T17, U12, U16, Type Description Primary Address/Data. Multiplexed address data bus. Address indicated P_FRAME# assertion. Write data stable valid when P_IRDY# asserted read data stable valid when P_TRDY# asserted. Data transferred rising clock edges when both P_IRDY# P_TRDY# asserted. During idle, PI7C7300A drives P_AD valid logic level when P_GNT# asserted.
P_CBE[3:0]
P_PAR
P_FRAME#
PSTS
Primary Command/Byte Enables. Multiplexed command field byte enable field. During address phase, initiator drives transaction type these pins. initiator then drives byte enables during data phases. During idle, PI7C7300A drives P_CBE[3:0] valid logic level when P_GNT# asserted. Primary Parity. Parity even across P_AD[31:0], P_CBE[3:0], P_PAR (i.e. even number 1's). P_PAR input valid stable cycle after address phase (indicated assertion P_FRAME#) address parity. write data phases, P_PAR input valid clock after P_IRDY# asserted. read data phase, P_PAR output valid clock after P_TRDY# asserted. Signal P_PAR tri-stated cycle after P_AD lines tri-stated. During idle, PI7C7300A drives P_PAR valid logic level when P_GNT# asserted. Primary FRAME (Active LOW). Driven initiator transaction indicate beginning duration access. de-assertion P_FRAME# indicates final data phase requested initiator. Before being tri-stated, driven de-asserted state cycle.
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Name P_IRDY# Type PSTS Description Primary IRDY (Active LOW). Driven initiator transaction indicate ability complete current data phase primary side. Once asserted data phase, de-asserted until data phase. Before tri-stated, driven de-asserted state cycle. Primary TRDY (Active LOW). Driven target transaction indicate ability complete current data phase primary side. Once asserted data phase, de-asserted until data phase. Before tri-stated, driven de-asserted state cycle. Primary Device Select (Active LOW). Asserted target indicating that device accepting transaction. master, PI7C7300A waits assertion this signal within cycles P_FRAME# assertion; otherwise, terminate with master abort. Before tri-stated, driven de-asserted state cycle. Primary STOP (Active LOW). Asserted target indicating that target requesting initiator stop current transaction. Before tri-stated, driven de-asserted state cycle. Primary LOCK (Active LOW). Asserted master multiple transactions complete. Primary Select. Used chip select line Type configuration accesses PI7C7300A configuration space. Primary Parity Error (Active LOW). Asserted when data parity error detected data received primary interface. Before being tri-stated, driven de-asserted state cycle. Primary System Error (Active LOW). driven device indicate system error condition. PI7C7300A drives this Address parity error Posted write data parity error target Secondary S1_SERR# S2_SERR# asserted Master abort during posted write transaction Target abort during posted write transaction Posted write transaction discarded Delayed write request discarded Delayed read request discarded Delayed transaction master timeout This signal requires external pull-up resistor proper operation. Primary Request (Active LOW). This asserted PI7C7300A indicate that wants start transaction primary bus. PI7C7300A de-asserts this least clock cycles before asserting again. Primary Grant (Active LOW). When asserted, PI7C7300A access primary bus. During idle P_GNT# asserted, PI7C7300A will drive P_AD, P_CBE, P_PAR valid logic levels. Primary RESET (Active LOW). When P_RESET# active, signals should asynchronously tri-stated.
P_TRDY#
PSTS
P_DEVSEL#
PSTS
P_STOP#
PSTS
P_LOCK# P_IDSEL
PSTS
P_PERR#
PSTS
P_SERR#
P_REQ#
P_GNT#
P_RESET#
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Name P_M66EN Type Description Primary Interface 66MHz Operation. This input used specify PI7C7300A capable running 66MHz. 66MHz operation Primary bus, this signal should pulled "HIGH". 33MHz operation Primary bus, this signal should pulled "LOW". this condition, S1_M66EN S2_M66EN will both need "LOW", forcing both secondary buses 33MHz also.
SECONDARY INTERFACE SIGNALS
Name S1_AD[31:0], B20, B19, C20, C19, C18, D20, D19, D17, E19, E18, E17, F20, F19, F17, G20, G19, L20, L19, L18, M20, M19, M17, N20, N19, N18, N17, P17, R20, R19, R18, T20, D10, E20, G18, K17, Type Description Secondary Address/Data. Multiplexed address data bus. Address indicated S1_FRAME# S2_FRAME# assertion. Write data stable valid when S1_IRDY# S2_IRDY# asserted read data stable valid when S1_IRDY# S2_IRDY# asserted. Data transferred rising clock edges when both S1_IRDY# S2_IRDY# S1_TRDY# S2_TRDY# asserted. During idle, PI7C7300A drives S1_AD S2_AD valid logic level when S1_GNT# S2_GNT# asserted respectively.
S2_AD[31:0]
S1_CBE[3:0], S2_CBE[3:0]
S1_PAR, S2_PAR
K18,
S1_FRAME#, S2_FRAME#
H20,
PSTS
Secondary Command/Byte Enables. Multiplexed command field byte enable field. During address phase, initiator drives transaction type these pins. initiator then drives byte enables during data phases. During idle, PI7C7300A drives S1_CBE[3:0] S2_CBE[3:0] valid logic level when internal grant asserted. Secondary Parity. Parity even across S1_AD[31:0], S1_CBE[3:0], S1_PAR S2_AD[31:0], S2_CBE[3:0], S2_PAR (i.e. even number 1's). S1_PAR S2_PAR input valid stable cycle after address phase (indicated assertion S1_FRAME# S2_FRAME#) address parity. write data phases, S1_PAR S2_PAR input valid clock after S1_IRDY# S2_IRDY# asserted. read data phase, S1_PAR S2_PAR output valid clock after S1_TRDY# S2_TRDY# asserted. Signal S1_PAR S2_PAR tri-stated cycle after S1_AD S2_AD lines tri-stated. During idle, PI7C7300A drives S1_PAR S2_PAR valid logic level when internal grant asserted. Secondary FRAME (Active LOW). Driven initiator transaction indicate beginning duration access. de-assertion S1_FRAME# S2_FRAME# indicates final data phase requested initiator. Before being tristated, driven de-asserted state cycle.
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Name S1_IRDY#, S2_IRDY# H19, Type PSTS Description Secondary IRDY (Active LOW). Driven initiator transaction indicate ability complete current data phase secondary side. Once asserted data phase, de-asserted until data phase. Before tri-stated, driven de-asserted state cycle. Secondary TRDY (Active LOW). Driven target transaction indicate ability complete current data phase secondary side. Once asserted data phase, de-asserted until data phase. Before tri-stated, driven de-asserted state cycle. Secondary Device Select (Active LOW). Asserted target indicating that device accepting transaction. master, PI7C7300A waits assertion this signal within cycles S1_FRAME# S2_FRAME# assertion; otherwise, terminate with master abort. Before tri-stated, driven deasserted state cycle. Secondary STOP (Active LOW). Asserted target indicating that target requesting initiator stop current transaction. Before tristated, driven de-asserted state cycle. Secondary LOCK (Active LOW). Asserted master multiple transactions complete. Secondary Parity Error (Active LOW). Asserted when data parity error detected data received secondary interface. Before being tri-stated, driven de-asserted state cycle. Secondary System Error (Active LOW). driven device indicate system error condition. Secondary Request (Active LOW). This asserted external device indicate that wants start transaction secondary bus. input externally pulled through resistor VDD. Secondary Grant (Active LOW). PI7C7300A asserts this access secondary bus. PI7C7300A deasserts this least clock cycles before asserting again. During idle S1_GNT# S2GNT# asserted, PI7C7300A will drive S1_AD, S1_CBE, S1_PAR S2_AD, S2_CBE, S2_PAR. Secondary RESET (Active LOW). Asserted when following conditions met: Signal P_RESET# asserted. Secondary reset bridge control register configuration space set. When asserted, control signals tri-stated zeroes driven S1_AD, S1_CBE, S1_PAR S2_AD, S2_CBE, S2_PAR. Secondary Enable (Active HIGH). When S1_EN S2_EN inactive, secondary will asynchronously tri-stated. Secondary Interface 66MHz Operation. This input used specify PI7C7300A capable running 66MHz secondary side. When HIGH, 66MHz. When LOW, only 33MHz. P_M66EN pulled LOW, both S1_M66EN S2_M66EN need LOW.
S1_TRDY#, S2_TRDY#
H18,
PSTS
S1_DEVSEL#, S2_DEVSEL#
J20,
PSTS
S1_STOP#, S2_STOP#
J19,
PSTS
S1_LOCK#, S2_LOCK# S1_PERR#, S2_PERR#
J18, J17,
PSTS PSTS
S1_SERR#, S2_SERR# S1_REQ#[7:0], S2_REQ#[6:0] S1_GNT#[7:0] S2_GNT#[6:0]
K20, B11, A12, D13, C13, C15, A16, C17, C11, B12, B13, A14, D14, B16, D16,
S1_RESET#, S2_RESET#
B10,
S1_EN, S2_EN S1_M66EN, S2_M66EN
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Name S_CFN# Type Description Secondary Central Function Control Pin. When tied LOW, enables internal arbiter. When tied HIGH, external arbiter must used. S1_REQ#[0] S2_REQ#[0] reconfigured secondary grant input, S1_GNT#[0] S2_GNT#[0] reconfigured secondary request output.
CLOCK SIGNALS
Name P_CLK S1_CLKOUT [7:0] S2_CLKOUT [7:0] A11, C12, A13, B14, B15, C16, A18, Type Description Primary Clock Input. Provides timing transactions primary interface. Secondary Clock Output. Provides secondary clocks phase synchronous with P_CLK. Secondary Clock Output. Provides secondary clocks phase synchronous with P_CLK.
MISCELLANEOUS SIGNALS
Name BYPASS PLL_S_CLKIN SCAN_TM# Type Description Reserved. Reserved future use. Must tied HIGH. Reserved. Reserved future use. Must tied LOW. Reserved. Reserved future use. Must tied LOW. Full-Scan Test Mode Enable (Active LOW). Connect HIGH normal operation. When SCAN_TM# active, scan chains will enabled. scan clock P_CLK. scan input outputs follows: S1_REQ[6], S1_REQ[5], S1_REQ[4], S1_REQ[3], S1_REQ[2], S2_REQ#[6], S2_REQ#[5], S2_REQ#[4], S2_REQ#[3], S2_REQ#[2], S1_GNT#[6], S1_GNT#[5], S1_GNT#[4], S1_GNT#[3], S1_GNT#[2], S2_GNT#[6], S2_GNT#[5], S2_GNT#[4], S2_GNT#[3], S2_GNT#[2] Full-Scan Enable Control. SCAN_EN should tied normal mode. When SCAN_EN LOW, fullscan shift operation SCAN_TM# active. When SCAN_EN HIGH, full-scan parallel operation SCAN_TM# active.
SCAN_EN
COMPACT HOT-SWAP SIGNALS
Name Type Description Swap LED. output this lights blue indicate insertion removal ready status. HS_EN LOW, S2_GNT#[7]. Swap Switch. When driven LOW, this signal indicates that board ejector handle indicates insertion impending extraction board. HS_EN LOW, S2_REQ#[7]. Swap Enable. enable Swap Friendly support, this signal should pulled HIGH.
HS_SW#
HS_EN
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Name ENUM# Type Description Swap Status Indicator. output ENUM# indicates system that insertion occurred that extraction about occur.
JTAG BOUNDARY SCAN SIGNALS
Name Type Description Test Clock. Used clock state information data into PI7C7300A during boundary scan. Test Mode Select. Used control state Test Access Port controller. Test Data Output. When SCAN_EN HIGH, used conjunction with TCK) shift data Test Access Port (TAP) serial stream. Test Data Input. When SCAN_EN HIGH, used conjunction with TCK) shift data instructions into Test Access Port (TAP) serial stream. Test Reset. Active signal reset Test Access Port (TAP) controller into initialized state.
TRST#
POWER GROUND
Name C14, D11, D15, F18, L17, P19, U10, V15, A10, A15, A17, A20, D12, D18, G17, H17, J10, J11, J12, K10, K11, K12, K19, L10, L11, L12, M10, M11, M12, M18, P18, T18, U14, U17, V17, W11, Type Description 3.3V Digital Power
Digital Ground
AVCC AGND
Analog 3.3V Analog Ground
PI7C7300A PBGA LIST
Name S2_CBE[2] S2_CBE[0] S2_AD[2] S1_CLKOUT[7] S1_CLKOUT[5] Type Name S2_TRDY# S2_CBE[1] S2_AD[10] S1_REQ#[6] S1_GNT#[4] S1_REQ#[2] Type PSTS
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Name S1_CLKOUT[0] S2_AD[16] S2_LOCK# S2_AD[14] S2_AD[8] S2_AD[3] S1_REQ#[7] S1_GNT#[5] S1_CLKOUT[3] S1_REQ#[0] S1_AD[30] S2_AD[17] S2_STOP# S2_AD[15] S2_AD[9] S2_AD[4] S1_GNT#[7] S1_REQ#[4] S1_REQ#[3] S1_REQ#[1] S1_AD[28] S2_AD[18] S2_DEVSEL# S1_M66EN S2_AD[5] S1_REQ#[5] S1_AD[24] S1_AD[25] S2_AD[20] S1_AD[21] S1_AD[23] S2_CBE[3] S2_AD[22] S1_AD[18] S1_AD[19] S2_AD[26] S2_AD[25] S1_AD[16] S2_AD[30] S2_AD[28] S1_IRDY# S2_CLKOUT[0] S1_PERR# S1_STOP# S2_REQ#[1] S2_REQ#[0] S1_CBE[1] S2_GNT#[1] S2_CLKOUT[2] Type PSTS PSTS PSTS PSTS PSTS PSTS Name S1_CLKOUT[1] S2_IRDY# S2_PAR S2_AD[11] S1_RESET# S1_GNT#[6] S1_CLKOUT[4] S1_GNT#[2] S1_GNT#[0] S1_AD[31] S2_SERR# S2_AD[12] S2_AD[6] S2_AD[0] S1_CLKOUT[6] S1_CLKOUT[2] S1_AD[27] S1_AD[29] S2_FRAME# S2_PERR# S2_AD[13] S2_AD[7] S2_AD[1] S1_GNT#[3] S1_GNT#[1] S1_AD[26] S2_AD[19] S1_AD[22] S1_CBE[3] S2_AD[23] S2_AD[21] S1_AD[20] S2_AD[24] S1_CBE[2] S1_AD[17] S2_AD[29] S2_AD[27] S1_TRDY# S1_FRAME# S2_AD[31] S1_LOCK# S1_DEVSEL# S2_GNT#[0] S1_PAR S1_SERR# S2_CLKOUT[1] S2_GNT#[2] Type PSTS PSTS PSTS PSTS PSTS PSTS PSTS
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Name S1_AD[14] S2_REQ#[2] S2_GNT#[3] S1_AD[10] S1_AD[11] S2_CLKOUT[4] S1_AD[6] S1_AD[8] S2_REQ#[4] S2_CLKOUT[5] S1_AD[5] S2_GNT#[5] S2_REQ#[6] P_AD[0] S1_AD[3] S2_CLKOUT[6] S2_CLKOUT[7] P_AD[1] S1_AD[0] TRST# SCAN_EN P_GNT# P_AD[19] P_TRDY# P_PAR P_AD[7] S_CLKIN P_CBE[3] P_AD[20] P_IRDY# P_CBE[0] S1_EN S2_M66EN P_AD[30] P_AD[24] P_FRAME# P_SERR# P_AD[12] P_AD[6] AVCC PLL_P_RESET# P_AD[31] P_AD[25] P_AD[21] P_PERR# Type PSTS Name S1_AD[13] S1_AD[15] S2_REQ#[3] S2_CLKOUT[3] S1_AD[12] S2_GNT#[4] S1_AD[7] S1_AD[9] S2_REQ#[5] S2_GNT#[6] S1_CBE[0] ENUM# S1_AD[2] S1_AD[4] HS_SW S2_RESET# S1_AD[1] AGND HS_EN P_AD[26] P_CBE[2] P_CBE[1] P_AD[10] P_AD[4] SCAN_TM# P_CLK P_AD[27] P_AD[22] P_AD[16] P_LOCK# P_AD[15] P_M66EN# P_AD[3] S2_EN P_REQ# P_AD[28] P_AD[23] P_AD[17] P_STOP# P_AD[14] P_AD[9] S_CFN# BYPASS P_AD[29] P_IDSEL P_AD[18] P_DEVSEL# P_AD[13] Type PSTS PSTS PSTS
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Name P_AD[11] P_AD[5] Type Name P_AD[8] P_AD[2] Type
OPERATION
This Chapter offers information about transactions, transaction forwarding across PI7C7300A, transaction termination. PI7C7300A three 128-byte buffers buffering upstream downstream transactions. These hold addresses, data, commands, byte enables used both read write transactions.
TYPES TRANSACTIONS
This section provides summary transactions performed PI7C7300A. Table lists command code name each transaction. Master Target columns indicate support each transaction when PI7C7300A initiates transactions master, primary secondary (S1, buses, when PI7C7300A responds transactions target, primary secondary (S1, buses. Table TRANSACTIONS
Types Transactions 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Interrupt Acknowledge Special Cycle Read Write Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write Invalidate Initiates Master Primary (Type only) Secondary Responds Target Primary Secondary (Type only)
indicated Table 4-1, following commands supported PI7C7300A: PI7C7300A never initiates transaction with reserved command code and, target, PI7C7300A ignores reserved command codes. PI7C7300A does generate interrupt acknowledge transactions. PI7C7300A ignores interrupt acknowledge transactions target. PI7C7300A does respond special cycle transactions. PI7C7300A cannot guarantee delivery special cycle transaction downstream buses because Page 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION broadcast nature special cycle command inability control transaction target. generate special cycle transactions other buses, either upstream downstream, Type configuration write must used. PI7C7300A neither generates Type configuration transactions primary responds Type configuration transactions secondary buses.
SINGLE ADDRESS PHASE
32-bit address uses single address phase. This address driven P_AD[31:0], command driven P_CBE[3:0]. PI7C7300A supports linear increment address mode only, which indicated when lowest address bits equal zero. either lowest address bits nonzero, PI7C7300A automatically disconnects transaction after first data transfer.
DUAL ADDRESS PHASE
64-bit address uses address phases. first address phase denoted asserting edge FRAME#. second address phase always follows next clock cycle. 32-bit interface, first address phase contains dual address command code C/BE#[3:0] lines, address bits AD[31:0] lines. second address phase consists specific memory transaction command code C/BE#[3:0] lines, high address bits AD[31:0] lines. this way, 64-bit addressing supported 32-bit buses. PCI-to-PCI Bridge Architecture Specification supports dual address transactions prefetchable memory range only. Section 5.3.2 discussion prefetchable address space. PI7C7300A supports dual address transactions both upstream downstream direction. PI7C7300A supports programmable 64-bit address range prefetchable memory downstream forwarding dual address transactions. Dual address transactions falling outside prefetchable address range forwarded upstream, downstream. Prefetching posting performed manner consistent with guidelines given this specification each type memory transaction prefetchable memory space.
DEVICE SELECT (DEVSEL#) GENERATION
PI7C7300A always performs positive address decoding (medium decode) when accepting transactions either primary secondary buses. PI7C7300A never does subtractive decode.
DATA PHASE
address phase transaction followed more data phases. data phase completed when IRDY# either TRDY# STOP# asserted. Page 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION transfer data occurs only when both IRDY# TRDY# asserted during same clock cycle. last data phase transaction indicated when FRAME# de-asserted both TRDY# IRDY# asserted, when IRDY# STOP# asserted. Section further discussion transaction termination. Depending command type, PI7C7300A support multiple data phase transactions. detailed descriptions PI7C7300A imposes disconnect boundaries, Section 4.6.4 write address boundaries Section 4.7.3 read address boundaries.
WRITE TRANSACTIONS
Write transactions treated either posted write delayed write transactions. Table shows method forwarding used each type write operation. Table WRITE TRANSACTION FORWARDING
Type Transaction Memory Write Memory Write Invalidate Memory Write memory Write Type Configuration Write Type Forwarding Posted (except memory) Posted Delayed Delayed Delayed
4.6.1
MEMORY WRITE TRANSACTIONS
Posted write forwarding used "Memory Write" "Memory Write Invalidate" transactions. When PI7C7300A determines that memory write transaction forwarded across bridge, PI7C7300A asserts DEVSEL# with medium timing TRDY# next cycle, provided that enough buffer space available posted memory write queue address least DWORD data. Under this condition, PI7C7300A accepts write data without obtaining access target bus. PI7C7300A accept DWORD write data every clock cycle. That target wait state inserted. write data stored internal posted write buffers subsequently delivered target. PI7C7300A continues accept write data until following events occurs: initiator terminates transaction de-asserting FRAME# IRDY#. internal write address boundary reached, such cache line boundary aligned boundary, depending transaction type. posted write data buffer fills
When last events occurs, PI7C7300A returns target disconnect requesting initiator this data phase terminate transaction. Once posted write data moves head posted data queue, PI7C7300A asserts request target bus. This occur while PI7C7300A still receiving data initiator bus. When grant target received target detected idle condition, PI7C7300A asserts FRAME# drives stored write Page 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION address target bus. following cycle, PI7C7300A drives first DWORD write data continues transfer write data until write data corresponding that transaction delivered, until target termination received. long write data exists queue, PI7C7300A drive DWORD write data each clock cycle; that master wait states inserted. write data flowing through PI7C7300A initiator stalls, PI7C7300A will signal last data phase current transaction target queue empties. PI7C7300A will restart follow-on transactions queue data. PI7C7300A ends transaction target when following conditions met: posted write data been delivered target. target returns target disconnect target retry (PI7C7300A starts another transaction deliver rest write data). target returns target abort (PI7C7300A discards remaining write data). master latency timer expires, PI7C7300A longer target grant (PI7C7300A starts another transaction deliver remaining write data).
Section 4.9.3.2 provides detailed information about PI7C7300A responds target termination during posted write transactions.
4.6.2
MEMORY WRITE INVALIDATE TRANSACTIONS
Posted write forwarding used Memory Write Invalidate transactions. PI7C7300A disconnects Memory Write Invalidate commands aligned cache line boundaries. cache line size value cache line size register gives number DWORD cache line. value cache line size register does meet memory write invalidate conditions, PI7C7300A returns target disconnect initiator either cache line boundary when posted write buffer fills. When Memory Write Invalidate transaction disconnected before cache line boundary reached, typically because posted write buffer fills, trans-action converted Memory Write transaction.
4.6.3
DELAYED WRITE TRANSACTIONS
Delayed write forwarding used write transactions Type configuration write transactions. delayed write transaction guarantees that actual target response returned back initiator without holding initiating wait states. delayed write transaction limited single DWORD data transfer.
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION When write transaction first detected initiator bus, PI7C7300A forwards delayed transaction, PI7C7300A claims access asserting DEVSEL# returns target retry initiator. During address phase, PI7C7300A samples command, address, address parity cycle later. After IRDY# asserted, PI7C7300A also samples first data DWORD, byte enable bits, data parity. This information placed into delayed transaction queue. transaction queued only other existing delayed transactions have same address command, delayed transaction queue full. When delayed write transaction moves head delayed transaction queue ordering constraints with posted data satisfied. PI7C7300A initiates transaction target bus. PI7C7300A transfers write data target. PI7C7300A receives target retry response write transaction target bus, continues repeat write transaction until data transfer completed, until error condition encountered. PI7C7300A unable deliver write data after (default) (maximum) attempts, PI7C7300A will report system error. PI7C7300A also asserts P_SERR# primary SERR# enable command register. Section information assertion P_SERR#. When initiator repeats same write transaction (same command, address, byte enable bits, data), completed delayed transaction head queue, PI7C7300A claims access asserting DEVSEL# returns TRDY# initiator, indicate that write data transferred. initiator requests multiple DWORD, PI7C7300A also asserts STOP# conjunction with TRDY# signal target disconnect. Note that only those bytes write data with valid byte enable bits compared. byte enable bits turned (driven HIGH), corresponding byte write data compared. initiator repeats write transaction before data been transferred target, PI7C7300A returns target retry initiator. PI7C7300A continues return target retry initiator until write data delivered target, until error condition encountered. When write transaction repeated, PI7C7300A does make entry into delayed transaction queue. Section 4.9.3.1 provides detailed information about PI7C7300A responds target termination during delayed write transactions. PI7C7300A implements discard timer that starts counting when delayed write completion head delayed transaction completion queue. initial value this timer retry counter register offset 78h. initiator does repeat delayed write transaction before discard timer expires, PI7C7300A discards delayed write completion from delayed transaction completion queue. PI7C7300A also conditionally asserts P_SERR# (see Section 7.4).
4.6.4
WRITE TRANSACTION ADDRESS BOUNDARIES
PI7C7300A imposes internal address boundaries when accepting write data. aligned address boundaries used prevent PI7C7300A from continuing transaction over device address boundary provide upper limit maximum latency. PI7C7300A returns target disconnect initiator when reaches aligned address boundaries under conditions shown Table 4-3.
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Table WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES
Type Transaction Delayed Write Posted Memory Write Posted Memory Write Posted Memory Write Invalidate Posted Memory Write Invalidate Condition Memory write disconnect control 0(1) Memory write disconnect control 1(1) Cache line size Cache line size Aligned Address Boundary Disconnects after data transfer aligned address boundary Disconnects cache line boundary aligned address boundary
Cache line boundary posted memory write data FIFO does have enough space cache line Note Memory write disconnect control chip control register offset configuration space.
4.6.5
BUFFERING MULTIPLE WRITE TRANSACTIONS
PI7C7300A continues accept posted memory write transactions long space least DWORD data posted write data buffer remains. posted write data buffer fills before initiator terminates write transaction, PI7C7300A returns target disconnect initiator. Delayed write transactions posted long least open entry delayed transaction queue exists. Therefore, several posted delayed write transactions exist data buffers same time. Chapter information about multiple posted delayed write transactions ordered.
4.6.6
FAST BACK-TO-BACK WRITE TRANSACTIONS
PI7C7300A recognize post fast back-to-back write transactions. When PI7C7300A cannot accept second transaction because buffer space limitations, returns target retry initiator. fast back-to-back enable must command register upstream write transactions, bridge control register downstream write transactions.
READ TRANSACTIONS
Delayed read forwarding used read transactions crossing PI7C7300A. Delayed read transactions treated either prefetchable non-prefetchable. Table shows read behavior, prefetchable non-prefetchable, each type read operation.
4.7.1
PREFETCHABLE READ TRANSACTIONS
prefetchable read transaction read transaction where PI7C7300A performs speculative DWORD reads, transferring data from target before requested from initiator. This behavior allows prefetchable read transaction consist multiple data transfers. However, byte enable bits cannot forwarded data phases done single data phase non-prefetchable read transaction. prefetchable read transactions, PI7C7300A forces byte enable bits turned data phases. Page 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Prefetchable behavior used memory read line memory read multiple transactions, well memory read transactions that fall into prefetchable memory space. amount data that pre-fetched depends type transaction. amount pre-fetching also affected amount free buffer space available PI7C7300A, read address boundaries encountered. Pre-fetching should used those read transactions that have side effects target device, that control status registers, FIFOs, target device's base address register registers indicate memory address region prefetchable.
4.7.2
NON-PREFETCHABLE READ TRANSACTIONS
non-prefetchable read transaction read transaction where PI7C7300A requests only DWORD from target disconnects initiator after delivery first DWORD read data. Unlike prefetchable read transactions, PI7C7300A forwards read byte enable information data phase. Non-prefetchable behavior used configuration read transactions, well memory read transactions that fall into non-prefetchable memory space. extra read transactions could have side effects, example, when accessing FIFO, non-prefetchable read transactions those locations. Accordingly, important retain value byte enable bits during data phase, non-prefetchable read transactions. these locations mapped memory space, memory read command target into non-prefetchable (memory-mapped I/O) memory space non-prefetching behavior.
4.7.3
READ PREFETCH ADDRESS BOUNDARIES
PI7C7300A imposes internal read address boundaries read pre-fetched data. When read transaction reaches these aligned address boundaries, PI7C7300A stops pre-fetched data, unless target signals target disconnect before read pre-fetched boundary reached. When PI7C7300A finishes transferring this read data initiator, returns target disconnect with last data transfer, unless initiator completes transaction before pre-fetched read data delivered. leftover prefetched data discarded. Prefetchable read transactions flow-through mode pre-fetch nearest aligned address boundary, until initiator de-asserts FRAME#. Section 4.7.6 describes flowthrough mode during read operations. Table shows read pre-fetch address boundaries read transactions during nonflow-through mode. Table READ PREFETCH ADDRESS BOUNDARIES
Type Transaction Configuration Read Read Memory Read Address Space Non-Prefetchable Cache (CLS) Line Size Prefetch Aligned Address Boundary DWORD prefetch) DWORD prefetch) DWORD prefetch)
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Memory Read Memory Read Memory Read Line Memory Read Line Memory Read Multiple Prefetchable Prefetchable 16-DWORD aligned address boundary Cache line address boundary 16-DWORD aligned address boundary Cache line boundary 32-DWORD aligned address boundary cache line boundary
Memory Read Multiple does matter prefetchable non-prefetchable don't care
Table READ TRANSACTION PREFETCHING
Read Behavior Prefetching never allowed Prefetching never allowed Downstream: Prefetching used address prefetchable space Memory Read Upstream: Prefetching used programmable Memory Read Line Prefetching always used Memory Read Multiple Prefetching always used Section detailed information about prefetchable non-prefetchable address spaces. Type Transaction Read Configuration Read
4.7.4
DELAYED READ REQUESTS
PI7C7300A treats read transactions delayed read transactions, which means that read request from initiator posted into delayed transaction queue. Read data from target placed read data queue directed toward initiator interface transferred initiator when initiator repeats read transaction. When PI7C7300A accepts delayed read request, first samples read address, read command, address parity. When IRDY# asserted, PI7C7300A then samples byte enable bits first data phase. This information entered into delayed transaction queue. PI7C7300A terminates transaction signaling target retry initiator. Upon reception target retry, initiator required continue repeat same read transaction until least data transfer completed, until target response (target abort master abort) other than target retry received.
4.7.5
DELAYED READ COMPLETION WITH TARGET
When delayed read request reaches head delayed transaction queue, PI7C7300A arbitrates target initiates read transaction only previously queued posted write transactions have been delivered. PI7C7300A uses exact read address read command captured from initiator during initial delayed read request initiate read transaction. read transaction nonprefetchable read, PI7C7300A drives captured byte enable bits during next cycle. transaction prefetchable read transaction, drives byte enable bits zero data phases. PI7C7300A receives target retry response read transaction target bus, continues repeat read transaction until least data transfer completed, until error condition encountered. transaction terminated normal master termination target disconnect after least data transfer been completed, PI7C7300A does initiate further attempts read more data.
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION PI7C7300A unable obtain read data from target after (default) (maximum) attempts, PI7C7300A will report system error. number attempts programmable. PI7C7300A also asserts P_SERR# primary SERR# enable command register. Section information assertion P_SERR#. Once PI7C7300A receives DEVSEL# TRDY# from target, transfers data read opposite direction read data queue, pointing toward opposite inter-face, before terminating transaction. example, read data response downstream read transaction initiated primary placed upstream read data queue. PI7C7300A accept DWORD read data each clock cycle; that master wait states inserted. number DWORD transferred during delayed read transaction depends conditions given Table (assuming disconnect received from target).
4.7.6
DELAYED READ COMPLETION INITIATOR
When transaction been completed target bus, delayed read data head read data queue, ordering constraints with posted write transactions have been satisfied, PI7C7300A transfers data initiator when initiator repeats transaction. memory read transactions, PI7C7300A aliases memory read, memory read line, memory read multiple commands when matching command transaction command delayed transaction queue. PI7C7300A returns target disconnect along with transfer last DWORD read data initiator. PI7C7300A initiator terminates transaction before read data been transferred, remaining read data left data buffers discarded. When master repeats transaction starts transferring prefetchable read data from data buffers while read transaction target still progress before read boundary reached target bus, read transaction starts operating flow-through mode. Because data flowing through data buffers from target initiator, long read bursts then sustained. this case, read transaction allowed continue until initiator terminates trans-action, until aligned address boundary reached, until buffer fills, whichever comes first. When buffer empties, PI7C7300A reflects stalled condition initiator disconnecting initiator with data. initiator retry transaction later data needed. initiator does need more data, initiator will continue disconnected transaction. this case, PI7C7300A will start master timeout timer. remaining read data will discarded after master timeout timer expires. provide better latency, there other pending data other transactions (Read Data Buffer), remaining read data will discarded even though master timeout timer expired. PI7C7300A implements master timeout timer that starts counting when delayed read completion head delayed transaction queue, read data head read data queue. initial value this timer program-mable through configuration register. initiator does repeat read transaction before master timeout timer expires (215 default), PI7C7300A discards read transaction read data from queues. PI7C7300A also conditionally asserts P_SERR# (see Section 7.4).
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION PI7C7300A capability post multiple delayed read requests, maximum four each direction. initiator starts read transaction that matches address read command read transaction that already queued, current read command posted already contained delayed transaction queue. Section discussion delayed read transactions ordered when crossing PI7C7300A.
4.7.7
FAST BACK-TO-BACK READ TRANSACTION
PI7C7300A recognize fast back-to-back read transactions.
CONFIGURATION TRANSACTIONS
Configuration transactions used initialize system. Every device configuration space that accessed configuration commands. registers accessible configuration space only. addition accepting configuration transactions initialization configuration space, PI7C7300A also forwards configuration transactions device initialization hierarchical systems, well special cycle generation. support hierarchical systems, types configuration transactions specified: Type Type Type configuration transactions issued when intended target resides same initiator. Type configuration transaction identified configuration command lowest bits address 00b. Type configuration transactions issued when intended target resides another bus, when special cycle generated another bus. Type configuration command identified configuration command lowest address bits 01b. register number found both Type Type formats gives DWORD address configuration register accessed. function number also included both Type Type formats indicates which function multifunction device accessed. single-function devices, this value decoded. addresses Type configuration transaction include 5-bit field designating device number that identifies device target that accessed. addition, number Type transactions specifies which transaction targeted.
4.8.1
TYPE ACCESS PI7C7300A
configuration space accessed Type configuration transaction primary interface. configuration space cannot accessed from secondary bus. PI7C7300A responds Type configuration transaction asserting P_DEVSEL# when following conditions during address phase: Page 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION command configuration read configuration write transaction. Lowest address bits P_AD[1:0] must 00b. Signal P_IDSEL must asserted.
Function code either configuration space configuration space PI7C7300A multi-function device. PI7C7300A limits configuration access single DWORD data transfer returns target-disconnect with first data transfer additional data phases requested. Because read transactions configuration space have side effects, bytes requested DWORD returned, regardless value byte enable bits. Type configuration write read transactions data buffers; that these transactions completed immediately, regardless state data buffers. PI7C7300A ignores Type transactions initiated secondary interface.
4.8.2
TYPE TYPE CONVERSION
Type configuration transactions used specifically device configuration hierarchical system. PCI-to-PCI bridge only type device that should respond Type configuration command. Type configuration commands used when configuration access intended device that resides other than where Type transaction generated. PI7C7300A performs Type Type translation when Type transaction generated primary intended device attached directly secondary bus. PI7C7300A must convert configuration command Type format that secondary device respond Type Type translations performed only downstream direction; that PI7C7300A generates Type transaction only secondary bus, never primary bus. PI7C7300A responds Type configuration transaction translates into Type transaction secondary when following conditions during address phase: lowest address bits P_AD[1:0] 01b. number address field P_AD[23:16] equal value secondary number register configuration space. command P_CBE[3:0] configuration read configuration write transaction.
When PI7C7300A translates Type transaction Type transaction secondary interface, performs following translations address: Sets lowest address bits S1_AD[1:0] S2_AD[1:0] 00b.
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Decodes device number drives pattern specified Table S1_AD[31:16] S2_AD[31:16] purpose asserting device's IDSEL signal. Sets S1_AD[15:11] S2_AD[15:11] Leaves unchanged function number register number fields.
PI7C7300A asserts unique address line based device number. These address lines used secondary IDSEL signals. mapping address lines depends device number Type address bits P_AD[15:11]. Table presents mapping that PI7C7300A uses. Table DEVICE NUMBER IDSEL S1_AD S2_AD MAPPING
Device Number P_AD[15:11] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 11110 11111 Secondary IDSEL S1_AD[31:16] S2_AD[31:16] 0000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 Generate special cycle (P_AD[7:2] 00h) 0000 0000 0000 0000 (P_AD[7:2] 00h) S1_AD S2_AD
PI7C7300A assert unique address lines used IDSEL signals devices secondary bus, device numbers ranging from through Because electrical loading constraints bus, more than IDSEL signals should necessary. However, device numbers greater than desired, some external method generating IDSEL lines must used, upper address bits then asserted. configuration transaction still translated passed from primary secondary bus. IDSEL asserted secondary device, transaction ends master abort. PI7C7300A forwards Type Type configuration read write transactions delayed transactions. Type Type configuration read write transactions limited single 32-bit data transfer.
4.8.3
TYPE TYPE FORWARDING
Type Type transaction forwarding provides hierarchical configuration mechanism when more levels PCI-to-PCI bridges used.
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION When PI7C7300A detects Type configuration transaction intended downstream from secondary bus, PI7C7300A forwards transaction unchanged secondary bus. Ultimately, this transaction translated Type configuration command special cycle transaction downstream PCI-to-PCI bridge. Downstream Type Type forwarding occurs when following conditions during address phase: lowest address bits equal 01b. number falls range defined lower limit (exclusive) secondary number register upper limit (inclusive) subordinate number register. command configuration read write transaction.
PI7C7300A also supports Type Type forwarding configuration write transactions upstream support upstream special cycle generation. Type configuration command forwarded upstream when following conditions met: lowest address bits equal 01b. number falls outside range defined lower limit (inclusive) secondary number register upper limit (inclusive) subordinate number register. device number address bits AD[15:11] equal 11111b. function number address bits AD[10:8] equal 111b. command configuration write transaction.
PI7C7300A forwards Type Type configuration write transactions delayed transactions. Type Type configuration write transactions limited single data transfer.
4.8.4
SPECIAL CYCLES
Type configuration mechanism used generate special cycle transactions hierarchical systems. Special cycle transactions ignored acting target forwarded across bridge. Special cycle transactions generated from Type configuration write transactions either upstream down-stream direction. PI7C7300A initiates special cycle target when Type configuration write transaction being detected initiating following conditions during address phase: lowest address bits AD[1:0] equal 01b. device number address bits AD[15:11] equal 11111b. function number address bits AD[10:8] equal 111b. Page 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION register number address bits AD[7:2] equal 000000b. number equal value secondary number register configuration space downstream forwarding equal value primary number register configuration space upstream forwarding. command CBE# configuration write command.
When PI7C7300A initiates transaction target interface, command changed from configuration write special cycle. address data for-warded unchanged. Devices that special cycles ignore address decode only command. data phase contains special cycle message. transaction forwarded delayed transaction, this case target response forwarded back (because special cycles result master abort). Once transaction completed target bus, through detection master abort condition, PI7C7300A responds with TRDY# next attempt con-figuration transaction from initiator. more than data transfer requested, PI7C7300A responds with target disconnect operation during first data phase.
TRANSACTION TERMINATION
This section describes PI7C7300A returns transaction termination conditions back initiator. initiator terminate transactions with following types termination: Normal termination Normal termination occurs when initiator de-asserts FRAME# beginning last data phase, de-asserts IRDY# last data phase conjunction with either TRDY# STOP# assertion from target. Master abort master abort occurs when target response detected. When initiator does detect DEVSEL# from target within five clock cycles after asserting FRAME#, initiator terminates transaction with master abort. FRAME# still asserted, initiator de-asserts FRAME# next cycle, then de-asserts IRDY# following cycle. IRDY# must asserted same cycle which FRAME# deasserts. FRAME# already de-asserted, IRDY# de-asserted next clock cycle following detection master abort condition. target terminate transactions with following types termination: Normal termination TRDY# DEVSEL# asserted conjunction with FRAME# de-asserted IRDY# asserted. Target retry STOP# DEVSEL# asserted with TRDY# de-asserted during first data phase. data transfers occur during transaction. This transaction must repeated. Target disconnect with data transfer Page 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION STOP#, DEVSEL# TRDY# asserted. signals that this last data transfer transaction. Target disconnect without data transfer STOP# DEVSEL# asserted with TRDY# de-asserted after previous data transfers have been made. Indicates that more data transfers will made during this transaction. Target abort STOP# asserted with DEVSEL# TRDY# de-asserted. Indicates that target will never able complete this transaction. DEVSEL# must asserted least cycle during transaction before target abort signaled.
4.9.1
MASTER TERMINATION INITIATED PI7C7300A
PI7C7300A, initiator, uses normal termination DEVSEL# returned target within five clock cycles PI7C7300A's assertion FRAME# target bus. initiator, PI7C7300A terminates transaction when following conditions met: During delayed write transaction, single DWORD delivered. During non-prefetchable read transaction, single DWORD transferred from target. During prefetchable read transaction, pre-fetch boundary reached. posted write transaction, write data transaction transferred from data buffers target. burst transfer, with exception "Memory Write Invalidate" transactions, master latency timer expires PI7C7300A's grant deasserted. target terminates transaction with retry, disconnect, target abort.
PI7C7300A delivering posted write data when terminates transaction because master latency timer expires, initiates another transaction deliver remaining write data. address transaction updated reflect address current DWORD delivered. PI7C7300A pre-fetching read data when terminates transaction because master latency timer expires, does repeat transaction obtain more data.
4.9.2
MASTER ABORT RECEIVED PI7C7300A
initiator initiates transaction target does detect DEVSEL# returned target within five clock cycles assertion FRAME#, PI7C7300A terminates transaction with master abort. This sets received-master-abort status register corresponding target bus.
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION delayed read write transactions, PI7C7300A able reflect master abort condition back initiator. When PI7C7300A detects master abort response delayed transaction, when initiator repeats transaction, PI7C7300A does respond transaction with DEVSEL# which induces master abort condition back initiator. transaction then removed from delayed transaction queue. When master abort received response posted write transaction, PI7C7300A discards posted write data makes more attempts deliver data. PI7C7300A sets received-master-abort status register when master abort received primary bus, sets received master abort secondary status register when master abort received secondary interface. When master abort detected posted write transaction with both master-abort-mode (bit bridge control register) SERR# enable (bit command register secondary set, PI7C7300A asserts P_SERR# master-abort-onposted-write set. master-abort-on-posted-write P_SERR# event disable register (offset 64h). Note: When PI7C7300A performs Type special cycle conversion, master abort expected termination special cycle target bus. this case, master abort received set, Type configuration transaction disconnected after first data phase.
4.9.3
TARGET TERMINATION RECEIVED PI7C7300A
When PI7C7300A initiates transaction target target responds with DEVSEL#, target transaction with following types termination: Normal termination (upon de-assertion FRAME#) Target retry Target disconnect Target abort
PI7C7300A handles these terminations different ways, depending type transaction being performed. 4.9.3.1 DELAYED WRITE TARGET TERMINATION RESPONSE When PI7C7300A initiates delayed write transaction, type target termination received from target passed back initiator. Table shows response each type target termination that occurs during delayed write transaction. PI7C7300A repeats delayed write transaction until following conditions met: PI7C7300A completes least data transfer. PI7C7300A receives master abort. PI7C7300A receives target abort. Page 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION PI7C7300A makes (default) (maximum) write attempts resulting response target retry. Table DELAYED WRITE TARGET TERMINATION RESPONSE
Target Termination Normal Target Retry Target Disconnect Target Abort Response Returning disconnect initiator with first data transfer only multiple data phases requested. Returning target retry initiator. Continue write attempts target Returning disconnect initiator with first data transfer only multiple data phases requested. Returning target abort initiator. received target abort target interface status register. signaled target abort initiator interface status register.
After PI7C7300A makes (default) attempts same delayed write trans-action target bus, PI7C7300A asserts P_SERR# SERR# enable (bit command register secondary delayed-write-non- delivery set. delayed-write-non-delivery P_SERR# event disable register (offset 64h). PI7C7300A will report system error. Section description system error conditions. 4.9.3.2 POSTED WRITE TARGET TERMINATION RESPONSE When PI7C7300A initiates posted write transaction, target termination cannot passed back initiator. Table shows response each type target termination that occurs during posted write transaction. Table RESPONSE POSTED WRITE TARGET TERMINATION
Target Termination Normal Target Retry Target Disconnect Target Abort Repsonse additional action. Repeating write transaction target. Initiate write transaction delivering remaining posted write data. received-target-abort target interface status register. Assert P_SERR# enabled, signaled-system-error primary status register.
Note that when target retry target disconnect returned posted write data associated with that transaction remains write buffers, PI7C7300A initiates another write transaction attempt deliver rest write data. there target retry, exact same address will driven initial write trans-action attempt. target disconnect received, address that driven subsequent write transaction attempt will updated reflect address current DWORD. initial write transaction Memory-Write-and-Invalidate transaction, partial delivery write data target performed before target disconnect received, PI7C7300A will memory write command deliver rest write data. because incomplete cache line will transferred subsequent write transaction attempt. After PI7C7300A makes (default) write transaction attempts fails deliver posted write data associated with that transaction, PI7C7300A asserts P_SERR# primary SERR# enable (bit command register secondary posted-write-non-delivery set. posted-write-non-delivery P_SERR# event disable register (offset 64h). PI7C7300A will report system error. Section discussion system error conditions.
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 4.9.3.3 DELAYED READ TARGET TERMINATION RESPONSE When PI7C7300A initiates delayed read transaction, abnormal target responses passed back initiator. Other target responses depend much data initiator requests. Table shows response each type target termination that occurs during delayed read transaction. PI7C7300A repeats delayed read transaction until following conditions met: PI7C7300A completes least data transfer. PI7C7300A receives master abort. PI7C7300A receives target abort. PI7C7300A makes (default) read attempts resulting response target retry.
Table RESPONSE DELAYED READ TARGET TERMINATION
Target Termination Normal Target Retry Target Disconnect Target Abort Response prefetchable, target disconnect only initiator requests more data than read from target. non-prefetchable, target disconnect first data phase. Re-initiate read transaction target initiator requests more data than read from target, return target disconnect initiator. Return target abort initiator. received target abort target interface status register. signaled target abort initiator interface status register.
After PI7C7300A makes 224(default) attempts same delayed read transaction target bus, PI7C7300A asserts P_SERR# primary SERR# enable (bit command register secondary delayed-write-non-delivery set. delayed-write-non-delivery P_SERR# event disable register (offset 64h). PI7C7300A will report system error. Section description system error conditions.
4.9.4
TARGET TERMINATION INITIATED PI7C7300A
PI7C7300A return target retry, target disconnect, target abort initiator reasons other than detection that condition target interface.
4.9.4.1
TARGET RETRY PI7C7300A returns target retry initiator when cannot accept write data return read data result internal conditions. PI7C7300A returns target retry initiator when following conditions met: delayed write transactions: transaction being entered into delayed transaction queue. Transaction already been entered into delayed transaction queue, target response been received. Page 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Target response been received progressed head return queue. delayed transaction queue full, transaction cannot queued. transaction with same address command been queued. locked sequence being propagated across PI7C7300A, write transaction locked transaction. target locked write transaction locked transaction. more than clocks accept this transaction.
delayed read transactions: transaction being entered into delayed transaction queue. read request already been queued, read data available. Data been read from target, head read data queue posted write transaction precedes delayed transaction queue full, transaction cannot queued. delayed read request with same address command already been queued. locked sequence being propagated across PI7C7300A, read transaction locked transaction. PI7C7300A currently discarding previously pre-fetched read data. target locked write transaction locked transaction. more than clocks accept this transaction.
posted write transactions: posted write data buffer does have enough space address least DWORD write data. locked sequence being propagated across PI7C7300A, write transaction locked transaction.
When target retry returned initiator delayed transaction, initiator must repeat transaction with same address command well data write transaction, within time frame specified master timeout value. Otherwise, transaction discarded from buffers. 4.9.4.2 TARGET DISCONNECT
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION PI7C7300A returns target disconnect initiator when following conditions met: PI7C7300A hits internal address boundary. PI7C7300A cannot accept more write data. PI7C7300A more read data deliver.
Section 4.6.4 description write address boundaries, Section 4.7.3 description read address boundaries. 4.9.4.3 TARGET ABORT PI7C7300A returns target abort initiator when following conditions met: PI7C7300A returning target abort from intended target.
When PI7C7300A returns target abort initiator, sets signaled target abort status register corresponding initiator interface.
4.10
CONCURRENT MODE OPERATION
Bridge configured concurrent operation. Concurrent operation defined cycles going from device secondary another device same other secondary bus. This off-loads traffic from primary bus, allowing other traffic primary concurrently. Bridge already configured handle concurrent operation. However, devices themselves need configured Meaning, device drivers specific device used will have configured perform operation. Please section more information addressing.
ADDRESS DECODING
PI7C7300A uses three address ranges that control memory transaction forwarding. These address ranges defined base limit address registers configuration space. This chapter describes these address ranges, well ISA-mode VGA-addressing support.
ADDRESS RANGES
PI7C7300A uses following address ranges that determine which memory transactions forwarded from primary secondary bus, from secondary primary bus: Page 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 32-bit address ranges 32-bit memory-mapped (non-prefetchable memory) ranges 32-bit prefetchable memory address ranges
Transactions falling within these ranges forwarded downstream from primary secondary buses. Transactions falling outside these ranges forwarded upstream from secondary buses primary bus. address translation required PI7C7300A. addresses that marked downstream always forwarded upstream. However, address transaction initiated from located marked address range down-stream marked address range downstream bus, transaction will forwarded instead primary bus. same token, address transaction initiated from located marked address range downstream marked address range downstream bus, transaction will forwarded instead primary bus.
ADDRESS DECODING
PI7C7300A uses following mechanisms that defined configuration space specify address space downstream upstream forwarding: base limit address registers enable mode snoop
This section provides information address registers mode. Section provides information modes. enable downstream forwarding transactions, enable must command register configuration space. transactions initiated primary will ignored enable set. enable upstream forwarding transactions, master enable must command register. masterenable set, PI7C7300A ignores memory transactions initiated secondary bus. master-enable also allows upstream forwarding memory transactions set. CAUTION configuration state affecting transaction forwarding changed configuration write operation primary same time that transactions ongoing secondary bus, PI7C7300A response secondary transactions predictable. Configure base limit address registers, enable bit, mode bit, snoop before setting enable Page 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION master enable bits, change them subsequently only when primary secondary buses idle.
5.2.1
BASE LIMIT ADDRESS REGISTER
PI7C7300A implements base limit address registers configuration space that define address range port downstream forwarding. PI7C7300A supports 32-bit addressing, which allows addresses downstream PI7C7300A mapped anywhere address space. transactions with addresses that fall inside range defined base limit registers forwarded downstream from primary secondary bus. transactions with addresses that fall outside this range forwarded upstream from secondary primary bus. range turned setting base address value greater than that limit address. When range turned off, trans-actions forwarded upstream, transactions forwarded downstream. range minimum granularity aligned boundary. maximum range size. base register consists 8-bit field configuration address 1Ch, 16-bit field address 30h. bits 8-bit field define bits [15:12] base address. bottom bits read only indicate that PI7C7300A supports 32-bit addressing. Bits [11:0] base address assumed which naturally aligns base address boundary. bits contained base upper bits register configuration offset define AD[31:16] base address. bits read/write. After primary reset chip reset, value base address initialized 0000 0000h. limit register consists 8-bit field configuration offset 16-bit field offset 32h. bits 8-bit field define bits [15:12] limit address. bottom bits read only indicate that 32-bit addressing supported. Bits [11:0] limit address assumed FFFh, which naturally aligns limit address address block. bits contained limit upper bits register configuration offset define AD[31:16] limit address. bits read/write. After primary reset chip reset, value limit address reset 0000 0FFFh. Note: initial states base limit address registers define range 0000 0000h 0000 0FFFh, which bottom space. Write these registers with their appropriate values before setting either enable master enable command register configuration space.
5.2.2
MODE
PI7C7300A supports mode providing enable bridge control register configuration space. mode modifies response PI7C7300A inside address range order support mapping space presence system. This only affects response PI7C7300A when transaction falls inside address range defined base limit address registers, only Page 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION when this address also falls inside first 64KB space (address bits [31:16] 0000h). When enable set, PI7C7300A does forward downstream transactions addressing bytes each aligned block. Only those transactions addressing bottom bytes aligned block inside base limit address range forwarded downstream. Transactions above 64KB address boundary forwarded defined address range defined base limit registers. Accordingly, enable set, PI7C7300A forwards upstream those transactions addressing bytes each aligned block within first 64KB space. master enable command configuration register must also enable upstream forwarding. other transactions initiated secondary forwarded upstream only they fall outside address range. When enable set, devices downstream PI7C7300A have space mapped into first bytes each chunk below 64KB boundary, anywhere space above 64KB boundary.
MEMORY ADDRESS DECODING
PI7C7300A three mechanisms defining memory address ranges forwarding memory transactions: Memory-mapped base limit address registers Prefetchable memory base limit address registers mode
This section describes first mechanisms. Section 5.4.1 describes mode. enable downstream forwarding memory transactions, memory enable must command register configuration space. enable upstream forwarding memory transactions, master-enable must command register. master-enable also allows upstream forwarding transactions set. CAUTION configuration state affecting memory transaction forwarding changed configuration write operation primary same time that memory transactions ongoing secondary bus, response secondary memory transactions predictable. Configure memory-mapped base limit address registers, prefetchable memory base limit address registers, mode before setting memory enable master enable bits, change them subsequently only when primary secondary buses idle.
5.3.1
MEMORY-MAPPED BASE LIMIT ADDRESS REGISTERS
Memory-mapped also referred non-prefetchable memory. Memory addresses that cannot automatically pre-fetched that conditionally prefetched based command type should mapped into this space. Read trans-actions nonprefetchable space exhibit side effects; this space have non-memory-like behavior. PI7C7300A prefetches this space only memory read line memory Page 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION read multiple commands used; transactions using memory read command limited single data transfer. memory-mapped base address memory-mapped limit address registers define address range that PI7C7300A uses determine when forward memory commands. PI7C7300A forwards memory transaction from primary secondary interface transaction address falls within memory-mapped address range. PI7C7300A ignores memory transactions initiated secondary interface that fall into this address range. transactions that fall outside this address range ignored primary interface forwarded upstream from secondary interface (provided that they fall into prefetchable memory range forwarded downstream mechanism). memory-mapped range supports 32-bit addressing only. PCI-to-PCI Bridge Architecture Specification does provide 64-bit addressing memory-mapped space. memory-mapped address range granularity alignment 1MB. maximum memory-mapped address range 4GB. memory-mapped address range defined 16-bit memory-mapped base address register configuration offset 16-bit memory-mapped limit address register offset 22h. bits each these registers correspond bits [31:20] memory address. bits hardwired lowest bits memory-mapped base address assumed 0000h, which results natural alignment boundary. lowest bits memory-mapped limit address assumed FFFFFh, which results alignment block. Note: initial state memory-mapped base address register 0000 0000h. initial state memory-mapped limit address register 000F FFFFh. Note that initial states these registers define memory-mapped range bottom block memory. Write these registers with their appropriate values before setting either memory enable master enable command register configuration space. turn memory-mapped address range, write memory-mapped base address register with value greater than that memory-mapped limit address register.
5.3.2
PREFETCHABLE MEMORY BASE LIMIT ADDRESS REGISTERS
Locations accessed prefetchable memory address range must have true memorylike behavior must exhibit side effects when read. This means that extra reads prefetchable memory location must have side effects. PI7C7300A pre-fetches types memory read commands this address space. prefetchable memory base address prefetchable memory limit address registers define address range that PI7C7300A uses determine when for- ward memory commands. PI7C7300A forwards memory transaction from primary secondary interface transaction address falls within prefetchable memory address range. PI7C7300A ignores memory transactions initiated secondary Page 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION interface that fall into this address range. PI7C7300A does respond transactions that fall outside this address range primary interface forwards those transactions upstream from secondary interface (provided that they fall into memory-mapped range forwarded mechanism). prefetchable memory range supports 64-bit addressing provides additional registers define upper bits memory address range, prefetchable memory base address upper bits register, prefetchable memory limit address upper bits register. address comparison, single address cycle (32-bit address) prefetchable memory transaction treated like 64-bit address transaction where upper bits address equal This upper 32-bit value compared prefetchable memory base address upper bits register prefetchable memory limit address upper bits register. prefetchable memory base address upper bits register must pass single address cycle transactions downstream. Prefetchable memory address range granularity alignment 1MB. Maximum memory address range when 32-bit addressing being used. Prefetchable memory address range defined 16-bit prefetchable memory base address register configuration offset 16-bit prefetchable memory limit address register offset 26h. bits each these registers correspond bits [31:20] memory address. lowest bits hardwired lowest bits prefetchable memory base address assumed 0000h, which results natural alignment boundary. lowest bits prefetchable memory limit address assumed FFFFFh, which results alignment block. Note: initial state prefetchable memory base address register 0000 0000h. initial state prefetchable memory limit address register 000F FFFFh. Note that initial states these registers define prefetchable memory range bottom block memory. Write these registers with their appropriate values before setting either memory enable master enable command register configuration space. turn prefetchable memory address range, write prefetchable memory base address register with value greater than that prefetchable memory limit address register. entire base value must greater than entire limit value, meaning that upper bits must considered. Therefore, disable address range, upper bits registers both same value, while lower base register greater than lower limit register. Otherwise, upper 32-bit base must greater than upper 32-bit limit.
SUPPORT
PI7C7300A provides modes support: mode, supporting VGA-compatible addressing snoop mode, supporting palette forwarding
5.4.1
MODE
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION When VGA-compatible device exists downstream from PI7C7300A, mode bridge control register configuration space enable mode. When PI7C7300A operating mode, forwards downstream those transactions addressing frame buffer memory registers, regardless values base limit address registers. PI7C7300A ignores transactions initiated secondary interface addressing these locations. frame buffer consists following memory address range: 000A 0000h-000B FFFFh Read transactions frame buffer memory treated non-prefetchable. PI7C7300A requests only single data transfer from target, read byte enable bits forwarded target bus. addresses range 3B0h-3BBh 3C0h-3DFh I/O. These addresses aliases every throughout first 64KB space. This means that address bits <15:10> decoded value, while address bits [31:16] must BIOS addresses starting C0000h decoded mode.
5.4.2
SNOOP MODE
PI7C7300A provides snoop mode, allowing palette write transactions forwarded downstream. This mode used when graphics device downstream from PI7C7300A needs snoop respond palette write transactions. enable mode, snoop command register configuration space. Note that PI7C7300A claims palette write transactions asserting DEVSEL# snoop mode. When snoop set, PI7C7300A forwards downstream transactions within 3C6h, 3C8h 3C9h addresses space. Note that these addresses also forwarded part compatibility mode previously described. Again, address bits <15:10> decoded, while address bits <31:16> must equal which means that these addresses aliases every throughout first 64KB space. Note: both mode snoop set, PI7C7300A behaves same only mode were set.
TRANSACTION ORDERING
maintain data coherency consistency, PI7C7300A complies with ordering rules forth Local Specification, Revision 2.2, transactions crossing bridge. This chapter describes ordering rules that control transaction forwarding across PI7C7300A.
TRANSACTIONS GOVERNED ORDERING RULES
Ordering relationships established following classes transactions crossing PI7C7300A:
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Posted write transactions, comprised memory write memory write invalidate transactions. Posted write transactions complete source before they complete destination; that data written into intermediate data buffers before reaches target. Delayed write request transactions, comprised write configuration write transactions. Delayed write requests terminated target retry initiator queued delayed transaction queue. delayed write transaction must complete target before completes initiator bus. Delayed write completion transactions, comprised write configuration write transactions. Delayed write completion transactions complete target bus, target response queued buffers. delayed write completion transaction proceeds direction opposite that original delayed write request; that delayed write completion transaction proceeds from target initiator bus. Delayed read request transactions, comprised memory read, read, configuration read transactions. Delayed read requests terminated target retry initiator queued delayed transaction queue. Delayed read completion transactions, comprised memory read, read, configuration read transactions. Delayed read completion transactions complete target bus, read data queued read data buffers. delayed read completion transaction proceeds direction opposite that original delayed read request; that delayed read completion transaction proceeds from target initiator bus. PI7C7300A does combine merge write transactions: PI7C7300A does combine separate write transactions into single write transaction-this optimization best implemented originating master. PI7C7300A does merge bytes separate masked write transactions same DWORD address-this optimization also best implemented originating master. PI7C7300A does collapse sequential write transactions same address into single write transaction-the Local Specification does permit this combining transactions.
GENERAL ORDERING GUIDELINES
Independent transactions primary secondary buses have relationship only when those transactions cross PI7C7300A. following general ordering guidelines govern transactions crossing PI7C7300A:
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION ordering relationship transaction with respect other transactions determined when transaction completes, that when transaction ends with termination other than target retry. Requests terminated with target retry accepted completed order with respect other transactions that have been terminated with target retry. order completion delayed requests important, initiator should start second delayed transaction until first been completed. more than delayed transaction initiated, initiator should repeat delayed transaction requests, using some fairness algorithm. Repeating delayed transaction cannot contingent completion another delayed transaction. Otherwise, deadlock occur. Write transactions flowing direction have ordering requirements with respect write transactions flowing other direction. PI7C7300A accept posted write transactions both interfaces same time, well initiate posted write transactions both interfaces same time. acceptance posted memory write transaction target never contingent completion non-locked, non-posted transaction master. This true PI7C7300A must also true other agents. Otherwise, deadlock occur. PI7C7300A accepts posted write transactions, regardless state completion delayed transactions being forwarded across PI7C7300A.
ORDERING RULES
Table shows ordering relationships transactions refers number ordering rules that follow. Table SUMMARY TRANSACTION ORDERING
Pass Posted Write Delayed Read Request Delayed Write Request Delayed Read Completion Delayed Write Completion Posted Write Delayed Read Request Yes5 Delayed Write Request Yes5 Delayed Read Completion Yes5 Delayed Write Completion Yes5
Note: superscript accompanying some table entries refers applicable ordering rule listed this section. Many entries governed these ordering rules; therefore, implementation choose whether transactions pass each other. entries without superscripts reflect PI7C7300A's implementation choices. following ordering rules describe transaction relationships. Each ordering rule followed explanation, ordering rules referred number Table 6-1. These ordering rules apply posted write transactions, delayed write read requests, delayed write read completion transactions crossing PI7C7300A
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION same direction. Note that delayed completion transactions cross PI7C7300A direction opposite that corresponding delayed requests. Posted write transactions must complete target order which they were received initiator bus. subsequent posted write transaction setting flag that covers data first posted write transaction; second transaction were complete before first transaction, device checking flag could subsequently consume stale data. delayed read request traveling same direction previously queued posted write transaction must push posted write data ahead posted write transaction must complete target before delayed read request attempted target bus. read transaction same location write data, read transaction were pass write transaction, would return stale data. delayed read completion must ``pull'' ahead previously queued posted write data traveling same direction. this case, read data traveling same direction write data, initiator read transaction same side PI7C7300A target write transaction. posted write transaction must complete target before read data returned initiator. read transaction reading status register initiator posted write data therefore should complete until write transaction complete. Delayed write requests cannot pass previously queued posted write data. posted memory write transactions, delayed write transaction flag that covers data posted write transaction. delayed write request were complete before earlier posted write transaction, device checking flag could subsequently consume stale data. Posted write transactions must given opportunities pass delayed read write requests completions. Otherwise, deadlocks occur when some bridges which support delayed transactions other bridges which support delayed transactions being used same system. fairness algorithm used arbitrate between posted write queue delayed transaction queue.
DATA SYNCHRONIZATION
Data synchronization refers relationship between interrupt signaling data delivery. Local Specification, Revision 2.2, provides following alternative methods synchronizing data interrupts: device signaling interrupt performs read data just written (software). device driver performs read operation register interrupting device before accessing data written device (software).
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION System hardware guarantees that write buffers flushed before interrupts forwarded.
PI7C7300A does have hardware mechanism guarantee data synchronization posted write transactions. Therefore, posted write transactions must followed read operation, either from device location just written some other location along same path), from device driver device registers.
ERROR HANDLING
PI7C7300A checks, forwards, generates parity both primary secondary interfaces. maintain transparency, PI7C7300A always tries forward existing parity condition other bus, along with address data. PI7C100 always attempts transparent when reporting errors, this always possible, given presence posted data delayed transactions. support error reporting bus, PI7C7300A implements following: PERR# SERR# signals both primary secondary interfaces Primary status secondary status registers device-specific P_SERR# event disable register
This chapter provides detailed information about PI7C7300A handles errors. also describes error status reporting error operation disabling.
ADDRESS PARITY ERRORS
PI7C7300A checks address parity transactions both buses, address commands. When PI7C7300A detects address parity error primary interface, following events occur: parity error response command register, PI7C7300A does claim transaction with P_DEVSEL#; this allow transaction terminate master abort. parity error response set, PI7C7300A proceeds normally accepts transaction directed across PI7C7300A. PI7C7300A sets detected parity error status register. PI7C7300A asserts P_SERR# sets signaled system error status register, both following conditions met: SERR# enable command register. parity error response command register.
When PI7C7300A detects address parity error secondary interface, following events occur:
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION parity error response bridge control register, PI7C7300A does claim transaction with S1_DEVSEL# S2_DEVSEL#; this allow transaction terminate master abort. parity error response set, PI7C7300A proceeds normally accepts transaction directed across PI7C7300A. PI7C7300A sets detected parity error secondary status register. PI7C7300A asserts P_SERR# sets signaled system error status register, both following conditions met: SERR# enable command register. parity error response bridge control register.
DATA PARITY ERRORS
When forwarding transactions, PI7C7300A attempts pass data parity condition from interface other unchanged, whenever possible, allow master target devices handle error condition. following sections describe, each type transaction, sequence events that occurs when parity error detected which parity condition forwarded across PI7C7300A.
7.2.1
CONFIGURATION WRITE TRANSACTIONS CONFIGURATION SPACE
When PI7C7300A detects data parity error during Type configuration write transaction PI7C7300A configuration space, following events occur: parity error response command register, PI7C7300A asserts P_TRDY# writes data configuration register. PI7C7300A also asserts P_PERR#. parity error response set, PI7C7300A does assert P_PERR#. PI7C7300A sets detected parity error status register, regardless state parity error response bit.
7.2.2
READ TRANSACTIONS
When PI7C7300A detects parity error during read transaction, target drives data data parity, initiator checks parity conditionally asserts PERR#. downstream transactions, when PI7C7300A detects read data parity error secondary bus, following events occur: PI7C7300A asserts S_PERR# cycles following data transfer, secondary interface parity error response bridge control register. PI7C7300A sets detected parity error secondary status register. Page 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION PI7C7300A sets data parity detected secondary status register, secondary interface parity error response bridge control register. PI7C7300A forwards parity with data back initiator primary bus. data with parity pre-fetched read initiator primary bus, data discarded data with parity returned initiator. PI7C7300A completes transaction normally.
upstream transactions, when PI7C7300A detects read data parity error primary bus, following events occur: PI7C7300A asserts P_PERR# cycles following data transfer, primary interface parity error response command register. PI7C7300A sets detected parity error primary status register. PI7C7300A sets data parity detected primary status register, primary interface parity-error-response command register. PI7C7300A forwards parity with data back initiator secondary bus. data with parity pre-fetched read initiator secondary bus, data discarded data with parity returned initiator. PI7C7300A completes transaction normally.
PI7C7300A returns initiator data parity that received from target. When initiator detects parity error this read data enabled report initiator asserts PERR# cycles after data transfer occurs. assumed that initiator takes responsibility handling parity error condition; therefore, when PI7C7300A detects PERR# asserted while returning read data initiator, PI7C7300A does take further action completes transaction normally.
7.2.3
DELAYED WRITE TRANSACTIONS
When PI7C7300A detects data parity error during delayed write transaction, initiator drives data data parity, target checks parity conditionally asserts PERR#. delayed write transactions, parity error occur following times: During original delayed write request transaction When initiator repeats delayed write request transaction When PI7C7300A completes delayed write transaction target
When delayed write transaction normally queued, address, command, address parity, data, byte enable bits, data parity captured target retry returned Page 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION initiator. When PI7C7300A detects parity error write data initial delayed write request transaction, following events occur: parity-error-response corresponding initiator set, PI7C7300A asserts TRDY# initiator transaction queued. multiple data phases requested, STOP# also asserted cause target disconnect. cycles after data transfer, PI7C7300A also asserts PERR#. parity-error-response set, PI7C7300A returns target retry. queues transaction usual. PI7C7300A does assert PERR#. this case, initiator repeats transaction. PI7C7300A sets detected-parity-error status register corresponding initiator bus, regardless state parity-error-response bit.
Note: parity checking turned data parity errors have occurred queued subsequent delayed write transactions initiator bus, possible that initiator's re-attempts write transaction match original queued delayed write information contained delayed transaction queue. this case, master timeout condition occur, possibly resulting system error (P_SERR# assertion). downstream transactions, when PI7C7300A delivering data target secondary S_PERR# asserted target, following events occur: PI7C7300A sets secondary interface data parity detected secondary status register, secondary parity error response bridge control register. PI7C7300A captures parity error condition forward back initiator primary bus.
Similarly, upstream transactions, when PI7C7300A delivering data target primary P_PERR# asserted target, following events occur: PI7C7300A sets primary interface data-parity-detected status register, primary parity-error-response command register. PI7C7300A captures parity error condition forward back initiator secondary bus.
delayed write transaction completed initiator when initiator repeats write transaction with same address, command, data, byte enable bits delayed write command that head posted data queue. Note that parity compared when determining whether transaction matches those delayed transaction queues. cases must considered: When parity error detected initiator subsequent re-attempt transaction detected target When parity error forwarded back from target
Page 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION downstream delayed write transactions, when parity error detected initiator PI7C7300A write status return, following events occur: PI7C7300A first asserts P_TRDY# then asserts P_PERR# cycles later, primary interface parity-error-response command register. PI7C7300A sets primary interface parity-error-detected status register. Because there exact data parity match, write status returned transaction remains queue.
Similarly, upstream delayed write transactions, when parity error detected initiator PI7C7300A write status return, following events occur: PI7C7300A first asserts S1_TRDY# S2_TRDY# then asserts S_PERR# cycles later, secondary interface parity-error-response bridge control register (offset 3Ch). PI7C7300A sets secondary interface parity-error-detected secondary status register. Because there exact data parity match, write status returned transaction remains queue.
downstream transactions, where parity error being passed back from target parity error condition originally detected initiator bus, following events occur: PI7C7300A asserts P_PERR# cycles after data transfer, following both true: parity-error-response command register primary interface. parity-error-response bridge control register secondary interface.
PI7C7300A completes transaction normally.
upstream transactions, when parity error being passed back from target parity error condition originally detected initiator bus, following events occur: PI7C7300A asserts S_PERR# cycles after data transfer, following both true: parity error response command register primary interface. parity error response bridge control register secondary interface.
PI7C7300A completes transaction normally.
Page 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
7.2.4
POSTED WRITE TRANSACTIONS
During downstream posted write transactions, when PI7C7300A responds target, detects data parity error initiator (primary) following events occur: PI7C7300A asserts P_PERR# cycles after data transfer, parity error response command register primary interface. PI7C7300A sets parity error detected status register primary interface. PI7C7300A captures forwards parity condition secondary bus. PI7C7300A completes transaction normally.
Similarly, during upstream posted write transactions, when PI7C7300A responds target, detects data parity error initiator (secondary) bus, following events occur: PI7C7300A asserts S_PERR# cycles after data transfer, parity error response bridge control register secondary interface. PI7C7300A sets parity error detected status register secondary interface. PI7C7300A captures forwards parity condition primary bus. PI7C7300A completes transaction normally.
During downstream write transactions, when data parity error reported target (secondary) target's assertion S_PERR#, following events occur: PI7C7300A sets data parity detected status register secondary interface, parity error response bridge control register secondary interface. PI7C7300A asserts P_SERR# sets signaled system error status register, following conditions met: SERR# enable command register. posted write parity error P_SERR# event disable register set. parity error response bridge control register secondary interface. parity error response command register primary interface. PI7C7300A detected parity error primary (initiator) which parity error forwarded from primary secondary bus.
Page 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION During upstream write transactions, when data parity error reported target (primary) target's assertion P_PERR#, following events occur: PI7C7300A sets data parity detected status register, parity error response command register primary interface. PI7C7300A asserts P_SERR# sets signaled system error status register, following conditions met: SERR# enable command register. parity error response bridge control register secondary interface. parity error response command register primary interface. PI7C7300A detected parity error secondary (initiator) which parity error forwarded from secondary primary bus.
Assertion P_SERR# used signal parity error condition when initiator does know that error occurred. Because data already been delivered with errors, there other signal this information back initiator. parity error forwarded from initiating target bus, P_SERR# will asserted.
DATA PARITY ERROR REPORTING SUMMARY
previous sections, responses PI7C7300A data parity errors presented according type transaction progress. This section organizes responses PI7C7300A data parity errors according status bits that PI7C7300A sets signals that asserts. Table shows setting detected parity error status register, corresponding primary interface. This when PI7C7300A detects parity error primary interface. Table SETTING PRIMARY INTERFACE DETECTED PARITY ERROR
Primary Detected Parity Error Transaction Type Direction Where Error Detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Primary/ Secondary Parity Error Response Bits
Read Read Read Read Posted Write Posted Write Posted Write Posted Write Delayed Write Delayed Write Delayed Write
Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Downstream Downstream Upstream
Page 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Primary Detected Parity Error don't care Transaction Type Direction Where Error Detected Secondary Primary/ Secondary Parity Error Response Bits
Delayed Write
Upstream
Table shows setting detected parity error secondary status register, corresponding secondary interface. This when PI7C7300A detects parity error secondary interface. Table SETTING SECONDARY INTERFACE DETECTED PARITY ERROR
Secondary Detected Parity Error don't care Transaction Type Direction Where Error Detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary/ Secondary Parity Error Response Bits
Read Read Read Read Posted Write Posted Write Posted Write Posted Write Delayed Write Delayed Write Delayed Write Delayed Write
Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream
Table shows setting data parity detected primary interface's status register. This under following conditions: PI7C7300A must master primary bus. parity error response command register, corresponding primary interface, must set. P_PERR# signal detected asserted parity error detected primary bus.
Table SETTING PRIMARY INTERFACE DATA PARITY ERROR DETECTED
Primary Data Parity don't care Transaction Type Direction Where Error Detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Parity Error Response Bits
Read Read Read Read Posted Write Posted Write Posted Write Posted Write Delayed Write Delayed Write Delayed Write Delayed Write
Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream
Page 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Table shows setting data parity detected status register secondary interface. This under following conditions: PI7C7300A must master secondary bus. parity error response must bridge control register secondary interface. S_PERR# signal detected asserted parity error detected secondary bus.
Table SETTING SECONDARY INTERFACE DATA PARITY ERROR DETECTED
Secondary Detected Parity Detected don't care Transaction Type Direction Where Error Detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Parity Error Response Bits
Read Read Read Read Posted Write Posted Write Posted Write Posted Write Delayed Write Delayed Write Delayed Write Delayed Write
Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream
Table shows assertion P_PERR#. This signal under following conditions: PI7C7300A either target write transaction initiator read transaction primary bus. parity-error-response must command register primary interface. PI7C7300A detects data parity e

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