16-/8-BIT SINGLE-CHIP MICROCONTROLLERS DESCRIPTION µPD784038
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INTEGRATED CIRCUIT
16-/8-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
µPD784038Y based µPD784038 with control function added, ideal audio-visual applications. One-time PROM EPROM versions, such µPD78P4038Y, that operate same voltage range mask versions, various development tools provided. functions explained detail following User's Manual. sure read this manual when designing your system.
µPD784038, 784038Y Subseries User's Manual Hardware: U11316E
78K/IV Series User's Manual Instruction: U10905E
FEATURES
78K/IV Series Pin-compatible with µPD78234 Subseries, Timer/counter 16-bit timer/counter units 16-bit timer unit output: outputs Standby function HALT/STOP/IDLE mode Clock division function Watchdog timer: channel Clock output function Selectable from fCLK, fCLK/2, CLK/4, fCLK/8, fCLK/16 converter: 8-bit resolution channels converter: 8-bit resolution channels Supply voltage:
µPD784026 Subseries, µPD784038
Subseries Higher internal memory capacity than µPD78234 Subseries µPD784026 Subseries Minimum instruction execution time: 32-MHz operation) ports: Serial interface: channels UART/IOE (3-wire serial I/O): channels (3-wire serial I/O, 2-wire serial I/O, bus): channel
APPLICATION FIELDS
Cellular phones, cordless phones, audio-visual systems, etc. Unless contextually excluded, references this document µPD784038Y mean µPD784035Y, µPD784036Y, µPD784037Y.
information this document subject change without notice.
Document U10741EJ1V0DS00 (1st edition) Date Published July 1997 Printed Japan
mark shows major revised points.
1996
µPD784035Y, 784036Y, 784037Y, 784038Y
ORDERING INFORMATION
Part Number Package Internal (Bytes) Internal (Bytes)
Note Under development
80-pin plastic 2.7-mm thick) 80-pin plastic 1.4-mm thick) 80-pin plastic 2.7-mm thick) 80-pin plastic 1.4-mm thick) 80-pin plastic 2.7-mm thick) 80-pin plastic 1.4-mm thick) 80-pin plastic TQFP (fine pitch) 80-pin plastic 2.7-mm thick) 80-pin plastic 1.4-mm thick) 80-pin plastic TQFP (fine pitch)
2048 2048 2048 2048 2048 2048 3584 3584 3584 4352 4352 4352
80-pin plastic TQFP (fine pitch)
80-pin plastic TQFP (fine pitch)
Remark indicates code suffix.
µPD784035Y, 784036Y, 784037Y, 784038Y
78K/IV Series Product Development
Under mass production Under development supported Multi-master supported
PD784038Y PD784038
PD784225Y PD784225
80-pin, collection added Multi-master supported
Standard models
PD784026
A/D, 16-bit timer, enhanced power management
Enhanced internal memory capacity Pin-compatible with PD784026 Multi-master supported
PD784216Y PD784216
100-pin, enhanced internal memory capacity
µPD784218Y µPD784218
Enhanced internal memory capacity, collection added
PD784054 µPD784046
ASSP models
µPD784908
On-chip IEBuscontroller
On-chip 10-bit
PD78F4943
56-Kbyte flash memory CD-ROM Multi-master supported
PD784928Y PD784928
Enhanced functions PD784915
µPD784915
Software servo control On-chip analog circuit VCRs Enhanced timer
µPD784035Y, 784036Y, 784037Y, 784038Y
FUNCTIONS
Part Number Item Number basic instructions (mnemonics) General-purpose register Minimum instruction execution time Internal memory Memory space port Total Input Pins with ancillary functionNote Pins with pullup resistor LEDs direct drive output Transistor direct drive Real-time output port Timer/counter bits registers banks, bits registers banks (memory mapping) ns/250 ns/500 ns/1000 32-MHz operation) KBytes 2048 Bytes bits bits Timer/counter Timer register bits) Capture register Compare register Timer/counter Timer register (8/16 bits) Capture register Capture/compare register Compare register Timer/counter Timer register (8/16 bits) Capture register Capture/compare register Compare register Timer (8/16 bits) output Serial interface converter converter Clock output Watchdog timer Standby Interrupt Software source Maskable Timer register Compare register Pulse output Toggle output PWM/PPG output One-shot pulse output Pulse output Real-time output bits KBytes KBytes 3584 Bytes KBytes 4352 Bytes
µPD784035Y
µPD784036Y
µPD784037Y
µPD784038Y
MByte with program data spaces combined
Pulse output Toggle output PWM/PPG output
12-bit resolution channels UART/IOE (3-wire serial I/O) channels (on-chip baud rate generator) (3-wire serial I/O, 2-wire serial I/O, bus) channel 8-bit resolution channels 8-bit resolution channels Selectable from fCLK, fCLK/2, fCLK/4, fCLK/8, fCLK/16 (can also used 1-bit output port) channel HALT/STOP/IDLE mode Hardware source (internal: external: (variable sampling clock input: instruction, BRKCS instruction, operand error Internal: external: programmable priority levels processing styles: vectored interrupt/macro service/context switching Non-maskable Internal: external:
Supply voltage Package
80-pin plastic 2.7-mm thick) 80-pin plastic 1.4-mm thick) 80-pin plastic TQFP (fine pitch)
Note pins with ancillary function included pins.
µPD784035Y, 784036Y, 784037Y, 784038Y
CONTENTS
DIFFERENCES AMONG MODELS µPD784038Y SUBSERIES MAJOR DIFFERENCES FROM µPD784026 SUBSERIES µPD78234 SUBSERIES CONFIGURATION (TOP VIEW) BLOCK DIAGRAM FUNCTION
Port Pins Non-Port Pins Types Circuits Connections Unused Pins
ARCHITECTURE
Memory Space Registers 6.2.1 6.2.2 6.2.3 General-purpose registers Control registers Special function registers (SFRs)
PERIPHERAL HARDWARE FUNCTIONS
Ports Clock Generation Circuit Real-Time Output Port Timer/Counter Output (PWM0, PWM1) Converter Converter Serial Interface 7.8.1 7.8.2 Asynchronous serial interface/3-wire serial (UART/IOE) Clocked serial interface (CSI)
Clock Output Function
7.10 Edge Detection Function 7.11 Watchdog Timer
INTERRUPT FUNCTION
Interrupt Sources Vectored Interrupt Context Switching Macro Service Application Example Macro Service
µPD784035Y, 784036Y, 784037Y, 784038Y
LOCAL INTERFACE
Memory Expansion Memory Space Programmable Wait Pseudo Static Refresh Function Hold Function
STANDBY FUNCTION RESET FUNCTION INSTRUCTION
ELECTRICAL SPECIFICATIONS PACKAGE DRAWINGS
RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS
µPD784035Y, 784036Y, 784037Y, 784038Y
DIFFERENCES AMONG MODELS µPD784038Y SUBSERIES
only difference among µPD784035Y, 784036Y, 784037Y, 784038Y lies internal memory capacity. µPD78P4038Y provided with 128-KB one-time PROM EPROM instead mask above models. These differences summarized Table 1-1. Table 1-1. Differences among Models µPD784038Y Subseries
Part Number Item Internal available KBytes (mask ROM) KBytes (mask ROM) KBytes (mask ROM) KBytes (mask ROM) KBytes (one-time PROM EPROM) Internal Package 2048 Bytes 80-pin plastic 2.7-mm thick) 80-pin plastic 1.4-mm thick) 80-pin plastic TQFP (fine pitch) 80-pin ceramic WQFN 3584 Bytes 4352 Bytes
µPD784031Y
µPD784035Y
µPD784036Y
µPD784037Y
µPD784038Y
µPD78P4038Y
µPD784035Y, 784036Y, 784037Y, 784038Y
MAJOR DIFFERENCES FROM µPD784026 SUBSERIES µPD78234 SUBSERIES
Series Name Item Number basic instructions (mnemonics) Minimum instruction execution time 32-MHz operation) Memory space (program/data) Timer/counter MByte combined 16-bit timer/counter 8-/16-bit timer/counter 8-/16-bit timer Clock output function Watchdog timer Serial interface Provided Provided UART/IOE (3-wire serial I/O) channels (3-wire serial I/O, 2-wire serial I/O, busNote) channel Interrupt Context switching Priority Standby function Operating clock function MODE levels HALT/STOP/IDLE modes Selectable from fXX/2, fXX/4, fXX/8, None levels HALT/STOP modes Fixed Specifies ROM-less mode (always high level with Provided None UART/IOE (3-wire serial I/O) channels channel 25-MHz operation) 12-MHz operation) KBytes/1 MByte 16-bit timer/counter 8-bit timer/counter 8-bit timer None None UART channel (3-wire serial I/O, SBI)
µPD784038Y Subseries µPD784038 Subseries
µPD784026 Subseries
µPD78234 Subseries
(3-wire serial I/O, SBI) channel
µPD78233 78237)
TEST Device test Usually, level Package 80-pin plastic 2.7-mm thick) 80-pin plastic 1.4-mm thick) 80-pin plastic TQFP (fine pitch) 80-pin ceramic WQFN mm): 80-pin plastic 2.7-mm thick) 80-pin plastic TQFP (fine pitch) mm): 80-pin plastic 2.7-mm thick) 94-pin plastic 84-pin plastic (1150 1150 mil) 94-pin ceramic WQFN mm): µPD78P238 only None
µPD784021 only
80-pin ceramic WQFN mm):
µPD78P4026 only
µPD78P4038Y
78P4038 only
Note
µPD784038Y Subseries only
µPD784035Y, 784036Y, 784037Y, 784038Y
CONFIGURATION (Top View)
80-pin plastic 2.7-mm thick)
80-pin plastic 1.4-mm thick)
80-pin plastic TQFP (fine pitch)
P31/TxD/SO1 P30/RxD/SI1 P27/SI0 P26/INTP5 P25/INTP4/ASCK/SCK1 P24/INTP3 P23/INTP2/CI P22/INTP1 P21/INTP0 P20/NMI AVREF3 AVREF2 ANO1 ANO0 AVSS AVREF1 AVDD P77/ANI7 P76/ANI6 P75/ANI5
P32/SCK0/SCL P33/SO0/SDA P34/TO0 P35/TO1 P36/TO2 P37/TO3 RESET VDD1 VSS1 P67/REFRQ/HLDAK 2021 4041
P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 VDD0 P14/TxD2/SO2 P13/TxD2/SI2 P12/ASCK2/SCK2 P11/PWM1 P10/PWM0 Note TEST VSS0 ASTB/CLKOUT P40/AD0 P41/AD1 P42/AD2
Notes Under development TEST should connected VSS0 directly.
P66/WAIT/HLDRQ P65/WR P64/RD P63/A19 P62/A18 P61/A17 P60/A16 P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3
µPD784035Y, 784036Y, 784037Y, 784038Y
ANI0 ANI7 ANO0, ANO1 ASCK, ASCK2 ASTB AVDD AVSS CLKOUT HLDAK HLDRQ Address Address/Data Analog Input Analog Output Asynchronous Serial Clock Address Strobe Analog Power Supply Analog Ground Clock Input Clock Output Hold Acknowledge Hold Request Non-maskable Interrupt Port0 Port1 Port2 Port3 Port4 Port5 PWM0, PWM1 REFRQ RESET RxD, RxD2 SCK0 SCK2 TEST TxD, TxD2 VDD0 VDD1 VSS0 VSS1 WAIT Port6 Port7 Pulse Width Modulation Output Read Strobe Refresh Request Reset Receive Data Serial Clock Serial Clock Serial Data Serial Input Serial Output Test Timer Output Transmit Data Power Supply Ground Wait Write Strobe Crystal
AVREF1 AVREF3 Reference Voltage
INTP0 INTP5 Interrupt from Peripherals
µPD784035Y, 784036Y, 784037Y, 784038Y
BLOCK DIAGRAM
INTP0 INTP5 PROGRAMMABLE INTERRUPT CONTROLLER UART/IOE2 BAUD-RATE GENERATOR UART/IOE1 BAUD-RATE GENERATOR RxD/SI1 TxD/SO1 ASCK/SCK1 RxD2/SI2 TxD2/SO2 ASCK2/SCK2
INTP3
TIMER/COUNTER0 BITS)
INTP0
TIMER/COUNTER1 BITS)
CLOCKED SERIAL INTERFACE CLOCK OUTPUT 78K/IV CORE
SCK0/SCL SO0/SDA ASTB/CLKOUT WAIT/HLDRQ REFRQ/HLDAK RESET TEST VDD0, VDD1 VSS0, VSS1
INTP1 INTP2/CI
TIMER/COUNTER2 BITS)
TIMER3 BITS)
REAL-TIME OUTPUT PORT
PORT0 PORT1
PWM0 PWM1 ANO0 ANO1 AVREF2 AVREF3 ANI0 ANI7 AVDD AVREF1 AVSS INTP5
PORT2 PORT3
CONVERTER
PORT4 PORT5 PORT6
CONVERTER WATCHDOG TIMER
PORT7 SYSTEM CONTROL
Remark internal capacities differ depending model.
µPD784035Y, 784036Y, 784037Y, 784038Y
FUNCTION
Port Pins
Name Alternate function Port (P0): 8-bit port used real-time output port bits input output mode bitwise. Pins input mode connected internal pull-up resistors software. drive transistor. Input INTP0 INTP1 INTP2/CI INTP3 INTP4/ASCK/SCK1 INTP5 RxD/S1 TxD/SO1 SCK0/SCL SO0/SDA Port (P4): 8-bit port input output mode bitwise. Pins input mode connected internal pull-up resistors software. drive LEDs. Port (P5): 8-bit port input output mode bitwise. Pins input mode connected internal pull-up resistors software. drive LEDs. Port (P3): 8-bit port input output mode bitwise. Pins input mode connected internal pull-up resistors software. PWM0 PWM1 ASCK2/SCK2 RxD2/SI2 TxD2/SO2 Port (P2): 8-bit input port cannot used general-purpose port (non-maskable interrupt). However, input level checked interrupt routine. through connected internal pull-up resistors software 6-bit units. P25/INTP4/ASCK/SCK1 operate SCK1 output specified CSIM1. Port (P1): 8-bit port input output mode bitwise. Pins input mode connected internal pull-up resistors software. drive LEDs. Function
µPD784035Y, 784036Y, 784037Y, 784038Y
Name
Alternate function WAIT/HLDRQ REFRQ/HLDAK Port6 (P6): 8-bit port
Function
input output mode bitwise. Pins input mode connected internal pull-up resistors software.
AN10 AN17
Port (P7): 8-bit port input output mode bitwise.
µPD784035Y, 784036Y, 784037Y, 784038Y
Non-Port Pins
Name RxD2 TxD2 ASCK ASCK2 SCK0 SCK1 SCK2 INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 WAIT REFRQ HLDRQ HLDAK ASTB Output Output Output Output Input Output Input Output Output Input Output Input Input Output Output Input Input Alternate function P23/INTP2 P30/SI1 P13/SI2 P31/SO1 P14/SO2 P25/INTP4/SCK1 P12/SCK2 P33/SO0 P30/RxD P13/RxD2 P33/SDA P31/TxD P14/TxD2 P32/SCL P25/INTP4/ASCK P12/ASCK2 P32/SCK0 P23/CI P25/ASCK/SCK1 P66/HLDRQ P67/HLDAK P66/WAIT P67/REFRQ CLKOUT Timer output Count clock input timer/counter Serial data input (UART0) Serial data input (UART2) Serial data output (UART0) Serial data output (UART2) Baud rate clock input (UART0) Baud rate clock input (UART2) Serial data input/output (2-wire serial I/O, bus) Serial data input (3-wire serial I/O0) Serial data input (3-wire serial I/O1) Serial data input (3-wire serial I/O2) Serial data output (3-wire serial I/O0) Serial data output (3-wire serial I/O1) Serial data output (3-wire serial I/O2) Serial clock input/output (3-wire serial I/O0) Serial clock input/output (3-wire serial I/O1) Serial clock input/output (3-wire serial I/O2) Serial clock input/output (2-wire serial I/O, bus) External interrupt requests Count clock input timer/counter Capture trigger signal CR11 CR12 Count clock input timer/counter Capture trigger signal CR22 Count clock input timer/counter Capture trigger signal CR21 Count clock input timer/counter Capture trigger signal CR02 Conversion start trigger input converter Time-division address/data (for external memory connection) Higher address (for external memory connection) Higher address when address extended (for external memory connection) Read strobe external memory Write strobe external memory Wait insertion Refresh pulse output external pseudo static memory hold request input hold acknowledge output Latch timing output time-division address through (when accessing external memory) CLKOUT Output ASTB Clock output Function
µPD784035Y, 784036Y, 784037Y, 784038Y
Name RESET ANI0 ANI7 ANO0, ANO1 AVREF1 AVREF2, AVREF3 AVDD AVSS VDD0Note1 VDD1Note1 VSS0Note2 VSS1Note2 TEST
Input Input Input Output
Alternate function Chip reset
Function
Crystal connection system clock oscillation (Clock also input X1).
Analog voltage input converter Analog voltage output from converter Reference voltage converter Reference voltage converter converter power supply converter Positive power supply port block Positive power supply except port block port block except port block Directly connect VSS0 test pin).
Notes potential VDD0 must equal that VDD1 pin. potential VSS0 must equal that VSS1 pin.
µPD784035Y, 784036Y, 784037Y, 784038Y
Types Circuits Connections Unused Pins
Table shows types circuits connections unused pins. input/output circuit each type, refer Figure 5-1. Table 5-1. Types Circuits Connections Unused Pins
Name P10/PWM0 P11/PWM1 P12/ASCK2/SCK2 P13/RxD2/SI2 P14/TxD2/SO2 P20/NMI P21/INTP0 P22/INTP1 P23/INTP2/CI P24/INTP3 P25/INTP4/ASCK/SCK1 Input: Connect VDD0 Output: Open P26/INTP5 P27/SI0 P30/RxD/SI1 P31/TxD/SO1 P32/SCK0/SCL P33/SO0/SDA P34/TO0 P37/TO3 P40/AD0 P47/AD7 P50/A8 P57/A15 P60/A16 P63/A19 P64/RD P65/WR P66/WAIT/HLDRQ P67/REFRQ/HLDAK P70/ANI0 P77/ANI7 20-A Input: Connect VDD0 VSS0. Output: Open ANO0, ANO1 ASTB/CLKOUT Output Open 10-B Input: Connect VDD0. Output: Open Input Connect VDD0. Connect VDD0. Input Connect VDD0 VSS0. Circuit Type Recommended Connection Unused Pins Input: Connect VDD0 Output: Open
µPD784035Y, 784036Y, 784037Y, 784038Y
Name RESET TEST AVREF1 AVREF3 AVSS AVDD
Circuit Type
Input
Recommended Connection Unused Pins Directly connect VSS0. Connect VSS0.
Connect VDD0.
Caution Connect whose input/output mode unstable VDD0 resistor several (especially voltage reset input rises higher than low-level input level power application when mode switched between input output software). Remark Because circuit type numbers shown above table commonly used with models Series, these numbers some models serial (because some circuits provided some models).
µPD784035Y, 784036Y, 784037Y, 784038Y
Figure 5-1. Types Circuits
Type VDD0 VSS0 Type Schmitt trigger input with hysteresis characteristics Type Schmitt trigger input with hysteresis characteristics Type VDD0 data output disable VSS0 Push-pull output that into high-impedance state (with both P-ch N-ch off) Type VDD0 output disable input enable Type VSS0 VDD0 Type VDD0
pullup enable
pullup enable
VDD0 IN/OUT
data
pullup enable data
VDD0 IN/OUT Analog output voltage
output disable
VSS0
Type 10-B
VDD0
Type 20-A data
VDD0 IN/OUT
pullup enable VDD0 data
output disable IN/OUT Comparator VSS0 input enable VSS0
open drain output disable
AVSS AVREF (threshold voltage)
µPD784035Y, 784036Y, 784037Y, 784038Y
ARCHITECTURE Memory Space
memory space MByte accessed. Mapping internal data area (special function registers internal RAM) specified LOCATION instruction. LOCATION instruction must always executed after RESET cancellation, must used more than once. When LOCATION instruction executed Internal memory internal data area internal area mapped follows: Part Number Internal Data Area 0F700H-0FFFFH Internal Area 00000H-0BFFFH 00000H-0F6FFH 0F100H-0FFFFH 00000H-0F0FFH 10000H-17FFFH
µPD784035Y µPD784036Y µPD784037Y µPD784038Y
0EE00H-0FFFFH
00000H-0FDFFH 10000H-1FFFFH
Caution following areas that overlap internal data area internal cannot used when LOCATION instruction executed. Part Number Unusable Area 0F700H-0FFFFH (2304 Bytes) 0F100H-0FFFFH (3840 Bytes) 0EE00H-0FFFFH (4608 Bytes)
µPD784035Y µPD784036Y µPD784037Y µPD784038Y
External memory
external memory accessed external memory expansion mode. When LOCATION instruction executed Internal memory internal data area internal area mapped follows: Part Number Internal Data Area FF700H-FFFFFH Internal Area 00000H-0BFFFH 00000H-0FFFFH FF100H-FFFFFH FEE00H-FFFFFH 00000H-17FFFH 00000H-1FFFFH
µPD784035Y µPD784036Y µPD784037Y µPD784038Y
External memory
external memory accessed external memory expansion mode.
execution LOCATION instruction
Figure 6-1. Memory µPD784035Y
execution LOCATION instruction
Special FDFH Note FD0H
function registers (SFR) (256 Bytes)
External memory (960 KBytes)
Note
General-purpose registers (128 Bytes)
FFE8
Internal (2048 Bytes)
Special FDFH Note FD0H
function registers (SFR) (256 Bytes)
Macro service control word area Bytes) Data area (512 Bytes)
FFE3 FFE0
Internal (2048 Bytes)
Program/data area (1536 Bytes)
External memory (997120 Bytes)
Note
µPD784035Y, 784036Y, 784037Y, 784038Y
Note
External memory (14080 KBytes)
Note
Program/data area KBytes)
CALLF entry area
Note
Internal KBytes)
CALLT table area Bytes) Vector table area Bytes)
Internal KBytes)
Notes Accessed external memory expansion mode. Base area entry area reset interrupt. However, internal area used reset entry area.
Figure 6-2. Memory µPD784036Y
execution LOCATION instruction
execution LOCATION instruction
Special FDFH Note FD0H
function registers (SFR) (256 Bytes)
External memory (960 KBytes)
Note
General-purpose registers (128 Bytes)
FFE8
Internal (2048 Bytes)
Special FDFH Note FD0H
function registers (SFR) (256 Bytes)
Macro service control word area Bytes) Data area (512 Bytes)
FFE3 FFE0
µPD784035Y, 784036Y, 784037Y, 784038Y
Internal (2048 Bytes)
Program/data area (1536 Bytes)
External memory (980736 Bytes)
Note
Note
Program/data area
Note
Note
Internal (63232 Bytes)
CALLF entry area KBytes)
CALLT table area Bytes) Vector table area Bytes)
Internal KBytes)
Note
Notes Accessed external memory expansion mode. This 2304-Byte area used internal only when LOCATION instruction executed. execution LOCATION instruction: 63232 Bytes, execution LOCATION instruction: 65536 Bytes Base area entry area reset interrupt. However, internal area used reset entry area.
execution LOCATION instruction
Figure 6-3. Memory µPD784037Y
execution LOCATION instruction
Special FDFH Note FD0H
function registers (SFR) (256 Bytes)
External memory (928 KBytes)
Note
General-purpose registers (128 Bytes)
FFE8
Internal (3584 Bytes)
Internal
(32768 Bytes) Special function registers FDFH Note FD0H (256 Bytes) Internal (3584 Bytes)
(SFR)
Macro service control word area Bytes) Data area (512 Bytes)
FFE3 FFE0
Program/data area (3072 Bytes)
External memory (946432 Bytes)
Note
µPD784035Y, 784036Y, 784037Y, 784038Y
Note
Note
Program/data area
Note
Internal (61696 Bytes)
CALLF entry area KBytes)
CALLT table area Bytes) Vector table area Bytes)
Internal KBytes)
Note
Notes Accessed external memory expansion mode. This 3840-Byte area used internal only when LOCATION instruction executed. execution LOCATION instruction: 94464 Bytes, execution LOCATION instruction: 98304 Bytes Base area entry area reset interrupt. However, internal area used reset entry area.
Figure 6-4. Memory µPD784038Y
execution LOCATION instruction
execution LOCATION instruction
Special FDFH Note FD0H
function registers (SFR) (256 Bytes)
External memory (896 KBytes)
Note
General-purpose registers (128 Bytes)
FFE8
Internal (4352 Bytes)
Internal
(65536 Bytes) Special function registers FDFH Note FD0H (256 Bytes) Internal (4352 Bytes)
(SFR)
Macro service control word area Bytes) Data area (512 Bytes)
FFE3 FFE0
µPD784035Y, 784036Y, 784037Y, 784038Y
Program/data area (3840 Bytes)
External memory (912896 Bytes)
Note
Note
Note
Program/data area
Note
Internal (60928 Bytes)
CALLF entry area KBytes)
CALLT table area Bytes) Vector table area Bytes)
Internal (128 KBytes)
Note
Notes Accessed external memory expansion mode. This 4608-Byte area used internal only when LOCATION instruction executed. execution LOCATION instruction: 126464 Bytes, execution LOCATION instruction: 131072 Bytes Base area entry area reset interrupt. However, internal area used reset entry area.
µPD784035Y, 784036Y, 784037Y, 784038Y
Registers
6.2.1 General-purpose registers
Sixteen 8-bit general-purpose registers available. 8-bit registers also used pairs 16-bit register. 16-bit registers, four used combination with 8-bit register address expansion 24bit address specification registers. Eight banks these registers available which selected using software context switching function. general-purpose registers except registers address expansion mapped internal RAM. Figure 6-5. General-Purpose Register Format
(R1) (RP0) (R3) (RP1) (RG4) (RP4)
(R0) (R2)
(RP5) (RG5) (R13) (R12) (RP6) (RG6) (R15) (R14) banks (RG7) (RP7) indicate absolute name.
Parentheses
Caution Registers RP2, used registers, respectively, setting However, this function only recycling program 78K/III Series.
µPD784035Y, 784036Y, 784037Y, 784038Y
6.2.2 Control registers Program counter (PC) program counter 20-bit register whose contents automatically updated when program executed. Figure 6-6. Program Counter (PC) Format
Program status word (PSW) This register holds statuses CPU. contents automatically updated when program executed. Figure 6-7. Program Status Word (PSW) Format
PSWH PSWL
Note
RBS2
RBS1
RBS0
Note
This flag provided maintain compatibility with 78K/III Series. sure clear this flag except when software 78K/III Series used.
Stack pointer (SP) This 24-bit pointer that holds first address stack. sure write higher bits this pointer. Figure 6-8. Stack Pointer (SP) Format
µPD784035Y, 784036Y, 784037Y, 784038Y
6.2.3 Special function registers (SFRs) special function registers, such mode registers control registers internal peripheral hardware, registers which special functions allocated. These registers mapped 256-Byte space addresses 0FF00H through 0FFFFHNote. Note execution LOCATION instruction. FFF00H through FFFFFH execution LOCATION instruction. Caution access address this area which allocated. such address accessed mistake, µPD784038Y deadlock status. This deadlock status cleared only inputting RESET signal. Table lists special function registers (SFRs). meanings symbols this table follows: Symbol Symbol indicating SFR. compiler (CC78K4). Indicates whether read-only, write-only, read/write. Read/write Read-only Write-only This symbol reserved NEC's assembler
(RA78K4). used variable #pragma command with
units manipulation units which value manipulated. SFRs that manipulated 16-bit units described operand sfrp instruction. specify address this SFR, describe even address. SFRs that manipulated 1-bit units described operand manipulation instruction. After reset Indicates status register when RESET signal been input.
µPD784035Y, 784036Y, 784037Y, 784038Y
Table 6-1. Special Function Registers (SFRs)
AddressNote Special Function Register (SFR) Name Symbol units manipulation 0FF00H 0FF01H 0FF02H 0FF03H 0FF04H 0FF05H 0FF06H 0FF07H 0FF0EH 0FF0FH 0FF10H 0FF12H 0FF14H 0FF15H 0FF16H 0FF17H 0FF18H 0FF19H 0FF1AH 0FF1BH 0FF1CH 0FF1DH 0FF20H 0FF21H 0FF23H 0FF24H 0FF25H 0FF26H 0FF27H 0FF2EH 0FF30H 0FF31H 0FF32H 0FF33H Port buffer register Compare register (timer/counter Capture/compare register (timer/counter Compare register (timer/counter Compare register (timer/counter Capture/compare register (timer/counter Capture/compare register (timer/counter Compare register (timer/counter Compare register (timer/counter Capture/compare register (timer/counter Capture/compare register (timer/counter Compare register (timer Compare register (timer Port mode register Port mode register Port mode register Port mode register Port mode register Port mode register Port mode register Real-time output port control register Capture/compare control register Timer output control register Capture/compare control register Capture/compare control register Port Port Port Port Port Port Port Port Port buffer register CR00 CR01 CR10 CR10W CR11 CR11W CR20 CR20W CR21 CR21W CR30 CR30W RTPC CRC0 CRC1 bits bits Undefined Undefined After reset
CRC2
Note
When LOCATION instruction executed. When LOCATION instruction executed, "F0000H" added this value.
µPD784035Y, 784036Y, 784037Y, 784038Y
AddressNote Special Function Register (SFR) Name Symbol units manipulation 0FF36H 0FF38H 0FF39H 0FF3AH 0FF3BH 0FF41H 0FF43H 0FF4EH 0FF50H 0FF51H 0FF52H 0FF53H 0FF54H 0FF55H 0FF56H 0FF57H 0FF5CH 0FF5DH 0FF5EH 0FF5FH 0FF60H 0FF61H 0FF62H 0FF68H 0FF6AH 0FF70H 0FF71H 0FF72H 0FF74H 0FF7DH 0FF80H 0FF81H 0FF82H 0FF83H Prescaler mode register Timer control register Prescaler mode register Timer control register conversion value setting register conversion value setting register converter mode register converter mode register conversion result register control register prescaler register modulo register modulo register One-shot pulse output control register control register Timer register Timer register Timer register TM1W TM2W TM3W PRM0 TMC0 PRM1 TMC1 DACS0 DACS1 ADCR PWMC PWPR PWM0 PWM1 OSPC IICC SPRM CSIM R/WNote
Note
After reset
bits
bits 0000H
Capture register (timer/counter Capture register (timer/counter Capture register (timer/counter Capture register (timer/counter Capture register (timer/counter Port mode control register Port mode control register Pull-up resistor option register Timer register
CR02 CR12 CR12W CR22 CR22W PMC1 PMC3
0000H
Undefined Undefined
Prescaler mode register serial clock Clocked serial interface mode register Slave address register
Notes When LOCATION instruction executed. When LOCATION instruction executed, "F0000H" added this value. read-only. Only manipulated units.
µPD784035Y, 784036Y, 784037Y, 784038Y
AddressNote Special Function Register (SFR) Name Symbol units manipulation 0FF84H 0FF85H 0FF86H 0FF88H 0FF89H 0FF8AH 0FF8BH 0FF8CH Clocked serial interface mode register Clocked serial interface mode register Serial shift register Asynchronous serial interface mode register CSIM1 CSIM2 ASIM bits bits FFFFH Undefined After reset
Asynchronous serial interface mode register ASIM2 Asynchronous serial interface status register Asynchronous serial interface status register Serial receive buffer: UART0 Serial transmit shift register: UART0 Serial shift register: IOE1 ASIS ASIS2 SIO1 RXB2 TXS2 SIO2 BRGC BRGC2 INTM0 INTM1 SCS0 ISPR MK0L MK0H MK1L STBC HLDM CLOM PWC1 PWC2
Note Note
0FF8DH
Serial receive buffer: UART2 Serial transmit shift register: UART2 Serial shift register: IOE2
0FF90H 0FF91H 0FFA0H 0FFA1H 0FFA4H 0FFA8H 0FFAAH 0FFACH 0FFADH 0FFAEH 0FFC0H 0FFC2H 0FFC4H 0FFC5H 0FFC6H 0FFC7H 0FFC8H
Baud rate generator control register Baud rate generator control register External interrupt mode register External interrupt mode register Sampling clock select register In-service priority register Interrupt mode control register Interrupt mask register Interrupt mask register Interrupt mask register Standby control register Watchdog timer mode register Memory expansion mode register Hold mode register Clock output mode register Programmable wait control register Programmable wait control register
AAAAH
Notes When LOCATION instruction executed. When LOCATION instruction executed, "F0000H" added this value. Data written using only dedicated instruction such "MOV STBC, #byte instruction" "MOV WDM, #byte instruction", cannot written with other instructions.
µPD784035Y, 784036Y, 784037Y, 784038Y
AddressNote Special Function Register (SFR) Name Symbol units manipulation 0FFCCH 0FFCDH 0FFCFH Refresh mode register Refresh area specification register Oscillation stabilization time specification register 0FFD0H0FFDFH 0FFE0H 0FFE1H 0FFE2H 0FFE3H 0FFE4H 0FFE5H 0FFE6H 0FFE7H 0FFE8H 0FFE9H 0FFEAH 0FFEBH 0FFECH 0FFEDH 0FFEEH 0FFEFH Interrupt control register (INTP0) Interrupt control register (INTP1) Interrupt control register (INTP2) Interrupt control register (INTP3) Interrupt control register (INTC00) Interrupt control register (INTC01) Interrupt control register (INTC10) Interrupt control register (INTC11) Interrupt control register (INTC20) Interrupt control register (INTC21) Interrupt control register (INTC30) Interrupt control register (INTP4) Interrupt control register (INTP5) Interrupt control register (INTAD) Interrupt control register (INTSER) Interrupt control register (INTSR) Interrupt control register (INTCSI1) 0FFF0H 0FFF1H 0FFF2H 0FFF3H Interrupt control register (INTST) Interrupt control register (INTCSI) Interrupt control register (INTSER2) Interrupt control register (INTSR2) Interrupt control register (INTCSI2) 0FFF4H 0FFF5H Interrupt control register (INTST2) Interrupt control register (INTSPC) PIC0 PIC1 PIC2 PIC3 CIC00 CIC01 CIC10 CIC11 CIC20 CIC21 CIC30 PIC4 PIC5 ADIC SERIC SRIC CSIIC1 STIC CSIIC SERIC2 SRIC2 CSIIC2 STIC2 SPCIC External area OSTS bits bits After reset
Note
When LOCATION instruction executed. When LOCATION instruction executed, "F0000H" added this value.
µPD784035Y, 784036Y, 784037Y, 784038Y
PERIPHERAL HARDWARE FUNCTIONS Ports
ports shown Figure provided make various control operations possible. Table shows function each port. Ports through connected internal pull-up resistors software when inputting. Figure 7-1. Port Configuration
Port Port
P20-P27
Port
Port Port Port Port Port
µPD784035Y, 784036Y, 784037Y, 784038Y
Table 7-1. Port Functions
Port Name Name Function Specification Pull-up Resistor Connection Software Port input output mode 1-bit units. operate 4-bit real-time output port (P00 through through P07) drive transistor. Port input output mode 1-bit units. drive LEDs. Port Port Input port input output mode 1-bit units. Port input output mode 1-bit units. drive LEDs. Port input output mode 1-bit units. drive LEDs. Port input output mode 1-bit units. Port input output mode 1-bit units. port pins input mode port pins input mode port pins input mode 6-bit units (P22 through P27) port pins input mode port pins input mode port pins input mode
Clock Generation Circuit
on-chip clock generation circuit necessary operation provided. This clock generation circuit divider circuit. high-speed operation necessary, internal operating frequency lowered divider circuit reduce current consumption. Figure 7-2. Block Diagram Clock Generation Circuit
Oscillation circuit
Selector
fCLK Peripheral circuit
fXX/2 UART/IOE INTP0 noise reduction circuit Oscillation stabilization timer
Remark oscillation frequency external clock input fCLK: internal operating frequency
µPD784035Y, 784036Y, 784037Y, 784038Y
Figure 7-3. Example Using Oscillation Circuit Crystal/ceramic oscillation
PD784038Y
VSS1
External clock EXTC OSTS EXTC OSTS
PD784038Y
PD784038Y
PD74HC04, etc.
Open
Caution When using clock oscillation circuit, wire dotted portion above figure follows avoid adverse influences wiring capacitance. Keep wiring length short possible. cross wiring with other signal lines. route wiring vicinity lines through which high alternating current flows. Always keep potential ground point capacitor oscillation circuit same VSS1. ground ground pattern through which high current flows. extract signals from oscillation circuit.
µPD784035Y, 784036Y, 784037Y, 784038Y
Real-Time Output Port
real-time output port outputs data stored buffer synchronization with coincidence interrupt generated timer/counter with external interrupt. result, pulses without jitter output. real-time output port therefore ideal applications where arbitrary patterns must output specific intervals (such open loop control stepping motor). real-time output port mainly consists port port buffer registers (P0H P0L) shown Figure 7-4. Figure 7-4. Block Diagram Real-Time Output Port
Internal
Real-time output port control register (RTPC)
Buffer register
INTP0 (from external source) INTC10 (from timer/counter INTC11 (from timer/counter Output trigger control circuit
Output latch (P0)
µPD784035Y, 784036Y, 784037Y, 784038Y
Timer/Counter
Three units timers/counters unit timer provided. Because total seven interrupt requests supported, these timers/counters timer used seven units timers/counters. Table 7-2. Operations Timers/Counters
Name Item Count width bits bits Operation mode Interval timer External event counter One-shot timer Function Timer output Toggle output PWM/PPG output One-shot pulse outputNote Real-time output Pulse width measurement Number interrupt requests input input inputs Timer/Counter Timer/Counter Timer/Counter Timer
Note
one-shot pulse output function makes pulse output level active software inactive hardware (interrupt request signal). This function different nature from one-shot timer function timer/counter
µPD784035Y, 784036Y, 784037Y, 784038Y
Figure 7-5. Block Diagram Timers/Counters Timer/counter
Clear control Selector Software trigger
fXX/8
Prescaler
Timer register (TM0)
Compare register (CR01)
Match
Pulse output control
Compare register (CR00)
Match
INTP3
Edge detection INTP3
Capture register (CR02)
INTC00 INTC01
Timer/counter
Clear control Selector
fXX/8
Prescaler
Timer register (TM1/TM1W)
Event input
Compare register (CR10/CR10W)
Match
INTC10 real-time output port
INTP0
Edge detection INTP0
Capture/Compare register (CR11/CR11W)
Match
INTC11
Capture register (CR12/CR12W)
Timer/counter
Clear control Selector
fXX/8
Prescaler
Timer register (TM2/TM2W)
INTP2/CI
Edge detection INTP2
Capture/Compare register (CR21/CR21W)
Match
Pulse output control
Compare register (CR20/CR20W)
Match
INTP1
Edge detection INTP1
Capture register (CR22/CR22W)
INTC20 INTC21
Timer
fXX/8 Prescaler Timer register (TM3/TM3W) Clear
Capture register (CR30/CR30W)
match
INTC30
Remark OVF: overflow flag
µPD784035Y, 784036Y, 784037Y, 784038Y
Output (PWM0, PWM1)
channels (pulse width modulation) output circuits with resolution bits repeat frequency 62.5 (fCLK MHz) provided. Both these output channels select high level active level. These outputs ideal controlling speed motor. Figure 7-6. Block Diagram Output Unit
Internal modulo register PWMn control register (PWMC)
Reload control
fCLK
Prescaler
8-bit down counter
Pulse control circuit 4-bit counter
Output control
PWMn (output pin)
1/256
Remark
µPD784035Y, 784036Y, 784037Y, 784038Y
Converter
analog-to-digital (A/D) converter with eight multiplexed inputs (ANI0 through ANI7) provided. This converter successive approximation type. result conversion retained 8-bit conversion result register (ADCR). Therefore, high-speed, high-accuracy conversion performed (conversion time: approx. fCLK MHz). conversion started either following modes: Hardware start: Conversion started trigger input (INTP5). Software start: Conversion started setting converter mode register (ADM). After started, converter operates following modes: Scan mode: more analog inputs sequentially selected, data converted obtained from input pins. Select mode: Only analog input used continuously obtain converted values. These operation modes whether starting stopping converter specified ADM. When result conversion transferred ADCR, interrupt request INTAD generated. using this request macro service, converted values successively transferred memory. Figure 7-7. Block Diagram Converter
ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7
Input selector
Sample hold circuit
Series resistor string AVREF1 Voltage comparator
Successive approximation register (SAR) Edge detection circuit Conversion trigger INTAD
INTP5
Control Circuit
selector
AVSS
Trigger enable converter mode register (ADM) conversion result register (ADCR)
Internal
µPD784035Y, 784036Y, 784037Y, 784038Y
Converter
circuits digital-to-analog (D/A) converters provided. These converters voltage output type have resolution bits. conversion method R-2R resistor ladder type. writing value output 8-bit conversion value setting register (DACSn: analog value output ANOn pin. output voltage range determined voltage applied across AVREF2 AVREF3 pins. Because output impedance high, current extracted from output. impedance load low, insert buffer amplifier between load output pin. ANOn goes into high-impedance state while RESET signal low. When RESET signal deasserted, DACSn cleared Figure 7-8. Block Diagram Converter
ANOn AVREF2
Selector
AVREF3
DACSn
DACEn
Internal
Remark
µPD784035Y, 784036Y, 784037Y, 784038Y
Serial Interface
Three independent serial interface channels provided. Asynchronous serial interface (UART)/3-wire serial (IOE) Clocked serial interface (CSI) 3-wire serial (IOE) 2-wire serial (IOE) interface (I2C) Therefore, communication with external system local communication within system simultaneously executed (refer Figure 7-9). Figure 7-9. Example Serial Interface UART
PD784038Y (master)
PD4711A
[UART] RS-232-C driver/receiver Port
PD6272 (EEPROMTM)
PD78062Y (slave)
PD4711A
[UART] RxD2 RS-232-C driver/receiver TxD2 Port
UART 3-wire serial 2-wire serial
PD784038Y (master)
PD4711A
[UART] RS-232-C driver/receiver Port SCK1 INTPm Port Note [3-wire serial I/O]
PD75108 (slave)
Port
PD78014 (slave)
INTPn Port [2-wire serial I/O] Note SCK0 Port
Note
Handshake line
µPD784035Y, 784036Y, 784037Y, 784038Y
7.8.1 Asynchronous serial interface/3-wire serial (UART/IOE)
channels serial interfaces that select asynchronous serial interface mode 3-wire serial mode provided. Asynchronous serial interface mode this mode, data byte following start transferred received. Because on-chip baud rate generator provided, wide range baud rates set. Moreover, clock input ASCK divided define baud rate. When baud rate generator used, baud rate conforming MIDI standard (31.25 kbps) also obtained. Figure 7-10. Block Diagram Asynchronous Serial Interface Mode
Internal
Receive buffer
RXB, RXB2
RXD, RXD2
Receive shift register
Transmit shift register
TXS, TXS2
TXD, TXD2
Receive control parity check
INTSR, INTSR2 INTSER, INTSER2
Trnsmit control Parity append
INTST, INTST2
Baud rate generator
1/2m fXX/2 ASCK, ASCK2
Selector
1/2n+1 1/2m
Remark fXX: oscillation frequency external clock input through through
µPD784035Y, 784036Y, 784037Y, 784038Y
3-wire serial mode this mode, master device starts transfer making serial clock active transfers 1-byte data synchronization with this clock. This mode used communicate with device having conventional clocked serial interface. Basically, communication established using three lines: serial clock (SCK) serial data lines. Generally, handshake line necessary check communication state. Figure 7-11. Block Diagram 3-wire Serial Mode
Internal
Direction control circuit
SIO1, SIO2 SI1, Shift register Output latch
SO1,
SCK1, SCK2
Serial clock counter
Interrupt signal generation circuit
INTCSI1, INTCSI2
Selector
1/2n+1
fXX/2
Serial clock control circuit
Remark fXX: oscillation frequency external clock input through through
µPD784035Y, 784036Y, 784037Y, 784038Y
7.8.2 Clocked serial interface (CSI)
this mode, master device starts transfer making serial clock active communicates 1-byte data synchronization with this clock. Figure 7-12. Block Diagram Clocked Serial Interface
Internal
Direction control register
Slave address register Match signal
Selector SO0/SDA Shift register
Output latch
Reset
N-ch open drain output 2-wire mode)
Start condition detection circuit Acknowledge detection circuit
Acknowledge detection control
Wake-up control circuit
Stop condition detection circuit
INTSPC
SCK0/SCL
Serial clock counter
Interrupt signal generation circuit
INTCSI
Serial clock control circuit Selector N-ch open drain output 2-wire mode) CLS0 CLS1
Timer output fXX/16
Selector
Prescaler
fXX/2
Remark fXX: oscillation frequency external clock input
µPD784035Y, 784036Y, 784037Y, 784038Y
3-wire serial mode This mode communicate with devices having conventional clocked serial interface. Basically, communication established this mode with three lines: serial clock (SCK0) serial data (SI0 SO0) lines. Generally, handshake line necessary check communication status. 2-wire serial mode This mode transfer 8-bit data using lines: serial clock (SCL) serial data (SDA). Generally, handshake line necessary check communication status. (Inter mode This mode communicate with devices conforming format. This mode transfer 8-bit data with more devices using lines: serial clock (SCL) serial data (SDA). During transfer, "start condition", "data", "stop condition" output onto serial data bus. During reception, these data automatically detected hardware.
Clock Output Function
operating clock divided output external device. that outputs clock also used 1-bit port. When this function used, local interface cannot used because ASTB CLKOUT pins multiplexed. Figure 7-13. Block Diagram Clock Output Function
fCLK fCLK/2
Selector
fCLK/4 fCLK/8 fCLK/16
Output control
CLKOUT
Output enable Output level
µPD784035Y, 784036Y, 784037Y, 784038Y
7.10 Edge Detection Function
interrupt input pins (NMI INTP0 through INTP5) used only input interrupt requests also input trigger signals internal hardware units. Because these pins operate edge input signal, they have function detect edge. Moreover, noise reduction circuit also provided prevent erroneous detection noise. Name INTP0-INTP3 INTP4, INTP5 Detectable Edge Either rising falling edge Either both rising falling edges Noise Reduction analog delay clock samplingNote analog delay
Note
INTP0 select sampling clock.
7.11 Watchdog Timer
watchdog timer provided detect hang CPU. This watchdog timer generates non-maskable interrupt unless cleared software within specified interval time. Once enabled operate, watchdog timer cannot stopped software. Whether interrupt watchdog timer interrupt input from takes precedence specified. Figure 7-14. Block Diagram Watchdog Timer
fCLK
Timer
fCLK/221 fCLK/220 fCLK/219 fCLK/217
Selector
INTWDT
Clear signal
µPD784035Y, 784036Y, 784037Y, 784038Y
INTERRUPT FUNCTION
servicing response interrupt request, three types shown Table selected program. Table 8-1. Servicing Interrupt Request
Servicing Mode Vectored interrupt Entity Servicing Software Servicing Branches executes servicing routine (servicing arbitrary). Context switching Automatically switches register bank, branches executes servicing routine (servicing arbitrary). Macro service Firmware Executes data transfer between memory (servicing fixed) Retained Contents Saves restores from stack. Saves restores from fixed area register bank
Interrupt Sources
Table shows interrupt sources available. shown, interrupts generated types sources, execution instruction BRKCS instruction, operand error. priority interrupt servicing four levels, that nesting controlled during interrupt servicing that which more interrupts that simultaneously occur should serviced first. When macro service function used, however, nesting always proceeds. default priority priority (fixed) service that performed more interrupt requests, having same request, simultaneously generate (refer Table 8-2).
µPD784035Y, 784036Y, 784037Y, 784038Y
Table 8-2. Interrupt Sources
Type Software Default Priority Name instruction BRKCS instruction Operand error Source Trigger Instruction execution result exclusive between byte operand byte when "MOV STBC, #byte", "MOV WDM, #byte", "LOCATION" instruction executed Detection input edge Overflow watchdog timer Detection input edge (TM1/TM1W capture trigger, TM1/TM1W event counter input) Detection input edge (TM2/TM2W capture trigger, TM2/TM2W event counter input) Detection input edge (TM2/TM2W capture trigger TM2/TM2W event counter input) Detection input edge (TM0 capture trigger, event counter input) Generation TM0-CR00 match signal Generation TM0-CR01 match signal Generation TM1-CR10 match signal 8-bit operation mode) Generation TM1W-CR10W match signal 16-bit operation mode) Generation TM1-CR11 match signal 8-bit operation mode) Generation TM1W-CR11W match signal 16-bit operation mode) Generation TM2-CR20 match signal 8-bit operation mode) Generation TM2W-CR20W match signal 16-bit operation mode) Generation TM2-CR21 match signal 8-bit operation mode) Generation TM2W-CR21W match signal 16-bit operation mode) Generation TM3-CR30 match signal 8-bit operation mode) Generation TM3W-CR30W match signal 16-bit operation mode) Detection input edge Detection input edge conversion (transfer ADCR) Occurrence ASI0 reception error ASI0 reception CSI1 transfer ASI0 transfer CSI1 transfer Occurrence ASI2 reception error ASI2 reception CSI2 transfer ASI2 transfer stop condition interrupt Internal/ External Macro service
Non-maskable Maskable
(highest)
INTP0
External Internal External
INTP1
INTP2
INTP3 INTC00 INTC01 INTC10
Internal
INTC11
INTC20
INTC21
INTC30
(lowest)
INTP4 INTP5 INTAD INTSER INTSR INTCSI1 INTST INTCSI INTSER2 INTSR2 INTCSI2 INTST2 INTSPC
External Internal
Remark ASI: asynchronous serial interface CSI: clocked serial interface
µPD784035Y, 784036Y, 784037Y, 784038Y
Vectored Interrupt
Execution branches servicing routing using memory contents vector table address corresponding interrupt source address branch destination. that performs interrupt servicing, following operations performed: branching: Saves status (contents PSW) stack returning: Restores status (contents PSW) from stack return main routine from interrupt service routine, RETI instruction used. branch destination address range FFFFH. Table 8-3. Vector Table Address Interrupt Source instruction Operand error INTP0 INTP1 INTP2 INTP3 INTC00 INTC01 INTC10 INTC11 INTC20 INTC21 INTC30 INTP4 INTP5 INTAD INTSER INTSR INTCSI1 INTST INTCSI INTSER2 INTSR2 INTCSI2 INTST2 INTSPC 002EH 0030H 0026H 0028H 002AH 002CH Vector Table Address 003EH 003CH 0002H 0004H 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H 0018H 001AH 001CH 001EH 0020H 0022H 0024H
µPD784035Y, 784036Y, 784037Y, 784038Y
Context Switching
When interrupt request generated when BRKCS instruction executed, predetermined register bank selected hardware. Context switching function that branches execution vector address stored advance register bank, stack current contents program counter (PC) program status word (PSW) register bank. branch address range FFFFH. Figure 8-1. Context Switching Operation When Interrupt Request Generated
0000B Transfer Register bank PC19-16 PC15-0 Save (bits through temporary register) Exchange Save Temporary register Save
Register bank
Switching register bank (RBS0 RBS2
Macro Service
This function transfer data between memory special function register (SFR) without intervention CPU. macro service controller accesses memory same transfer cycle directly transfers data without loading Because this function does save restore status CPU, load data, data transferred high speeds. Figure 8-2. Macro Service
Read Memory Write Macro service controller
Write Read
Internal
µPD784035Y, 784036Y, 784037Y, 784038Y
Application Example Macro Service
Transfer serial interface
Transfer data storage buffer (memory) Data Data
Data Data
Internal
Transfer shift register TXS(SFR)
Transfer control
INTST
Each time macro service request (INTST) generated, next transfer data transferred from memory TXS. When data (last byte) been transferred (when transfer data storage buffer become empty), vectored interrupt request (INTST) generated. Reception serial interface
Receive data storage buffer (memory) Data Data
Data Data
Internal
Receive buffer
RXB(SFR)
Receive shift register
Reception control
INTSR
Each time macro service request (INTSR) generated, receive data transferred from memory. When data (last byte) been transferred memory (when receive data storage buffer become full), vectored interrupt request (INTSR) generated.
µPD784035Y, 784036Y, 784037Y, 784038Y
Real-time output port INTC10 INTC11 serve output triggers real-time output port. macro services these following output pattern intervals simultaneously. Therefore, INTC10 INTC11 control stepping motors independently each other. They also used output control motors.
Output pattern profile (memory) Pn-1 Output timing profile (memory) Tn-1
Internal
Internal
Match (SFR) INTC10 Output latch P00-P03 CR10 (SFR)
Each time macro service request (INTC10) generated, pattern timing transferred buffer register (P0L) compare register (CR10), respectively. When contents timer register (TM1) coincide with those CR10, INTC10 generated again, contents transferred output latch. When (last byte) transferred CR10, vectored interrupt request (INTC10) generated. same applies INTC11.
µPD784035Y, 784036Y, 784037Y, 784038Y
LOCAL INTERFACE
local interface connect external memory (memory mapped I/O) support memory space MByte (refer Figure 9-1). Figure 9-1. Example Local Interface
PD784038Y
A16-A19 Decoder
REFRQ Pseudo SRAM PROM PD27C1001A
Character generator PD24C1000
AD0-AD7
Data
ASTB
Latch
A8-A15
Address
Gate array expansion Centronics I/F, etc.
Memory Expansion
memory capacity expanded seven steps, from Bytes MByte, connecting external program memory data memory.
µPD784035Y, 784036Y, 784037Y, 784038Y
Memory Space
1-MByte memory space divided into eight spaces logical addresses. Each space controlled using programmable wait function pseudo static refresh function. Figure 9-2. Memory Space
KBytes
KBytes KBytes KBytes KBytes KBytes KBytes KBytes
µPD784035Y, 784036Y, 784037Y, 784038Y
Programmable Wait
memory space divided into eight spaces wait states independently inserted each these spaces while signals active. Even when memory with different access time connected, therefore, efficiency entire system does drop. addition, address wait function that extends active period ASTB signal also provided have sufficient address decode time (this function entire space).
Pseudo Static Refresh Function
following refresh operations performed: Pulse refresh: cycle that outputs refresh pulse REFRQ fixed cycle inserted. memory spaces divided into eight spaces, refresh pulse output from REFRQ while specified memory space accessed. Therefore, normal memory access kept wait refresh cycle. Power-down self-refresh: level output REFRQ standby mode retain contents pseudo static RAM.
Hold Function
hold function provided facilitate connection controller. When hold request signal (HLDRQ) received from external master, address bus, address/data bus, ASTB, pins into high-impedance state when current cycle been completed. This makes hold acknowledge (HLDAK) signal active, releases external master. Note that, while hold function used, external wait function pseudo static refresh function cannot used.
µPD784035Y, 784036Y, 784037Y, 784038Y
STANDBY FUNCTION
This function reduce power dissipation chip, used following modes: HALT mode: Stops supply operating clock CPU. This mode used combination with normal operation mode intermittent operation reduce average power dissipation. IDLE mode: Stops entire system with oscillation circuit continuing operation. power dissipation this mode close that STOP mode. However, time required restore normal program operation from this mode almost same that from HALT mode. STOP mode: Stops oscillator thereby stop internal operations chip. Consequently, power dissipation minimized with only leakage current flowing. These modes programmable. macro service started from HALT mode. Figure 10-1. Transition Standby Status
bilizati Program tion Oscilla expires operation Waits oscillation stabilization
Macro service request processing macro service
Macro service
STOP (standby)
IDLE (standby)
Interrupt request masked interrupt
HALT (standby)
Notes When INTP4 INTP5 masked Only interrupt requests that masked Remark Only externally input valid. watchdog timer cannot used release standby mode (STOP/IDLE mode).
µPD784035Y, 784036Y, 784037Y, 784038Y
RESET FUNCTION
When level input RESET pin, internal hardware initialized (reset status). When RESET goes high, following data program counter (PC). Lower bits contents address 0000H Middle bits contents address 0001H Higher bits Program execution started from branch destination address which contents Therefore, system reset started from address. contents each register program necessary. RESET input circuit noise reduction circuit prevent malfunctioning noise. This noise reduction circuit sampling circuit analog delay. Figure 11-1. Accepting RESET Signal
Delay Delay Delay Initialize Executes instruction reset start address
RESET (input)
Internal reset signal
Reset starts
Reset ends
Assert RESET signal active until oscillation stabilization time (approx. elapses execute powerON reset operation. Figure 11-2. Power-ON Reset Operation
Executes instruction reset start address
Oscillation stabilization time
Delay
Initialize
RESET (input)
Internal reset signal
Reset ends
µPD784035Y, 784036Y, 784037Y, 784038Y
INSTRUCTION
8-bit instructions (The instructions parentheses combinations realized describing MOV, XCH, ADD, ADDC, SUBC, AND, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHIKL, CHKLA Table 12-1. Instruction List 8-Bit Addressing
Second Operand #byte First Operand (MOV)
Note
saddr saddr'
!addr16 !!addr24
[saddrp] [%saddrg]
PSWL PSWH
[WHL+] [WHL-]
None Note
(MOV) (XCH)
(MOV)Note (XCH)Note
(XCH)
(MOV) (XCH)
(MOV) (XCH) (ADD)Note RORNote MULU DIVUW
(ADD)Note (ADD)Note (ADD)Note (ADD)Note ADDNote ADDNote
Note
(MOV) (XCH)
(ADD)Note ADDNote ADDNote ADDNote
saddr
ADDNote
(MOV)Note
ADDNote
DBNZ PUSH CHKL CHKLA
(ADD)Note ADDNote
ADDNote (ADD)Note ADDNote
!addr16 !!addr24 [saddrp] [%saddrg] mem3
(MOV) ADDNote ADDNote
ROR4 ROL4
PSWL PSWH STBC, [TDE+] [TDE-]
DBNZ (MOV) (ADD)
Note
MOVBKNote
MOVMNote
Notes operands ADDC, SUB, SUBC, AND, XOR, same that ADD. Either second operand used, second operand operand address. operands ROL, RORC, ROLC, SHR, same that ROR. operands XCHM, CMPME, CMPMNE, CMPMNC, CMPMC same that MOVM. operands XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC same that MOVBK. code length some instructions having saddr2 saddr this combination short.
µPD784035Y, 784036Y, 784037Y, 784038Y
16-bit instructions (The instructions parentheses combinations realized describing MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW Table 12-2. Instruction List 16-Bit Addressing
Second Operand #word First Operand (MOVW) ADDW
Note
saddrp saddrp'
sfrp
!addr16 !!addr24
[saddrp] [%saddrg]
[WHL+]
byte
NoneNote
(MOVW) (XCHW)
(MOVW) (MOVW) (XCHW) (XCHW)
Note
MOVW (XCHW)
(MOVW) XCHW
MOVW XCHW
(MOVW) (XCHW)
Note
(ADD)Note (ADDW)Note (ADDW)Note (ADDW)Note MOVW ADDW
Note
(MOVW) (XCHW) (ADDW)
Note
MOVW XCHW ADDW
Note
MOVW XCHW ADDW
Note
MOVW XCHW ADDW
Note
MOVW
SHRW SHLW
MULWNote INCW DECW INCW DECW
saddrp
MOVW ADDWNote
(MOVW)Note (ADDW)Note
MOVW ADDWNote
MOVW XCHW ADDWNote
sfrp
MOVW
MOVW
MOVW
PUSH MOVTBLW
ADDWNote (ADDW)Note ADDWNote !addr16 !!addr24 [saddrp] [%saddrg] MOVW MOVW (MOVW) MOVW
PUSH
ADDWG SUBWG
post
PUSH PUSHU POPU
[TDE+] byte
(MOVW)
SACW MACW MACSW
Notes operands SUBW CMPW same that ADDW. Either second operand used, second operand operand address. code length some instructions having saddrp2 saddrp this combination short. operands MULUW DIVUX same that MULW.
µPD784035Y, 784036Y, 784037Y, 784038Y
24-bit instructions (The instructions parentheses combinations realized describing MOVG, ADDG, SUBG, INCG, DECG, PUSH, Table 12-3. Instruction List 24-Bit Addressing
Second Operand #imm24 First Operand (MOVG) (ADDG) (SUBG) MOVG ADDG SUBG (MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG) MOVG ADDG SUBG (MOVG) ADDG SUBG MOVG MOVG INCG DECG PUSH saddrg !!addr24 mem1 [%saddrg] MOVG (MOVG) (MOVG) MOVG MOVG MOVG INCG DECG MOVG MOVG (MOVG) MOVG MOVG MOVG saddrg !!addr24 mem1 [%saddrg] NoneNote
Note
Either second operand used, second operand operand address.
µPD784035Y, 784036Y, 784037Y, 784038Y
manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BTCLR, BFSET Table 12-4. Manipulation Instructions
Second Operand saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit First Operand !addr16.bit !!addr24.bit MOV1 AND1 XOR1 saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit !addr16.bit !!addr24.bit MOV1 NOT1 SET1 CLR1 BTCLR BFSET /saddr.bit /sfr. /A.bit /X.bit /PSWL.bit /PSWH.bit /mem2.bit /!addr16.bit /!!addr24.bit AND1 NOT1 SET1 CLR1 NoneNote
Note
Either second operand used, second operand operand address.
µPD784035Y, 784036Y, 784037Y, 784038Y
Call return/branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BNZ, BNE, BNC, BNL, BNV, BPO, BPE, BLT, BGE, BLE, BGT, BNH, BTCLR, BFSET, DBNZ Table 12-5. Call Return/Branch Instructions
Operand Instruction Address Basic instruction BCNote CALL CALL RETCS RETCSB Compound instruction BTCLR BFSET DBNZ CALL CALL CALL CALL CALL CALLF CALLF BRKCS RETI RETB $addr20 $!addr20 !addr16 !!addr20 [rp] [rg] !addr11 [addr5] None
Note
operands BNZ, BNE, BNC, BNL, BNV, BPO, BPE, BLT, BGE, BLE, BGT, BNH, same
Other instructions ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, SWRS
µPD784035Y, 784036Y, 784037Y, 784038Y
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Parameter Supply voltage Symbol AVDD AVSS Input voltage Output voltage Low-level output current High-level output current converter reference input voltage converter reference input voltage Operating ambient temperature Storage temperature Total output pins Total output pins AVREF1 AVREF2 AVREF3 Tstg Conditions Ratings -0.5 +7.0 AVSS VDD+0.5 -0.5 +0.5 -0.5 VDD+0.5 -0.5 VDD+0.5 -100 -0.5 VDD+0.3 -0.5 VDD+0.3 -0.5 VDD+0.3 +150 Unit
Caution Absolute maximum ratings rated values beyond which physical damage will caused product; rated value parameters above table exceeded, even momentarily, quality product deteriorate. Always product within rated values.
µPD784035Y, 784036Y, 784037Y, 784038Y
OPERATING CONDITIONS Operating ambient temperature (TA) +85°C Rising time falling time (tr, pins which specified) Power supply voltage clock cycle time Figure 13-1
Figure 13-1. Power Supply Voltage Clock Cycle Time
10000 4000
Clock Cycle Time tCYK [ns]
1000 Guaranteed Operating Range 62.5
Power Supply Voltage
CAPACITANCE
Parameter Input capacitance Output capacitance capacitance Symbol Unmeasured pins returned Conditions MIN. TYP. MAX. Unit
µPD784035Y, 784036Y, 784037Y, 784038Y
OSCILLATOR CHARACTERISTICS +4.5
Resonator Ceramic resonator crystal resonator VSS1 Recommended Circuit Parameter Oscillator frequency (fXX) MIN. MAX. Unit
External clock
input frequency (fX)
input rising/falling time (tXR, tXF)
HCMOS inverter
input high-/low-level width (tWXH, tWXL)
Caution When using system clock oscillator, wiring area enclosed with broken line should carried follows avoid adverse effect from wiring capacitance. Wiring should short possible. Wiring should cross other signal lines. Wiring should placed close varying high current. potential oscillator capacitor ground should same VSS1. ground wiring ground pattern which high current flows. fetch signal from oscillator.
µPD784035Y, 784036Y, 784037Y, 784038Y
OSCILLATOR CHARACTERISTICS +2.7
Resonator Ceramic resonator crystal resonator VSS1 Recommended Circuit Parameter Oscillator frequency (fXX) MIN. MAX. Unit
External clock
input frequency (fX)
input rising/falling time (tXR, tXF)
HCMOS inverter
input high-/low-level width (tWXH, tWXL)
Caution When using system clock oscillator, wiring area enclosed with broken line should carried follows avoid adverse effect from wiring capacitance. Wiring should short possible. Wiring should cross other signal lines. Wiring should placed close varying high current. potential oscillator capacitor ground should same VSS1. ground wiring ground pattern which high current flows. fetch signal from oscillator.
µPD784035Y, 784036Y, 784037Y, 784038Y
CHARACTERISTICS +2.7 (1/2)
Parameter Low-level input voltage Symbol VIL1 VIL2 VIL3 High-level input voltage VIH1 VIH2 VIH3 Low-level output voltage VOL1 VOL2 Conditions pins other than those described Notes pins described Notes +5.0 V±10% pins described Notes pins other than those described Notes pins described Notes +5.0 V±10% pins described Notes pins other than those described Note pins described Note pins described Note VOL3 +5.0 V±10% pins described Notes +5.0 V±10% pins other than those described Note EXTC VIL2 EXTC VIH2 VDD-1.0 VDD-1.4 MIN. -0.3 -0.3 -0.3 0.7VDD 0.8VDD TYP. MAX. 0.3VDD 0.2VDD +0.8 VDD+0.3 VDD+0.3 VDD+0.3 Unit
High-level output voltage
VOH1 VOH2
low-level input current high-level input current
Notes RESET, P12/ASCK2/SCK2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, TEST P40/AD0 P47/AD7 P50/A8 P57/A15 P60/A16 P63/A19, P64/RD, P65/WR, P66/WAIT/HLDRQ, P67/REFRQ/HLDAK P32/SCK0/SCL P33/SO0/SDA
µPD784035Y, 784036Y, 784037Y, 784038Y
CHARACTERISTICS +2.7 (2/2)
Parameter Input leakage current Output leakage current supply current Symbol IDD1 Conditions pins other than when EXTC Operation mode +5.0 V±10% +2.7 IDD2 HALT mode +5.0 V±10% +2.7 IDD3 IDLE mode (EXTC +5.0 V±10% +2.7 Pull-up resistance MIN. TYP. MAX. Unit
µPD784035Y, 784036Y, 784037Y, 784038Y
CHARACTERISTICS +2.7 Read/write operation (1/2)
Parameter Address setup time Symbol tSAST Conditions +5.0 V±10% MIN. (0.5+a)T-15 (0.5+a)T-31 ASTB high-level width tWSTH +5.0 V±10% (0.5+a)T-17 (0.5+a)T-40 Address hold time (from ASTB) Address hold time (from delay time from address Address float time (from Data input time from address Data input time from ASTB Data input time from delay time from ASTB Data hold time (from Address active time from tHRID tDRA After program read +5.0 V±10% 0.5T-8 0.5T-12 After data read +5.0 V±10% 1.5T-8 1.5T-12 ASTB delay time from low-level width tDRST tWRL +5.0 V±10% 0.5T-17 (1.5+n)T-30 (1.5+n)T-40 Address hold time (from delay time from address Data output delay time from ASTB Data output delay time from output delay time from ASTB tHWA tDAW +5.0 V±10% 0.5T-14 (1+a)T-5 (1+a)T-15 tDSTOD +5.0 V±10% 0.5T+19 0.5T+35 tDWOD tDSTW 0.5T-9 0.5T-11 tHSTLA +5.0 V±10% 0.5T-24 0.5T-34 tHRA tDAR +5.0 V±10% 0.5T-14 (1+a)T-9 (1+a)T-15 tFRA tDAID +5.0 V±10% (2.5+a+n)T-37 (2.5+a+n)T-52 tDSTID +5.0 V±10% (2+n)T-40 (2+n)T-60 tDRID +5.0 V±10% (1.5+n)T-50 (1.5+n)T-70 tDSTR 0.5T-9 MAX. Unit
Remark TCYK (system clock cycle time) (during address wait), otherwise, Number wait states
µPD784035Y, 784036Y, 784037Y, 784038Y
Read/write operation (2/2)
Parameter Symbol Conditions +5.0 V±10% MIN. (1.5+n)T-30 (1.5+n)T-40 Data hold time (from Note ASTB delay time (from low-level width tDWST tWWL +5.0 V±10% tHWOD +5.0 V±10% 0.5T-5 0.5T-25 0.5T-12 (1.5+n)T-30 (1.5+n)T-40 MAX. Unit
Data setup time tSODW
Note
hold time includes time during which VOH1 VOL1 held under load conditions
Remark TCYK (system clock cycle time) Number wait states hold timing
Parameter Float delay time from HLDRQ HLDAK delay time from HLDRQ HLDAK delay time from float HLDAK delay time from HLDRQ Active delay time from HLDAK tDHQLHAL +5.0 V±10% 2T+40 2T+60 tDHAC +5.0 V±10% 1T-20 1T-30 tDHQHHAH +5.0 V±10% (7+a+n)T+30 (7+a+n)T+40 tDCFHA 1T+30 Symbol tFHQC Conditions MIN. MAX. (6+a+n)T+50 Unit
Remark TCYK (system clock cycle time) (during address wait), otherwise, Number wait states
µPD784035Y, 784036Y, 784037Y, 784038Y
External wait timing
Parameter WAIT input time from address WAIT input time from ASTB WAIT hold time from ASTB WAIT delay time from ASTB WAIT input time from WAIT hold time from WAIT delay time from Data input time from WAIT delay time from WAIT delay time from WAIT WAIT input time from WAIT hold time from WAIT delay time from Symbol tDAWT tDSTWT tHSTWTH tDSTWTH tDRWTL tHRWT tDRWTH tDWTID tDWTW tDWTR tDWWTL tHWWT tDWWTH +5.0 V±10% +5.0 V±10% +5.0 V±10% nT+5 nT+10 (1+n)T-40 (1+n)T-70 Conditions +5.0 V±10% +5.0 V±10% +5.0 V±10% +5.0 V±10% +5.0 V±10% +5.0 V±10% +5.0 V±10% +5.0 V±10% 0.5T 0.5T T-75 nT+5 nT+10 (1+n)T-40 (1+n)T-60 0.5T-5 0.5T-10 (0.5+n)T+5 (0.5+n)T+10 (1.5+n)T-40 (1.5+n)T-60 T-50 T-70 MIN. MAX. (2+a)T-40 (2+a)T-60 1.5T-40 1.5T-60 Unit
Remark TCYK (system clock cycle time) (during address wait), otherwise, Number wait states Refresh timing
Parameter Random read/write cycle time REFRQ low-level pulse width Symbol tWRFQL +5.0 V±10% Conditions MIN. 1.5T-25 1.5T-30 0.5T-9 1.5T-9 1.5T-9 0.5T-15 +5.0 V±10% 1.5T-25 1.5T-30 MAX. Unit
REFRQ delay time from tDSTRFQ ASTB REFRQ delay time from tDRRFQ REFRQ delay time from tDWRFQ ASTB delay time from REFRQ tDRFQST
REFRQ high-level pulse tWRFQH width
Remark TCYK (system clock cycle time)
µPD784035Y, 784036Y, 784037Y, 784038Y
SERIAL OPERATION +2.7 AVSS
Parameter Serial clock cycle time (SCK0) Symbol tCYSK0 Input Output Serial clock low-level width (SCK0) tWSKL0 Input Output Serial clock high-level width (SCK0) tWSKH0 Input Output setup time SCK0) hold time (from SCK0) output delay time (from SCK0) tHSSK0 tDSBSK1 tDSBSK2 CMOS push-pull output (3-wire serial mode) Open-drain output (2-wire serial mode), 5/fXX+40 5/fXX+150 5/fXX+400 tSSSK0 External clock When SCK0 CMOS External clock When SCK0 CMOS Conditions External clock When SCK0 CMOS MIN. 10/fXX+380 5/fXX+150 0.5T-40 5/fXX+150 0.5T-40 MAX. Unit
Remarks values this table those when Serial clock cycle software. minimum value 16/fXX. fXX: Oscillation frequency
Parameter Symbol Standard mode MIN. clock frequency Hold time clock low-level state Hold time clock high-level state Data hold time Data setup time Rising time signals Falling time signals Load capacitance each line fSCL tLOW tHIGH tHD; tSU; 1000 MAX. High-speed mode MIN. 20+0.1Cb 20+0.1Cb MAX. Unit
µPD784035Y, 784036Y, 784037Y, 784038Y
IOE1, IOE2
Parameter Serial clock cycle time (SCK1, SCK2) Symbol tCYSK1 Input Conditions +5.0 V±10% MIN. 0.5T-40 0.5T-40 During data transfer 0.5tCYSK1-40 MAX. Unit
Output Serial clock low-level width (SCK1, SCK2) tWSKL1 Input
Internal clock divided +5.0 V±10%
Output Serial clock high-level width (SCK1, SCK2) tWSKH1 Input
Internal clock divided +5.0 V±10%
Output SI1, setup time SCK1, SCK2) SI1, hold time (from SCK1, SCK2) SO1, output delay time (from SCK1, SCK2) SO1, output hold time (from SCK1, SCK2 tSSSK1 tHSSK1 tDSOSK tHSOSK
Internal clock divided
Remarks values this table those when Serial clock cycle software. minimum value 16/fXX. UART, UART2
Parameter ASCK clock input cycle time ASCK clock low-level width ASCK clock high-level width Symbol tCYASK Conditions +5.0 V±10% MIN. tWASKL +5.0 V±10% 52.5 tWASKH +5.0 V±10% 52.5 MAX. Unit
µPD784035Y, 784036Y, 784037Y, 784038Y
CLOCK OUTPUT OPERATION
Parameter CLKOUT cycle time CLKOUT low-level width Symbol tCYCL tCLL +5.0 V±10% Conditions MIN. 0.5tCYCL-10 0.5tCYCL-20 CLKOUT high-level width tCLH +5.0 V±10% 0.5tCYCL-10 0.5tCYCL-20 CLKOUT rising time tCLR +5.0 V±10% CLKOUT falling time tCLF +5.0 V±10% MAX. Unit
Remark Divided frequency ratio software tCYK (system clock cycle time) OTHER OPERATIONS
Parameter low-level width high-level width INTP0 low-level width INTP0 high-level width INTP1 INTP3, low-level width INTP1 INTP3, high-level width INTP4, INTP5 low-level width Symbol tWNIL tWNIH tWIT0L tWIT0H tWIT1L tWIT1H tWIT2L Conditions MIN. 3tCYSMP+10 3tCYSMP+10 3tCYCPU+10 3tCYCPU+10 MAX. Unit
INTP4, INTP5 high-level tWIT2H width RESET low-level width RESET high-level width tWRSL tWRSH
Remark tCYSMP: Sampling clock software tCYCPU: operation clock software
µPD784035Y, 784036Y, 784037Y, 784038Y
CONVERTER CHARACTERISTICS +85°C, REF1 +2.7
Parameter Resolution Total error
Note Note
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
±1/2 tCONV -0.3 1000 MHz, STOP mode, AVREF1+0.3
tCYK tCYK tCYK tCYK
Linearity calibration Quantization error Conversion time
Sampling time
tSAMP
Analog input voltage Analog input impedance AVREF1 current AVDD supply current
VIAN AIREF1 AIDD1 AIDD2
Note
Quantization error included. This parameter indicated ratio full-scale value.
Remark tCYK: System clock cycle time
µPD784035Y, 784036Y, 784037Y, 784038Y
CONVERTER CHARACTERISTICS +85°C, AVDD +2.7 AVSS
Parameter Resolution Total error Load conditions: AVDD AVREF2 +2.7 AVREF3 AVDD +2.7 AVREF2 0.75VDD AVREF3 0.25VDD Load conditions: AVDD AVREF2 +2.7 AVREF3 AVDD +2.7 AVREF2 0.75VDD AVREF3 0.25VDD Settling time Output resistance Analog reference voltage AVREF2 AVREF3 AVREF2, AVREF3 resistance RAIREF Reference power supply input current AIREF2 AIREF3 DACS0, Load conditions: DACS0, 0.75VDD 0.25VDD Symbol Conditions MIN. TYP. MAX. Unit
µPD784035Y, 784036Y, 784037Y, 784038Y
DATA RETENTION CHARACTERISTICS
Parameter Data retention voltage Data retention current Symbol VDDDR IDDDR STOP mode VDDDR +2.7 VDDDR +2.5 rising time falling time tRVD tFVD Crystal resonator Ceramic resonator Specific pins
Note
Conditions
MIN.
TYP.
MAX.
Unit
hold time tHVD (from STOP mode setting) STOP release signal input time Oscillation stabilization wait time Low-level input voltage High-level input voltage tDREL tWAIT
0.9VDDDR 0.1VDDDR VDDDR
Note
RESET, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/ INTP5, P27/SI0, P32/SCK0/SCL, P33/SO0/SDA pins
TIMING TEST POINTS
0.8VDD Test Points
0.8VDD
0.45
µPD784035Y, 784036Y, 784037Y, 784038Y
TIMING WAVEFORM Read operation
tWSTH ASTB tSAST tHSTLA tDSTID tDRST
tDAID tDSTR tDAR tWRL tFRA tDRID
tHRA
tHRID tDRA
Write operation
tWSTH ASTB tSAST tHSTLA tDSTOD tDWST
tHWA tDSTW tDAW tWWL tDWOD tSODW tHWOD
µPD784035Y, 784036Y, 784037Y, 784038Y
HOLD TIMING
ADTB, A19, AD7, tFHQC HLDRQ tDHQHHAH HLDAK tDHQLHAL tDCFHA tDHAC
EXTERNAL WAIT SIGNAL INPUT TIMING Read operation
ASTB tDSTWTH tHSTWTH
tDSTWT
tDAWT tDRWTL WAIT tHRWT tDRWTH tDWTR tDWTID
Write operation
ASTB tDSTWTH tHSTWTH
tDSTWT
tDAWT tDWWTL WAIT tHWWT tDWWTH tDWTW
µPD784035Y, 784036Y, 784037Y, 784038Y
REFRESH TIMING WAVEFORM Random read/write cycle
ASTB
When refresh memory accessed read write same time
ASTB
tDSTRFQ tDRFQST tWRFQH
REFRQ tWRFQL
Refresh after read
ASTB tDRFQST tDRRFQ REFRQ tWRFQL
Refresh after write
ASTB tDRFQST tDWRFQ REFRQ tWRFQL
µPD784035Y, 784036Y, 784037Y, 784038Y
SERIAL OPERATION
tWSKL0 tCYSK0 tDSBSK1 tHSBSK1 tSSSK0 tHSSK0 Input data tWSKH0
Output data
tHIGH tLOW
tHD; tSU;
IOE1, IOE2
tWSKL1 tCYSK1 tDSOSK tHSOSK tSSSK1 tHSSK1 tWSKH1
Input data
Output data
UART, UART2
tWASKH tWASKL
ASCK, ASCK2 tCYASK
µPD784035Y, 784036Y, 784037Y, 784038Y
CLOCK OUTPUT TIMING
tCLH
tCLL
CLKOUT tCLR tCYCL tCLF
INTERRUPT INPUT TIMING
tWNIH tWNIL
tWIT0H
tWIT0L
INTP0
tWIT1H
tWIT1L
INTP1 INTP3
tWIT2H
tWIT2L
INTP4, INTP5
RESET INPUT TIMING
tWRSH tWRSL
RESET
µPD784035Y, 784036Y, 784037Y, 784038Y
EXTERNAL CLOCK TIMING
tWXH
tWXL
tCYX
DATA RETENTION CHARACTERISTICS
STOP mode setting
tHVD tFVD
VDDDR tRVD tDREL tWAIT
RESET
(Clearing falling edge)
(Clearing rising edge)
µPD784035Y, 784036Y, 784037Y, 784038Y
PACKAGE DRAWINGS
PLASTIC
detail lead
NOTE Each lead centerline located within 0.13 (0.005 inch) true position (T.P.) maximum material condition.
ITEM
MILLIMETERS 17.2±0.4 14.0±0.2 14.0±0.2 17.2±0.4 0.825 0.825 0.30±0.10 0.13 0.65 (T.P.) 1.6±0.2 0.8±0.2 0.15 +0.10 -0.05 0.10 0.1±0.1 5°±5° MAX.
INCHES 0.677±0.016 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.677±0.016 0.032 0.032 0.012 +0.004 -0.005 0.005 0.026 (T.P.) 0.063±0.008 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 0.004±0.004 5°±5° 0.119 MAX. S80GC-65-3B9-4
Remark shape material version same those corresponding mass-produced product.
µPD784035Y, 784036Y, 784037Y, 784038Y
PLASTIC
detail lead
NOTE Each lead centerline located within 0.13 (0.005 inch) true position (T.P.) maximum material condition.
ITEM MILLIMETERS 17.20±0.20 14.00±0.20 14.00±0.20 17.20±0.20 0.825 0.825 0.32±0.06 0.13 0.65 (T.P.) 1.60±0.20 0.80±0.20 0.17 +0.03 -0.07 0.10 1.40±0.10 0.125±0.075 1.70 MAX. INCHES 0.677±0.008 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.677±0.008 0.032 0.032 0.013 +0.002 -0.003 0.005 0.026 (T.P.) 0.063±0.008 0.031 +0.009 -0.008 0.007 +0.001 -0.003 0.004 0.055±0.004 0.005±0.003 0.067 MAX. P80GC-65-8BT
Remark shape material version same those corresponding mass-produced product.
µPD784035Y, 784036Y, 784037Y, 784038Y
PLASTIC TQFP (FINE PITCH)
detail lead
NOTE Each lead centerline located within 0.10 (0.004 inch) true position (T.P.) maximum material condition.
ITEM MILLIMETERS 14.0±0.2 12.0±0.2 12.0±0.2 14.0±0.2 1.25 1.25 0.22 +0.05 -0.04 0.10 (T.P.) 1.0±0.2 0.5±0.2 0.145 +0.055 -0.045 0.10 1.05 0.05±0.05 5°±5° 1.27 MAX. INCHES 0.551 +0.009 -0.008 0.472 +0.009 -0.008 0.472 +0.009 -0.008 0.551 +0.009 -0.008 0.049 0.049 0.009±0.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.006±0.002 0.004 0.041 0.002±0.002 5°±5° 0.050 MAX. P80GK-50-BE9-4
Remark shape material version same those corresponding mass-produced product.
µPD784035Y, 784036Y, 784037Y, 784038Y
RECOMMENDED SOLDERING CONDITIONS
recommended that µPD784035Y, 784036Y, 784037Y, 784038Y soldered under following conditions. details recommended soldering conditions, refer information document "Semiconductor Device Mounting Technology Manual" (C10535E). soldering methods conditions other than those recommended, please consult representative. Caution soldering conditions undefined because these products currently under development. Table 15-1. Soldering Conditions Surface Mount Type (1/2) 80-pin plastic 2.7-mm thick)
80-pin plastic 2.7-mm thick) 80-pin plastic 2.7-mm thick) 80-pin plastic 2.7-mm thick)
Soldering Method Infrared reflow Wave soldering Soldering Conditions Package peak temperature: 235°C, Reflow time: seconds less (210°C more) Number reflow processes: less Package peak temperature: 215°C, Reflow time: seconds less (200°C more) Number reflow processes: less Solder bath temperature: 260°C less, Flow time: seconds less, Number flow processes: Preheating temperature: 120°C max. (package surface temperature) temperature: 300°C less, Flow time: seconds less (for side device) Recommended Condition Symbol IR35-00-3 VP15-00-3 WS60-00-1
Partial heating
Caution apply more different soldering methods chip (except partial heating method). 80-pin plastic 1.4-mm thick)
80-pin plastic 1.4-mm thick) 80-pin plastic 1.4-mm thick) 80-pin plastic 1.4-mm thick)
Soldering Method Infrared reflow Wave soldering Soldering Conditions Package peak temperature: 235°C, Reflow time: seconds less (210°C more) Number reflow processes: less Package peak temperature: 215°C, Reflow time: seconds less (200°C more) Number reflow processes: less Solder bath temperature: 260°C less, Flow time: seconds less, Number flow processes: Preheating temperature: 120°C max. (package surface temperature) temperature: 300°C less, Flow time: seconds less (for side device) Recommended Condition Symbol IR35-00-2 VP15-00-2 WS60-00-1
Partial heating
Caution apply more different soldering methods chip (except partial heating method).
µPD784035Y, 784036Y, 784037Y, 784038Y
Table 15-1. Soldering Conditions Surface Mount Type (2/2) 80-pin plastic TQFP (fine-pitch)
80-pin plastic TQFP (fine-pitch)
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235°C, Reflow time: seconds less (210°C more) Number reflow processes: less Exposure limit: daysNote hours pre-baking required 125°C afterward) Package peak temperature: 215°C, Reflow time: seconds less (200°C more) Number reflow processes: less Exposure limit: daysNote hours pre-baking required 125°C afterward) temperature: 300°C less, Flow time: seconds less (per side device) VP15-107-2 Recommended Condition Symbol IR35-107-2
Partial heating
Note
Maximum number days during which product stored temperature 25°C relative humidity less after dry-pack package opened.
Caution apply more different soldering methods chip (except partial heating method).
µPD784035Y, 784036Y, 784037Y, 784038Y
APPENDIX DEVELOPMENT TOOLS
following development tools available supporting development system using µPD784038Y. Language processor software RA78K4Note CC78K4Note CC78K4-LNote Assembler package common 78K/IV Series compiler package common 78K/IV Series compiler library source file common 78K/IV Series
PROM writing tool PG-1500 PA-78P4026GC PA-78P4038GK PA-78P4026KK PG-1500 controllerNote Debugging tool IE-784000-R IE-784000-R-BK IE-784038-R-EM1 IE-784000-R-EM IE-70000-98-IF-B IE-70000-98N-IF IE-70000-PC-IF-B IE-78000-R-SV3 EP-78230GC-R EP-78054GK-R EV-9200GC-80 TGK-080SDW EV-9900 SM78K4Note ID78K4Note DF784038Note Real-time RX78K/IVNote MX78K4Note Real-time 78K/IV Series 78K/IV Series Interface adapter when PC-9800 series (except notebook type) used host machine Interface adapter cable when notebook type PC-9800 series used host machine Interface adapter when PC/ATis used host machine Interface adapter cable when used host machine Emulation probe 80-pin plastic (GC-3B9, GC-8BT type) common µPD784038Y Subseries Emulation probe 80-pin plastic TQFP (fine pitch) (GK-BE9 type) common In-circuit emulator common 78K/IV Series Break board common 78K/IV Series Emulation board evaluation µPD784038Y Subseries PG-1500 control program PROM program writer Programmer adapter connected PG-1500
µPD784038Y Subseries
Socket mounted board target system created 80-pin plastic (GC-3B9, GC-8BT type) Adapter mounted board target system created 80-pin plastic TQFP (fine pitch) (GK-BE9) used remove µPD78P4038YKK-T from EV-9200GC-80 System simulator common 78K/IV Series Integrated debugger IE-784000-R Device file µPD784038Y Subseries
µPD784035Y, 784036Y, 784037Y, 784038Y
Notes.
PC-9800 series (MS-DOSTM) base PC/AT compatible machine DOSTM, WindowsTM, MS-DOS, DOSTM) base HP9000 series 700(HP-UXTM) base SPARCstation (SunOSTM) base NEWS(NEWS-OSTM) base PC-9800 series (MS-DOS) base PC/AT compatible machine DOS, Windows, MS-DOS, DOS) base PC-9800 series (MS-DOS+Windows) base PC/AT compatible machine DOS, Windows, MS-DOS, DOS) base HP9000 series (HP-UX) base SPARCstation (SunOS) base PC-9800 series (MS-DOS) base PC/AT compatible machine DOS, Windows, MS-DOS, DOS) base HP9000 series (HP-UX) base SPARCstation (SunOS) base
Remarks RA78K4, CC78K4, SM78K4, ID78K4 used combination with DF784038. TGK-080SDW product TOKYO ELETECH CORPORATION (Tokyo, 03-5295-1661). Consult sales representative about purchasing.
µPD784035Y, 784036Y, 784037Y, 784038Y
APPENDIX RELATED DOCUMENTS
Documents related device
Document Name Japanese Document English U11504E This manual U10742E U11316J U10905E U10095E
µPD784031Y Data Sheet µPD784035Y, 784036Y, 784037Y, 784038Y Data Sheet µPD78P4038Y Data Sheet
µPD784038, 784038Y Subseries User's Manual Hardware µPD784038Y Subseries Special Function Register Table 78K/IV Series User's Manual Instructions 78K/IV Series Instruction Table 78K/IV Series Instruction 78K/IV Series Application Note Software Basics
U11504J U10741J U10742J U11316J U11091J U10905J U10594J U10595J U10095J
Documents related development tools (User's Manuals)
Document Name Japanese RA78K4 Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor CC78K4 Series Operation Language CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOS) Based PG-1500 Controller Series DOS) Based IE-784000-R IE-784038-R-EM1 EP-78230 EP-78054GK-R SM78K4 System Simulator Windows Based SM78K Series System Simulator Reference External component user open interface specification ID78K4 Integrated Debugger Windows Based ID78K4 Integrated Debugger HP9000 Series (HP-UX) Based Reference Reference U10440J U11960J U10440E Under preparation U11334J U11162J EEU-817 EEU-960 EEU-961 U12322J U11940J EEU-704 EEU-5008 EEU-5004 U11383J EEU-985 EEU-932 U10093J U10092J Document English U11334E EEU-1402 EEU-1335 EEU-1291 U10540E EEU-1534 U11383E EEU-1515 EEU-1468 U10093E U10092E
Caution contents above related documents subject change without notice. sure latest edition document designing.
µPD784035Y, 784036Y, 784037Y, 784038Y
Documents related embedded software (User's Manual)
Document Name Japanese 78K/IV Series Real-Time Basics Installation Debugger 78K/IV Series MX78K4 Basics U10603J U10604J U10364J U11779J Document English U10603E U10604E
Other documents
Document Name Japanese Package Manual Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Devices Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide Quality Assurance Semiconductor Devices Guide Microcontroller-Related Products Third Parties C10943X C10535J C11531J C10983J MEM-539 C11893J U11416J C10535E C11531E C10983E MEI-1202 Document English
Caution contents above related documents subject change without notice. sure latest edition document designing.
µPD784035Y, 784036Y, 784037Y, 784038Y
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
µPD784035Y, 784036Y, 784037Y, 784038Y
Regional Information
Some information contained this document vary from country country. Before using product your application, please contact office your country obtain list authorized representatives distributors. They will verify: Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290
Electronics (France) S.A.
Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics Taiwan Ltd. Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
Brasil S.A.
Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689
J96.
µPD784035Y, 784036Y, 784037Y, 784038Y
Caution Purchase components conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips. EEPROM IEBUS trademarks Corporation. MS-DOS Windows either registered trademarks trademarks Microsoft Corporatin United States and/or other countries. DOS, PC/AT, trademarks International Business Machines Corporation. HP9000 series HP-UX trademarks Hewlett-Packard Corporation. SPARCstation trademark SPARC International, Inc. SunOS trademark Microsystems, Inc. NEWS NEWS-OS trademarks Sony Corporation. related documents indicated this publication include preliminary versions. However, preliminary versions marked such.
export this product from Japan regulated Japanese government. export this product prohibited without governmental license, need which must judged customer. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative.
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance. Anti-radioactive design implemented this product.
96.5
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