Download

PDF Abstract Text:

SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS

D Controlled Baseline D D D D

SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
D Controlled Baseline D D D D
- One Assembly / Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree Low-Price / High-Performance Floating-Point Digital Signal Processors (DSPs): 320C67x (SM320C6712, C6712C, C6712D) - Eight 32-Bit Instructions / Cycle - 100-, 167-MHz Clock Rates - 10-, 6-ns Instruction Cycle Times - 600, 1000 MFLOPS Advanced Very Long Instruction Word (VLIW) C67x DSP Core - Eight Highly Independent Functional Units: - Four ALUs (Floating- and Fixed-Point) - Two ALUs (Fixed-Point) - Two Multipliers (Floating- and Fixed-Point) - Load-Store Architecture With 32 32-Bit General-Purpose Registers - Instruction Packing Reduces Code Size - All Instructions Conditional Instruction Set Features - Hardware Support for IEEE Single-Precision and Double-Precision Instructions - Byte-Addressable (8-, 16-, 32-Bit Data) - 8-Bit Overflow Protection - Saturation - Bit-Field Extract, Set, Clear - Bit-Counting - Normalization Device Configuration - Boot Mode: 8- and 16-Bit ROM Boot - Endianness: Little Endian (12 / 12C) Little Endian, Big Endian (12D)
D L1 / L2 Memory Architecture
- 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped) - 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative) - 512K-Bit (64K-Byte) L2 Unified Mapped RAM / Cache (Flexible Data / Program Allocation) Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels) 16-Bit External Memory Interface (EMIF) - Glueless Interface to Asynchronous Memories: SRAM and EPROM - Glueless Interface to Synchronous Memories: SDRAM and SBSRAM - 256M-Byte Total Addressable External Memory Space Two Multichannel Buffered Serial Ports (McBSPs) - Direct Interface to T1 / E1, MVIP, SCSA Framers - ST-Bus-Switching Compatible - Up to 256 Channels Each - AC97-Compatible - Serial-Peripheral-Interface (SPI) Compatible (Motorola) Two 32-Bit General-Purpose Timers Flexible Phase-Locked-Loop (PLL) Clock Generator C6712 Flexible Software-Configurable PLL-Based Clock Generator Module C6712C / C6712D A Dedicated General-Purpose Input / Output (GPIO) Module With 5 Pins 12C / 12D IEEE-1149.1 (JTAG) Boundary-Scan-Compatible CMOS Technology - 0.13-µm / 6-Level Copper Metal Process (C6712C / C6712D) - 0.18-µm / 5-Level Metal Process (C6712)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
320C67x and C67x are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc. Other trademarks are the property of their respective owners.
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but
is not limited to, Highly Accelerated Stress Test (HAST) or biased 85 / 85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
This document contains information on products in more than one phase of development. The status of each device is indicated on the page(s) specifying its electrical characteristics.
Copyright 2004, Texas Instruments Incorporated
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
Table of Contents
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
GFN BGA package (bottom view) C6712 only
GFN 256-PIN BALL GRID ARRAY (BGA) PACKAGE ( BOTTOM VIEW )
GDP BGA package (bottom view) C6712C / 12D only
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
description
TMS320C6000 and C6000 are trademarks of Texas Instruments. Windows is a registered trademark of the Microsoft Corporation. Throughout the remainder of this document, the SM320C6712-EP, SM320C6712C-EP, and SM320C6712D-EP shall be referred to as 320C67x or C67x where generic, and where specific, their individual full device part numbers will be used or abbreviated as C6712, C6712C, C6712D, 12, 12C, or 12D, etc.
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
device characteristics
Table 1 provides an overview of the C6712 / C6712C / C6712D DSPs. The table shows significant features of each device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count. For more details on the C6000 DSP device part numbers and part numbering, see Table 17 and Figure 5. Table 1. Characteristics of the C6712, C6712C, and C6712D Processors
HARDWARE FEATURES EMIF EDMA Peripherals McBSPs 32-Bit Timers GPIO Module Size (Bytes) On-Chip Memory Organization INTERNAL CLOCK SOURCE ECLKIN SYSCLK3 or ECLKIN CPU clock frequency CPU / 2 clock frequency SYSCLK2 CPU / 4 clock frequency 1 / 2 of SYSCLK2 SYSCLK2 1 2 - 2 - - 72K C6712 (FLOATING-POINT DSP) 1 1 1 - 2 - 2 1 72K C6712C / C6712D (FLOATING-POINT DSPs)
4K-Byte (4KB) L1 Program (L1P) Cache 4KB L1 Data (L1D) Cache 64KB Unified Mapped RAM / Cache (L2) 0x0202 100 10 ns (C6712-100) 1.8 3.3 Bypass (x1), x4 - 256-Pin BGA (GFN) 0.18 µm PP 0x0203 167 6 ns (C6712D-167) 6 ns (C6712C-167) 1.20 3.3 - / 1, / 2, / 3, .., / 32 x4, x5, x6, .., x25 / 1, / 2, / 3, .., / 32 272-Pin BGA (GDP) 0.13 µm PP (C6712C) PD (C6712D)
CPU ID+ CPU Rev ID Frequency Cycle Time Voltage PLL Options Clock Generator Options BGA Package Process Technology
Control Status Register (CSR.31:16) MHz ns Core (V) I / O (V) CLKIN frequency multiplier Prescaler Multiplier Postscaler 27 x 27 mm µm
Product Status Product Preview (PP) Advance Information (AI) Production Data (PD)
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. This value is compatible with existing 1.26V designs.
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
device compatibility
The 320C6712 and C6211 / C6711 devices are pin-compatible thus, making new system designs easier and providing faster time to market. The following list summarizes the device characteristic differences among the C6211, C6211B, C6711, C6711B, C6711C, C6711D, C6712, C6712C, and C6712D devices:
D The C6211 and C6211B devices have a fixed-point TMS320C62x DSP core (CPU), while the C6711,
C6711B, C6711C, C6711D, C6712, C6712C, and C6712D devices have a floating-point C67x CPU.
D The C6211, C6211B, C6711, C6711B, C6711C, and C6711D devices have a 32-bit EMIF, while the C6712,
C6712C, and C6712D devices have a 16-bit EMIF.
D The C6211, C6211B, C6711, C6711B, C6711C, and C6711D devices feature an HPI, while the C6712,
C6712C, and C6712D devices do not.
D The C6712, C6712C, and C6712D devices have dedicated device configuration pins, BOOTMODE,
LENDIAN, and EMIFBE (12D only) that specify the boot-load operation and device endianness, respectively, during reset. On the C6211 / C6211B and C6711 / C6711B / C6711C / C6711D devices, these configuration pins are integrated with the HPI pins.
D The C6211 / C6211B device runs at -167 and -150 MHz clock speeds (with a C6211BGFNA extended
temperature device that also runs at -150 MHz), while the C6711 / C6711B device runs at -150 and -100 MHz (with a C6711BGFNA extended temperature device that also runs at -100 MHz) and the C6711C / C6711D device runs at -200 clock speed (with a C6711CGDPA extended temperature device that also runs at -167 MHz). The C6712 device runs at -100 MHz clock speed and the C6712C / C6712D device runs at -167 MHz clock speed.
D The C6211 / C6211B, C6711-100, C6711B and C6712 devices have a core voltage of 1.8 V, the C6711-150
device has a core voltage is 1.9 V, and the C6711C / C6711D and C6712C / C6712D devices operate with a core voltage of 1.20 V.
D There are several enhancements and features that are only available on the C6711C / C6711D and
C6712C / C6712D devices, such as: the CLKOUT3 signal, a software-programmable PLL and PLL Controller, and a GPIO peripheral module. The C6711D and C6712D devices also have additional enhancements such as: EMIF Big Endian mode correctness EMIFBE and the L1D requestor priority to L2 bit "P" bit in the cache configuration (CCFG) register. C6712D supports Big Endian mode.
D The C6712 / C6712C / C6712D is the lowest-cost entry in the TMS320C6000 platform.
For a more detailed discussion on the similarities / differences among the C6211, C6711, and C6712 devices, see the How to Begin Development Today with the TMS320C6211 DSP, How to Begin Development with the TMS320C6711 DSP, and How to Begin Development With the TMS320C6712 DSP application reports (literature number SPRA474, SPRA522, and SPRA693, respectively). For a more detailed discussion on the migration of a C6211, C6211B, C6711, or C6711B device to a TMS320C6711C device, see the Migrating from TMS320C6211(B) / 6711(B) to TMS320C6711C application report (literature number SPRA837). For a more detailed discussion on the migration of a C6712 device to a TMS320C6712C device, see the Migrating from TMS320C6712 to TMS320C6712C application report (literature number SPRA852).
TMS320C62x and C67x are trademarks of Texas Instruments. This value is compatible with existing 1.26V designs.
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
functional block and CPU (DSP core) diagram
SDRAM SBSRAM SRAM ROM / FLASH I / O Devices Timer 0 C67x CPU (DSP Core) Timer 1 Enhanced DMA Controller (16 channel) L2 Memory 4 Banks 64K Bytes Total Instruction Fetch Instruction Dispatch Instruction Decode Data Path A A Register File Data Path B B Register File Control Registers Control Logic Test In-Circuit Emulation Interrupt Control
C6712 / C6712C / C6712D Digital Signal Processors
External Memory Interface (EMIF) L1P Cache Direct Mapped 4K Bytes Total
Framing Chips: H.100, MVIP, SCSA, T1, E1 AC97 Devices, SPI Devices, Codecs
Multichannel Buffered Serial Port 1 (McBSP1)
Multichannel Buffered Serial Port 0 (McBSP0)
.L1 .S1 .M1 .D1
.D2 .M2 .S2 .L2
Interrupt Selector Power-Down Logic
L1D Cache 2-Way Set Associative 4K Bytes Total PLL
Boot Configuration
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
CPU (DSP core) description
C62x is a trademark of Texas Instruments.
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
CPU (DSP core) description (continued)
.L1 src2
dst long dst long src
LD1 32 MSB ST1
Data Path A
dst src1 .M1 src2
LD1 32 LSB
dst src1 src2
src2 src1 dst
LD2 32 LSB
.M2 src1 dst src2
Data Path B
src1 dst long dst long src
LD2 32 MSB ST2
In addition to fixed-point instructions, these functional units execute floating-point instructions.
Figure 1. 320C67x CPU (DSP Core) Data Paths
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
long src long dst dst .L2 src2
long src long dst dst .S1 src1
Register File A (A0-A15) 2X 1X Register File B (B0-B15) Control Register File 9
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
memory map summary
Table 2 shows the memory map address ranges of the C6712 / C6712C / C6712D devices. Internal memory is always located at address 0 and can be used as both program and data memory. The C6712 / C6712C / C6712D configuration registers for the common peripherals are located at the same hex address ranges. The external memory address ranges in the C6712 / C6712C / C6712D devices begin at the address location 0x8000 0000. Table 2. 320C6712 / C6712C / C6712D Memory Map Summary
MEMORY BLOCK DESCRIPTION Internal RAM (L2) Reserved External Memory Interface (EMIF) Registers L2 Registers Reserved McBSP 0 Registers McBSP 1 Registers Timer 0 Registers Timer 1 Registers Interrupt Selector Registers Device Configuration Registers C6712C / C6712D only Reserved EDMA RAM and EDMA Registers Reserved GPIO Registers C6712C / C6712D only Reserved PLL Controller Registers C6712C / C6712D only Reserved QDMA Registers Reserved McBSP 0 Data / Peripheral Data Bus McBSP 1 Data / Peripheral Data Bus Reserved Reserved EMIF CE0 EMIF CE1 EMIF CE2 EMIF CE3 Reserved BLOCK SIZE (BYTES) 64K 24M - 64K 256K 256K 256K 256K 256K 256K 256K 512 4 256K - 516 256K 768K 16K 480K 8K 4M + 520K 52 736M - 52 64M 64M 64M 1G + 64M 256M 256M 256M 256M 1G HEX ADDRESS RANGE 0000 0000 - 0000 FFFF 0001 0000 - 017F FFFF 0180 0000 - 0183 FFFF 0184 0000 - 0187 FFFF 0188 0000 - 018B FFFF 018C 0000 - 018F FFFF 0190 0000 - 0193 FFFF 0194 0000 - 0197 FFFF 0198 0000 - 019B FFFF 019C 0000 - 019C 01FF 019C 0200 - 019C 0203 019C 0204 - 019F FFFF 01A0 0000 - 01A3 FFFF 01A4 0000 - 01AF FFFF 01B0 0000 - 01B0 3FFF 01B0 4000 - 01B7 BFFF 01B7 C000 - 01B7 DFFF 01B7 E000 - 01FF FFFF 0200 0000 - 0200 0033 0200 0034 - 2FFF FFFF 3000 0000 - 33FF FFFF 3400 0000 - 37FF FFFF 3800 0000 - 3BFF FFFF 3C00 0000 - 7FFF FFFF 8000 0000 - 8FFF FFFF 9000 0000 - 9FFF FFFF A000 0000 - AFFF FFFF B000 0000 - BFFF FFFF
C000 0000 - FFFF FFFF The number of EMIF address pins (EA21:2) limits the maximum addressable memory (SDRAM) to 128MB per CE space. To get 256MB of addressable memory, additional general-purpose output pin or external logic is required.
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
peripheral register descriptions
Table 3 through Table 13 identify the peripheral registers for the C6712 / C6712C / C6712D devices by their register names, acronyms, and hex address or hex address range. For more detailed information on the register contents, bit names, and their descriptions, see the specific peripheral reference guide listed in the TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190). Table 3. EMIF Registers
HEX ADDRESS RANGE 0180 0000 0180 0004 0180 0008 0180 000C 0180 0010 0180 0014 0180 0018 0180 001C 0180 0020 0180 0024 - 0183 FFFF ACRONYM GBLCTL CECTL1 CECTL0 - CECTL2 CECTL3 SDCTL SDTIM SDEXT - EMIF global control EMIF CE1 space control EMIF CE0 space control Reserved EMIF CE2 space control EMIF CE3 space control EMIF SDRAM control EMIF SDRAM refresh control EMIF SDRAM extension Reserved REGISTER NAME
Table 4. L2 Cache Registers
HEX ADDRESS RANGE 0184 0000 0184 4000 0184 4004 0184 4010 0184 4014 0184 4020 0184 4024 0184 4030 0184 4034 0184 5000 0184 5004 0184 8200 0184 8204 0184 8208 0184 820C 0184 8240 0184 8244 0184 8248 0184 824C 0184 8280 0184 8284 0184 8288 0184 828C 0184 82C0 0184 82C4 0184 82C8 0184 82CC 0184 82D0 - 0187 FFFF ACRONYM CCFG L2WBAR L2WWC L2WIBAR L2WIWC L1PIBAR L1PIWC L1DWIBAR L1DWIWC L2WB L2WBINV MAR0 MAR1 MAR2 MAR3 MAR4 MAR5 MAR6 MAR7 MAR8 MAR9 MAR10 MAR11 MAR12 MAR13 MAR14 MAR15 - Cache configuration register L2 writeback base address register L2 writeback word count register L2 writeback-invalidate base address register L2 writeback-invalidate word count register L1P invalidate base address register L1P invalidate word count register L1D writeback-invalidate base address register L1D writeback-invalidate word count register L2 writeback all register L2 writeback-invalidate all register Controls CE0 range 8000 0000 - 80FF FFFF Controls CE0 range 8100 0000 - 81FF FFFF Controls CE0 range 8200 0000 - 82FF FFFF Controls CE0 range 8300 0000 - 83FF FFFF Controls CE1 range 9000 0000 - 90FF FFFF Controls CE1 range 9100 0000 - 91FF FFFF Controls CE1 range 9200 0000 - 92FF FFFF Controls CE1 range 9300 0000 - 93FF FFFF Controls CE2 range A000 0000 - A0FF FFFF Controls CE2 range A100 0000 - A1FF FFFF Controls CE2 range A200 0000 - A2FF FFFF Controls CE2 range A300 0000 - A3FF FFFF Controls CE3 range B000 0000 - B0FF FFFF Controls CE3 range B100 0000 - B1FF FFFF Controls CE3 range B200 0000 - B2FF FFFF Controls CE3 range B300 0000 - B3FF FFFF Reserved REGISTER NAME
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
peripheral register descriptions (continued)
Table 5. Interrupt Selector Registers
Table 6. Device Registers
HEX ADDRESS RANGE ACRONYM REGISTER DESCRIPTION This C6712C / C6712D-only register allows the user control of the EMIF input clock source. For more detailed information on the device configuration register, see the Device Configurations section of this data sheet. Identifies which CPU and defines the silicon revision of the CPU. This register also offers the user control of device operation. For more detailed information on the CPU Control Status Register, see the CPU CSR Register Description section of this data sheet.
019C 0200
DEVCFG
Device Configuration
019C 0204 - 019F FFFF
Reserved
CPU Control Status Register
Table 7. EDMA Parameter RAM
HEX ADDRESS RANGE 01A0 0000 - 01A0 0017 01A0 0018 - 01A0 002F 01A0 0030 - 01A0 0047 01A0 0048 - 01A0 005F 01A0 0060 - 01A0 0077 01A0 0078 - 01A0 008F 01A0 0090 - 01A0 00A7 01A0 00A8 - 01A0 00BF 01A0 00C0 - 01A0 00D7 01A0 00D8 - 01A0 00EF 01A0 00F0 - 01A0 00107 01A0 0108 - 01A0 011F 01A0 0120 - 01A0 0137 01A0 0138 - 01A0 014F 01A0 0150 - 01A0 0167 01A0 0168 - 01A0 017F 01A0 0180 - 01A0 0197 01A0 0198 - 01A0 01AF .. 01A0 07E0 - 01A0 07F7 01A0 07F8 - 01A0 07FF - - ACRONYM - - - - - - - - - - - - - - - - - - REGISTER NAME Parameters for Event 0 (6 words) or Reload / Link Parameters for other Event Parameters for Event 1 (6 words) or Reload / Link Parameters for other Event Parameters for Event 2 (6 words) or Reload / Link Parameters for other Event Parameters for Event 3 (6 words) or Reload / Link Parameters for other Event Parameters for Event 4 (6 words) or Reload / Link Parameters for other Event Parameters for Event 5 (6 words) or Reload / Link Parameters for other Event Parameters for Event 6 (6 words) or Reload / Link Parameters for other Event Parameters for Event 7 (6 words) or Reload / Link Parameters for other Event Parameters for Event 8 (6 words) or Reload / Link Parameters for other Event Parameters for Event 9 (6 words) or Reload / Link Parameters for other Event Parameters for Event 10 (6 words) or Reload / Link Parameters for other Event Parameters for Event 11 (6 words) or Reload / Link Parameters for other Event Parameters for Event 12 (6 words) or Reload / Link Parameters for other Event Parameters for Event 13 (6 words) or Reload / Link Parameters for other Event Parameters for Event 14 (6 words) or Reload / Link Parameters for other Event Parameters for Event 15 (6 words) or Reload / Link Parameters for other Event Reload / link parameters for Event 0-15 Reload / link parameters for Event 0-15 .. Reload / link parameters for Event 0-15
Scratch pad area (2 words) The C6712 / C6712C / C6712D device has 85 EDMA parameters total: 16 Event / Reload parameters and 69 Reload-only parameters.
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
peripheral register descriptions (continued)
For more details on the EDMA parameter RAM 6-word parameter entry structure, see Figure 2.
31 Word 0 Word 1 Word 2 Word 3 Word 4 Word 5 EDMA Channel Options Parameter (OPT) EDMA Channel Source Address (SRC) Array / Frame Count (FRMCNT) Array / Frame Index (FRMIDX) Element Count Reload (ELERLD) Element Count (ELECNT) Element Index (ELEIDX) Link Address (LINK) EDMA Channel Destination Address (DST)
EDMA Parameter OPT SRC CNT DST IDX RLD
Figure 2. EDMA Channel Parameter Entries (6 Words) for Each EDMA Event Table 8. EDMA Registers
HEX ADDRESS RANGE 01A0 0800 - 01A0 FEFC 01A0 FF00 01A0 FF04 01A0 FF08 - 01A0 FF0B 01A0 FF0C 01A0 FF1F - 01A0 FFDC 01A0 FFE0 01A0 FFE4 01A0 FFE8 01A0 FFEC 01A0 FFF0 01A0 FFF4 01A0 FFF8 01A0 FFFC 01A1 0000 - 01A3 FFFF ACRONYM - ESEL0 ESEL1 - ESEL3 - PQSR CIPR CIER CCER ER EER ECR ESR - Reserved EDMA event selector 0 C6712C / C6712D Only EDMA event selector 1 C6712C / C6712D Only Reserved EDMA event selector 3 C6712C / C6712D Only Reserved Priority queue status register Channel interrupt pending register Channel interrupt enable register Channel chain enable register Event register Event enable register Event clear register Event set register Reserved REGISTER NAME
Table 9. Quick DMA (QDMA) and Pseudo Registers
HEX ADDRESS RANGE 0200 0000 0200 0004 0200 0008 0200 000C 0200 0010 0200 0014 - 0200 001C 0200 0020 0200 0024 0200 0028 0200 002C 0200 0030 ACRONYM QOPT QSRC QCNT QDST QIDX - QSOPT QSSRC QSCNT QSDST QSIDX QDMA options parameter register QDMA source address register QDMA frame count register QDMA destination address register QDMA index register Reserved QDMA pseudo options register QDMA pseudo source address register QDMA pseudo frame count register QDMA pseudo destination address register REGISTER NAME
QDMA pseudo index register All the QDMA and Pseudo registers are write-accessible only
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
peripheral register descriptions (continued)
Table 10. PLL Controller Registers C6712C / C6712D Only
HEX ADDRESS RANGE 01B7 C000 01B7 C004 - 01B7 C0FF 01B7 C100 01B7 C104 - 01B7 C10F 01B7 C110 01B7 C114 01B7 C118 01B7 C11C 01B7 C120 01B7 C124 01B7 C128 - 01B7 DFFF ACRONYM PLLPID - PLLCSR - PLLM PLLDIV0 PLLDIV1 PLLDIV2 PLLDIV3 OSCDIV1 - REGISTER NAME Peripheral identification register (PID) Reserved PLL control / status register Reserved PLL multiplier control register PLL controller divider 0 register PLL controller divider 1 register PLL controller divider 2 register PLL controller divider 3 register Oscillator divider 1 register Reserved C6712D value: 0x00010801 for PLL Controller C6712C value: 0x00010801 for PLL Controller
Table 11. GPIO Registers C6712C / C6712D Only
HEX ADDRESS RANGE 01B0 0000 01B0 0004 01B0 0008 01B0 000C 01B0 0010 01B0 0014 01B0 0018 01B0 001C 01B0 0020 01B0 0024 01B0 0028 - 01B0 3FFF ACRONYM GPEN GPDIR GPVAL - GPDH GPHM GPDL GPLM GPGC GPPOL - REGISTER NAME GPIO enable register GPIO direction register GPIO value register Reserved GPIO delta high register GPIO high mask register GPIO delta low register GPIO low mask register GPIO global control register GPIO interrupt polarity register Reserved
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
peripheral register descriptions (continued)
Table 12. Timer 0 and Timer 1 Registers
HEX ADDRESS RANGE TIMER 0 0194 0000 TIMER 1 0198 0000 ACRONYM REGISTER NAME COMMENTS Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin. Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. Contains the current value of the incrementing counter. -
Timer x control register
Timer x period register
0194 0008 0194 000C - 0197 FFFF
0198 0008 0198 000C - 019B FFFF
CNTx -
Timer x counter register Reserved
Table 13. McBSP0 and McBSP1 Registers
HEX ADDRESS RANGE McBSP0 018C 0000 3000 0000 - 33FF FFFF 018C 0004 3000 0000 - 33FF FFFF 018C 0008 018C 000C 018C 0010 018C 0014 018C 0018 018C 001C 018C 0020 018C 0024 018C 0028 - 018F FFFF McBSP1 0190 0000 3400 0000 - 37FF FFFF 0190 0004 3400 0000 - 37FF FFFF 0190 0008 0190 000C 0190 0010 0190 0014 0190 0018 0190 001C 0190 0020 0190 0024 0190 0028 - 0193 FFFF ACRONYM REGISTER DESCRIPTION McBSPx data receive register via Configuration Bus DRRx DRRx DXRx DXRx SPCRx RCRx XCRx SRGRx MCRx RCERx XCERx PCRx - The CPU and EDMA controller can only read this register they cannot write to it. McBSPx data receive register via Peripheral Data Bus McBSPx data transmit register via Configuration Bus McBSPx data transmit register via Peripheral Data Bus McBSPx serial port control register McBSPx receive control register McBSPx transmit control register McBSPx sample rate generator register McBSPx multichannel control register McBSPx receive channel enable register McBSPx transmit channel enable register McBSPx pin control register Reserved
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
signal groups description
Reset and Interrupts Clock / PLL
BIG / LITTLE ENDIAN
TMS TDO TDI TCK TRST EMU0 EMU1 EMU2 EMU3 EMU4 EMU5
RSV RSV IEEE Standard 1149.1 (JTAG) Emulation Reserved
RSV RSV
BOOTMODE Control / Status
BOOTMODE1 BOOTMODE0
16 ED15:0 CE3 CE2 CE1 CE0 EA21:2 20 Data Memory Control Memory Map Space Select ECLKIN ECLKOUT ARE / SDCAS / SSADS AOE / SDRAS / SSOE AWE / SDWE / SSWE ARDY
Address Bus Arbitration
BE1 BE0
HOLD HOLDA BUSREQ
Byte Enables EMIF (16-bit) (External Memory Interface)
Figure 3. CPU (DSP Core) and Peripheral Signals
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
signal groups description (continued)
TOUT1 TINP1
Timer 1
Timer 0
TOUT0 TINP0
Timers
McBSP1
McBSP0
CLKX1 FSX1 DX1
Transmit
CLKX0 FSX0 DX0
CLKR1 FSR1 DR1
Receive
CLKR0 FSR0 DR0
CLKS1
Clock
CLKS0
McBSPs (Multichannel Buffered Serial Ports)
General-Purpose Input / Output (GPIO) Port For proper C6712C / C6712D device operation, these pins must be externally pulled up with a 10-k resistor. Only the C6712C / C6712D device supports the general-purpose input / output (GPIO) port peripheral.
Figure 4. Peripheral Signals
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
DEVICE CONFIGURATIONS
On the C6712, C6712C, and C6712D devices, bootmode and certain device configurations / peripheral selections are determined at device reset. For the C6712C / C6712D devices only, other device configurations (e.g., EMIF input clock source) are software-configurable via the device configurations register (DEVCFG) address location 0x019C0200 after device reset.
device configurations at device reset
Table 14 describes the C6712 / 12C / 12D device configuration pins, which are set up via internal or external pullup / pulldown resistors through the LENDIAN, EMIFBE 12D only, BOOTMODE1:0, and CLKMODE0 pins. These configuration pins must be in the desired state until reset is released. For more details on these device configuration pins, see the Terminal Functions table of this data sheet. Table 14. Device Configurations Pins at Device Reset (LENDIAN, EMIFBE 12D only, BOOTMODE1:0, and CLKMODE0)
LENDIAN
BOOTMODE1:0
C19, C20
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
DEVICE CONFIGURATIONS (CONTINUED) DEVCFG register description C6712C / C6712D only
The device configuration register (DEVCFG) allows the user control of the EMIF input clock source for the C6712C / C6712D device only. For more detailed information on the DEVCFG register control bits, see Table 15 and Table 16. Table 15. Device Configuration Register (DEVCFG) Address location: 0x019C0200 - 0x019C02FF
Table 16. Device Configuration (DEVCFG) Register Selection Bit Descriptions
EKSRC
Reserved
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
TERMINAL FUNCTIONS
The terminal functions table identifies the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type (I, O / Z, or I / O / Z), whether the pin has any internal pullup / pulldown resistors and a functional pin description. For more detailed information on device configuration, see the Device Configurations section of this data sheet.
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
Terminal Functions
CLKOUT1
CLKOUT2
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
Terminal Functions (Continued)
EMU1 EMU0
BOOTMODE1 BOOTMODE0
C19 C20
LENDIAN
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
Terminal Functions (Continued)
SIGNAL NAME PIN NO. GFN GDP TYPE IPD / IPU RESETS AND INTERRUPTS RESET A13 A13 I IPU Device reset. When using Boundary Scan mode on the C6712C / C6712D device, drive the EMU1:0 and RESET pins low. For the C6712D device, this pin does not have an IPU. Nonmaskable interrupt · Edge-driven (rising edge) Any noise on the NMI pin may trigger an NMI interrupt therefore, if the NMI pin is not used, it is recommended that the NMI pin be grounded versus relying on the IPD. External interrupts C6712 · Edge-driven · Polarity independently selected via the External Interrupt Polarity Register bits (EXTPOL.3:0) I IPU DESCRIPTION
CE3 CE2 CE1 CE0 BE1 BE0
V6 W6 W18 V17 U19 V20
HOLDA HOLD BUSREQ ECLKIN
J18 J17 J19 Y11
EMIF - ASYNCHRONOUS / SYNCHRONOUS DRAM / SYNCHRONOUS BURST SRAM MEMORY CONTROL#
ECLKOUT
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
Terminal Functions (Continued)
SIGNAL NAME PIN NO. GFN GDP TYPE IPD / IPU DESCRIPTION
EMIF - ASYNCHRONOUS / SYNCHRONOUS DRAM / SYNCHRONOUS BURST SRAM MEMORY CONTROL (CONTINUED)# ARE / SDCAS / SSADS AOE / SDRAS / SSOE AWE / SDWE / SSWE ARDY EA21 EA20 EA19 EA18 EA17 EA16 EA15 EA14 EA13 EA12 EA11 EA10 EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2 ED15 ED14 ED13 ED12 ED11 ED10 ED9 V11 W10 V12 Y5 U18 Y18 W17 Y16 V16 Y15 W15 Y14 W14 V14 W13 V10 Y9 V9 Y8 W8 V8 W7 V7 Y6 T19 T20 T18 R20 R19 P20 P18 V11 W10 V12 Y5 U18 Y18 W17 Y16 V16 Y15 W15 Y14 W14 V14 W13 V10 Y9 V9 Y8 W8 V8 W7 V7 Y6 EMIF - DATA# T19 T20 T18 R20 R19 P20 P18 I / O / Z IPU External data O / Z IPU EMIF external address Note: EMIF address numbering for the C6712, C6712C, and C6712D devices start with EA2 to maintain signal name compatibility with other C671x devices (e.g., C6711, C6713) see the 16-bit EMIF addressing scheme in the TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (literature number SPRU266). O / Z O / Z O / Z I IPU IPU IPU IPU Asynchronous memory read enable / SDRAM column-address strobe / SBSRAM address strobe Asynchronous memory output enable / SDRAM row-address strobe / SBSRAM output enable Asynchronous memory write enable / SDRAM write enable / SBSRAM write enable Asynchronous memory ready input EMIF - ADDRESS#
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
Terminal Functions (Continued)
SIGNAL NAME PIN NO. GFN N19 N18 M20 M19 L19 L18 K19 K18 F1 F2 G1 G2 GDP N19 N18 M20 M19 L19 L18 K19 K18 TIMER1 TOUT1 TINP1 TOUT0 TINP0 F1 F2 G1 G2 O I O I IPD IPD IPD IPD Timer 1 or general-purpose output Timer 1 or general-purpose input TIMER0 Timer 0 or general-purpose output Timer 0 or general-purpose input External clock source (as opposed to internal) On the C6712C / 12D device, this pin does not have an internal pulldown (IPD). For proper C6712C / 12D device operation, the CLKS1 pin should either be driven externally at all times or be pulled up with a 10-k resistor to a valid logic level. Because it is common for some ICs to 3-state their outputs at times, a 10-k pullup resistor may be desirable even when an external device is driving the pin. Receive clock Transmit clock Receive data On the C6712C / 12D device, this pin does not have an internal pullup (IPU). For proper C6712C / 12D device operation, the DR1 pin should either be driven externally at all times or be pulled up with a 10-k resistor to a valid logic level. Because it is common for some ICs to 3-state their outputs at times, a 10-k pullup resistor may be desirable even when an external device is driving the pin. Transmit data Receive frame sync I / O / Z IPU External data TYPE IPD / IPU EMIF - DATA (CONTINUED)# ED7 ED6 ED5 ED4 ED3 ED2 ED1 ED0 DESCRIPTION
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
CLKS1
CLKR1 CLKX1
IPD IPD
DX1 FSR1
IPU IPD
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
Terminal Functions (Continued)
SIGNAL NAME PIN NO. GFN K3 H3 G3 J1 H2 J3 H1 GDP K3 H3 G3 J1 H2 J3 H1 TYPE IPD / IPU DESCRIPTION
GENERAL-PURPOSE INPUT / OUTPUT (GPIO) MODULE C6712C / 12D ONLY
RESERVED FOR TEST
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
Terminal Functions (Continued)
SIGNAL NAME RSV RSV PIN NO. GFN A5 D3 GDP A5 - TYPE O O IPD / IPU IPU DESCRIPTION Reserved (leave unconnected, do not connect to power or ground) Reserved (leave unconnected, do not connect to power or ground) Reserved (leave unconnected, do not connect to power or ground) C6712 RSV N2 N2 O Reserved. For proper C6712C / 12D device operation, this pin must be externally pulled up with a 10-k resistor. Reserved (leave unconnected, do not connect to power or ground) Reserved. For proper C6712C / 12D device operation, this pin must be externally pulled up with a 10-k resistor. Reserved (leave unconnected, do not connect to power or ground) IPD Reserved (leave unconnected, do not connect to power or ground) Reserved (leave unconnected, do not connect to power or ground) Reserved (leave unconnected, do not connect to power or ground) ADDITIONAL RESERVED FOR TEST A15 A16 A18 B14 B16 B18 C14 C16 C17 D18 D20 E18 E19 RSV E20 F18 F20 G18 G19 G20 H19 H20 J20 N3 P1 P2 P3 A15 A16 A18 B14 B16 B18 C14 C16 C17 D18 D20 E18 E19 E20 F18 F20 G18 G19 G20 H19 H20 J20 N3 P1 P2 Reserved (leave unconnected, do not connect to power or ground)
RSV RSV RSV RSV RSV RSV
- N1 B5 D7 A12 B11
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
Terminal Functions (Continued)
SIGNAL NAME PIN NO. GFN R2 R3 T1 T2 U1 U2 U3 RSV V1 V2 V4 V5 W4 Y3 Y4 GDP R2 R3 T1 T2 U1 U2 U3 V1 V2 V4 V5 W4 Y3 Reserved (leave unconnected, do not connect to power or ground) TYPE IPD / IPU ADDITIONAL RESERVED FOR TEST DESCRIPTION
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
Terminal Functions (Continued)
SIGNAL NAME PIN NO. GFN A17 B3 B8 B13 C5 C10 D1 D16 D19 F3 H18 J2 M18 N1 DVDD R1 R18 T3 U5 U7 U12 U16 V13 V15 V19 W3 W9 W12 Y7 Y17 - A9 A10 A12 B2 CVDD B19 C3 C7 C18 D5 GDP A17 B3 B8 B13 - C10 D1 D16 D19 F3 H18 J2 M18 - R1 R18 T3 U5 U7 U12 U16 V13 V15 V19 W3 W9 W12 Y7 Y17 A4 A9 A10 - B2 B19 C3 C7 C18 D5 S 1.20-V supply voltage (C6712C / C6712D) 1.8-V supply voltage (C6712) (see the power-supply decoupling portion of this data sheet) S 3.3-V supply voltage (see the power-supply decoupling portion of this data sheet) TYPE SUPPLY VOLTAGE PINS DESCRIPTION
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
Terminal Functions (Continued)
SIGNAL NAME PIN NO. GFN D11 D14 D15 F4 F17 K1 K4 K17 L4 L17 L20 CVDD R4 R17 U6 U10 U11 U14 U15 V3 V18 W2 W19 A1 A2 A11 A14 A19 A20 B1 B4 VSS B11 B15 B20 - C8 C9 D4 D8 GDP D11 D14 D15 F4 F17 K1 K4 K17 L4 L17 L20 R4 R17 U6 U10 U11 U14 U15 V3 V18 W2 W19 GROUND PINS A1 A2 A11 A14 A19 A20 B1 B4 - B15 B20 C6 C8 C9 D4 D8 GND Ground pins S 1.20-V supply voltage (C6712C / C6712D) 1.8-V supply voltage (C6712) (see the power-supply decoupling portion of this data sheet) TYPE DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED)
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
Terminal Functions (Continued)
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
Terminal Functions (Continued)
SIGNAL NAME PIN NO. GFN U13 U17 U20 W1 W5 W11 VSS W16 W20 Y1 Y2 Y13 Y19 - GDP U13 U17 U20 W1 W5 W11 W16 W20 Y1 Y2 Y13 Y19 GND Ground pins TYPE GROUND PINS (CONTINUED) DESCRIPTION
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
development support
TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of C6000 DSP-based applications: Software Development Tools: Code Composer Studio Integrated Development Environment (IDE): including Editor C / C++ / Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP / BIOS), which provides the basic run-time target software needed to support any DSP application. Hardware Development Tools: Extended Development System (XDS) Emulator (supports C6000 DSP multiprocessor system debug) EVM (Evaluation Module) For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
Code Composer Studio, DSP / BIOS, and XDS are trademarks of Texas Instruments.
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. Fully qualified development-support product
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
device and development-support tool nomenclature (continued) Table 17. 320C6712 / C6712C / C6712D Device Part Numbers (P / Ns) and Ordering Information
Ball Grid Array Quad Flatpack
Figure 5. TMS320C6000 DSP Platform Device Nomenclature (Including the SM320C6712, SM320C6712C, and SM320C6712D Devices)
MicroStar BGA and PowerPAD are trademarks of Texas Instruments. This value is compatible with existing 1.26V designs.
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
documentation support
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
CPU CSR register description
The CPU control status register (CSR) contains the CPU ID and CPU Revision ID (bits 16-31) as well as the status of the device power-down modes PWRD field (bits 15-10), program and data cache control modes, the endian bit (EN, bit 8) and the global interrupt enable (GIE, bit 0) and previous GIE (PGIE, bit 1). Figure 6 and Table 18 identify the bit fields in the CPU CSR register. For more detailed information on the bit fields in the CPU CSR register, see the TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190) and the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).
31 24 23 16 REVISION ID R-0x02 C6712 R-0x03 C6712C / 12D
CPU ID
R-0x02
15 PWRD
EN R-1
PGIE R / W-0
Figure 6. CPU Control Status Register (CPU CSR)
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
CPU CSR register description (continued)
Table 18. CPU CSR Register Bit Field Description
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
cache configuration (CCFG) register description (12D)
The C6712D device includes an enhancement to the cache configuration (CCFG) register. A "P" bit (CCFG.31) allows the programmer to select the priority of accesses to L2 memory originating from the transfer crossbar (TC) over accesses originating from the L1D memory system. An important class of TC accesses is EDMA transfers, which move data to or from the L2 memory. While the EDMA normally has no issue accessing L2 memory due to the high hit rates on the L1D memory system, there are pathological cases where certain CPU behavior could block the EDMA from accessing the L2 memory for long enough to cause a missed deadline when transferring data to a peripheral such as the McASP or McBSP. This can be avoided by setting the P bit to "1" because the EDMA will assume a higher priority than the L1D memory system when accessing L2 memory. For more detailed information on the P-bit function and for silicon advisories concerning EDMA L2 memory accesses blocked, see the TMS320C6712, TMS320C6712C, TMS320C6712D Digital Signal Processors Silicon Errata (literature number SPRZ182C or later).
7 Reserved R-0 0000
3 2 L2MODE R / W-000
Reserved
Figure 7. Cache Configuration Register (CCFG) Table 19. CCFG Register Bit Field Description
ID Reserved
L2MODE
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
interrupt sources and interrupt selector C6712 only
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
interrupt sources and interrupt selector C6712C / C6712D only
Table 22. Interrupt Selector 12C / 12D
INTERRUPT SELECTOR VALUE (BINARY) 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 INTERRUPT EVENT - TINT0 TINT1 SDINT GPINT4 GPINT5 GPINT6 GPINT7 EDMAINT EMUDTDMA EMURTDXRX EMURTDXTX XINT0 RINT0 XINT1 RINT1 GPINT0 MODULE
- Timer 0 Timer 1 EMIF GPIO GPIO GPIO GPIO EDMA Emulation Emulation Emulation McBSP0 McBSP0 McBSP1 McBSP1 GPIO
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
EDMA channel synchronization events C6712 only
The C67x EDMA on the C6712 device supports up to 16 EDMA channels. Four of the sixteen channels (channels 8-11) are reserved for EDMA chaining, leaving 12 EDMA channels available to service peripheral devices. Table 23 lists the source of synchronization events associated with each of the programmable EDMA channels. For the C6712, the association of an event to a channel is fixed each of the EDMA channels has one specific event associated with it. For more detailed information on the EDMA module, associated channels, and event-transfer chaining, see the TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRU234). Table 23. 320C6712 EDMA Channel Synchronization Events
McBSP1 receive event EDMA channels 8 through 11 are used for transfer chaining only. For more detailed information on event-transfer chaining, see the TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRU234).
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
EDMA module and EDMA selector 12C / 12D only
The C67x EDMA for the C6712C / C6712D device also supports up to 16 EDMA channels. Four of the sixteen channels (channels 8-11) are reserved for EDMA chaining, leaving 12 EDMA channels available to service peripheral devices. On the C6712C / C6712D device, the user, through the EDMA selector registers, can control the EDMA channels servicing peripheral devices. The EDMA selector registers are located at addresses 0x01A0FF00 (ESEL0), 0x01A0FF04 (ESEL1), and 0x01A0FF0C (ESEL3). These EDMA selector registers control the mapping of the EDMA events to the EDMA channels. Each EDMA event has an assigned EDMA selector code (see Table 25). By loading each EVTSELx register field with an EDMA selector code, users can map any desired EDMA event to any specified EDMA channel. Table 24 lists the default EDMA selector value for each EDMA channel. See Table 24 and Table 25 for the EDMA Event Selector registers and their associated bit descriptions.
Table 24. EDMA Channels C6712C / C6712D Only
EDMA CHANNEL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 EDMA SELECTOR CONTROL REGISTER ESEL05:0 ESEL013:8 ESEL021:16 ESEL029:24 ESEL15:0 ESEL113:8 ESEL121:16 ESEL129:24 DEFAULT SELECTOR VALUE (BINARY) 000000 000001 000010 000011 000100 000101 000110 000111 DEFAULT EDMA EVENT
Table 25. EDMA Selector 12C / 12D Only
EDMA SELECTOR CODE (BINARY) 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000-111111 XEVT0 REVT0 XEVT1 REVT1 Reserved GPINT2 Reserved McBSP0 McBSP0 McBSP1 McBSP1 TINT0 TINT1 SDINT GPINT4 GPINT5 GPINT6 GPINT7 Reserved Reserved GPIO EDMA EVENT Reserved TIMER0 TIMER1 EMIF GPIO GPIO GPIO GPIO MODULE
TINT0 TINT1 SDINT GPINT4 GPINT5 GPINT6 GPINT7 TCC8 (Chaining) TCC9 (Chaining) TCC10 (Chaining) TCC11 (Chaining) XEVT0 REVT0 XEVT1 REVT1
ESEL35:0 ESEL313:8 ESEL321:16 ESEL329:24
The GPINT4-7 interrupt events are sourced from the GPIO module via the external interrupt capable GP4-7 pins 12C / 12D only.
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
EDMA module and EDMA selector 12C / 12D only (continued)
Table 26. EDMA Event Selector Registers (ESEL0, ESEL1, and ESEL3) ESEL0 Register (0x01A0 FF00)
Reserved R-0
EVTSEL3 R / W-00 0011b
Reserved R-0
EVTSEL2 R / W-00 0010b
0 EVTSEL0
Reserved R-0
EVTSEL1 R / W-00 0001b
Reserved R-0
R / W-00 0000b
ESEL1 Register (0x01A0 FF04)
Reserved R-0
EVTSEL7 R / W-00 0111b
Reserved R-0 6 5 Reserved R-0
EVTSEL6 R / W-00 0110b
0 EVTSEL4
Reserved R-0
EVTSEL5 R / W-00 0101b
R / W-00 0100b
ESEL3 Register (0x01A0 FF0C)
Reserved R-0
EVTSEL15 R / W-00 1111b
Reserved R-0
EVTSEL14 R / W-00 1110b
Reserved R-0
EVTSEL13 R / W-00 1101b
Reserved R-0
EVTSEL12 R / W-00 1100b
Table 27. EDMA Event Selection Registers (ESEL0, ESEL1, and ESEL3) Description
BIT # 31:30 23:22 15:14 7:6 NAME DESCRIPTION
Reserved
Reserved. Read-only, writes have no effect.
EDMA event selection bits for channel x. Allows mapping of the EDMA events to the EDMA channels. 29:24 21:16 13:8 5:0 The EVTSEL0 through EVTSEL15 bits correspond to the channels 0 to 15, respectively. These EVTSELx fields are user-selectable. By configuring the EVTSELx fields to the EDMA selector value of the desired EDMA sync event number (see Table 25), users can map any EDMA event to the EDMA channel. For example, if EVTSEL15 is programmed to 00 0001b (the EDMA selector code for TINT0), then channel 15 is triggered by Timer0 TINT0 events.
EVTSELx
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
clock PLL C6712 only
All of the internal C6712 clocks are generated from a single source through the CLKIN pin. This source clock either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock, or bypasses the PLL to become the internal CPU clock. To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 8 shows the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes. Figure 9 shows the external PLL circuitry for a system with ONLY x1 (PLL bypass) mode. To minimize the clock jitter, a single clean power supply should power both the C6712 device and the external clock oscillator circuit. Noise coupling into PLLF will directly impact PLL clock jitter. The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements, see the input and output clocks electricals section. Table 28 lists some examples of compatible CLKIN external clock sources. Table 28. Compatible CLKIN External Clock Sources C6712
COMPATIBLE PARTS FOR EXTERNAL CLOCK SOURCES (CLKIN) PART NUMBER JITO-2 STA series, ST4100 series Oscillators SG-636 342 PLL
3.3V PLLV EMI Filter
MANUFACTURER Fox Electronix SaRonix Corporation Epson America Corning Frequency Control Integrated Circuit Systems
ICS525-02
CLKMODE0 C3 10 mF C4 0.1 mF CLKIN CLKIN LOOP FILTER 0 PLLMULT PLLCLK 1
Internal to C6712
CPU CLOCK
Available Multiply Factors CLKMODE0 0 1 PLL Multiply Factors x1(BYPASS) x4 CPU Clock Frequency f(CPU CLOCK) 1 x f(CLKIN) 4 x f(CLKIN) C2 C1 PLLG (For C1, C2, and R1 values, see Table 29.) R1 PLLF
NOTES: A. Keep the lead length and the number of vias between the PLLF pin, the PLLG pin, and R1, C1, and C2 to a minimum. In addition, place all PLL external components (R1, C1, C2, C3, C4, and the EMI Filter) as close to the C6000 DSP device as possible. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than the ones shown. B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4, and the EMI filter). C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I / O voltage, DVDD. D. EMI filter manufacturer: TDK part number ACF451832-333, 223, 153, 103. Panasonic part number EXCCET103U.
Figure 8. External PLL Circuitry for Either PLL x4 Mode or x1 (Bypass) Mode C6712
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
clock PLL C6712 only (continued)
3.3V PLLV Internal to C6712 CLKMODE0
PLLMULT PLLCLK
CLKIN
CLKIN LOOP FILTER
CPU CLOCK
NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF terminal to the PLLG terminal. B. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I / O voltage, DVDD.
Figure 9. External PLL Circuitry for x1 (Bypass) Mode Only C6712 Table 29. C6712 PLL Component Selection Table
CLKMODE
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
PLL and PLL controller C6712C / C6712D only
The 320C6712C / C6712D includes a PLL and a flexible PLL controller peripheral consisting of a prescaler (D0) and four dividers (OSCDIV1, D1, D2, and D3). The PLL controller is able to generate different clocks for different parts of the system (i.e., DSP core, Peripheral Data Bus, External Memory Interface, McASP, and other peripherals). Figure 10 illustrates the PLL, the PLL controller, and the clock generator logic.
+3.3 V C1 EMI filter 10 µF C2 0.1 µF
PLLHV
CLKMODE0 CLKIN PLLREF
DIVIDER D0
PLLOUT
DIVIDER D1
1 Reserved 0
D1EN (PLLDIV1.15) D0EN (PLLDIV0.15)
OSCDIV1
DIVIDER D2
SYSCLK1 (DSP Core)
CLKOUT3 For Use in System
D2EN (PLLDIV2.15)
DIVIDER D3
SYSCLK2 (Peripherals)
OD1EN (OSCDIV1.15) D3EN (PLLDIV3.15) ECLKIN (EMIF Clock Input)
EKSRC Bit (DEVCFG.4)
C6712C / C6712D DSPs
EMIF ECLKOUT
Dividers D1 and D2 must never be disabled. Never write a "0" to the D1EN or D2EN bits in the PLLDIV1 and PLLDIV2 registers. NOTES: A. Place all PLL external components (C1, C2, and the EMI Filter) as close to the C67x DSP device as possible. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than the ones shown. B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI Filter). C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I / O voltage, DVDD. D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U.
Figure 10. PLL and Clock Generator Logic C6712C / C6712D Only
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
PLL and PLL controller C6712C / C6712D only (continued)
MIN PLL Lock Time PLL Reset Time 125 TYP 75 MAX 187.5 UNIT µs ns
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
PLL and PLL controller C6712C / C6712D only (continued)
Table 32. PLL Clock Frequency Ranges
SYSCLK2 rate must be exactly half of SYSCLK1. Also see the electrical specification (timing requirements and switching characteristics parameters) in the Input and Output Clocks section of this data sheet.
The EMIF itself may be clocked by an external reference clock via the ECLKIN pin or can be generated on-chip as SYSCLK3. SYSCLK3 is derived from divider D3 off of PLLOUT (see Figure 10, PLL and Clock Generator Logic). The EMIF clock selection is programmable via the EKSRC bit in the DEVCFG register. The settings for the PLL multiplier and each of the dividers in the clock generation block may be reconfigured via software at run time. If either the input to the PLL changes due to D0, CLKMODE0, or CLKIN, or if the PLL multiplier is changed, then software must enter bypass first and stay in bypass until the PLL has had enough time to lock (see electrical specifications). For the programming procedure, see the TMS320C6000 DSP Software-Programmable Phase-Locked Loop (PLL) Controller Reference Guide (literature number SPRU233). SYSCLK2 is the internal clock source for peripheral bus control. SYSCLK2 (Divider D2) must be programmed to be half of the SYSCLK1 rate. For example, if D1 is configured to divide-by-2 mode ( / 2), then D2 must be programmed to divide-by-4 mode ( / 4). SYSCLK2 is also tied directly to CLKOUT2 pin (see Figure 10). During the programming transition of Divider D1 and Divider D2 (resulting in SYSCLK1 and SYSCLK2 output clocks, see Figure 10), the order of programming the PLLDIV1 and PLLDIV2 registers must be observed to ensure that SYSCLK2 always runs at half the SYSCLK1 rate or slower. For example, if the divider ratios of D1 and D2 are to be changed from / 1, / 2 (respectively) to / 5, / 10 (respectively) then, the PLLDIV2 register must be programmed before the PLLDIV1 register. The transition ratios become / 1, / 2 / 1, / 10 and then / 5, / 10. If the divider ratios of D1 and D2 are to be changed from / 3, / 6 to / 1, / 2 then, the PLLDIV1 register must be programmed before the PLLDIV2 register. The transition ratios, for this case, become / 3, / 6 / 1, / 6 and then / 1, / 2. The final SYSCLK2 rate must be exactly half of the SYSCLK1 rate. Note that Divider D1 and Divider D2 must always be enabled (i.e., D1EN and D2EN bits are set to "1" in the PLLDIV1 and PLLDIV2 registers). For detailed information on the clock generator (PLL Controller registers) and their associated software bit descriptions, see Table 33 through Table 36.
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320C6712 EP, SM320C6712C EP, SM320C6712D EP FLOATING POINT DIGITAL SIGNAL PROCESSORS
SGUS055 - SEPTEMBER 2004
PLL and PLL controller C6712C / C6712D only (continued)
PLLCSR Register (0x01B7 C100)
31 28 27 24 23 Reserved R-0 15 12 11 8 7 6 STABLE R-x 5 4 Reserved R-0 3 PLLRST RW-1 2 Reserved R / W-0 1 PLLPWRDN R / W-0b PLLEN RW-0 0 20 19 16
Reserved R-0
Table 33. PLL Control / Status Register (PLLCSR)
BIT # 31:7 6 5:4 3 2 1 NAME Reserved STABLE Reserved PLLRST Reserved PLLPWRDN DESCRIPTION Reserved. Read-only, writes have no effect. Clock Input Stable. This bit indicates if the clock input has stabilized. 0 - Clock input not yet stable. Clock counter is not finished counting (default). 1 - Clock input stable. Reserved. Read-only, writes have no effect. Asserts RESET to PLL 0 - PLL Reset Released. 1 - PLL Reset Asserted (default). Reserved. The user must write a "0" to this bit. Select PLL Power Down 0 - PLL Operational (default). 1 - PLL Placed in Power-Down State. PLL Mode Enable 0 - Bypass Mode (default). PLL disabled. Divider D0 and PLL are bypassed. SYSCLK1 / SYSCLK2 / SYSCLK3 are divided down directly from input reference clock. 1 - PLL Enabled. Divider D0 and PLL are not bypassed. SYSCLK1 / SYSCLK2 /