SINGLE-CHIP SET-TOP DECODER WITH HARD DISK DRIVE SUPPORT DATA SHE
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SINGLE-CHIP SET-TOP DECODER WITH HARD DISK DRIVE SUPPORT
DATA SHEET
STi5518 highly integrated single-chip decoder, designed feature-rich mass-market set-top boxes. integrates high-performance 32-bit CPU, dedicated block DVB/DirecTV transport demultiplexing descrambling, modules MPEG-2 video audio decoding with 3D-surround support, advanced display graphics features, digital video encoder system peripherals required typical low-cost interactive receiver. cover needs DVD-capable set-top boxes, STi5518 integration options include decryption block, Dolby Digital audio decoder Macrovision copy protection. ATAPI interface built-in, supporting glueless connection standard Hard Disk Drives. this way, STi5518 ideal set-top boxes featuring trick modes such live recording, pausing time-shifting. STi5518 backward compatible with popular STi5500 set-top decoder, allowing easy migration from previous generation. high level integration single PQFP-208 package makes STi5518 ideally suited low-cost, high-volume set-top applications.
channels arbitrator Programmable memory interface MPEG-2 multichannel Dolby Digital® MP3, Alignment beep
STi5518
Integrated 32-bit host Kbytes Icache, Kbytes Dcache, Kbytes SRAM configurable Dcache. Audio decoder channel Dolby Digital® /MPEG-2 multi-channel decoding, 2-channel outputs IEC60958 -IEC61937 digital output SRS®/TruSurround® DTS® digital decoding Alignment beep satellite dishes. Video decoder Supports MPEG-2 MP@ML Fully programmable zoom-in zoom-out NTSC conversion. SVCD subpicture decoder High performance on-screen display bits pixel options Anti-flicker, anti-flutter anti-aliasing filters. PAL/NTSC/SECAM encoder RGB, CVBS, outputs with 10-bit DACs Macrovision® 7.01/6.1 compatible (optional). Shared SDRAM memory interface 2x16-Mbit, 1x64-Mbit SDRAM. Programmable memory interface SDRAM, ROM, peripherals. Front-end interface DVD, VCD, SVCD CD-DA compatible Serial, parallel ATAPI interfaces Hardware sector filtering Integrated decryption track buffer. Hardware transport-stream demultiplexor Parallel/serial input descramblers support. Integrated peripherals UARTs, SmartCards, controller, outputs, capture timers Modem support bits programmable transmitter/receiver. Professional toolset support ANSI compiler libraries. PQFP package.
Front-end interface (sector processor decryption)
instruction cache data cache SRAM UART, SmartCard, PIO, 3PWM, MAFE interface blaster Diagnostics controller system services
ST20
MPEG2 video Sub-picture background
PAL/NTSC SECAM
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information this data sheet subject change without notice.
April 2001
Table contents 1.10 1.11 1.12 1.13 1.14 1.15 1.16
3.6.1 3.6.2 3.6.3 3.6.4
STi5518
Architecture overview Introduction Central processor
MPEG video decoder Audio decoder transmitter/receiver Modem analog front-end interface Memory subsystem Serial communication
Front-end interface On-chip Diagnostic controller (DCU) Interrupt subsystem PAL/NTSC/SECAM encoder SmartCard interfaces counter module Parallel module data list sorted function Pins sorted number Central processing unit Registers Processes concurrency
Priority Process communications Timers Traps exceptions
Trap groups Events that cause traps Trap handlers Restrictions trap handlers
Instruction Instruction cycles Instruction characteristics Instruction-set tables Interrupt system Introduction Interrupt controller Interrupt vector table Interrupt handlers
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7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6
Interrupt latency Pre-emption interrupt priority Restrictions interrupt handlers Interrupt level controller Interrupt assignments
Memory map- Overview Mapping System memory Memory External memory On-chip SRAM memory
locations
Caching
Outline operation Cache initialization Cache subsystem control Data cache Instruction cache Cacheable non-cacheable memory
8.3.1 8.3.2 8.3.3 8.3.4 8.3.5
Programmable memory interface functions Configuration list External cycles
DRAM SDRAM SRAM peripheral access cycles Wait Bank-width based address shifting
10.1 10.2 10.3 10.4 10.5 12.1 12.2
configuration
Default configuration System services Power-on hard reset Bootstrap
Diagnostic controller Diagnostic hardware Access features Software debugging features Controlling diagnostic controller Peeking poking host from target
Test access port Data flow- On-chip modules Video data flow
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12.3 13.1 13.2 13.3 13.4 13.5 13.6 13.7 14.1 14.2 14.3 14.4
14.4.1 14.4.2 14.4.3 14.4.4 14.4.5 14.4.6 14.4.7 14.4.8
Audio data flow Front-end interface
Introduction
Serial interface DVB-CI mode (optional) Parallel interface ATAPI interface interface Decryption cell Link Introduction MPEG-2 systems layers Detailed description
STi5518
Overview
Input interface NRSS interface Descrambler SDAV/P1394 interface FRAM Clock recovery Interrupts
14.5 14.6 15.1 15.2 15.3
15.3.1 15.3.2 15.3.3
DVD/link data analyzer Hard disk drive buffer control MPEG video decoder Decoder operation Reset buffer start-code detection (video)
buffer Start code detection Handling time-stamps
15.4 15.5 15.6
15.6.1 15.6.2 15.6.3 15.6.4 15.6.5
Video decoding pipeline control Quantization table loading Memory mapping data
Mapping 16-Mbit SDRAM Mapping 64-Mbit SDRAM Memory segments Arrangement pixel-pairs inside luma SDRAM Arrangement pixel-pairs inside chroma SDRAM
15.7 15.8
15.8.1 15.8.2
Using picture pointers
Video pipeline
Decoding task Error recovery missing macroblock concealment
15.9 15.10
parser
Enhanced trick-modes
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16.1 16.2 16.3 16.4
Sub-picture decoder- Introduction Buffer management pointers
16.4.1 16.4.2
Operation
Sub-picture display
Look-up tables Sub-picture areas
17.1 17.2 17.3 17.4 18.1 18.2 18.3
18.3.1 18.3.2 18.3.3 18.3.4
Overlay graphics texts Introduction Operation Buffer management
Display Display planes Overview Background color plane
Setting-up display Sample rate converter Block-to-row converter Degradation mode
MPEG video plane
18.4
18.4.1 18.4.2 18.4.3 18.4.4 18.4.5 18.4.6 18.4.7 18.4.8 18.4.9 18.4.10 18.4.11
On-screen display (OSD)
Using regions specification region position Color palette bit-map block header format specification block examples Mixing with video Anti-flicker anti-flutter filters active signal
18.5 18.6
18.6.1
Sub-picture cursor plane Mixing display planes
4:2:2 Output control
20.1 20.2 20.3 20.4 20.5
20.5.1 20.5.2 20.5.3 20.5.4
SDRAM block move Digital encoder Introduction Video timing Reset procedure Master mode Slave modes
Introduction Line-based synchronization Frame-based synchronization Sync-in-data based synchronization
20.6
Input demultiplexor
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20.7 20.8 20.9 20.10 20.12
Subcarrier generation
Burst insertion (PAL NTSC)
20.11 20.13 20.14 20.15 20.16 20.17 20.18 20.19 20.20 21.1 21.2 21.3 21.4 21.5 22.1 22.2 22.3 22.4 22.5 23.1 23.2 23.3 23.4 23.5 23.6 23.7 23.8 23.9 23.10 23.11 23.12 23.13
Subcarrier insertion (SECAM)
Luminance encoding Chrominance encoding
STi5518
Composite video signal generation encoding Closed-captioning CGMS encoding encoding encoding Teletext encoding Line skip line insert capability
CVBS, S-VHS, outputs Teletext Introduction Teletext packet format Data transfer sequence Interrupt control Teletext registers Double triple video Description Input codes video application Video output voltage level Video specifications setup
Output-stage adaptation amplification
Audio decoder Features Architecture overview Operation Decoding process Decoding states Stream parsers Decoding modes output SPDIF output Interrupts
Audio/video synchronization beep tone Audio trick modes
Description Slow forward Fast forward SPDIF output audio trick modes
23.13.1 23.13.2 23.13.3 23.13.4
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25.1 25.2 25.3 25.4 25.5 25.6 28.1 28.2 28.3 28.4 28.5 29.1 29.2 30.1
30.1.1 30.1.2
External audio decoder interface Clock generator
Introduction
System clocks clock Auxiliary clock Low-power, watchdog power-down
SmartCard clocks
MPEGDMA controller Block move counter module External interface outputs
Capture inputs Compare (programmable timer) facilities Capture/compare counter, prescaling clocking Smartcard interface External interface SmartCard clock generator Asynchronous serial controller Control
Resetting FIFOs Transmission reception 8-bit data frames 9-bit data frames Transmission with FIFOs enabled Double-buffered transmission Hardware error detection Input buffering modes Time-out mechanism Baud rates
30.2
30.2.1 30.2.2
Data frames
30.3
30.3.1 30.3.2
Transmission
30.4
30.4.1 30.4.2 30.4.3
Reception
30.5
30.5.1
Baud rate generation Interrupt control
30.6
30.6.1 30.6.2
Using interrupts when FIFOs disabled (double-buffered operation) Using interrupts when FIFOs enabled Control registers Transmission Reception Divergence from SmartCard specification
30.7
30.7.1 30.7.2 30.7.3 30.7.4
SmartCard operation
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31.1 31.2 31.3 31.4 31.5 31.6 31.7 31.8 31.9 33.1 33.2 33.3
33.3.1 33.3.2
Synchronous serial controller- Introduction Synchronous serial channel operation
clocking Half-duplex operation
STi5518
Continuous transfers Baud rates Hardware error detection capabilities Interrupt control hardware configuration Parallel input/output port Modem analog front-end interface Overview Using MAFEIF connect modem Software
Data exchange Control/status exchange
34.1 34.2 35.1 35.2
35.2.1 35.2.2 35.2.3
Infrared transmitter/receiver- Introduction Functional description Electrical specifications Absolute maximum ratings electrical characteristics
Static ST20 running 60.75 ST20 running 81.0
35.3 35.4 35.5
35.5.1 35.5.2 35.5.3 35.5.4 35.5.5 35.5.6 35.5.7 35.5.8 35.5.9 35.5.10
test conditions Operating conditions Timing diagrams interfaces
Input clock interface Video interface interface interface Link interface interface Parallel interface Audio interface ATAPI interface
37.1 37.2 37.3
Package mechanical data Revision history Changes Changes Changes
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figure below shows architecture STi5518.
Architecture overview Introduction
Internal peripherals Front-end link interface DMAs Clock generator Refill control Central command port (C2+)
Architecture overview
This chapter gives brief overview each functional blocks STi5518.
UART SmartCards
CACHE SUBSYSTEM ICache SRAM
Debug block move
QPSK, COFDM receiver, ATAPI,
MPEG MPEG
DCache Diagnostic controller
Communications arbiter
arbiter
JTAG debugging interface
peripherals: Flash, additional DRAM SDRAM
Programmable interface (EMI)
ST20 arbiter memory controller
SDRAM block move
FIFOs
Command
Mbit SDRAM
Shared SDRAM interface (SMI)
SDRAM arbiter (LMC)
Analog/digital video output
DENC
OSD, decoder mixing
Video filtering
Video decoder
Audio decoder
Audio
Figure Functional block diagram
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Architecture overview
Central processor
STi5518 Central Processing Unit ST20C2+ 32-bit processor core. contains instruction processing logic, instruction data pointers, operand register. directly accesses high-speed on-chip SRAM, which store data programs uses cache reduce access time off-chip program data memory. processor access memory Programmable Interface (often referred EMI) Shared Memory Interface (SMI), which shared with video, audio, sub-picture decoders.
STi5518
MPEG video decoder
This real-time video compression processor supporting MPEG-1 MPEG-2 standards video rates Picture format conversion display performed vertical horizontal filters. User-defined bitmaps super-imposed display picture using on-screen display function. display unit part MPEG video decoder, overlays four display planes shown figure below. display planes normally overlaid order illustrated, with background color back sub-picture front (used cursor plane). sub-picture plane alternatively positioned between MPEG video planes where used second on-screen display plane.
Background color
08:23pm
MPEG video
08:23pm
Replay Stats Score
Replay Score
Stats
On-screen display
08:23pm
Replay Score
Stats
Overlaid planes Sub-picture plane
Figure Display planes
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STi5518
Audio decoder
audio decoder accepts: Dolby Digital, MPEG-1 layers III, MPEG-2 layer 6-channel, PCM, CDDA data formats; MPEG2 streams MPEG-2, MPEG-1, Dolby Digital, MP3, Linear (LPCM). audio decoder supports DTS® digital (DVD CDDA DTS). SPDIF input data (IEC-60958 IEC-61937 standards) accepted external circuitry extracts clock from stream. Skip frame, repeat blocks soft mute frame features used synchronize audio video data. audio extraction also supported. device outputs channels data appropriate clocks external digital-to-analog converters. Programmable downmix enables 1,2,3 channel outputs. Data output either format Sony format. decoder format output data according IEC-60958 standard (for compressed data: channels, 24-bits) IEC-61937 standard (for compressed data), kHz, kHz, 44.1 kHz. Sampling frequencies kHz, kHz, 44.1 kHz, half sampling frequencies supported. downsampling filter kHz/48 kHz) available. decoder supports dual mode MPEG Dolby Digital. includes Dolby surround compatible downmix ProLogic decoder. pink noise generator enables accurate positioning speakers optimal surround sound setup. beep tone special mode used Box. generates triangular signal variable frequency amplitude left right channels. global mute mode, decoder decodes incoming bitstream normally SPDIF outputs softmuted. This mode used prepare period decoding mode, synchronize audio video data without hearing audio. Slow-forward fast-forward trick modes available compressed non-compressed data. control interface decoder activated memory mapped registers ST20 address space.
Architecture overview
transmitter/receiver
STi5518 provides pulse-position modulated signal automatic programming set-top box. signal output blast accessory jack pin, simultaneously. pulse frequency, number pulses (envelope length) total cycle time controlled registers.
Modem analog front-end interface
Modem Analog Front-end interface used transfer transmit receive samples between memory external modem analog front-end (MAFE), using synchronous serial protocol. used transfer sample data between memory buffers MAFE interface module, with separate transmit receive buffers double buffering buffer pointers. FIFOs used take into account access latency memory, worst case system allow bursts memory bandwidth efficiency improvement. standard supported.
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Architecture overview
Memory subsystem
On-chip
on-chip memory includes 2Kbytes instruction cache, 2Kbytes data cache 4Kbytes SRAM that optionally configured data cache. subsystem provides 240M/bytes internal bandwidth, supporting pipelined 2cycle internal memory access. instruction data caches direct-mapped, with write-back system data-cache. caches support burst accesses external memories refill write-back. Burst access increases performance pagemode DRAM memories. Off-chip There off-chip memory interfaces:
STi5518
external memory interface (EMI) accessed ST20 used transfer data programs between
STi5518 external peripherals, flash additional SDRAM DRAM.
Shared memory interface (SMI) controls movement data between STi5518 Mbits
SDRAM. This external SDRAM stores display data generated MPEG decoder code data. uses minimal external support logic support memory subsystems, accesses Mbytes physical address space (greater SDRAM DRAM used) four general purpose memory banks bits wide, address lines, byte select. applications requiring extra memory, supports this extra memory with zero external support logic, even 16-bit SDRAM devices. configured wide variety timing decode functions configuration registers. timing each four memory banks separately, with different device types being placed each bank with need external hardware.
Serial communication
Asynchronous serial controllers Asynchronous Serial Controller (ASC), also referred UART interface, provides serial communication between STi5518 other microcontrollers, microprocessors external peripherals. STi5518 four ASCs, which generally used SmartCard controllers. Eight nine data transfer, parity generation, number stop bits programmable. Parity, framing, overrun error detection increase data transfer reliability. Transmission reception data double-buffered, 16-deep FIFOs used. mechanism distinguish address from data bytes included multiprocessor communication. Testing supported loop-back option. 16-bit baud-rate generator provides with separate serial clock signal. ASCs support full-duplex half-duplex asynchronous communication, where both transmitter receiver same data frame format same baud rate. Each operate SmartCard mode when interfacing SmartCard. Synchronous serial controller Synchronous Serial Controllers (SSC) provide high-speed interfaces wide variety serial memories, remote control receivers other microcontrollers. SSCs support features Serial Peripheral Interface (SPI) bus. SSCs programmed interface other serial standards. SSCs share pins with parallel input/output (PIO) ports, support half-duplex synchronous communication.
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Front-end interface
STi5518 connected front-end through following interfaces:
interface;
multi-format serial interface; multi-format parallel interface; ATAPI interface (for Hard Disk Drives DVD-ROMs)
Architecture overview
1.10 On-chip
on-chip accepts input generates internal high-frequency clocks needed CPU, MPEG audio subsystems.
1.11 Diagnostic controller (DCU)
ST20 Diagnostic Controller Unit (DCU) used boot control monitor chip systems standard IEEE 1194.1 Test Access Port. includes on-chip hardware with Circuit Emulation) (Logic State Analyzer) features facilitate verification debugging software running on-chip real time. independent hardware module with private link from host support real-time diagnostics.
1.12 Interrupt subsystem
interrupt system allows on-chip module external interrupt interrupt active process that interrupt handling process run. interrupt signalled following: signal external interrupt pin, signal from internal peripheral subsystem, software asserting interrupt pending register. Interrupts implemented on-chip interrupt controller on-chip interrupt-level controller. interrupt controller supports eight prioritized interrupts inputs manages pending interrupts. This allows nesting pre-emptive interrupts real-time system design. Each interrupt programmed lower higher priority than high priority process queue.
1.13 PAL/NTSC/SECAM encoder
integrated digital encoder converts multiplexed 4:2:2 4:4:4 YCbCr stream into standard analog baseband PAL/NTSC SECAM signal into RGB, YUV, CVBS components. encoder perform closed-caption, CGMS encoding, allows Macrovision7.01/6.1 copy protection. DENC able encode Teletext according "CCIR/ITU-R Broadcast Teletext System specification, also known "World System Teletext". applications, Teletext data embedded within streams MPEG data packets. responsibility software handle incoming data packets particular store Teletext packets buffer, which then passes them DENC request.
1.14 SmartCard interfaces
SmartCard interfaces support SmartCards compliant with ISO7816-3. Each interface UART (ASC), dedicated programmable clock generator, eight bits parallel port.
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Architecture overview
1.15 counter module
counter module provides three encoder outputs, three decoder (capture) inputs four programmable timers. Each capture input programmed detect rising edge, falling edge, both edges neither edge (disabled). These facilities clocked independent clocks, outputs capture inputs/timers. counter 8-bit, with 8-bit registers output-high time. capture/compare counter compare capture registers 32-bit. module generates single interrupt signal.
STi5518
1.16 Parallel module
bits parallel configured ports, each programmable output input. output configured totem-pole open-drain driver. input compare logic generate interrupt change input bit. Many parallel have alternate functions connected internal peripheral signal such UART SSC.
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PIO2[5] PIO2[6] PIO2[7] VDD3_3 PIO3[0] PIO3[1] PIO3[2] PIO3[3] PIO3[4] PIO3[5] PIO3[6] PIO3[7] VDD2_5 B_DATA B_BCLK B_FLAG B_SYNC PIO5[0] PIO5[1] PIO5[2] VDD_RGB VSS_RGB B_OUT G_OUT R_OUT V_REF_RG I_REF_RG VDD_YCC VSS_YCC Y_OUT C_OUT CV_OUT V_REF_YC I_REF_YC VDD2_5 PIO4[0] PIO4[1] PIO4[2] PIO4[3] PIO4[4] PIO4[5] PIO4[6] PIO4[7] VDD3_3 VDD_PCM VSS_PCM DAC_SCLK DAC_PCMOUT0
data
DAC_PCMOUT1 DAC_PCMOUT2 DAC_PCMCLK DAC_LRCLK SPDIF_OUT SMI_ADR[4] SMI_ADR[5] SMI_ADR[6] SMI_ADR[7] SMI_ADR[8] SMI_ADR[9] VDD2_5 SMI_ADR[3] SMI_ADR[2] SMI_ADR[1] SMI_ADR[0] SMI_ADR[10] SMI_ADR[11] SMI_ADR[12] SMI_ADR[13] SMI_CS[0] SMI_CS[1] SMI_RAS SMI_CAS SMI_WE SMI_DQML SMI_DQMU VDD3_3 SMI_CLKIN SMI_DATA[0] SMI_DATA[1] SMI_DATA[2] SMI_DATA[3] SMI_DATA[4] SMI_DATA[5] SMI_DATA[6] SMI_DATA[7] SMI_DATA[8] SMI_DATA[9] VDD2_5 SMI_CLKOUT SMI_DATA[10] SMI_DATA[11] SMI_DATA[12] SMI_DATA[13] SMI_DATA[14] SMI_DATA[15] PIO5[3] PIO5[4]
PIO2[4] PIO2[3] PIO2[2] PIO2[1] PIO2[0] TRIGGER_OUT TRIGGER_IN PIO1[5] PIO1[4] VDD2_5 PIO1[3] PIO1[2] PIO1[1] PIO1[0] PIO0[7] PIO0[6] PIO0[5] PIO0[4] PIO0[3] PIO0[2] PIO0[1] PIO0[0] VDD3_3 CPU_ADR[21] CPU_ADR[20] CPU_ADR[19] CPU_ADR[18] CPU_ADR[17] CPU_ADR[16] CPU_ADR[15] CPU_ADR[14] CPU_ADR[13] CPU_ADR[12] CPU_ADR[11] VDD2_5 CPU_ADR[10] CPU_ADR[9] CPU_ADR[8] CPU_ADR[7] CPU_ADR[6] CPU_ADR[5] CPU_ADR[4] CPU_ADR[3] CPU_ADR[2] CPU_ADR[1] VDD3_3 CPU_DATA[15] CPU_DATA[14]
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PQFP (rev
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CPU_DATA[13] CPU_DATA[12] CPU_DATA[11] CPU_DATA[10] CPU_DATA[9] CPU_DATA[8] VDD2_5 CPU_DATA[7] CPU_DATA[6] CPU_DATA[5] CPU_DATA[4] CPU_DATA[3] CPU_DATA[2] CPU_DATA[1] CPU_DATA[0] CPU_CAS1 CPU_CAS0 CPU_RAS1 VDD3_3 CPU_CE[0] CPU_CE[1] CPU_CE[2] CPU_CE[3] CPU_WAIT CPU_RW CPU_BE[1] CPU_BE[0] IRQ[0] IRQ[1] IRQ[2] RESET VSS_PLL VDD_PLL PIX_CLK VDD2_5 CPU_PROCLK CPU_OE PWM0 PWM1 PWM2 TRST VDD3_3 AUXCLK PIO5[5]
data
data
list sorted function
Alternate functions printed Italic show suggested PIO; alternate functions printed Italic multiplexed with specific hardware.
number Audio
Main function over sampling clock output output output clock Left/right clock SPDIF output
STi5518
Alternate function Type Input Output
name
DAC_SCLK DAC_PCMOUT0 DAC_PCMOUT1 DAC_PCMOUT2 DAC_PCMCLK DAC_LRCLK SPDIF_OUT VDD_PCM VSS_PCM RESET VDD_PLL VSS_PLL _CLK PIO0[0] PIO0[1] PIO0[2] PIO0[3] PIO0[4] PIO0[5] PIO0[6] PIO0[7] PIO1[0] PIO1[1] PIO1[2] PIO1[3] PIO1[4] PIO1[5] TRIGGER_IN TRIGGER_OUT PIO2[0] PIO2[1]
EXT_AUD_CLK EXT_AUD_DATA EXT_AUD_REQ
EXT_AUD_WCLK
2.5V 2.5V
freq synthesizer=2.5V freq synthesizer=GND Chip reset PLL=2.5V PLL=GND main clock PIO0[0] PIO0[1] PIO0[2] PIO0[3] PIO0[4] PIO0[5] PIO0[6] PIO0[7] PIO1[0] PIO1[1] PIO1[2] PIO1[3] PIO1[4] PIO1[5] Trigger input Trigger output PIO2[0] PIO2[1] UART3_DATA (SC1_DATA) UART1_RXD MAFEIF_DOUT PARA_REQ UART2_RXD PARA_SYNC UART1_TXD SC0_DETECT SSC0_DATA (MTSROut/MRSTin) SSC0_CLOCK EXTERNAL CLOCK PARA_DVALID UART2_TXD UART0_DATA (SC0_DATA) TTX_IN_CLOCK ATAPI_RD ATAPI_WR SC0_CLOCK SC0_RST SC0_CMD_VCC SC0_DATA_DIR
Clock reset
PIOs communication
Table Pins sorted function
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number 39-46
name PIO2[2]
PIO2[3] PIO2[4] PIO2[5] PIO2[6] PIO2[7] PIO3[0] PIO3[1] PIO3[2] PIO3[3]
Main function PIO2[2] PIO2[3] PIO2[4] PIO2[5] PIO2[6] PIO2[7] PIO3[0] PIO3[1] PIO3[2] PIO3[3] PIO3[4] PIO3[5] PIO3[6] PIO3[7] PIO4[0:7] PIO5[0]
data
Alternate function Type Input PARA_STR Output MAFEIF_HC1 SC1_CLOCK SC1_RST SC1_CMD_VCC SC1_DATA_DIR SC1_DETECT MAFEIF_SCLK PARA_DATA{0] MAFEIF_DIN PARA_DATA[1] MAFEIF_FSI PARA_DATA[2] CAPTURE_IN0 PARA_DATA[3] CAPTURE_IN1 PARA_DATA[4] CAPTURE_IN2 PARA_DATA[5] PARA_DATA[6] UART1 (CTS1) PARA_DATA[7] UART2 (CTS2) B_WCLK SSC1_DATA/ NRSS_CLOCK1 UART1 (RTS1) UART2 (RTS2) COMP_OUT1 COMP_OUT0 YC[0:7]
PIO3[4] PIO3[5] PIO3[6] PIO3[7] PIO4[0:7] PIO5[0]
PIO5[1]
PIO5[1]
B_V4
NRSS_OUT SSC1_CLOCK
PIO5[2]
PIO5[2]
IRB_IRinput/NRSS_IN2 SDAV_CLK/ P1394_Clk3
PIO5[3]4
PIO5[3]
IRB_UHFinput4 SDAV_DATA3
PIO5[4]
PIO5[4]
IRB_drivePPMsignal SDAV_DIR P1394_P_CLK3
PIO5[5]
PIO5[5]
IRB_drive0orZ5 (jack) OSC_IN_CLK3
Auxiliary Clock Interface 161-170 173-183 141-148 CPU_ADR[1:10] CPU_ADR[11:21] CPU_DATA[0:7] Address[1:10] Address[11:21] Data[0:7] Table Pins sorted function Auxiliary Clock
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data
number 151-158 Interrupt Timers JTAG Front-end
name
CPU_DATA[8:15] CPU_RAS1 CPU_WAIT CPU_RW CPU_BE[0] CPU_BE[1] CPU_CAS0 CPU_CAS1 CPU_CE[0] CPU_CE[1] CPU_CE[2] CPU_CE[3] CPU_PROCLK CPU_OE IRQ[0] IRQ[1] IRQ[2] PWM0 PWM1 PWM2 TRST
Main function Data[8:15] DRAM Wait state Read-not-write Byte enable Byte enable DRAM DRAM DRAM Chip sel. bank Chip sel. bank Chip sel. bank clock Output enable IRQ[0] (SERVO_IRQ) IRQ[1] (ATAPI IRQ) IRQ[2] (MD_IRQ) Pulse Width Modulator Pulse Width Modulator Pulse Width Modulator Test clock Test data Test data Test mode select Test reset
STi5518
Alternate function Type Input Output NOT_SDRAM_CS1 CHIPSEL. BANK3 NOT_SDRAM_WE DQM[0] DQM[1] SDRAM_CAS/ CPU_ADR[22] NOT_SDRAM_CS0
SDRAM_RAS NOTCHIPSELBANK0 CS_SUB_BANK3 HSYNC BOOT_FROM_ROM VSYNC
B_DATA B_BCLK B_FLAG B_SYNC
data clock error flag sector/ABS time
FEC_DATA FEC_B_CLK FEC_D_VALID (DVD) FEC_P_CLK (DVB/DSS) FEC_P_START (DVD) FEC_ERROR (DVB/ DSS)
Video R_OUT, G_OUT, B_OUT R_OUT, G_OUT, B_OUT Table Pins sorted function
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number 69-66 58-63 70-73 Power supply
name
Y_OUT, C_OUT, CV_OUT I_REF_RGB V_REF_RGB I_REF_YCC V_REF_YCC
Main function Y_OUT, C_OUT, CV_OUT reference current reference voltage reference current reference voltage VDDA_RGB=2.5V VSSA_RGB=GND VDDA_YCC=2.5V VSSA_YCC=GND Address SDRAM Address SDRAM Address SDRAM Data SDRAM Chip select bank SDRAM SDRAM SDRAM write enable mask low, SDRAM clock SDRAM clock POWER SUPPLY 2.5V POWER SUPPLY
data
Alternate function Type Input Output 2.5V 2.5V
VDD_RGB VSS_RGB VDD_YCC VSS_YCC SMI_ADR[0:3] SMI_ADR[4:9] SMI_ADR [10:13] SMI_CS[0,1] SMI_RAS SMI_CAS SMI_WE SMI_DQML, SMI_CLKIN SMI_CLKOUT
Shared memory interface
84-93, 97-102 SMI_DATA[0:15]
107, VDD3_3 136, 159, VDD2_5 119, 149, 171, 108, 121, 137, 150, 160, 172, 185,
Ground
Table Pins sorted function FEI_CFG bits must programmed according required NRSS configuration. NRSS_IN NRSS_OUT pins swapped around STi5518 compared STi5508. Register LNK_SDAV_CONF (SDE) must validate output path. Inverted. ATTENTION! input also inverted. must configured open drain. BOOT_FROM_ROM active during reset. whenever JTAG used.
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data
Pins sorted number
Left Side
name
Alternate function Main function Input Output PIO2[5] PIO2[6] PIO2[7] power supply Ground PIO3[0] PIO3[1] PIO3[2] PIO3[3] PIO3[4] PIO3[5] PIO3[6] PIO3[7] 2.5V power supply Ground data clock error flag sector/ABS time
STi5518
func.
PIO2[5] PIO2[6] PIO2[7] VDD3_3 PIO3[0] PIO3[1] PIO3[2] PIO3[3] PIO3[4] PIO3[5] PIO3[6] PIO3[7] VDD2_5 B_DATA B_BCLK B_FLAG B_SYNC
SC1_CMD_VCC SC1_DATA_DIR SC1_DETECT
POWER POWER
MAFEIF_SCLK PARA_DATA{0] MAFEIF_DIN PARA_DATA[1] MAFEIF_FSI PARA_DATA[2] CAPTURE_IN0 PARA_DATA[3] CAPTURE_IN1 PARA_DATA[4] CAPTURE_IN2 PARA_DATA[5] PARA_DATA[6] UART1 (CTS1) PARA_DATA[7] UART2 (CTS2) UART1 (RTS1) UART2 (RTS2) COMP_OUT1 COMP_OUT0
POWER POWER
FEC_DATA FEC_B_CLK FEC_D_VALID (DVD) FEC_P_CLK (DVB/DSS) FEC_P_START (DVD) FEC_ERROR (DVB/ DSS) B_WCLK SSC1_DATA/ NRSS_CLOCK1
PIO5[0]
PIO5[0]
PIO5[1]
PIO5[1]
B_V4
NRSS_OUT2 SSC1_CLOCK
PIO5[2]
PIO5[2]
IRB_IRinput/NRSS_IN2 SDAV_CLK/ P1394_CLK3
VDD_RGB VSS_RGB B_OUT
VDDA_RGB=2.5V VSSA_RGB=GND output Table Pins sorted number
POWER POWER
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Bottom side
name G_OUT
R_OUT
Main function output output reference voltage reference current VDDA_YCC=2.5V VSSA_YCC=GND output output output reference voltage reference current 2.5V power supply Ground PIO4[0] PIO4[1] PIO4[2] PIO4[3] PIO4[4] PIO4[5] PIO4[6] PIO4[7] power supply freq synthesizer=2.5V freq synthesizer=GND Ground Sampling clock output
data
Alternate function func. Input Output POWER POWER POWER POWER YC[0] YC[1] YC[2] YC[3] YC[4] YC[5] YC[6] YC[7] POWER POWER POWER POWER EXT_AUD_CLK EXT_AUD_DATA
V_REF_RGB
I_REF_RGB VDD_YCC VSS_YCC Y_OUT C_OUT CV_OUT V_REF_YCC I_REF_YCC VDD2_5 PIO4[0] PIO4[1] PIO4[2] PIO4[3] PIO4[4] PIO4[5] PIO4[6] PIO4[7] VDD3_3 VDD_PCM VSS_PCM DAC_SCLK DAC_PCMOUT0
DAC_PCMOUT1 DAC_PCMOUT2 DAC_PCMCLK DAC_LRCLK SPDIF_OUT SMI_ADR[4] SMI_ADR[5] SMI_ADR[6] SMI_ADR[7] SMI_ADR[8] SMI_ADR[9] VDD2_5
output output clock Left/right clock SPDIF output Address SDRAM Adress SDRAM Adress SDRAM Adress SDRAM Adress SDRAM Adress SDRAM 2.5V power supply
EXT_AUD_REQ
EXT_AUD_WCLK POWER
Table Pins sorted number
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data
name
SMI_ADR[3] SMI_ADR[2] SMI_ADR[1] SMI_ADR[0]
Main function Ground Adress SDRAM Adress SDRAM Adress SDRAM Adress SDRAM Adress SDRAM Adress SDRAM Adress SDRAM Adress SDRAM Chip select bank Chip select bank SDRAM SDRAM SDRAM write enable mask mask power supply SDRAM clock Ground Data SDRAM Data SDRAM Data SDRAM Data SDRAM Data SDRAM Data SDRAM Data SDRAM Data SDRAM Data SDRAM Data SDRAM 2.5V power supply SDRAM clock Ground Data SDRAM Data SDRAM Data SDRAM Data SDRAM Data SDRAM Data SDRAM PIO5[3]
STi5518
Alternate function func. Input Output POWER POWER POWER POWER POWER IRB_UHFinput
SMI_ADR[10] SMI_ADR[11] SMI_ADR[12] SMI_ADR[13] SMI_CS[0] SMI_CS[1] SMI_RAS SMI_CAS SMI_WE SMI_DQML SMI_DQMU VDD3_3 SMI_CLKIN SMI_DATA[0] SMI_DATA[1] SMI_DATA[2] SMI_DATA[3] SMI_DATA[4] SMI_DATA[5] SMI_DATA[6] SMI_DATA[7] SMI_DATA[8] SMI_DATA[9] VDD2_5 SMI_CLKOUT SMI_DATA[10] SMI_DATA[11] SMI_DATA[12] SMI_DATA[13] SMI_DATA[14] SMI_DATA[15] PIO5[3]
SDAV_DATA3
Table Pins sorted number
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name PIO5[4]
Right side
Main function PIO5[4] PIO5[5]
data
Alternate function func. Input Output IRB_drivePPM signal Sdav_dir P1394_P_CLK3
PIO5[5]
IRB_drive0orZ5 (jack) OSC_IN_CLK3
Auxiliary Clock VDD3_3 TRST6 PWM2 PWM1 PWM0 CPU_OE CPU_PROCLK VDD2_5 _CLK VDD_PLL VSS_PLL RESET IRQ[2] IRQ[1] IRQ[0] CPU_BE[0] CPU_BE[1] CPU_RW CPU_WAIT CPU_CE[3] CPU_CE[2] CPU_CE[1] CPU_CE[0] VDD3_3 CPU_RAS1 power supply Ground Test reset Test mode select Test data Test data Test clock Pulse Width Modulator Pulse Width Modulator Pulse Width Modulator Output enable clock 2.5V power supply main clock Ground PLL=2.5V PLL=GND Chip reset IRQ[2] (MD_IRQ) IRQ[1] (ATAPI IRQ) IRQ[0] (SERVO_IRQ) Byte enable Byte enable Read-not-write Wait state Chip select bank Chip select bank Chip select bank DRAM power supply Ground DRAM Table Pins sorted number NOT_SDRAM_CS1 CHIPSEL. BANK3 SDRAM_RAS CS_SUB_BANK3 DQM[0] DQM[1] NOT_SDRAM_WE VSYNC BOOT_FROM_ROM7 HSYNC
POWER POWER POWER POWER POWER POWER POWER POWER
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data
side
name
CPU_CAS0
Main function DRAM DRAM Data[0] Data[1] Data[2] Data[3] Data[4] Data[5] Data[6] Data[7] 2.5V power supply Ground Data[8] Data[9] Data[10] Data[11] Data[12] Data[13]
STi5518
Alternate function func. Input Output SDRAM_CAS CPU_ADR[22] NOT_SDRAM_CS0 POWER POWER
CPU_CAS1 CPU_DATA[0] CPU_DATA[1] CPU_DATA[2] CPU_DATA[3] CPU_DATA[4] CPU_DATA[5] CPU_DATA[6] CPU_DATA[7] VDD2_5 CPU_DATA[8] CPU_DATA[9] CPU_DATA[10] CPU_DATA[11] CPU_DATA[12] CPU_DATA[13]
CPU_DATA[14] CPU_DATA[15] VDD3_3 CPU_ADR[1] CPU_ADR[2] CPU_ADR[3] CPU_ADR[4] CPU_ADR[5] CPU_ADR[6] CPU_ADR[7] CPU_ADR[8] CPU_ADR[9] CPU_ADR[10] VDD2_5 CPU_ADR[11] CPU_ADR[12] CPU_ADR[13] CPU_ADR[14]
Data[14] Data[15] power supply Ground Address[1] Address[2] Address[3] Address[4] Address[5] Address[6] Address[7] Address[8] Address[9] Address[10] 2.5V power supply Ground Address[11] Address[12] Address[13] Address[14] Table Pins sorted number
POWER POWER POWER POWER
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name
CPU_ADR[15] CPU_ADR[16] CPU_ADR[17] CPU_ADR[18] CPU_ADR[19] CPU_ADR[20] CPU_ADR[21]
Main function Address[15] Address[16] Address[17] Address[18] Address[19] Address[20] Address[21] power supply Ground PIO0[0] PIO0[1] PIO0[2] PIO0[3] PIO0[4] PIO0[5] PIO0[6] PIO0[7] PIO1[0] PIO1[1] PIO1[2] PIO1[3] 2.5V power supply Ground PIO1[4] PIO1[5] Trigger input Trigger output PIO2[0] PIO2[1] PIO2[2] PIO2[3] PIO2[4]
data
Alternate function func. Input Output POWER POWER UART0_DATA (SC0_DATA) TTX_IN_CLOCK ATAPI_RD ATAPI_WR SC0_CLOCK SC0_RST SC0_CMD_VCC SC0_DATA_DIR SC0_DETECT SSC0_DATA (MTSROut/MRSTin) SSC0_CLOCK EXTERNAL CLOCK PARA_DVALID UART2_TXD POWER POWER UART2_RXD PARA_SYNC UART1_TXD UART3_DATA (SC1_DATA) UART1_RXD PARA_STR MAFEIF_DOUT PARA_REQ MAFEIF_HC1 SC1_CLOCK SC1_RST
VDD3_3 PIO0[0] PIO0[1] PIO0[2] PIO0[3] PIO0[4] PIO0[5] PIO0[6] PIO0[7] PIO1[0] PIO1[1] PIO1[2] PIO1[3] VDD2_5 PIO1[4] PIO1[5] TRIGGER_IN TRIGGER_OUT PIO2[0] PIO2[1] PIO2[2] PIO2[3] PIO2[4]
Table Pins sorted number FEI_CFG bits must programmed according required NRSS configuration. NRSS_IN NRSS_OUT pins swapped around STi5518 compared STi5508. Register LNK_SDAV_CONF (SDE) must validate output path. Inverted. ATTENTION! input also inverted. must configured open drain.
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data
whenever JTAG used
BOOT_FROM_ROM active during reset.
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STi5518 Central Processing Unit ST20C2+ 32-bit processor core. contains instruction processing logic, instruction data pointers, operand register. directly accesses high-speed on-chip SRAM, which store data programs, uses cache reduce access time off-chip program data memory. access memory general purpose external memory interface (EMI) local memory interface (LMI), which shared with MPEG decoder. processor performs following manipultations:
Central processingT unit
Central processing unit
fast integer-multiply cycle multiply; fast bit-shift single cycle barrel shifter; byte part-word handling; scheduling interrupt support; 64-bit integer arithmetic support.
scheduler provides single level pre-emption. addition, multi-level pre-emption provided interrupt subsystem. Additionally, there per-priority trap handler improve support arithmetic errors illegal instructions.
Registers
contains registers which used execution sequential integer process. registers are:
Workspace pointer (Wptr) which points area store where local data kept. Instruction pointer (Iptr) which points next instruction executed. Status register (Status). Areg, Breg Creg registers which form evaluation stack.
Areg, Breg Creg registers sources destinations most arithmetic logical operations. Loading value into stack pushes Breg into Creg, Areg into Breg, before loading Areg. Storing value from Areg, pops Breg into Areg Creg into Breg. Creg left undefined.
Registers Areg Breg Creg Wptr Iptr Local data Program
Figure Registers used sequential integer processes
Expressions evaluated evaluation stack, instructions refer stack implicitly. example, instruction adds values stack places result stack. stack removes need instructions explicitly specify location their operands. hardware mechanism
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Central processing unit
provided detect that more than three values have been loaded onto stack; easy compiler ensure that this never happens. Note that location memory accessed relative workspace pointer, enabling workspace size. shadow registers provides fast, simple clean context switching.
STi5518
Processes concurrency
This section describes default behavior should noted that user alter this behavior, example disabling timeslicing installing user scheduler. process starts, performs number actions, then either stops without completing terminates complete. Typically, process sequence instructions. several processes parallel (concurrently). Processes assigned either high priority, there number each. processor microcoded scheduler which enables number concurrent processes executed together, sharing processor time. This removes need software kernel, although kernels still written desired. time, process active inactive being executed interrupted higher priority process list waiting executed waiting input waiting output waiting until specified time
scheduler operates such that inactive processes consume processor time. Each active high priority process executes until becomes inactive. scheduler allocates portion processor's time each active priority process turn (see section Section 3.3). Active processes waiting executed held linked lists process work spaces, high priority processes priority processes. Each list implemented using registers, which points first process list, other last. linked process list shown below, process executing active, awaiting execution. Only priority process queue registers shown; high priority process ones behave similar manner.
Registers FptrReg1 BptrReg1 Areg Iptr.s Breg Creg Wptr Iptr Iptr.s Link.s Local data Iptr.s Link.s Program
Figure Linked process list
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Function
Pointer front active process list
Pointer back active process list
High priority FptrReg0 BptrReg0 Table Priority queue control registers
Central processing unit
priority FptrReg1 BptrReg1
Each process runs until completed action descheduled. order several processes operate parallel, priority process only permitted execute maximum timeslice periods. After this, machine deschedules current process next timeslicing point, adds priority scheduling list instead executes next active process. timeslice period 1ms. There only certain instructions which process descheduled. These known descheduling points. process only timesliced certain descheduling points. These known timeslicing points defined such that operand stack always empty. This removes need saving operand stack when timeslicing. result, expression evaluation guaranteed execute without process being timesliced part through. Whenever process unable proceed, instruction pointer saved process workspace next process taken from list. processor core provides number special instructions support process model, including startp (start process) endp (end process). When main process executes parallel construct, startp used create necessary additional concurrent processes. startp instruction creates process adding workspace scheduling list, enabling concurrent process executed together with ones already being executed. When process made active always added list, thus cannot pre-empt processes already same list. correct termination parallel construct assured endp instruction. This uses data structure that includes counter parallel construct components which have still terminate. counter initialized number components before processes started. Each component ends with endp instruction which decrements tests counter. last component, counter zero component descheduled. last component, counter zero main process continues.
Priority
following section describes `default' behavior should noted that user alter this behavior, example, disabling timeslicing priority interrupts. processor execute processes priority levels, level urgent (high priority) processes, less urgent (low priority) processes. high priority process will always execute preference priority process both able High priority processes expected execute short time. more high priority processes active, then first queue selected executes until wait communication, timer input, until completes processing. process high priority active, more processes priority active, then selected. priority processes periodically timesliced provide even distribution processor time between tasks which computation. there priority processes, then maximum latency from time which priority process becomes active time when starts processing order timeslice periods. then able execute between timeslice periods, less time taken high priority processes. This assumes that process monopolizes time CPU; i.e. frequent timeslicing points.
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Central processing unit
specific condition high priority process start execution that idle running priority high priority queue non-empty. high priority process becomes able while priority process executing, priority process temporarily stopped high priority process executed. state priority process saved into `shadow' registers high priority process executed. When further high priority processes able run, state interrupted priority process re-loaded from shadow registers interrupted priority process continues executing. Instructions provided processor core allow high priority process store shadow registers memory load them from memory. Instructions also provided allow process exchange alternative process queue either priority process queue. These instructions allow extensions made scheduler custom run-time kernels.
STi5518
priority process interrupted after completed execution instruction. addition, minimize time taken interrupting high priority process start executing, potentially time consuming instructions interruptible. Also some instructions aborted, restarted when process next becomes active (refer Chapter Instruction page 36).
Process communications
Communication between processes takes place over channels, implemented hardware. Communication point-to-point, synchronized unbuffered. result, channel needs process queue, message queue message buffer. channel between processes executing same implemented single word memory; channel between processes executing different processors implemented point-to-point links. processor provides number operations support message passing, most important being (input message) (output message). instructions address channel determine whether channel internal external. This means that same instruction sequence used both hard soft channels, allowing process written compiled without knowledge where channels implemented. Communication takes place when both inputting outputting processes ready. Consequently, process which first becomes ready must wait until second also ready. inputting outputting processes only become active when communication completed. process performs input output loading evaluation stack with, pointer message, address channel, count number bytes transferred, then executing instruction.
Timers
There 32-bit hardware timer clocks which `tick' periodically. These independent on-chip peripheral real time clock. timers provide accurate process timing, allowing processes deschedule themselves until specific time. timer accessible only high priority processes incremented approximately every microsecond, cycling completely approximately 4295 seconds. other accessible only priority processes runs times slower, giving 15625 ticks second. full period approximately hours. Actual timer speeds derived from processor speed CPU_PROCLK given Clocks chapter. periods calculated follows: High_priority_clock_period Nominal_speed CPU_PROCLK_speed
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Low_priority_clock_period High_priority_clock_period
Register
ClockReg0 ClockReg1 TnextReg0 TnextReg1 TptrReg0 TptrReg1
Function
Central processing unit
Current value high priority (level process clock.
Current value priority (level process clock. Indicates time earliest event high priority (level timer queue. Indicates time earliest event priority (level timer queue. High priority timer queue. priority timer queue. Table Timer registers
current value processor clock read executing ldtimer (load timer) instruction. process arrange perform (timer input), which case will become ready execute after specified time been reached. instruction requires time specified. this time `past' then instruction effect. time `future' then process descheduled. When specified time reached process becomes active. addition, ldclock (load clock), stclock (store clock) instructions allow total control over clock value clockenb (clock enable), clockdis (clock disable) instructions allow each clock individually stopped restarted. Figure shows processes waiting timer queue, waiting time other time
Work spaces ClockReg0 Program
Comparator
TnextReg0
Alarm
TptrReg0
Empty
Figure Timer registers
Traps exceptions
software error, such arithmetic overflow array bounds violation, cause error flag CPU. flag directly connected ErrorOut pin. Both flag ignored, stopped. Stopping error means that error cannot cause further corruption. well containing error this possible determine state memory time error occurred. This
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Central processing unit
particularly useful postmortem debugging where debugger used examine state history processor leading causing error condition. addition, trap handler process installed, variety traps/exceptions trapped handled software. user supplied trap handler routine provided each high/low process priority level. handler started when trap occurs given reason trap. trap handler re-entrant must cause trap itself within same group. traps individually masked.
STi5518
3.6.1 Trap groups
trap mechanism arranged priority basis. each priority there handler each group traps, shown Figure
priority traps
High priority traps
Error trap handler Breakpoint trap handler System operations trap handler
Scheduler trap handler
Error trap handler Breakpoint trap handler System operations trap handler
Scheduler trap handler
Figure Trap arrangement
There four groups traps, detailed below. Breakpoint trap: breakpoint instruction (j0) calls breakpoint routine trap mechanism. Errors: traps this group IntegerError Overflow. Overflow represents arithmetic overflow, such arithmetic results which result word. IntegerError represents errors caused when data erroneous, example when range checking instruction finds that data range. System operations: This group consists LoadTrap, StoreTrap IllegalOpcode traps. IllegalOpcode trap signalled when attempt made execute illegal instruction. LoadTrap StoreTrap traps allow kernel intercept attempts monitored process change examine trap handlers trapped process information. enables user program signal kernel that wishes install trap handler. Scheduler: scheduler trap group consists ExternalChannel, InternalChannel, Timer, TimeSlice, Run, Signal, ProcessInterrupt QueueEmpty traps. ProcessInterrupt trap signals that machine performed priority interrupt from high. QueueEmpty trap indicates that there further executable work perform. other traps this group indicate that hardware scheduler wants schedule process process queue, with different traps enabling different sources this monitored. scheduler traps enable software scheduler kernel hardware scheduler implement multi-priority software scheduler. Note that scheduler traps different from other traps they caused micro-scheduler rather than executing process.
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Trap groups encoding shown below. These codes used identify trap groups various instructions.
Trap group Breakpoint
errors Scheduler
System operations
Central processing unit
Code
Table Trap group codes
addition trap groups mentioned above, CauseError flag Status register used signal when trap condition been activated causeerror instruction. used indicate when trap conditions have occurred user setting them, rather than system.
3.6.2 Events that cause traps
Table summarizes events that cause traps gives encoding bits trap Status Enable words.
Trap cause Breakpoint IntegerError Overflow IllegalOpcode LoadTrap StoreTrap InternalChannel ExternalChannel Timer Timeslice Signal ProcessInterrupt QueueEmpty CauseError Status/Enable codes (Status only) Trap group Any, encoded Comments When process executes breakpoint instruction (j0) then traps trap handler. Integer error other than integer overflow e.g. explicitly checked explicitly error. Integer overflow integer division zero. Attempt execute illegal instruction. This signalled when executed with invalid operand. When trap descriptor read with ldtraph instruction when trapped process status read with ldtrapped instruction. When trap descriptor written with sttraph instruction when trapped process status written with sttrapped instruction. Scheduler trap from internal channel. Scheduler trap from external channel. Scheduler trap from timer alarm. Scheduler trap from timeslice. Scheduler trap from runp (run process) startp (start process). Scheduler trap from signal. Start executing process priority level. Caused process active priority level. Signals that causeerror instruction trap flag.
Table Trap causes status/enable codes
3.6.3 Trap handlers
each trap handler there trap handler structure trapped process structure. Both trap handler structure trapped process structure memory accessed instructions, section Section trap handler structure specifies what should happen when trap condition present,
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Central processing unit
trapped process structure saves some state process that running when trap taken. addition, each priority, there Enables register Status register. Enables register contains flags enable each cause trap. Status register contains flags indicate which trap conditions have been detected. Enables Status register encodings given Table
STi5518
Comments Iptr trap handler process. Wptr trap handler process. null Wptr indicates that trap handler been installed. Contains Status register that trap handler starts with. word which encodes trap enable global interrupt masks, which will ANDed with existing masks allow trap handler disable various events while runs. Table Trap handler structure Comments
Location Base Base Base Base
IPTR WPTR Status Enables
Location Base Base Base Base Table Trapped process structure
Iptr Wptr Status Enables
Points instruction after that caused trap condition. Wptr process that running when trap taken. relevant trap set, trap codes. Interrupt enables.
trap will taken interruptible point trap corresponding trap enable Enables register. trap enabled then nothing done with trap condition. trap enabled then corresponding Status register indicate trap condition occurred. When process takes trap processor saves existing Iptr, Wptr, Status Enables trapped process structure. then loads Iptr, Wptr Status from equivalent trap handler structure ANDs value Enables with value structure. This allows user disable various events while handler, particular trap handler must disable traps trap group avoid possibility handler trapping itself. trap handler then executes. values trapped process structure examined using ldtrapped instruction (see section Section When trap handler completed operation returns trapped process tret (trap return) instruction. This reloads values saved trapped process structure clears trap flag Status. Note that when trap handler started, Areg, Breg Creg saved. trap handler must save Areg, Breg, Creg registers using (store local).
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Trap instructions
Trap handlers trapped processes examined ldtraph, sttraph, ldtrapped sttrapped instructions. Table describes instructions that used when dealing with traps.
Instruction ldtraph sttraph ldtrapped sttrapped trapenb trapdis tret causeerror
Meaning load trapped store trapped trap enable trap disable trap return cause error
Central processing unit
load trap handler store trap handler
Load trap handler from memory trap handler descriptor. Store existing trap handler descriptor memory. Load replacement trapped process status from memory. Store trapped process status memory. Enable traps. Disable traps. Used return from trap handler. Program simulate occurrence error.
Table Instructions which used when dealing with traps
first four instructions transfer data to/from trap handler structures trapped process structures from/to area memory. these instructions Areg contains trap group code Breg points word area memory used source destination transfer. addition Creg contains priority handler installed/examined case ldtraph sttraph. ldtrapped sttrapped apply only current priority. LoadTrap trap enabled then ldtraph ldtrapped perform transfer LoadTrap trap flag. StoreTrap trap enabled then sttraph sttrapped perform transfer StoreTrap trap flag. trap enable masks encoded array bits (see Table which indicate which traps enabled. This array bits stored lower half-word Enables register. There Enables register each priority. Traps enabled disabled loading mask into Areg with bits indicate which traps affected priority affect Breg. Executing trapenb mask supplied Areg with trap enables mask Enables register priority Breg. Executing trapdis negates mask supplied Areg ANDs with trap enables mask Enables register priority Breg. Both instructions return previous value trap enables mask Areg.
3.6.4 Restrictions trap handlers
There various restrictions that must placed trap handlers ensure that they work correctly.
Trap handlers must deschedule timeslice. Trap handlers alter Enables masks, therefore they must
allow other processes execute until they have completed.
Trap handlers must have their Enable masks mask traps their trap group avoid possibility trap
handler trapping itself.
Trap handlers must terminate tret (trap return) instruction. only exception this that scheduler
kernel restart return previously shadowed process.
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Instruction
This chapter provides information ST20-C2+ instruction set. contains tables listing instructions, where applicable provides details number processor cycles taken instruction. instruction been designed simple efficient compilation high-level languages. instructions have same format, designed give compact representation operations occurring most frequently programs. Each instruction consists single byte divided into 4-bit parts. four most significant bits (MSB) byte function code four least significant bits (LSB) data value, shown below.
Instruction Function
STi5518
Data
Figure Instruction format
further information instruction refer ST20C2/C4 Instruction Manual (document number 72TRN-273).
Instruction cycles
Timing information available some instructions. However, should noted that many instructions have ranges timings which data dependent. Where included, timing information based number clock cycles assuming memory accesses cycle internal memory other subsystem using memory. Actual time will dependent speed external memory memory availability. Note that actual time increased
instruction requiring value register stack from final memory read previous instruction
current instruction will stall until value becomes available.
first memory operation current instruction delayed while preceding memory operation
completes memory operations progress time, further operation will stall until first completes.
Memory operations current instructions delayed access instruction fetch subsystems
memory interface.
There delay between instructions while instruction fetch unit fetches partially decodes next
instruction this will case whenever instruction causes instruction flow jump. Note that instruction timings given refer `standard' behavior different example, traps instruction.
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Instruction characteristics
Table page gives basic function code each primary instructions. Where operand less than single byte encodes complete instruction. operand greater than prefix instruction (pfix) required each additional four bits operand. operand negative first prefix instruction will nfix. Examples pfix nfix coding given Table
Instruction
Mnemonic coded pfix coded pfix pfix coded nfix (ldc #FFFFFFE1) #987
Function code
Memory code
Table Prefix coding
instruction which instruction tables invalid instruction flagged illegal, returning error code trap handler, loaded enabled. Notes column tables indicates features instruction described Table
Ident Feature Instruction IntegerError trap Instruction cause LoadTrap trap Instruction cause StoreTrap trap Instruction cause Overflow trap Interruptible instruction Instruction aborted later restarted. Instruction deschedule Instruction timeslice Table Instruction features
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Instruction
Instruction-set tables
Function code
Memory code
Mnemonic ldlp pfix ldnl ldnlp nfix call stnl Processor cycles Table Primary functions Name jump load local pointer prefix load non-local load constant load non-local pointer negative prefix load local constant call conditional jump adjust workspace equals constant store local store non-local operate
STi5518
Notes
Memory code 22FA 23FE 23FD 21F8 25F0 21FC 21F7 25F4 2127FC 27FE
Mnemonic testpranal saveh savel sthf sthb stlf stlb sttimer lddevid ldmemstartval
Processor cycles
Name test processor analyzing save high priority queue registers save priority queue registers store high priority front pointer store high priority back pointer store priority front pointer store priority back pointer store timer load device identity load value MemStart address
Notes
Table Processor initialization operation codes
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Memory code 24F6 24FB 23F3 23F2 24F1 24F0 25F3 27F2 22FC 21FF 25FF 25F2 26F8 26F9 26FA
fmul diff prod satadd satsub satmul
Mnemonic
Instruction
Processor cycles
Name exclusive bitwise shift left shift right subtract multiply fractional multiply divide remainder greater than greater than unsigned difference product saturating saturating subtract saturating multiply
Notes
Table Arithmetic/logical operation codes Memory code 21F6 23F8 23F7 24FF 23F1 21FA 23F6 23F5 21F9 26F4 26F5 Mnemonic ladd lsub lsum ldiff lmul ldiv lshl lshr norm slmul sulmul Processor cycles Name long long subtract long long diff long multiply long divide long shift left long shift right normalize signed long multiply signed times unsigned long multiply Notes
Table Long arithmetic operation codes
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Instruction
Memory code 23FA 25F6
Mnemonic xword xdble csngl mint reboot cword
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Processor cycles
Name reverse extend word check word extend double check single minimum integer duplicate stack processor stack reboot
Notes
21FD 24FC 24F2 25FA 27F9 68FD
Table General operation codes Memory code 28F1 23F4 23FF 23FB 24FA Mnemonic bsub wsub wsubdb bcnt wcnt move Processor cycles Name byte subscript word subscript form double word subscript byte count word count load byte store byte move message Table Indexing/array operation codes Memory code 22F2 22FB 24FE 25F1 24F7 22FE Mnemonic ldtimer talt taltwt enbt dist Processor cycles Name load timer timer input timer start timer wait enable timer disable timer Table Timer handling operation codes Notes Notes
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Memory code
Mnemonic outword outbyte altwt altend enbs diss resetch enbc disc
Instruction
Processor cycles
Name input message output message output word output byte start wait enable skip disable skip reset channel enable channel disable channel
Notes
24F3 24F4 24F5 24F9 23F0 21F2 24F8 22FF
Table Input output operation codes Memory code 22F0 21FB 23FC 22F1 Mnemonic ldpi gajw gcall lend Processor cycles Name return load pointer instruction general adjust workspace general call loop Notes
Table Control operation codes Memory code 23F9 21F5 21FE Mnemonic startp endp runp stopp ldpri Processor cycles Name start process process process stop process load current priority Notes
Table Scheduling operation codes
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Instruction
Memory code 21F3 24FD 22F9 21F0 25F5 25F7 25F8 25F9
csub0 ccnt1 testerr seterr stoperr clrhalterr sethalterr testhalterr
Mnemonic
STi5518
Processor cycles
Name check subscript from check count from test error false clear error stop error error) clear halt-on-error halt-on-error test halt-on-error
Notes
Table Error handling operation codes Memory code 25FB 25FC 25FD 25FE Mnemonic move2dinit move2dall move2dnonzero move2dzero Processor cycles Name initialize data block move block copy block copy non-zero bytes block copy zero bytes Table block move operation codes Memory code 27F4 27F5 27F6 27F7 27F8 Mnemonic crcword crcbyte bitcnt bitrevword bitrevnbits Processor cycles Name calculate word calculate byte count bits word reverse bits word reverse bottom bits word Notes Notes
Table operation codes Memory code 27F3 29FC 26F3 26FD 26FC 27F1 Mnemonic cflerr fptesterr unpacksn roundsn postnormsn ldinf Processor cycles Name check floating point error load value true (FPU present) unpack single length floating point number round single length floating point number post-normalize correction single length floating point number load single length infinity Notes
Table Floating point support operation codes
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Memory code 2CF7 2CFC 2BFA 2FFA 2FFB 2FF8 2BF8 2BFB
ciru xsword xbword
Mnemonic
Instruction
Processor cycles
Name check range check range unsigned check byte check byte unsigned check sixteen check sixteen unsigned sign extend sixteen word sign extend byte word
Notes
Table Range checking conversion instructions Memory code 2CF1 2CFA 2CF8 2BF9 2FF9 Mnemonic ssub Processor cycles Name sixteen subscript load sixteen store sixteen load byte sign extend load sixteen sign extend Notes
Table ndexing/array instructions Memory code 2FF0 2FF2 2FF4 62F4 2FF1 2FF3 2FF5 Mnemonic devlb devls devlw devmove devsb devss devsw Processor cycles Name device load byte device load sixteen device load word device move device store byte device store sixteen device store word Notes
Table Device access instructions Memory code 60F5 60F4 Mnemonic wait signal Processor cycles Name wait signal Notes
Table Semaphore instructions
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Instruction
Memory code 60F0 60F1 60F3 60F2
swaptimer timeslice ldshadow stshadow restart causeerror iret
Mnemonic
swapqueue
STi5518
Processor cycles
Name swap scheduler queue swap timer queue insert front scheduler queue timeslice load shadow registers store shadow registers restart cause error interrupt return timeslicing status interrupt disable interrupt enable global interrupt disable global interrupt enable
Notes
insertqueue
60FC 60FD 62FE 62FF 61FF 2BF0 2CF4 2CF5 2CFD 2CFE
settimeslice intdis intenb gintdis gintenb
Table Scheduling support instructions Memory code 26FE 2CF6 2CFB 26FF 60F7 60F6 60FB Mnemonic ldtraph ldtrapped sttrapped sttraph trapenb trapdis tret Processor cycles Name load trap handler load trapped process status store trapped process status store trap handler trap enable trap disable trap return Notes
Table Trap handler instructions Memory code 68FC 63F0 Mnemonic ldprodid Processor cycles Name load product identity operation Notes
Table Processor initialization operation instructions Memory code 64FF 64FE 64FD 64FC Mnemonic clockenb clockdis ldclock stclock Processor cycles Name clock enable clock disable load clock store clock Notes
Table Clock instructions
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interrupt system allows on-chip module external interrupt interrupt active process that interrupt handling process run. Interrupts signalled following:
Interrupt systemNT Introduction
Interrupt system
signal external interrupt pin; signal from internal peripheral subsystem; software asserting interrupt pending register.
Interrupts implemented on-chip interrupt controller on-chip interrupt level controller. interrupt level controller multiplexes incoming interrupt sources onto eight programmable interrupt level inputs interrupt controller. This multiplexing controlled software. This illustrated figure below.
On-chip module
interrupt sources (where 0-30)
On-chip module On-chip module
prioritized interrupt levels Interrupt controller
On-chip module N=22 On-chip module N=23 IRQ0 SERVO interrupt request (N=24) IRQ1 ATAPI interrupt request (N=25) IRQ2 interrupt request (N=26)
Interrupt level controller
Audio interrupt from MPEGAV Block (N=27) Video interrupt from MPEGAV Block (N=28) interrupt from MPEGAV Block (N=29) Link Interface Interrupt (N=30)
Figure STi5518 Interrupt system
Interrupt controller
interrupt controller supports eight prioritized interrupts inputs, manages pending interrupts. This allows nested pre-emptive interrupts real-time system design. Interrupt level highest priority interrupt level lowest priority. interrupts higher priority than low-priority process queue. Each interrupt programmed lower higher priority than high-priority process queue writing priority INC_HandlerWptr registers. Interrupts which specified higher priority must contiguous from highest numbered interrupt downwards. example, interrupts programmed high-priority low-priority, then higher priority interrupts must Interrupt7:4 lower priority interrupts Interrupt3:0. Each eight interrupt levels interrupt controller programmed with interrupt trigger mode, using INC_TriggerMode register. trigger mode high level, rising edge, falling edge edge sensitive. Note that on-chip module interrupt sources produce active-high level interrupt signals. Therefore
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Interrupt system
interrupt level that these interrupt sources multiplexed onto interrupt level controller) must programmed with high-level trigger mode. Furthermore, each eight interrupt levels programmed enabled disabled INC_MASK register. default state INC_MASK that interrupt levels disabled. corresponding level INC_PENDING register interrupt signal from interrupt level controller matches level trigger condition. this highest priority INC_PENDING register, will then execute interrupt handler associated with that level INC_HANDLERWPTR register INC_PENDING will then reset. level INC_PENDING register highest priority set, then remains until highest priority level bit, then executes associated interrupt handler that level. Note will only execute interrupt handler then clear INC_PENDING register enabled INC_MASK register. Software write INC_PENDING register generate software interrupt eight interrupt-levels.
STi5518
Programming INC_MASK, INC_PENDING INC_TRIGGERMODE registers supported operating system time library functions STLite (a.k.a OS20). interrupt controller also contains INC_EXEC register used interrupt controller logic keep record which interrupt-level handler currently executing previously executing before being pre-empted high priority process, priority interrupts) which levels have been pre-empted higher priority interrupt levels. This register read user software, required, register must never written behavior undefined.
Interrupt when Priority Interrupt when Priority
High priority process Increasing pre-emption Interrupt when Priority Interrupt when Priority priority process
Figure Interrupt priority
Interrupt vector table
interrupt controller contains table pointers interrupt handlers. There interrupt handlers, each controlled work-space register INC_HandlerWptr 0-7. table pointer values contains work-space pointer each interrupt level. INC_HandlerWptr registers access code, data interrupt-save area interrupt handler. position INC_HandlerWptr register interrupt table sets priority interrupt. operating system time library (STLite a.k.a. OS20) supports setting programming vector table.
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Interrupt handlers
interruptible point execution, receive interrupt request from interrupt controller. immediately acknowledges request. response receiving interrupt, performs procedure call process vector table. state interrupted process stored work space interrupt handler shown Figure Each interrupt level work space.
Before interrupt Interrupting high priority process Interrupting priority process idle
Interrupt system
HandlerWptr
HandlerWptr
HandlerWptr
Handler Iptr Handler Status
Handler Iptr Handler Status Creg Breg Areg Iptr Wptr Status
Handler Iptr Handler Status
Null Status
Figure State interrupted process
interrupt routine initialized with space below HandlerWptr. Iptr Status word routine stored there permanently. This should programmed before HandlerWptr written into vector table. behavior interrupt differs depending priority when interrupt occurs. interrupt occurs when running high priority, interrupt higher priority than high priority process queue, saves current process state (Areg, Breg, Creg, Wptr, Iptr Status) into workspace interrupt handler. value HandlerWptr, which stored interrupt controller, points this work space. values Iptr Status used interrupt handler loaded from this work space starts executing handler. value Wptr then bottom this save area. interrupt occurs when running high priority, interrupt lower priority than high priority process queue, action taken interrupt waits queue until high priority process queue empty (see Pre-emption interrupt priority page 48). Interrupts always take priority over priority processes. interrupt occurs when idle running priority, Status saved. This indicates that valid process running (Null Status). interrupted processes (low priority process) state stored shadow registers. This state accessed ldshadow (load shadow registers) stshadow (store shadow registers) instructions. interrupt handler then high priority. When interrupt routine completed must adjust Wptr value start handler code then execute iret (interrupt return) instruction. This restores interrupted state from interrupt handler structure signals interrupt controller that interrupt completed. processor will then continue from where before being interrupted.
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Interrupt system
Interrupt latency
interrupt latency depends type data being accessed, position memory interrupt handler interrupted process. This allows trade-off between fast internal SRAM memory interrupt latency.
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Pre-emption interrupt priority
Each interrupt channel implied priority fixed place interrupt vector table. interrupts cause scheduled processes priority suspended interrupt handler started. Once interrupt been sent from controller controller keeps record current executing interrupt priority INC_EXEC register. This only cleared when interrupt handler executes return from interrupt (iret) instruction. Interrupts lower priority arriving blocked interrupt controller until interrupt priority enough routine execute. interrupt higher priority than currently executing handler passed causes current handler suspended until higher priority interrupt serviced. this way, interrupts nested higher priority interrupt always pre-empts lower priority one. Note: deep nesting placing frequent interrupts high priority result systems where priority interrupts never serviced time consumed nesting interrupt priorities instead executing interrupt handlers.
Restrictions interrupt handlers
optimum interrupt handling, following restrictions placed interrupt handlers:
Interrupt handlers must deschedule. Interrupt handlers must execute communication instructions. However they communicate with other
processes through shared variables using semaphore signal synchronize.
Interrupt handlers must perform block move instructions. Interrupt handlers must cause program traps. However they trapped scheduler trap.
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Interrupt level controller
interrupt level controller multiplexes incoming interrupt source signals onto eight interrupt level inputs interrupt controller. this way, gives programmable control priority interrupt sources extends number possible interrupts incoming interrupt signals generated on-chip subsystems received from external pins. Table page assigns each interrupt sources number from 0-30. Software assigns signal interrupt levels writing priority required input register INC_IntnPriority. Each interrupt sources interrupt level controller selectively enabled disabled source, writing INC_SRC_MASK register. This addition individual masking levels interrupt controller. This means that user disable just interrupt source from generating interrupt, without disabling other interrupt sources mapped onto that interrupt level. This would case INC_MASK register interrupt controller used. Each interrupt source used trigger interrupt programmed trigger rising falling edges, high logic level incoming interrupt source signal. This controlled writing INC_SRC_TRIGGERMODE registers. STi5518 enhanced feature interrupt level controller software backward compatible with interrupt level controller STi5500, STi5505 STi5508. Backward compatibility maintained setting interrupt trigger interrupt levels interrupt controller, done before. default state interrupt level controller trigger mode registers high, therefore, these registers need programmed. this case interrupt level controller will effectively pass interrupt source signal through, unmodified, interrupt controller. default state INC_SRC_MASK register bits meaning that interrupt sources enabled. This again maintain software backwards compatibility. non-default trigger modes interrupt level controller used, corresponding trigger mode interrupt level interrupt controller that source(s) mapped must programmed high level. Otherwise, trigger mode interrupt controller interrupt level controller conflict. INC_InputInterrupt register same function before STi5500, STi5505, STi5508 used indicate current logic state interrupt sources. Note that this register just buffered version interrupt source signals before trigger mode detection stage does latch signal, does INC_SRC_STATUS register, interrupt sources defined with edge sensitive trigger mode. INC_SRC_STATUS register more useful, because this feature, read interrupt handler software routine determine which interrupt sources have triggered. example, interrupt source external provides pulse, interrupt level controller would have interrupt source trigger mode rising edge. rising edge corresponding INC_SRC_STATUS register would high would remain until explicitly cleared interrupt handler routine writing corresponding INC_SRC_CLEAR register. However pulse short, time interrupt handler executed read INC_InputInterrupt register, pulse have returned logic would read zero. Thus cause interrupt could determined more than interrupt source been multiplexed onto interrupt level. now, using INC_SRC_STATUS register, possible multiplex interrupt sources different types, including edge sensitive, onto same interrupt level interrupt controller. STi5518 interrupt level controller also registers mapped into register address space, that have connection with normal interrupt operation. These registers controlling waking external interrupt pin, when been into power mode, power controller module. register INC_SELNOTINV controls whether three external interrupt pins active high low, wake from power mode. Note that setting this register effect triggering external interrupt pins interrupt level controller. register INC_EN_INT mask register enable disable external interrupt pins from waking from power mode. Again, this effect masking these interrupts interrupt level controller.
Interrupt system
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Interrupt system
Interrupt assignments
interrupts active high. Interrupts from internal peripherals external pins assigned table below.
20-23
Compare function Compare function Compare function Compare function Compare function
STi5518
Peripheral
Description functions
SSC0 SSC1 UART UART UART UART Capture MPEG3DMA MPEG3DMA MPEG3DMA BLOCK MOVE MODEM PIO5 Blaster TeleText Reserved IRQ0 IRQ1 IRQ2 MPEGAV block MPEGAV block MPEGAV block Link interface interrupt
SSC0TIR, SSC0RIR, SSC0EIR MASTER SSC1TIR, SSC1RIR, SSC1EIR MASTER ASC3TIR, ASC3TBIR, ASC3RIR, ASC3EIR ASC2TIR, ASC2TBIR, ASC2RIR, ASC2EIR ASC1TIR, ASC1TBIR, ASC1RIR, ASC1EIR ASC0TIR, ASC0TBIR, ASC0RIR, ASC0EIR PWMFunctions, (Capture0Int, Capture1Int TBD) MPEG3DMA0 Interrupt MPEG3DMA1 Interrupt MPEG3DMA inside Link Interface interrupt Blockmove Interrupt MAFE modem Interface Interrupt Compare Function interrupts Ttxt interrupt Tied internally SERVO interrupt request ATAPI interrupt request interrupt request Audio interrupt from MPEGAV block Video interrupt from MPEGAV block Sector processor interrupt link interrupt Link interface interrupt Table STi5518 Interrupt assignments
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STi5518 32-bit signed 2s-complement address space. byte memory addressed 30-bit word address plus 2-bit byte-selector identifier word. word memory addressed 30-bit word address with byte-selector zero. Memory divided into areas with different purposes. Some areas dedicated specific purpose, either because they contain memory-mapped devices because they reserved system. figure below shows memory map.
0xFFFFFFFF
Memory Overview
Memory
Region
available
0xC0800000 Shared SDRAM 0xC0000000
available Region
Kbyte configurable data cache SRAM Kbyte SRAM
0x80001800 0x80001000 0x80000000
Bank 0x70000000 Bank Region 0x60000000 Bank 0x50000000 Bank 0x40000000
Reserved Region
0x20040000
Peripheral configuration registers
0x00000000
Figure Memory
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Memory
Memory normally accessed load, store, block move channel instructions. These will data cache enabled, guarantee order accesses different addresses.
address space divided into following regions:
Mapping
STi5518
Region DCache SRAM, bottom Kbytes Kbytes data cache used) occupied on-chip
SRAM.
Region Shared SDRAM, Mbyte area from 0xC0000000 0xC07FFFFF SDRAM shared with
MPEG decoders;
Region Peripheral configuration registers, area from 0x00000000 0x3FFFFFFF dedicated memorymapped command-mapped on-chip peripherals;
Region banks0 0x40000000 0x7FFFFFFF external memory peripherals, accessed through
Designation MPEG Start #00000000 #00000200 #00000400 #00000600 #00000700 #00000800 #00000A00 #00000C00 #00000E00 Configuration #00002000 #00003000 #00004000 #00005000 #000001FF #000002FF #000005FF #000006FF #000007FF #000009FF #00000BFF #00000DFF #00000FFF #00002FFF #00003FFF #00004FFF #1FFFFFFF Description MPEG Video MPEG Audio Sub-Picture decoder DENC decoder Reserved MPEG Video fifos accesses MPEG Audio fifos accesses Sub-Picture decoder accesses MPEG control registers configuration Cache configuration Reserved
Table STi5518 memory
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Designation Peripherals
Start
#20000000
#20000FFF #20003FFF #20004FFF #20005FFF #20006FFF #20007FFF #20008FFF #20009FFF #2000A0FF #2000A1FF #2000A2FF #2000A3FF #2000AFFF #2000BFFF #2000CFFF #2000DFFF #2000EFFF #2000FFFF #20010FFF #20011FFF #20024FFF #20025FFF #20026FFF #20027FFF #20037FFF #2003FFFF
Memory
Description
Int. controller
#20003000 #20004000 #20005000 #20006000 #20007000 #20008000 #20009000 #2000A000 #2000A100 #2000A200 #2000A300 #2000A400 #2000B000 #2000C000 #2000D000 #2000E000 #2000F000 #20010000 #20011000 #20024000 #20025000 #20026000 #20027000 #20030000 #20038000
UART0 (ASC0) Smartcard UART1 (ASC1) UART2 (ASC2) UART3 (ASC3) Smartcard SCCG0 (Smcard clkgen SCCG1 (Smcard1 clkgen) SSC0 SSC1 PIO5 Blaster TTXT Reserved MPEGDMA MPEGDMA Block Move MODEM Reserved Link extra (Link Interface)
Table STi5518 memory
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Designation Region banks0
Start
0x40000000 0x50000000 0x60000000
0x4FFFFFFF 0x5FFFFFFF 0x6FFFFFFF 0x7FFFFFFF 0x80000003 0x8000000F 0x80000013 0x8000003F 0x8000004F 0x8000005F 0x8000006F 0x8000007F 0x8000008F 0x8000009F 0x800000AF 0x800000BF 0x800000CF 0x800000DF 0x800000EF 0x800000FF 0x8000010F 0x8000011F 0x8000012F 0x8000013F 0x80000FFF 0x800017FF 0xBFFFFFFF 0xC07FFFFF 0xFFFFFFFF
STi5518
Description
bank SDRAM/DRAM supported bank SDRAM/DRAM supported
bank SDRAM/DRAM supported bank normally used boot ROM. DRAM supported Boot entry point Reserved Reserved Reserved Reserved High priority Breakpoint trap handler High priority Breakpoint trapped process High priority Error trap handler High priority Error trapped process High priority SystemOperations trap handler High priority SystemOperations trapped process High priority Scheduler trap handler High priority Scheduler trapped process priority Breakpoint trap handler priority Breakpoint trapped process priority Error trap handler priority Error trapped process priority SystemOperations trap handler priority SystemOperations trapped process priority Scheduler trap handler priority Scheduler trapped process Internal SRAM: Kbytes user code, data stack Internal SRAM data cache enabled.User-code, data stack Reserved SDRAM. Video memory, user code, data, stack Reserved
0x70000000 0x7FFFFFFE
Region DCache SRAM
0x80000000 0x80000004 0x80000010 0x80000014 0x80000040 0x80000050 0x80000060 0x80000070 0x80000080 0x80000090 0x800000A0 0x800000B0 0x800000C0 0x800000D0 0x800000E0 0x800000F0 0x80000100 0x80000110 0x80000120 0x80000130 0x80000140 0x80001000 0x80001800
Region Shared SDRAM
0xC0000000 0xC0400000
Table STi5518 memory
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System memory
following sections address space reserved system use:
locations below address MemStart bottom memory dedicated processor use. address
MemStart returned ldmemstartval instruction.
When booting from ROM, system boots from predefined location BootEntry (0x7FFFFFFE)
memory. Areas memory reserved processor should accessed directly. Special instructions provided manipulating these areas. special address MemStart marks base user memory space. Peek poke words above MemStart, i.e. memory locations 0x80000140 0x80000147. peek poke described System services page Subsystem channels memory Each channel based subsystem allocated word storage below MemStart. This used processor store information about state that channel. This information should normally examined directly, although debugging kernels need Interrupting subsystems have channel word allocated rely interrupts perform synchronization with processes running processor. Memory trap handlers area memory reserved trap handlers broken down hierarchically follows:
Memory
each high/low process priority trap handlers; each trap handlers handler each four trap groups; each trap group handler trap handler structure trapped process structure; each structures contains four words.
contents these addresses accessed ldtraph, sttraph, ldtrapped sttrapped instructions. Boot When processor boots from ROM, jumps boot program held with entry point bytes from memory 0x7FFFFFFE. These bytes used encode negative jump bytes down program. large programs then necessary encode longer negative jump reach start routine.
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Memory
Memory
Programmable interface memory programmable interface memory (commonly referred EMI) decodes region address space into four banks, into which different external memories peripherals mapped. Further details found Programmable memory interface page banks support DRAM bank normally used boot ROM.
External memory
STi5518
Locations 0x40000000 0x5FFFFFFF (banks generally used SDRAM/DRAM, used
external memory peripherals.
locations 0x60000000 0x6FFFFFFF (bank used external memory peripherals except
SDRAM/DRAM.
locations 0x70000000 0x7FFFFFFF (bank used external memory peripherals except
SDRAM/DRAM, generally used boot ROM. When booting from ROM, system boots from predefined location BootEntry (0x7FFFFFFE) memory space. Accessing some areas memory causes special access characteristics (strobes etc.) generated depending programmed. provides address decoding, address data buses, timing strobes, enabling signals refresh where appropriate. Shared SDRAM memory shared SDRAM memory occupies first Mbits region shared with MPEG decoders. bitmaps, example, stored this memory. details shared SDRAM memory interface configuration set-up, refer Register Manual.
On-chip SRAM memory
This internal memory module, known on-chip memory, contains Kbytes SRAM, which mapped into lowest Kbytes memory space from MinInt (0x80000000) extending upwards, shown Figure page Part lowest Kbytes memory committed system use; System memory page details. remainder lowest Kbytes memory uncommitted used store on-chip data, stack code time-critical routines. upper Kbytes on-chip memory also uncommitted SRAM, contiguous with lower Kbytes. However, configured data cache, described below, which case available SRAM. Locations between 0x80001800 0x80001000 data cache used) 0xBFFFFFFF should addressed.
Caching
Cache used reduce average access delay imposed when accesses memory location read write. Some locations should cached, example those which other modules have direct memory access DMA) also requires access those locations. This because operations always bypass data cache cache incoherence problems will occur. therefore recommended configure such memory locations being non-cacheable. STi5518 cache subsystem provides:
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Kbytes direct-mapped write-back data cache
Kbytes direct-mapped read-only instruction cache
cache configuration held memory-mapped registers. registers must accessed using device access instructions. Device access instructions also used force access external memory they bypass cache. Device writes change value cache. These instructions used solve cache coherency issues, example where data being copied from cached location. However care must taken using device access instructions access memory (rather than device registers) cache coherency problems occur rather than being solved, also performs normal (therefore cached) memory accesses these locations. Registers provided configure areas memory cacheable non-cacheable data access, described Cacheable non-cacheable memory locations page Note that correct cache initialization sequences, described Cache initialization page must used before caches enabled.
Memory
7.3.1 Outline operation
cache four 32-bit words bytes) wide lines KBytes, words) high. direct-mapped (sometimes called associative). This shown Figure below.
bytes line Address bits
lines
Figure Kbyte data instruction cache2
Each line cache only store data from specific four-word sections memory Kbyte intervals, with bottom line cache coinciding with words just above each Kbyte boundary. Thus line number cache pinpoints four-word section memory within Kbyte block, i.e. bits address. most significant bits address selects Kbyte block. These bits stored registers, with
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Memory
register corresponding each cache lines. significance parts address when using cache shown figure below.
21-bit address
STi5518
4-bit selector byte within cache line 7-bit selector line Kbyte memory block cache
Figure Address fields when using cache
request made access cacheable memory location, copy that location held cache, then access said have made cache hit. identified comparing address bits with address cache line given address bits cache hit, then access completed cache subsystem. cache missed, appropriate cache line written back memory, necessary location memory read into that cache line. cache reads writes memory complete lines because efficiency accessing memory burst mode.
7.3.2 Cache initialization
Before caches enabled, they must correctly initialized. this cache must first invalidated before accessed. ensure this occurs, invalidate each cache must with cache disabled then enable enable cache. This sequence effect forcing cache invalid, which initializes cache state before other accesses considered cache.
7.3.3 Cache subsystem control
cache subsystem registers control cache functions such flushing invalidation, used mark sections memory space cacheable cacheable. Registers should accessed using device access instructions. CAC_CACHECONTROLLOCK must before some registers changed. After changing registers, CAC_CACHECONTROLLOCK should Once this lock cannot cleared except reset. recommended change cache configuration other than reset.
7.3.4 Data cache
possible select either data cache extra Kbyte on-chip SRAM. This done writing CAC_DCACHENOTSRAM register. default enable extra on-chip SRAM. CAC_DCACHENOTSRAM select data cache mode enable cache. access locations 0x80001000 0x800017FF when using data cache. cache invalidate should before enabling cache. Invalidating cache marks every line containing valid data. This done setting CAC_INVALIDATEDCACHE register This register automatically reset completion task, cannot directly read register write only. Therefore provided CAC_CACHESTATUS register indicate when invalidate operation completed.
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Note that data cache, setting CAC_INVALIDATEDCACHE register before cache enabled does actually cause invalidation sequence begin. This only occurs when cache enabled when writing CAC_DCACHENOTSRAM register. initialize sequence operations should
write CAC_INVALIDATEDCACHE register; write CAC_DCACHENOTSRAM register "atomic" operation.
Where, "atomic" means than other software processes tasks, trap handlers interrupt handlers execute time between write invalidate register write cache enable register. Note: this will normally case cache initialization should performed during initialization stage application code, before operating system (STLite/OS20) interrupt handlers have been installed.
Memory
wait invalidate sequence clock cycles) finish.
This done software delay loop and/ polling cache status register. Note recommended ensure that does attempt execute code access data cacheable memory locations before invalidate sequence finished. Therefore cache initialization done (rather than poking registers DCU, before booting application code from software toolset) software (code data) that waits invalidate sequence finish should reside noncacheable memory locations, that cache accessed while still invalidating. this ensured possible data corruption occur. recommended change selection from data cache SRAM during operation. However, necessary essential flush cache maintain memory integrity before making change. Flushing cache means forcing write-back memory every dirty line cache. dirty line line cache that been written since loaded last written back. Only data cache flushed; instruction cache never needs flushing since read only. flush data cache, CAC_FLUSHINGDCACHE register automatically reset completion task, cannot read directly register write only. Therefore check that flush operation finished necessary poll cache status register. Ensure that cache-flush software function "atomic" operates follows:
writes flush register; waits flush finish; writes CAC_DCACHENOTSRAM register "atomic" operation.
Where, "atomic" means than other software processes tasks, trap handlers interrupt handlers execute time between writing flush register DCache being changed back SRAM mode. Note: code function associated data used perform this sequence must placed non-cacheable memory locations, cache accessed while still flushing.
7.3.5 Instruction cache
instruction cache must first invalidated writing CAC_INVALIDATEICACHE register. Invalidating cache marks every line containing valid data. This done setting CAC_INVALIDATEICACHE register This register automatically reset completion task (128 cycles). However this register read CPU, write only, therefore Invalidating ICache) CAC_CACHESTATUS register read instead check that invalidate operation completed. instruction cache must allowed complete invalidate operation before cache enabled. Note: unlike data cache instruction cache actually starts invalidation sequence when CAC_INVALIDATEICACHE written allowed complete before enabling cache writing CAC_ENABLEICACHE register.
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Memory
instruction cache then enabled writing CAC_ENABLEICACHE register; default condition disabled, instruction cache. CAC_CACHESTATUS register read only, shows current state caches. cache configuration locked writing CAC_CACHECONTROLLOCK register bit. Reset this flag only performed hardware reset. This should after cache configuration registers have been written.
STi5518
7.3.6 Cacheable non-cacheable memory locations
Note: cacheability control registers both region1 region should programmed before caches enabled. this cacheable non-cacheable memory areas already defined when caches enabled, Cache initialization page dynamically change these registers after cache initialization.
MEMORY SIZE byte
bank3
0x7FFFFFFF 0x70000000 bank2 Region bank1 0x50000000 bank0
block0-7
0x60000000
0x40000000
cacheable data cache Region (Peripheral registers) cacheable instruction cache
0x00000000
available Region (Shared memory interface) 0xC0800000 SDRAM 16*512kbyte blocks SDRAM 16*64kbyte blocks 0xC0100000 0xC0000000
available Region (Internal SRAM) 2Kbytes DCache configurable SRAM SRAM
0x80001800 0x80001000 0x80000000
Figure Memory cacheability
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Region
REGION used only access internal SRAM therefore, never cacheable either ICACHE DCACHE. There always SRAM. Because DCACHE configured SRAM, there another SRAM (for total amount SRAM). This controlled CAC_DCACHENOTSRAM register, which must configured to'0' SRAM, to'1' DCACHE. Region This region mostly non-cacheable data access. programmed cacheable (default non-cacheable) either blocks bytes blocks 512K bytes. These blocks contiguous placed starting from address 0xC0000000. Each these blocks selected individually cacheable non-cacheable DCACHE memory accesses. This controlled registers (CAC_CACHECONTROL0 where each controls cacheability characteristics particular 64K/512K block. select between byte 512K byte block size, CAC_CACHECONTROL0 register used. After reset, blocks marked non-cacheable size each block byte. registers must then programmed mark certain blocks cacheable. remainder REGION1 non-cacheable DCACHE.
Memory
Kbyte Blocks
BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK 0xC00F 0000 0xC00E 0000 0xC00D 0000 0xC00C 0000 0xC00B 0000 0xC00A 0000 0xC009 0000 0xC008 0000 0xC007 0000 0xC006 0000 0xC005 0000 0xC004 0000 0xC003 0000 0xC002 0000 0xC001 0000 0xC000 0000
Kbyte Blocks
BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK 0xC078 0000 0xC070 0000 0xC068 0000 0xC060 0000 0xC058 0000 0xC050 0000 0xC048 0000 0xC040 0000 0xC038 0000 0xC030 0000 0xC028 0000 0xC020 0000 0xC018 0000 0xC010 0000 0xC008 0000 0xC000 0000
REGION 0xFFFF FFFF
REGION 0xFFFF FFFF
0xC010 0000 0xC00F FFFF
0xC080 0000 0xC07F FFFF
0xC000 0000
0xC000 0000
Figure Region1 cacheable area with block sizes byte 512Kbyte.
Region Always non-cacheable DCACHE, cacheable ICACHE.
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Memory
Region
This region split into banks, 0-3. ICACHE they cacheable. DCACHE they cacheable non-cacheable 4-bit register CAC_CACHECONTROL3, default non-cacheable. bank split into parts; upper part cacheable same banks lower part, containing 64Kbyte blocks, non-cacheable. These blocks, located between 0x40000000 0x4007FFFF, cacheable 8-bit register CAC_CACHECONTROL2.
0x7FFFFFFF
STi5518
bank 0x70000000 0x6FFFFFFF 0x60000000 0x5FFFFFFF 0x50000000 0x4FFFFFFF bank 0x4007FFFF 0x40000000 bank bank BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK 0x4008 0000 0x4007 0000 0x4006 0000 0x4005 0000 0x4004 0000 0x4003 0000 0x4002 0000 0x4001 0000 0x4000 0000
Kbyte Blocks
Figure Region
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Programmable Interface (EMI) controls movement data between STi5518 off-chip memory, except shared SDRAM which connected dedicated interface (SMI). uses minimal external support logic support memory subsystems. accesses Mbytes physical address space (greater SDRAM DRAM used) four general purpose memory banks bits wide, address lines, byte select. applications requiring extra memory, supports this extra memory with zero external support logic. interface configured wide variety timing decode functions through configuration registers. maps external memory into quarter address space partitioned into four banks with each bank occupying sixteenth total address space. Systems several memory types such SDRAM, DRAM, SRAM, Flash EPROM, other peripherals. figure below illustrates Programmable Interface memory allocation. Warning! possible have SDRAM DRAM Programmable Interface same time.
interface Programmable memory
Programmable memory interface
Physical addresses
7FFFFFFF 70000000 60000000 50000000 40000000 3FFFFFFF bank0 On-chip peripheral registers bank3 bank2 bank1
On-chip peripheral registers (including cache configuration registers) mapped into this region.
00000000 FFFFFFFF
C0000000 BFFFFFFF
80001800 80001000 80000000 SRAM (D-cache off) Internal SRAM
Figure Memory allocation
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Programmable memory interface
timing each four memory banks selected separately, with different device types being placed each bank with external hardware support. Banks configured contain 8-bit wide 16-bit wide devices. supports three memory types:
SDRAM with multiplexed column address; DRAM with multiplexed column address used support fast page mode; SRAM peripherals, which used support SRAMs, peripherals, EPROM Flash ROMs.
banks support either memory type, while banks only support SRAM peripheral memory types. Words byte bytes addressed. behavior some strobes depends whether bank being accessed been configured SDRAM, DRAM SRAM peripheral
STi5518
Note
functions
cycle defined processor clock cycle, phase half processor clock cycle.
table below describes functions Programmable Interface pins. Note that signal name prefixed indicates that active-low. pins listed alphabetical order.
BOOT_FROM_ Function When BOOT_FROM_ROM held low, STi5518 boots from DCU. When BOOT_FROM_ROM held high, STi5518 boots from ROM. Boot code from external bank memory). BOOT_FROM_ROM also used encode size bank3 (which 16-bit), this value overrides PortSize value bank configuration registers. STi5518 being booted DCU, then bootstrap must execute from internal memory until been configured. CPU_ADDR[1:21] address operates both multiplexed non-multiplexed modes. When bank configured conand [22] tain SDRAM, DRAM, another multiplexed memory, device type SDRAM DRAM, internally generated 32-bit address multiplexed column addresses through external address bus. extra address CPU_ADDR[22] used when DRAM SDRAM support required Programmable Interface. This allows direct addressing 8Mbytes peripheral SRAM modes. also used notCPU_CAS[0] signal. CPU_DATA[0:15] data transfers 8-bit data items depending width configuration. least significant data always CPU_DATA[0]. most significant varies with width. will CPU_DATA15 16-bit data items, CPU_DATA7 8-bit data items. This reference signal external cycles, which oscillates processor clock frequency. This signal indicates whether current cycle read write cycle. During writes, signal asserted beginning access (i.e. start RASTime DRAM banks start CSTime SRAM peripheral banks) de-asserted high access (end CASTime CSTime). other times this signal held high. Wait states generated taking CPU_WAIT high. CPU_WAIT only sampled during SRAM peripheral accesses. CPU_WAIT retains state strobe during cycle after which asserted, until deasserted. When CPU_WAIT de-asserted access continues programmed configuration interface. CPU_WAIT signal treated synchronous asynchronous CPU_PROCLK clock, depending state EMI_ConfigPadLogic register. This disabled software. used, this should pulled down with resistor. Table Programmable interface descriptions
CPU_PROCLK CPU_RW
CPU_WAIT
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notCPU_BE[0:1]
Function notCPU_BE[1] notCPU_BE[0]
uses word addressing, byte-enable strobes provided, byte enable pins depends width. 16-bit wide memory defined array 2-byte words: address-bits ST20 memory space select 2-byte word "notCPU_BE[0:1]" selects byte within word. 8-bit wide memory defined array 1-byte words with address-bits selecting word. 8-bit wide memory, lower order address (A0) multiplexed onto unused byte-enable notCPU_BE[1] give 32-bit address bus. This address made available address configuring bank width below. 16-bit external port size enables CPU_Data[8:15] enables CPU_Data[0:7] 8-bit external port size notCPU_ADDR[0] enables CPU_Data[8:15]
Programmable memory interface
banks configured SDRAM, notCPU_BE pins provide mask signals. banks configured DRAM, notCPU_BE strobes valid from start CASTime phase before CASTime. banks configured SRAM, notCPU_BE pins used data-enable strobes have same timing configured active read cycles, write cycles, both read write cycles. notCPU_CAS[0:1] notCPU_CAS[0:1] strobes have different meanings depending contents banks DRAM (bank byte mode), SDRAM SRAM. three configurations described below. Table Programmable interface descriptions
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Programmable memory interface
notCPU_CAS[0:1] strobes programmed per-bank basis modes. DRAM Bank mode which only strobe used entire bank sub-banks any). configuration
Function
STi5518
Byte mode which each strobe used byte decoded strobe used across both banks (and sub-banks).
Byte mode supports 16-bit wide DRAMs DRAM modules that provide multiple strobes, each byte, single write signal byte write operations. alternative type DRAMs that have multiple write signals, each byte, single allow byte write operations banks that constructed from 8-bit wide DRAMs interfaced using bank mode. Note Bank byte mode selected independently banks
strobes bank mode (DRAM) banks and1 DRAM device type with bank mode selected then notCPU_CAS[0] sole strobe bank notCPU_CAS[1] sole strobe bank1. Unused strobes remain inactive during access. strobes byte mode (DRAM) banks containing DRAM, which require byte decoded strobes, programmable strobe allocated each byte. Each strobes this mode will have timing programmed into timing configuration registers, bank being accessed, they active during that cycle. Byte mode strobes active during access byte corresponding strobe being accessed. During refresh cycles, strobes will start cycle remain until cycle. table below shows strobes used byte mode. Note that strobes common both banks sub-banks. Only strobes that enable bytes which being accessed will active during access cycle. table below summarizes Byte mode notCPU_CAS[0:1] strobe pins strobe notCPU_CAS[1] notCPU_CAS[0] Bank 16-bits wide enables CPU_DATA[8:15] enables CPU_DATA[0:7] Bank 16-bits wide enables CPU_DATA[8:15] enables CPU_DATA[0:7]
Mixing bank byte mode (DRAM) full flexibility, permutation bankwidth mode (byte bank) supported both banks following table gives full listing active strobes permutations DRAMs DRAM bank0 Bank Configuration bank mode byte mode notCPU_CAS[0] active active CPU_DATA[0:7] notCPU_CAS[1] unused active CPU_DATA[8:15] unused active CPU_DATA[8:15] unused active CPU_DATA[8:15]
DRAMs bank and1 DRAM bank0 bank mode active DRAM bank0 byte mode active CPU_DATA[0:7] DRAM bank1 bank mode unused DRAM bank1byte mode active CPU_DATA[0:7] Table Programmable interface descriptions
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notCPU_CAS[0:1] SDRAM configuration
Function DRAMs
notCPU_CAS[0]
Programmable memory interface
notCPU_CAS[1]
active chip select SDRAM
SDRAM bank0 SDRAM bank1 SDRAM bank0 SDRAM bank1
active (CAS strobe SDRAM)
active (CAS strobe both SDRAMs) active chip select SDRAM bank
notCPU_CAS[0:1] banks which contain SDRAM DRAM notCPU_CAS[1] inactive. there SDRAM DRAM programmable interface, notCPU_CAS[0] CPU_ADDR[22] allow 8MBytes SRAM SRAM addressing. configuration notCPU_CE[0:3] These four signals used programmable strobe (for example, chip select when corresponding bank configured SRAM/peripheral When SRAM/DRAM used corresponding interface, notCPU_CE[0:3] used signal. notCPU_OE
behavior notCPU_OE signal depends type memory being accessed. access bank configured DRAM then notCPU_OE strobe active only during read access when asserted CASe1Time after start CASTime, de-asserted high CASTime. accesses configured SRAM peripheral notCPU_OE strobe programmable will behave according values EMIConfigData registers that bank.
notCPU_RAS[0:1] These signals control strobe SDRAM DRAM. signals necessarily correspond individual banks. Bank0 (only) sub-decoded. DRAM, notCPU_RAS[0:1] strobes used strobes bank0, bank1, sub-banks. SDRAM, strobe used devices bank, sub-decoding carried using notCPU_RAS[1] notCPU_CAS[1]pins. bank0 programmed SDRAM DRAM, notCPU_RAS[0] strobe used chip-select (notCPU_CE[0]) bank. Signal notCPU_RAS[0] Type Definition strobe SDRAM/DRAM Bank strobe lowest DRAM sub-bank Bank0, chip select Bank0 strobe SDRAM/DRAM Bank1, strobe highest DRAM sub-bank Bank0, SDRAM chip select signal highest sub-bank Bank0
notCPU_RAS[1]
table below summarizes notCPU_RAS[0:1] strobes banks Bank Configuration Bank DRAM with sub-decoding Bank DRAM with sub-banks Bank SDRAM with sub-decoding Bank SDRAM with sub-banks Bank SRAM peripherals Bank 1DRAM with sub-decoding Bank 1DRAM with sub-banks Bank SDRAM with sub-decoding Bank SDRAM with sub-banks Bank 1contains SRAM peripheral notCPU_RAS[0] Bank strobe Bank sub-bank0 strobe Bank strobe Bank sub-bank0 strobe Bank chip select strobe Bank 1RAS strobe possible Bank strobe possible Unused bank1 notCPU_RAS[1] Unused bank0 Bank sub-bank1 strobe Unused bank0 Bank sub-bank1 with chip select Bank3 sub-decoding Unused bank1 possible Unused bank1 possible Bank3 sub-decoding
Table Programmable interface descriptions
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Programmable memory interface
Configuration list
following tables illustrate different configurations supported SDRAM, DRAM peripheral memories, different strobes used each case. Note that possible have SDRAM DRAM same time.
bank configuration Strobes bank0 Peripheral bank1 bank2 bank3 Peripheral Peripheral Peripheral notCPU_CE[0] bank0, notCPU_CE[1]for bank1, notCPU_CE[2]for bank2 notCPU_CE[3]for bank3. notCPU_RAS1 available subdecode bank3 notCPU_CAS0 CPU_ADD[22] allow Mbytes SRAM addressing notCPU_CAS1 used notCPU_OE shared each bank notCPU_BE[1:0] shared each bank CPU_R/W shared each bank CPU_WAIT shared each bank DRAM Peripheral DRAM Peripheral Peripheral Peripheral DRAM bank notCPU_CE[1] bank1 DRAM bank1: notCPU_CE[1] bank0 Peripheral Peripheral notCPU_CE[2]for bank2 notCPU_CE[3]for bank3 notCPU_CE[0] (RAS0) DRAM despite DRAM position notCPU_CAS0 (CAS0) used DRAM notCPU_CAS1 (CAS1) used DRAM only multi-byte mode enabled DRAM (and only bank0, then subdecoding DRAM sub-banks using CPU_RAS1 DRAM bank0 DRAM subdecoding DRAM bank1, CPU_RAS1 available subdecode bank3 notCPU_OE shared each bank notCPU_BE[1:0] shared each bank. CPU_R/W shared each bank. CPU_WAIT shared each bank Table List strobes used configurations
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bank configuration bank0 DRAM bank1
DRAM
bank2
bank3
Strobes
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