PALCE16V8 Family CMOS 20-Pin Universal Programmable Array Logic
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COM'L: H-5/7/10/15/25, Q-10/15/25 IND: H-10/15/25, Q-20/25
PALCE16V8 Family
CMOS 20-Pin Universal Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
function compatible with 20-pin devices Electrically erasable CMOS technology provides reconfigurable logic full testability High-speed CMOS technology 5-ns propagation delay "-5" version 7.5-ns propagation delay "-7" version Direct plug-in replacement PAL16R8 series most PAL10H8 series Outputs programmable registered combinatorial combination Peripheral Component Interconnect (PCI) compliant Programmable output polarity
Advanced Micro Devices
Programmable enable/disable control Preloadable output registers testability Automatic register reset power Cost-effective 20-pin plastic DIP, PLCC, SOIC packages Extensive third-party software programmer support through FusionPLD partners Fully tested 100% programming functional yields high reliability version utilizes split leadframe improved performance
GENERAL DESCRIPTION
PALCE16V8 advanced device built with low-power, high-speed, electrically-erasable CMOS technology. functionally compatible with 20-pin devices. macrocells provide universal device architecture. PALCE16V8 will directly replace PAL16R8 PAL10H8 series devices, with exception PAL16C1. PALCE16V8 utilizes familiar sum-of-products (AND/OR) architecture that allows users implement complex logic functions easily efficiently. Multiple levels combinatorial logic always reduced sum-of-products form, taking advantage very wide input gates available devices. equations programmed into device through floatinggate cells logic array that erased electrically. fixed array allows eight data product terms output logic functions. these products feeds output macrocell. Each macrocell programmed registered combinatorial with activehigh active-low output. output configuration determined global bits local controlling four multiplexers each macrocell. AMD's FusionPLD program allows PALCE16V8 designs implemented using wide variety popular industry-standard design tools. working closely with FusionPLD partners, certifies that tools provide accurate, quality support. ensuring that thirdparty tools available, costs lowered because designer does have complete tools each device. FusionPLD program also greatly reduces design time since designer tool that already installed familiar.
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Publication# 16493 Rev. Issue Date: February 1996
Amendment
BLOCK DIAGRAM
CLK/I0
Programmable Array
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
OE/I9
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7 16493D-1
CONNECTION DIAGRAMS View DIP/SOIC
CLK/I0 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 OE/I9
PLCC/LCC
CLK/I0 I/O7
I/O6 I/O5 I/O4 I/O3 I/O2
16493D-2
OE/I9 I/O0 I/O1
16493D-3
Note: marked orientation.
DESIGNATIONS
Clock Ground Input Input/Output Output Enable Supply Voltage PALCE16V8 Family
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ORDERING INFORMATION Commercial Industrial Products
programmable logic products commercial industrial applications available with several ordering options. order number (Valid Combination) formed combination
FAMILY TYPE Programmable Array Logic TECHNOLOGY CMOS Electrically Erasable NUMBER ARRAY INPUTS OUTPUT TYPE Versatile NUMBER OUTPUTS POWER Half Power ICC) Quarter Power ICC) SPEED
OPTIONAL PROCESSING Blank Standard Processing PROGRAMMING DESIGNATOR Blank Initial Algorithm First Revision Second Revision (Same Algorithm
OPERATING CONDITIONS Commercial (0°C +75°C) Industrial (-40°C +85°C) PACKAGE TYPE 20-Pin Plastic 020) 20-Pin Plastic Leaded Chip Carrier 020) 20-Pin Plastic Gull-Wing Small Outline Package 020)
Valid Combinations PALCE16V8H-5 PALCE16V8H-7 PALCE16V8H-10 PALCE16V8Q-10 PALCE16V8H-15 PALCE16V8Q-15 PALCE16V8Q-20 PALCE16V8H-25 PALCE16V8Q-25
Valid Combinations Valid Combinations lists configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
Blank,
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PALCE16V8H-5/7/10/15/25, Q-10/15/25 (Com'l) H-10/15/25, Q-20/25 (Ind)
FUNCTIONAL DESCRIPTION
PALCE16V8 universal device. eight independently configurable macrocells (MC0-MC7). Each macrocell configured registered output, combinatorial output, combinatorial dedicated input. programming matrix implements programmable logic array, which drives fixed logic array. Buffers device inputs have complementary outputs provide user-programmable input signal polarity. Pins serve either array inputs clock (CLK) output enable (OE), respectively, flip-flops. Unused input pins should tied directly GND. Product terms with bits unprogrammed (disconnected) assume logical HIGH state product terms with both true complement input signal connected assume logical state. programmable functions PALCE16V8 automatically configured from user's design
specification. design specification processed development software verify design create programming file (JEDEC). This file, once downloaded programmer, configures device according user's desired function. user given design options with PALCE16V8. First, programmed standard device from PAL16R8 PAL10H8 series. programmer manufacturer will supply device codes standard device architectures used with PALCE16V8. programmer will program PALCE16V8 corresponding architecture. This allows user existing standard device JEDEC files without making changes them. Alternatively, device programmed PALCE16V8. Here user must PALCE16V8 device code. This option allows full utilization macrocell.
Adjacent Macrocell
SL1X SL0X I/OX
From Adjacent
16493D-4
macrocells MC7, replaced feedback multiplexer.
PALCE16V8 Macrocell
PALCE16V8 Family
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Configuration Options
Each macrocell configured following: registered output, combinatorial output, combinatorial I/O, dedicated input. registered output configuration, output buffer enabled pin. combinatorial configuration, buffer either controlled product term always enabled. dedicated input configuration, always disabled. With exception MC7, macrocell configured dedicated input derives input signal from adjacent I/O. derives input from (OE) from (CLK). macrocell configurations controlled configuration control word. contains global bits (SG0 SG1) local bits (SL00 through SL07 SL10 through SL17). determines whether registers will allowed. determines whether PALCE16V8 will emulate PAL16R8 family PAL10H8 family device. Within each macrocell, SL0x, conjunction with SG1, selects configuration macrocell, SL1x sets output either active active high individual macrocell. configuration bits work acting control inputs multiplexers macrocell. There four multiplexers: product term input, enable select, output select, feedback select multiplexer. SL0x control signals four multiplexers. MC7, replaces feedback multiplexer. This accommodates being adjacent adjacent MC0.
feedback path will feedback path MC0.
Combinatorial Non-Registered Device
control settings SL0x Only seven product terms available gate. eighth product term used enable output buffer. signal back array feedback multiplexer. This allows used input. Because used non-registered device, pins available inputs. will feedback path will feedback path MC0.
Combinatorial Registered Device
control settings SL0x Only seven product terms available gate. eighth product term used output enable. feedback signal corresponding signal.
Dedicated Input Configuration
control settings SL0x output buffer disabled. Except feedback signal adjacent I/O. feedback signals pins These configurations summarized Table illustrated Figure Table Macrocell Configuration
Registered Output Configuration
control settings SL0x There only registered configuration. eight product terms available inputs gate. Data polarity determined SL1x. flip-flop loaded LOW-to-HIGH transition CLK. feedback path from register. output buffer enabled
Combinatorial Configurations
PALCE16V8 three combinatorial output configurations: dedicated output non-registered device, non-registered device registered device.
SL0X Cell Configuration Devices Emulated Device Uses Registers Registered Output PAL16R8, 16R6, 16R4 Combinatorial PAL16R6, 16R4 Device Uses Registers Combinatorial PAL10H8, 12H6, Output 14H4, 16H2, 10L8, 12L6, 14L4, 16L2 Input PAL12H6, 14H4, 16H2, 12L6, 14L4, 16L2 Combinatorial PAL16L8
Programmable Output Polarity
polarity each macrocell active-high active-low, either match output signal needs reduce product terms. Programmable polarity allows Boolean expressions written their most compact form (true inverted), output still desired polarity. also save "DeMorganizing" efforts. Selection through programmable SL1x which controls exclusive-OR gate output AND/ logic. output active high SL1x active SL1x
Dedicated Output Non-Registered Device
control settings SL0x eight product terms available gate. Although macrocell dedicated output, feedback used, with exception pins Pins feedback this mode. Because used non-registered device, pins available input signals. will 2-40
PALCE16V8 Family
Registered Active
Registered Active High
Combinatorial Active
Combinatorial Active High
Note
Note
Combinatorial Output Active
Combinatorial Output Active High
Notes: Feedback available pins combinatorial output mode. This configuration available pins
Adjacent Note
Dedicated Input Figure Macrocell Configurations PALCE16V8 Family
16493D-5
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Power-Up Reset
flip-flops power logic predictable system initialization. Outputs PALCE16V8 will depend whether they selected registered combinatorial. registered selected, output will HIGH. combinatorial selected, output will function logic.
Programming Erasing
PALCE16V8 programmed standard logic programmers. also erased reset previously configured device back virgin state. Erasure automatically performed programming hardware. special erase operation required.
Quality Testability
PALCE16V8 offers very high level built-in quality. erasability device provides direct means verifying performance parameters. addition, this verifies complete programmability functionality device provide highest programming yields post-programming functional yields industry.
Register Preload
register PALCE16V8 preloaded from output pins facilitate functional testing complex state machine designs. This feature allows direct loading arbitrary states, making unnecessary cycle through long test vector sequences reach desired state. addition, transitions from illegal states verified loading illegal states observing proper recovery.
Technology
high-speed PALCE16V8 fabricated with AMD's advanced electrically erasable (EE) CMOS process. array connections formed with proven cells. Inputs outputs designed compatible with devices. This technology provides strong input clamp diodes, output slew-rate control, grounded substrate clean switching.
Security
security provided PALCE16V8 deterrent unauthorized copying array configuration patterns. Once programmed, this defeats readback verification programmed pattern device programmer, securing proprietary designs from competitors. only erased conjunction with array during erase cycle.
Compliance
PALCE22V10H-7/10 fully compliant with Local Specification published Special Interest Group. PALCE22V10H-7/10's predictable timing ensures compliance with specifications independent design.
Electronic Signature Word
electronic signature word provided PALCE16V8 device. consists bits programmable memory that contain user-defined data. signature data always available user independent security bit.
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PALCE16V8 Family
LOGIC DIAGRAM
CLK/I
I/O7
I/O6
SL16
I/O5
I/O4
16493D-6
PALCE16V8 Family
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LOGIC DIAGRAM (continued)
I/O1
SL00
OE/I
16493D-6 (concluded)
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PALCE16V8 Family
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current 75°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Temperature (TA) Operating Free +75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL (Static) Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current Test Conditions -3.2 -100 -100 -150 Unit
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note Outputs Open (IOUT mA),
Notes: These absolute values with respect device ground overshoots system tester noise included. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
PALCE16V8H-5 (Com'l)
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CAPACITANCE (Note
Parameter Symbol COUT Parameter Descriptions Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol tSKEWR Clock Width Maximum Frequency (Note Output Enable Output Disable Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control Parameter Description Input Feedback Combinatorial Output Setup Time from Input Feedback Clock Hold Time Clock Output Skew Between Registered Outputs (Note HIGH External Feedback Internal Feedback (fCNT), Feedback 1/(tS+tCO) 1/(tS+tCF) (Note 1/(tWH+tWL) 142.8 (Note Unit
fMAX
tPZX tPXZ
Notes: Switching Test Circuit test conditions. These parameters 100% tested, calculated initial characterization time design modified where frequency affected. Skew testing takes into account pattern switching direction differences between outputs that have equal loading. Output delay minimums tPD, tCO, tPZX, tPXZ, tEA, defined under best case conditions. Future process improvements alter these values therefore, minimum values recommended simulation purposes only. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
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PALCE16V8H-5 (Com'l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current +75°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Temperature (TA) Operating Free +75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating Ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL (Dynamic) Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current Test Conditions -3.2 -100 -100 -150 Unit
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note (Note (Note VOUT Max, (Note VOUT (Note VOUT (Note Outputs Open, (IOUT mA), Max,
Notes: These absolute values with respect device ground overshoots system tester noise included. leakage worst case IOZL IOZH). more than output should tested time. Duration short-circuit test should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
PALCE16V8H-7 (Com'l)
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CAPACITANCE (Note
Parameter Symbol COUT Parameter Descriptions Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol tSKEWR fMAX tPZX tPXA Parameter Description Input Feedback Combinatorial Output Setup Time from Input Feedback Hold Time Clock Output Skew Between Registered Outputs (Note Clock Width Maximum Frequency (Note HIGH External Feedback Internal Feedback (fCNT) Feedback 1/(tS tCO) 1/(tS tCF) (Note 1/(tWH tWL) Outputs Switching Output Switching (Note Unit
Output Enable Output Disable Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control
Notes: Switching Test Circuit test conditions. These parameters 100% tested, calculated initial characterization time design modified where frequency affected. Skew testing takes into account pattern switching direction differences between outputs that have equal loading. Output delay minimums tPD, tCO, tPZX, tPXZ, tEA, defined under best case conditions. Future process improvements alter these values therefore, minimum values recommended simulation purposes only. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
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PALCE16V8H-7 (Com'l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current -40°C +85°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Temperature (TA) Operating Free +75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25 Industrial Devices Temperature (TA) Operating Free -40°C +85°C Supply Voltage (VCC) with Respect Ground +4.5 +5.5
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL INDUSTRIAL operating ranges
Parameter Symbol IOZH IOZL (Dynamic) Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Commercial Supply Current Industrial Supply Current Test Conditions -3.2 -100 -100 -150 Unit
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note
Outputs Open (IOUT Max,
Notes: These absolute values with respect device ground overshoots system tester noise included. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
PALCE16V8H-10 (Com'l, Ind)
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CAPACITANCE (Note
Parameter Symbol COUT Parameter Descriptions Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL INDUSTRIAL operating ranges (Note
Parameter Symbol Clock Width Parameter Description Input Feedback Combinatorial Output Setup Time from Input Feedback Clock Hold Time Clock Output HIGH External Feedback fMAX Maximum Frequency (Note Output Enable Output Disable Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control Internal Feedback (fCNT) Feedback 1/(tS tCO) 1/(tS tCF) (Note 1/(tWH tWL) (Note 66.7 71.4 83.3 Unit
tPZX tPXZ
Notes: Switching Test Circuit test conditions. These parameters 100% tested, calculated initial characterization time design modified where frequency affected. Output delay minimums tPD, tCO, tPZX, tPXZ, tEA, defined under best case conditions. Future process improvements alter these values therefore, minimum values recommended simulation purposes only. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
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PALCE16V8H-10 (Com'l, Ind)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current 75°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Temperature (TA) Operating Free +75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current (Dynamic) Test Conditions -3.2 -100 -100 -150 Unit
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note Outputs Open (IOUT Max,
Notes: These absolute values with respect device ground overshoots system tester noise included. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
PALCE16V8Q-10 (Com'l)
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CAPACITANCE (Note
Parameter Symbol COUT Parameter Descriptions Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol Clock Width Parameter Description Input Feedback Combinatorial Output Setup Time from Input Feedback Clock Hold Time Clock Output HIGH External Feedback Internal Feedback (fCNT) Feedback 1/(tS tCO) 1/(tS tCF) (Note 1/(tWH tWL) (Note 66.7 71.4 83.3 Unit
fMAX
Maximum Frequency (Note Output Enable Output Disable
tPZX tPXZ
Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control
Notes: Switching Test Circuit test conditions. These parameters 100% tested, calculated initial characterization time design modified where frequency affected. Output delay minimums tPD, tCO, tPZX, tPXZ, tEA, defined under best case conditions. Future process improvements alter these values therefore, minimum values recommended simulation purposes only. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
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PALCE16V8Q-10 (Com'l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current -40°C +85°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Temperature (TA) Operating Free +75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25 Industrial Devices Temperature (TA) Operating Free -40°C +85°C Supply Voltage (VCC) with Respect Ground +4.5 +5.5
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL INDUSTRIAL operating ranges
Parameter Symbol IOZH IOZL (Dynamic) (Dynamic) Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Commercial Supply Current Industrial Supply Current Test Conditions -3.2 -100 -100 -150 Unit
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note Outputs Open (IOUT Max, Outputs Open (IOUT Max,
Notes: These absolute values with respect device ground overshoots system tester noise included. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
PALCE16V8H-15/25, Q-15/25 (Com'l, Ind), Q-20 (Ind)
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CAPACITANCE (Note
Parameter Symbol COUT Parameter Descriptions Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL INDUSTRIAL operating ranges (Note
Parameter Symbol Maximum Frequency (Note Parameter Description Input Feedback Combinatorial Output Setup Time from Input Feedback Clock Hold Time Clock Output Clock Width HIGH External Feedback Internal Feedback (fCNT) Feedback tPZX tPXZ Output Enable Output Disable Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control 1/(tS tCO) 1/(tS tCO) (Note 1/(tWH tWL) 45.5 62.5 41.6 45.4 50.0 41.6 Unit
fMAX
Notes: Switching Test Circuit test conditions. These parameters 100% tested, calculated initial characterization time design modified where frequency affected. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
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PALCE16V8H-15/25, Q-15/25 (Com'l, Ind), Q-20 (Ind)
SWITCHING WAVEFORMS
Input Feedback Combinatorial Output
16493D-7
Input Feedback
Clock Registered Output
16493D-8
Combinatorial Output
Registered Output
Input Clock
16493D-9
0.5V 0.5V
Output
16493D-10
Clock Width
Input Output Disable/Enable
tPXZ Output 0.5V 0.5V tPZX
16493D-11
Output Disable/Enable
Notes: Input pulse amplitude Input rise fall times typical.
PALCE16V8 Family
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SWITCHING WAVEFORMS
WAVEFORM INPUTS Must Steady Change from Change from Don't Care, Change Permitted Does Apply OUTPUTS Will Steady Will Changing from Will Changing from Changing, State Unknown Center Line HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
Output Test Point
16493D-12
Commercial Specification tPD, Closed Open Closed Open Closed H-5:
Measured Output Value
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PALCE16V8 Family
TYPICAL CHARACTERISTICS 25°C
16V8H-5
16V8H-7 (mA) 16V8H-10 16V8H-15/25
16V8Q-10/15/25
16493D-13
Frequency (MHz)
Frequency
selected "typical" pattern utilized device resources. Half macrocells were programmed registered, other half were programmed combinatorial. Half available product terms were used each macrocell. vector, half outputs were switching. utilizing device, midpoint defined ICC. From this midpoint, designer scale graphs down estimate requirements particular design.
PALCE16V8 Family
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ENDURANCE CHARACTERISTICS
PALCE16V8 manufactured using AMD's advanced Electrically Erasable process. This technology uses cell replace fuse link used bipolar
Symbol Parameter Pattern Data Retention Time Reprogramming Cycles
parts. result, device erased reprogrammed-a feature which allows 100% testing factory.
Unit Years Years Cycles
Test Conditions Storage Temperature Operating Temperature Normal Programming Conditions
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PALCE16V8 Family
ROBUSTNESS FEATURES
PALCE16V8X-X/5 devices have some unique features that make them extremely robust, especially when operating high-speed design environments. Pull-up resistors inputs pins cause unconnected pins default known state. Input clamping circuitry limits negative overshoot, eliminating possibility false
clocking caused subsequent ringing. special noise filter makes programming circuitry completely insensitive positive overshoot that pulse width less than about versions. Selected devices also being retrofitted with these robustness features. chart below device listings.
INPUT/OUTPUT EQUIVALENT SCHEMATICS VERSIONS SELECTED VERSIONS*
Protection Clamping
Programming Pins only
Programming Voltage Detection
Positive Overshoot Filter
Programming Circuitry
Typical Input
Provides Protection Clamping Preload Circuitry Feedback Input
Typical Output
16493D-14
Letter Topside Marking: Filter Only Filter Pullups CMOS PLD's marked package PALCE16V8H-10 following manner: PALCE16V8H-15 PALCEXXXX Date Code numbers) characters)- -(Rev. Letter) PALCE16V8Q-15 Letter separated spaces. PALCE16V8H-25 Device PALCE16V8Q-25
PALCE16V8 Family
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POWER-UP RESET
PALCE16V8 been designed with capability reset during system power-up. Following power-up, flip-flops will reset LOW. output state will HIGH independent logic polarity. This feature provides extra flexibility designer especially valuable simplifying state machine initialization. timing diagram parameter table shown below. synchronous operation power-up reset
Parameter Symbol Parameter Descriptions Power-Up Reset Time Input Feedback Setup Time Clock Width
wide range ways rise steady state, conditions required insure valid power-up reset. These conditions are: rise must monotonic. Following reset, clock input must driven from HIGH until applicable input feedback setup times met.
1000
Unit
Switching Characteristics
Power
Registered Output
Clock
16493D-15
Power-Up Reset Waveform
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PALCE16V8 Family
TYPICAL THERMAL CHARACTERISTICS Devices (PALCE16V8H-10/4)
Measured 25°C ambient. These parameters tested.
Parameter Symbol Parameter Description Thermal Impedance, Junction Case Thermal Impedance, Junction Ambient Thermal Impedance, Junction Ambient with Flow Ifpm Ifpm Ifpm Ifpm PDIP PLCC Unit °C/W °C/W °C/W °C/W °C/W °C/W
Devices (PALCE16V8H-7/5)
Measured 25°C ambient. These parameters tested.
Parameter Symbol Parameter Description Thermal Impedance, Junction Case Thermal Impedance, Junction Ambient Thermal Impedance, Junction Ambient with Flow Ifpm Ifpm Ifpm Ifpm PDIP PLCC Unit °C/W °C/W °C/W °C/W °C/W °C/W
Plastic Considerations data listed plastic reference only recommended calculating junction temperatures. heat-flow paths plastic-encapsulated devices complex, making measurement relative specific location package surface. Tests indicate this measurement reference point directly below die-attach area bottom center package. Furthermore, tests packages performed constant-temperature bath, keeping package surface constant temperature. Therefore, measurements only used similar environment.
PALCE16V8 Family
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COM'L: -15/25
IND: -12/15/25
PALCE16V8Z FAMILY
Zero-Power 20-Pin CMOS Universal Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
Zero-Power CMOS technology 15-µA Standby Current (-15/25) 30-µA Standby Current (-12) 12-ns propagation delay "-12" version 15-ns propagation delay "-15" version Unused product term disable reduced power consumption Available Industrial operating range -40°C +85°C +4.5 +5.5 HCT-Compatible inputs outputs function compatible with 20-pin devices Electrically-erasable CMOS technology provides reconfigurable logic full testability
Advanced Micro Devices
Direct plug-in replacement PAL16R8 series most PAL10H8 series Outputs programmable registered combinatorial combination Programmable output polarity Programmable enable/disable control Preloadable output registers testability Automatic register reset power Cost-effective 20-pin plastic PLCC packages Extensive third-party software programmer support through FusionPLD partners Fully tested 100% programming functional yields high reliability
GENERAL DESCRIPTION
PALCE16V8Z advanced device built with zero-power, high-speed, electrically-erasable CMOS technology. functionally compatible with 20-pin devices. macrocells provide universal device architecture. PALCE16V8Z will directly replace PAL16R8 PAL10H8 series devices, with exception PAL16C1. PALCE16V8Z provides zero standby power high speed. 30-µA maximum standby current, PALCE16V8Z allows battery powered operation extended period. PALCE16V8Z utilizes familiar sum-of-products (AND/OR) architecture that allows users implement complex logic functions easily efficiently. Multiple levels combinatorial logic always reduced sum-of-products form, taking advantage very wide input gates available devices. equations programmed into device through floating-gate cells logic array that erased electrically. fixed array allows eight data product terms output logic functions. these products feeds output macrocell. Each macrocell programmed registered combinatorial with active-high active-low output. output configuration determined global bits local controlling four multiplexers each macrocell. AMD's FusionPLD program allows PALCE16V8Z designs implemented using wide variety popular industry-standard design tools. working closely with FusionPLD partners, certifies that tools provide accurate, quality support. ensuring that thirdparty tools available, costs lowered because designer does have complete tools each device. FusionPLD program also greatly reduces design time since designer tool that already installed familiar.
2-78
Publication# 13061 Rev. Issue Date: February 1996
Amendment
BLOCK DIAGRAM
CLK/I0
Programmable Array
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
OE/I9
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7 13061E-1
CONNECTION DIAGRAMS View
PLCC
CLK/I
CLK/I
OE/I
13061E-2
OE/I I/O0 I/O1
13061E-3
DESIGNATIONS
PALCE16V8Z Family Clock Ground Input Input/Output Output Enable Supply Voltage 2-79
Note:
marked orientation
ORDERING INFORMATION Commercial Industrial Products
programmable logic products commercial industrial applications available with several ordering options. order number (Valid Combination) formed combination
FAMILY TYPE Programmable Array Logic TECHNOLOGY CMOS Electrically Erasable NUMBER ARRAY INPUTS OUTPUT TYPE Versatile NUMBER FLIP-FLOPS POWER Zero Power Standby) SPEED OPERATING CONDITIONS Commercial (0°C +75°C) Industrial (-40°C +85°C) PACKAGE TYPE 20-Pin Plastic 020) 20-Pin Plastic Leaded Chip Carrier 020)
Valid Combinations PALCE16V8Z-12 PALCE16V8Z-15 PALCE16V8Z-25
Valid Combinations Valid Combinations lists configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
2-80
PALCE16V8Z-15/25 (Com'l), Z-12/15/25 (Ind)
FUNCTIONAL DESCRIPTION
PALCE16V8Z zero-power version PALCE16V8. architectural features PALCE16V8. addition, PALCE16V8Z zero standby power unused product term disable. PALCE16V8Z universal device. eight independently configurable macrocells (MC0-MC7). Each macrocell configured registered output, combinatorial output, combinatorial dedicated input. programming matrix implements programmable logic array, which drives fixed logic array. Buffers device inputs have complementary outputs provide user-programmable input signal polarity. Pins serve either array inputs clock (CLK) output enable (OE), respectively, flip-flops. Unused input pins should tied directly GND. Product terms with bits unprogrammed (disconnected) assume logical HIGH state product terms with both true complement input signal connected assume logical state.
programmable functions PALCE16V8Z automatically configured from user's design specification, which number formats. design specification processed development software verify design create programming file. This file, once downloaded programmer, configures device according user's desired function. user given design options with PALCE16V8Z. First, programmed standard device from PAL16R8 PAL10H8 series. programmer manufacturer will supply device codes standard device architectures used with PALCE16V8Z. programmer will program PALCE16V8Z corresponding architecture. This allows user existing standard device JEDEC files without making changes them. Alternatively, device programmed PALCE16V8Z. Here user must PALCE16V8Z device code. This option allows full utilization macrocell.
Adjacent Macrocell
SL0X SL1X *SG1 SL0X I/OX
From Adjacent
13061E-4
macrocells MC7, replaced feedback multiplexer.
Figure PALCE16V8Z Macrocell
PALCE16V8Z Family
2-81
Configuration Options
Each macrocell configured following: registered output, combinatorial output, combinatorial I/O, dedicated input. registered output configuration, output buffer enabled pin. combinatorial configuration, buffer either controlled product term always enabled. dedicated input configuration, always disabled. With exception MC7, macrocell configured dedicated input derives input signal from adjacent I/O. derives input from (OE) from (CLK). macrocell configurations controlled configuration control word. contains global bits (SG0 SG1) local bits (SL00 through SL07 SL10 through SL17). determines whether registers will allowed. determines whether PALCE16V8Z will emulate PAL16R8 family PAL10H8 family device. Within each macrocell, SL0x, conjunction with SG1, selects configuration macrocell, SL1x sets output either active active high individual macrocell. configuration bits work acting control inputs multiplexers macrocell. There four multiplexers: product term input, enable select, output select, feedback select multiplexer. SL0x control signals four multiplexers. MC7, replaces feedback multiplexer. This accommodates being adjacent adjacent MC0.
Combinatorial Non-Registered Device
control settings SL0x Only seven product terms available gate. eighth product term used enable output buffer. signal back array feedback multiplexer. This allows used input. Because used non-registered device, pins available inputs. will feedback path will feedback path MC0.
Combinatorial Registered Device
control settings SL0x Only seven product terms available gate. eighth product term used output enable. feedback signal corresponding signal.
Dedicated Input Configuration
control settings SL0x output buffer disabled. Except feedback signal adjacent I/O. feedback signals pins These configurations summarized Table illustrated Figure Table Macrocell Configuration
SL0X Cell Configuration Devices Emulated Device Uses Registers Registered Output Combinatorial PAL16R8, 16R6, 16R4 PAL16R6, 16R4
Registered Output Configuration
control settings SL0x There only registered configuration. eight product terms available inputs gate. Data polarity determined SL1x. flip-flop loaded LOW-to-HIGH transition CLK. feedback path from register. output buffer enabled
Device Uses Registers Combinatorial Output Input PAL10H8, 12H6, 14H4, 16H2, 10L8, 12L6, 14L4, 16L2 PAL12H6, 14H4, 16H2, 12L6, 14L4, 16L2 PAL16L8
Combinatorial Configurations
PALCE16V8Z three combinatorial output configurations: dedicated output non-registered device, non-registered device registered device.
Combinatorial
Programmable Output Polarity
polarity each macrocell active-high active-low, either match output signal needs reduce product terms. Programmable polarity allows Boolean expressions written their most compact form (true inverted), output still desired polarity. also save "DeMorganizing" efforts. Selection through programmable SL1x which controls exclusive-OR gate output AND/ logic. output active high SL1x active SL1x
Dedicated Output Non-Registered Device
control settings SL0x eight product terms available gate. Although macrocell dedicated output, feedback used, with exception MC4. feedback this mode. Because used non-registered device, pins available input signals. will feedback path will feedback path MC0. 2-82
PALCE16V8Z Family
Registered Active
Registered Active High
Combinatorial Active
Combinatorial Active High
Note
Note
Combinatorial Output Active
Combinatorial Output Active High
Notes: Feedback available pins combinatorial output mode. dedicated-input configuration available pins
Adjacent Note
Dedicated Input Figure Macrocell Configurations PALCE16V8Z Family
13061E-5
2-83
Zero-Standby Power Mode
PALCE16V8Z features zero-standby power mode. When none inputs switch extended period (typically ns), PALCE16V8Z will into standby mode, shutting down most internal circuitry. current will almost zero (ICC µA). outputs will maintain states held before device went into standby mode. There speed penalty associated with coming standby mode. When input switches, internal circuitry fully enabled power consumption returns normal. This feature results considerable power savings operation medium frequencies. This savings illustrated frequency graph.
preload function disabled security bit. This allows functional testing after security programmed.
Security
security provided PALCE16V8Z deterrent unauthorized copying array configuration patterns. Once programmed, this defeats readback programmed pattern device programmer, securing proprietary designs from competitors. However, programming verification also defeated security bit. only erased conjunction with array during erase cycle.
Electronic Signature Word
electronic signature word provided PALCE16V8Z device. consists bits programmable memory that contain user-defined data. signature data always available user independent security bit.
Product-Term Disable
programmed PALCE16V8Z, product terms that used disabled. Power from these product terms that they draw current. shown frequency graph, product-term disabling results considerable power savings. This savings greater higher frequencies. Further hints minimizing power consumption found Application Note, "Minimizing Power Consumption with Zero-Power PLDs".
Programming Erasing
PALCE16V8Z programmed standard logic programmers. also erased reset previously configured device back unprogrammed state. Erasure automatically performed programming hardware. special erase operation required.
Power-Up Reset
flip-flops power logic predictable system initialization. Outputs PALCE16V8Z will depend whether they selected registered combinatorial. registered selected, output will HIGH. combinatorial selected, output will function logic.
Quality Testability
PALCE16V8Z offers very high level built-in quality. erasability device provides direct means verifying performance parameters. addition, this verifies complete programmability functionality device yield highest programming yields post-programming function yields industry.
Register Preload
register PALCE16V8Z preloaded from output pins facilitate functional testing complex state machine designs. This feature allows direct loading arbitrary states, making unnecessary cycle through long test vector sequences reach desired state. addition, transitions from illegal states verified loading illegal states observing proper recovery.
Technology
high-speed PALCE16V8Z fabricated with AMD's advanced electrically-erasable (EE) CMOS process. array connections formed with proven cells. Inputs outputs designed compatible with devices. This technology provides strong input-clamp diodes, output slew-rate control, grounded substrate clean switching.
2-84
PALCE16V8Z Family
LOGIC DIAGRAM
CLK/I
I/O6
SL16
I/O5
I/O4
13061E-6
PALCE16V8Z Family
2-85
LOGIC DIAGRAM (continued)
I/O1
SL00
OE/I
13061E-6 (concluded)
2-86
PALCE16V8Z Family
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current -40°C +85°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Industrial Devices Operating Case Temperature (TC) -40°C +85°C
Supply Voltage (VCC) with Respect Ground +4.5 +5.5
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified
Parameter Symbol Parameter Description Output HIGH Voltage Output Voltage Test Conditions 3.84 0.33 Unit
IOZH IOZL
Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current (Static) Supply Current (Dynamic)
Guaranteed Input Logical HIGH Voltage Inputs (Notes Guaranteed Input Logical Voltage Inputs (Notes VCC, (Note (Note VOUT VCC, (Note VOUT (Note VOUT (Note
-150
Outputs Open (IOUT
Notes: These absolute values with respect device ground overshoots system tester noise included. Represents worst case standards, allowing compatibility with either. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
PALCE16V8Z-12 (Ind)
2-87
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Condition VOUT 25°C, Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note
Parameter Symbol Parameter Description Maximum Frequency (Notes Output Enable Output Disable Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control Input Feedback Combinatorial Output (Note Setup Time from Input Feedback Clock Hold Time Clock Output Clock Width HIGH External Feedback Internal Feedback (fCNT) Feedback 1/(tS tCO) 1/(tS tCF) 1/(tWH tWL) 62.5 (Note Unit
fMAX
tPZX tPXZ
Notes: Switching Test Circuit test conditions. This parameter tested standby mode. These parameters 100% tested, evaluated initial characterization time design modified where frequency affected. Output delay minimum tPD, tCO, tPZD, tEA, defined under best case conditions. Future process improvements alter these values therefore, minimum values recommended simulation purposes only. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
2-88
PALCE16V8Z-12 (Ind)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current 75°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) Operating Free +75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25 Industrial Devices Operating Case Temperature (TC) -40°C +85°C
Supply Voltage (VCC) with Respect Ground +4.5 +5.5
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL INDUSTRIAL operating ranges
Parameter Symbol Parameter Description Output HIGH Voltage Output Voltage Test Conditions 3.84 0.33 Unit
IOZH IOZL
Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current (Static) Supply Current (Dynamic)
Guaranteed Input Logical HIGH Voltage Inputs (Notes Guaranteed Input Logical Voltage Inputs (Notes VCC, (Note (Note VOUT VCC, (Note VOUT (Note VOUT (Note
-150
Outputs Open (IOUT
Notes: These absolute values with respect device ground overshoots system tester noise included. Represents worst case standards, allowing compatibility with either. leakage worst case IOZL IOZH more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
PALCE16V8Z-15 (Com'l, Ind)
2-89
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Condition VOUT 25°C, Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL INDUSTRIAL operating ranges (Note
Parameter Symbol Parameter Description Maximum Frequency (Notes Output Enable Output Disable Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control Input Feedback Combinatorial Output Setup Time from Input Feedback Clock Hold Time Clock Output Clock Width HIGH External Feedback Internal Feedback (fCNT) Feedback 1/(tS tCO) 1/(tS tCF) 1/(tWH tWL) 58.8 62.5 Unit
fMAX
tPZX tPXZ
Notes: Switching Test Circuit test conditions. These parameters 100% tested, evaluated initial characterization time design modified where frequency affected. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
2-90
PALCE16V8Z Family
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current 75°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) Operating Free +75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25 Industrial Devices Operating Case Temperature (TC) -40°C +85°C
Supply Voltage (VCC) with Respect Ground +4.5 +5.5
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL INDUSTRIAL operating ranges
Parameter Symbol Parameter Description Output HIGH Voltage Output Voltage Test Conditions 3.84 0.33 Unit
IOZH IOZL
Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current
Guaranteed Input Logical HIGH Voltage Inputs (Notes Guaranteed Input Logical Voltage Inputs (Notes VCC, (Note (Note VOUT VCC, (Note VOUT (Note VOUT (Note
-150
Outputs Open (IOUT
Notes: These absolute values with respect device ground overshoots system tester noise included. Represents worst case standards, allowing compatibility with either. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
PALCE16V8Z-25 (Com'l, Ind)
2-91
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Condition VOUT 25°C, Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL INDUSTRIAL operating ranges (Note
Parameter Symbol Parameter Description Maximum Frequency (Notes Output Enable Output Disable Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control Input Feedback Combinatorial Output (Note Setup Time from Input Feedback Clock Hold Time Clock Output Clock Width HIGH External Feedback Internal Feedback (fCNT) Feedback 1/(tS tCO) 1/(tS tCF) 1/(tS 33.3 Unit
fMAX
tPZX tPXZ
Notes: Switching Test Circuit test conditions. This parameter tested Standby Mode. When device Standby Mode, will typically faster. These parameters 100% tested, evaluated initial characterization time design modified where frequency affected. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
2-92
PALCE16V8Z-25 (Com'l, Ind)
SWITCHING WAVEFORMS
Input Feedback Input Feedback Clock Combinatorial Output
13061E-7
13061E-8
Registered Output
Combinatorial Output
Registered Output
Input Clock
13061E-9
0.5V 0.5V
13061E-10
Output
Clock Width
Input Output Disable/Enable
tPXZ Output 0.5V 0.5V tPZX
13061E-11
Output Disable/Enable
Notes: input signals VCC/2 output signals. Input pulse amplitude Input rise fall times typical.
PALCE16V8Z Family
2-93
SWITCHING WAVEFORMS
WAVEFORM INPUTS Must Steady Change from Change from Don't Care, Change Permitted Does Apply OUTPUTS Will Steady Will Changing from Will Changing from Changing, State Unknown Center Line HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
Output Test Point
13061E-12
Specification tPD, tPZX, tPXZ,
Closed Open Closed Open Closed
Closed Closed Open Closed Open
Measured Output Value VCC/2
VCC/2
2-94
PALCE16V8Z Family
TYPICAL CHARACTERISTICS PALCE16V8Z-12/15 25°C
(mA)
13061E-13
Frequency (MHz)
Frequency Graph PALCE16V8Z-12/15
selected "typical" pattern utilized device resources. Half macrocells were programmed registered, other half were programmed combinatorial. Half available product terms were used each macrocell. vector, half outputs were switching. utilizing device, midpoint defined ICC. From this midpoint, designer scale graphs down estimate requirements particular design.
PALCE16V8Z-12/15
2-95
TYPICAL CHARACTERISTICS PALCE16V8Z-25 25°C
(mA)
13061E-14
Frequency (MHz)
Frequency Graph PALCE16V8Z-25
selected "typical" pattern utilized device resources. Half macrocells were programmed registered, other half were programmed combinatorial. Half available product terms were used each macrocell. vector, half outputs were switching. utilizing device, midpoint defined ICC. From this midpoint, designer scale graphs down estimate requirements particular design.
2-96
PALCE16V8Z-25
ENDURANCE CHARACTERISTICS
PALCE16V8Z manufactured using AMD's advanced Electrically Erasable process. This technology
uses cell replace fuse link used bipolar parts. result, device erased reprogrammed feature which allows 100% testing factory.
Endurance Characteristics
Symbol Parameter Pattern Data Retention Time Test Conditions Storage Temperature Operating Temperature Reprogramming Cycles Normal Programming Conditions Unit Years Years Cycles
ROBUSTNESS FEATURES
PALCE16V8Z some unique features that make extremely robust, especially when operating highspeed design environments. Input clamping circuitry
limits negative overshoot, eliminating possibility false clocking caused subsequent ringing. special noise filter makes programming circuitry completely insensitive positive overshoot that pulse width less than about
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Input Protection Transition Detection Clamping
Programming Pins only
Programming Voltage Detection
Positive Overshoot Filter
Programming Circuitry
Typical Input
Provides Protection Clamping Preload Circuitry Feedback Input Input Transition Detection
13061E-16
Typical Output
PALCE16V8Z Family
2-97
POWER-UP RESET
PALCE16V8Z been designed with capability reset during system power-up. Following powerup, flip-flops will reset LOW. output state will HIGH independent logic polarity. This feature provides extra flexibility designer especially valuable simplifying state machine initialization. timing diagram parameter table shown below. synchronous operation power-up reset
Parameter Symbol Parameter Descriptions Power-Up Reset Time Input Feedback Setup Time Clock Width
wide range ways rise steady state, conditions required insure valid power-up reset. These conditions are:
rise must monotonic. Following reset, clock input must driven
from HIGH until applicable input feedback setup times met.
1000
Unit
Switching Characteristics
Power
Registered Output
Clock
13061E-17
2-98
PALCE16V8Z Family
TYPICAL THERMAL CHARACTERISTICS
Measured 25°C ambient. These parameters tested.
PALCE16V8Z-25
Parameter Symbol Parameter Description Thermal impedance, junction case Thermal impedance, junction ambient Thermal impedance, junction ambient with flow lfpm lfpm lfpm lfpm PDIP PLCC Unit °C/W °C/W °C/W °C/W °C/W °C/W
Plastic Considerations data listed plastic reference only recommended calculating junction temperatures. heat-flow paths plastic-encapsulated devices complex, making measurement relative specific location package surface. Tests indicate this measurement reference point directly below die-attach area bottom center package. Furthermore, tests packages performed constant-temperature bath, keeping package surface constant temperature. Therefore, measurements only used similar environment.
PALCE16V8Z Family
2-99
COM'L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25, Q-20/25
PALCE20V8 Family
CMOS 24-Pin Universal Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
function compatible with
Advanced Micro Devices
Peripheral Component Interconnect (PCI)
20V8/As Electrically erasable CMOS technology provides reconfigurable logic full testability High-speed CMOS technology 5-ns propagation delay "-5" version 7.5-ns propagation delay "-7" version Direct plug-in replacement wide range 24-pin devices Programmable enable/disable control Outputs individually programmable registered combinatorial
compliant
Preloadable output registers testability Automatic register reset power-up Cost-effective 24-pin plastic SKINNYDIP
28-pin PLCC packages
Extensive third-party software programmer
support through FusionPLD partners
Fully tested 100% programming func-
tional yields high reliability
Programmable output polarity 5-ns version utilizes split leadframe
improved performance
GENERAL DESCRIPTION
PALCE20V8 advanced device built with low-power, high-speed, electrically-erasable CMOS technology. macrocells provide universal device architecture. PALCE20V8 fully compatible with GAL20V8 directly replace PAL20R8 series devices most 24-pin combinatorial devices. Device logic automatically configured according user's design specification. design implemented using number popular design software packages, allowing automatic creation programming file based Boolean state equations. Design software also verifies design provide test vectors finished device. Programming accomplished standard device programmers. PALCE20V8 utilizes familiar sum-of-products (AND/OR) architecture that allows users implement complex logic functions easily efficiently. Multiple levels combinatorial logic always reduced sum-of-products form, taking advantage very wide input gates available devices. equations programmed into device through floatinggate cells logic array that erased electrically. fixed array allows eight data product terms output logic functions. these products feeds output macrocell. Each macrocell programmed registered combinatorial with active-high active-low output. output configuration determined global bits local controlling four multiplexers each macrocell.
BLOCK DIAGRAM
CLK/I0
Programmable Array
Input Mux.
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
Input Mux.
OE/I11
Publication# 16491 Rev. Issue Date: February 1996
I/O0
I/O1
I/O2
I/O4
I/O4
I/O5
I/O6
I/O7
16491D-1
Amendment
2-155
CONNECTION DIAGRAMS (Top View) SKINNYDIP
CLK/I0 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 OE/I11
16491D-2
PLCC/LCC
CLK/I0 I/O7 OE/I11 I/O0
16491D-3
I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
Note: marked orientation.
DESIGNATIONS
Clock Ground Input Input/Output Connect Output Enable Supply Voltage
2-156
PALCE20V8 Family
ORDERING INFORMATION Commercial Industrial Products
programmable logic products commercial industrial applications available with several ordering options. order number (Valid Combination) formed combination
FAMILY TYPE Programmable Array Logic TECHNOLOGY CMOS Electrically Erasable NUMBER ARRAY INPUTS OUTPUT TYPE Versatile NUMBER FLIP-FLOPS POWER Half Power (90-125 ICC) Quarter Power ICC) SPEED
PROGRAMMING DESIGNATOR Blank Initial Algorithm First Revision Second Revision (Same algorithm OPERATING CONDITIONS Commercial (0°C +75°C) Industrial (-40°C +85°C)
PACKAGE TYPE 24-Pin Plastic SKINNYDIP (PD3024) 28-Pin Plastic Leaded Chip Carrier 028)
Valid Combinations PALCE20V8H-5 PALCE20V8H-7 Blank, PALCE20V8H-10 PALCE20V8Q-10 PALCE20V8H-15 PALCE20V8Q-15 Blank, PALCE20V8Q-20 PALCE20V8H-25 PALCE20V8Q-25
Valid Combinations Valid Combinations lists configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
PALCE20V8H-5/7/10/15/25, Q-10/15/25 (Com'l) PALCE20V8H-15/25, Q-20/25 (Ind)
2-157
FUNCTIONAL DESCRIPTION
PALCE20V8 universal device. eight independently configurable macrocells (MC0.MC7). Each macrocell configured registered output, combinatorial output, combinatorial I/O, dedicated input. programming matrix implements programmable logic array, which drives fixed logic array. Buffers device inputs have complementary outputs provide user-programmable input signal polarity. Pins serve either array inputs clock (CLK) output enable (OE) flip-flops. Unused input pins should tied directly GND. Product terms with bits unprogrammed (disconnected) assume logical HIGH state product terms with both true complement input signal connected assume logical state. programmable functions PALCE20V8 automatically configured from user's design specification, which number formats. design
specification processed development software verify design create programming file. This file, once downloaded programmer, configures device according user's desired function. user given design options with PALCE20V8. First, programmed emulated device. This includes PAL20R8 series most 24-pin combinatorial devices. device programmer manufacturer will supply device codes standard architectures used with PALCE20V8. programmer will program PALCE20V8 corresponding device architecture. This allows user existing standard device JEDEC files without making changes them. Alternatively, device programmed directly PALCE20V8. Here user must PALCE20V8 device code. This option provides full utilization macrocells, allowing non-standard architectures built.
Adjacent Macrocell
SL0X SL1X *SG1 SL0X I/OX
From Adjacent
16491D-4
Macrocells MC7, replaced feedback multiplexer.
Figure PALCE20V8 Macrocell
2-158
PALCE20V8 Family
Configuration Options
Each macrocell configured following: registered output, combinatorial output, combinatorial dedicated input. registered output configuration, output buffer enabled pin. combinatorial configuration, buffer either controlled product term always enabled. dedicated input configuration, buffer always disabled. macrocell configured dedicated input derives input signal from adjacent I/O. macrocell configurations controlled configuration control word. contains global bits (SG0 SG1) local bits (SL00 through SL07 SL10 through SL17). determines whether registers will allowed. determines whether PALCE20V8 will emulate PAL20R8 family combinatorial device. Within each macrocell, SL0x, conjunction with SG1, selects configuration macrocell SL1x sets output either active active high. configuration bits work acting control inputs multiplexers macrocell. There four multiplexers: product term input, enable select, output select, feedback select multiplexer. SL0x control signals four multiplexers. MC7, replaces feedback multiplexer. These configurations summarized table illustrated figure PALCE20V8 configured combinatorial device, pins available inputs array. device configured with registers, pins cannot used data inputs.
Dedicated Output Non-Registered Device
control settings SL0x eight product terms available gate. Although macrocell dedicated output, feedback used, with exception pins 18(21) 19(23). Pins 18(21) 19(23) feedback this mode.
Dedicated Input Non-Registered Device
control settings SL0x output buffer disabled. feedback signal adjacent pin.
Combinatorial Non-Registered Device
control settings SL0x Only seven product terms available gate. eighth product term used enable output buffer. signal back array feedback multiplexer. This allows used input.
Combinatorial Registered Device
control settings SG0=0,SG1=1 SL0x Only seven product terms available gate. eighth product term used output enable. feedback signal corresponding signal. Table Macrocell Configurations
SL0x Cell Configuration Devices Emulated Device registers Registered Output Combinatorial PAL20R8, 20R6, 20R4 PAL20R6, 20R4
Registered Output Configuration
control settings SL0x There only registered configuration. eight product terms available inputs gate. Data polarity determined SL1x. SL1x input exclusive-OR gate which input flipflop. SL1x programmed inverted output non-inverted output. flip-flop loaded LOW-to-HIGH transition CLK. feedback path from register. output buffer enabled
Device registers Combinatorial Output Dedicated Input Combinatorial PAL20L2, 18L4,16L6,14L8 PAL20L2,18L4, 16L6 PAL20L8
Combinatorial Configurations
PALCE20V8 three combinatorial output configurations: dedicated output non-registered device, non-registered device registered device.
Programmable Output Polarity
polarity each macrocell output active high active low, either match output signal needs reduce product terms. Programmable polarity allows Boolean expressions written their most compact form (true inverted), output still desired polarity. also save "DeMorganizing" efforts. Selection made through programmable SL1x which controls exclusive-OR gate output AND/OR logic. output active high SL1x active SL1x PALCE20V8 Family 2-159
Registered Active
Registered Active High
Combinatorial Active
Combinatorial Active High
Note
Note
Combinatorial Output Active
Combinatorial Output Active High
Notes: Feedback available pins (21) (23) combinatorial output mode. This macrocell configuration available pins (21) (23).
Note
Adjacent
Dedicated Input Figure Macrocell Configurations 2-160 PALCE20V8 Family
16491D-5
Power-Up Reset
flip-flops power logic predictable system initialization. Outputs PALCE20V8 depend whether they selected registered combinatorial. registered selected, output will HIGH. combinatorial selected, output will function logic.
Programming Erasing
PALCE20V8 programmed standard logic programmers. also erased reset previously configured device back virgin state. Erasure automatically performed programming hardware. special erase operation required.
Quality Testability
PALCE20V8 offers very high level built-in quality. erasability device provides direct means verifying performance parameters. addition, this verifies complete programmability functionality device provide highest programming post-programming functional yields industry.
Register Preload
register PALCE20V8 preloaded from output pins facilitate functional testing complex state machine designs. This feature allows direct loading arbitrary states, making unnecessary cycle through long test vector sequences reach desired state. addition, transitions from illegal states verified loading illegal states observing proper recovery.
Technology
high-speed PALCE20V8H fabricated with AMD's advanced electrically erasable (EE) CMOS process. array connections formed with proven cells. Inputs outputs designed compatible with devices. This technology provides strong input clamp diodes, output slew-rate control, grounded substrate clean switching.
Security
security provided PALCE20V8 deterrent unauthorized copying array configuration patterns. Once programmed, this defeats readback verification programmed pattern device programmer, securing proprietary designs from competitors. only erased conjunction with array during erase cycle.
Compliance
PALCE20V8H-7/10 fully compliant with Local Specification published Special Interest Group. PALCE20V8H-7/10's predictable timing ensures compliance with specifications independent design. other hand, CPLD FPGA architectures without predictable timing, compliance dependent upon routing product term distribution.
Electronic Signature Word
electronic signature word provided PALCE20V8. consists bits programmable memory that contain user-defined data. signature data always available user independent security bit.
PALCE20V8 Family
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LOGIC DIAGRAM SKINNYDIP (PLCC LCC) Pinouts
CLK/I0
(28) (27)
I/O7 (26)
SL07
SL06
I/O6 (25)
SL06
SL05
I/O5 (24)
SL05
SL04
I/O4 (23)
SL04
16491D-6
2-162
PALCE20V8 Family
LOGIC DIAGRAM (continued) SKINNYDIP (PLCC LCC) Pinouts
SL03
I/O3 (21)
SL02
I/O2 (20)
(10)
SL02
SL01
(19)
(11)
SL01
SL00
I/O0 (18)
(12)
SL00
(13)
(17) OE/I11 (16)
16491D-6 (concluded)
PALCE20V8 Family
2-163
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current 75°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Temperature (TA) Operating Free 75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL (Static) Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current Test Conditions -3.2 -100 -100 -150 Unit
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note Outputs Open (IOUT mA),
Notes: These absolute values with respect device ground overshoots system and/or tester noise included. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
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PALCE20V8H-5 (Com'l)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Descriptions Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol tSKEWR Clock Width Parameter Description Input Feedback Combinatorial Output Setup Time from Input Feedback Clock Hold Time Clock Output Skew Between Registered Outputs (Note HIGH External Feedback fMAX Maximum Frequency (Note Output Enable Output Disable Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control Internal Feedback (fCNT) Feedback 1/(tS tCO) 1/(tS tCF) (Note 1/(tWH tWL) 142.8 (Note Unit
tPZX tPXZ
Notes: Switching Test Circuit test conditions. These parameters 100% tested, calculated initial characterization time design modified where frequency affected. Skew testing takes into account pattern switching direction differences between outputs that have equal loading. Output delay minimums tPD, tCO, tPZX, tPXZ, tEA, defined under best case conditions. Future process improvements alter these values therefore, minimum values recommended simulation purposes only. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
PALCE20V8H-5 (Com'l)
2-165
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current 75°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Temperature (TA) Operating Free 75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL (Dynamic) Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current Test Conditions -3.2 -100 -100 -150 Unit
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note Outputs Open (IOUT Max,
Notes: These absolute values with respect device ground overshoots system and/or tester noise included. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
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PALCE20V8H-7 (Com'l)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Descriptions Input Capacitance Output Capacitance Test Conditions 2.0V VOUT 25°C, Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol Parameter Description Input Feedback Combinatorial Output Outputs Switching Output Switching tSKEWR Maximum Frequency (Note Output Enable Output Disable Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control Setup Time from Input Feedback Clock Hold Time Clock Output Skew Between Registered Outputs (Note Clock Width HIGH External Feedback Internal Feedback (fCNT) Feedback 1/(tS tCO) 1/(tS tCF) (Note 1/(tWH tWL) Unit
fMAX
tPZX tPXZ
Notes: Switching Test Circuit test conditions. These parameters 100% tested, calculated initial characterization time design modified where frequency affected. Skew testing takes into account pattern switching direction differences between outputs that have equal loading. Output delay minimums tPD, tCO, tPZX, tPXZ, tEA, defined under best case conditions. Future process improvements alter these values therefore, minimum values recommended simulation purposes only. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
PALCE20V8H-7 (Com'l)
2-167
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current 75°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Temperature (TA) Operating Free 75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL (Dynamic) Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current Test Conditions -3.2 -100 -100 -150 Unit
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note Outputs Open (IOUT Max,
Notes: These absolute values with respect device ground overshoots system and/or tester noise included. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
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PALCE20V8H-10 (Com'l)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol Maximum Frequency (Note Output Enable Output Disable Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control Parameter Description Input Feedback Combinatorial Output Setup Time from Input Feedback Clock Hold Time Clock Output Clock Width HIGH External Feedback Internal Feedback (fCNT) Feedback 1/(tS tCO) 1/(tS tCF) (Note 1/(tWH tWL) (Note 66.7 71.4 83.3 Unit
fMAX
tPZX tPXZ
Notes: Switching Test Circuit test conditions. These parameters 100% tested, calculated initial characterization time design modified where frequency affected. Output delay minimums tPD, tCO, tPZX, tPXZ, tEA, defined under best case conditions. Future process improvements alter these values therefore, minimum values recommended simulation purposes only. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
PALCE20V8H-10 (Com'l)
2-169
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current 75°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Temperature (TA) Operating Free 75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL (Dynamic) Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current Test Conditions -3.2 -100 -100 -150 Unit
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note Outputs Open (IOUT Max, (Note
Notes: These absolute values with respect device ground overshoots system and/or tester noise included. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation. This parameter guaranteed worst case under test conditions. Refer frequency graph typical measurements.
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PALCE20V8Q-10 (Com'l)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol Maximum Frequency (Note Output Enable Output Disable Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control Parameter Description Input Feedback Combinatorial Output Setup Time from Input Feedback Clock Hold Time Clock Output Clock Width HIGH External Feedback Internal Feedback (fCNT) Feedback 1/(tS tCO) 1/(tS tCF) (Note 1/(tWH tWL) (Note 66.7 71.4 83.3 Unit
fMAX
tPZX tPXZ
Notes: Switching Test Circuit test conditions. These parameters 100% tested, calculated initial characterization time design modified where frequency affected. Output delay minimums tPD, tCO, tPZX, tPXZ, tEA, defined under best case conditions. Future process improvements alter these values therefore, minimum values recommended simulation purposes only. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
PALCE20V8Q-10 (Com'l)
2-171
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current +75°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Temperature (TA) Operating Free +75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current Test Conditions -3.2 -100 -100 -150 Unit
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note Outputs Open (IOUT Max,
Notes: These absolute values with respect device ground overshoots system and/or tester noise included. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
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PALCE20V8H-15/25 Q-15/25 (Com'l)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol fMAX tPZX tPXZ Clock Width Maximum Frequency (Note Parameter Description Input Feedback Combinatorial Output Setup Time from Input Feedback Clock Hold Time Clock Output HIGH External Feedback Internal Feedback (fCNT) Feedback 1/(tS tCO) 1/(tS tCF) (Note 1/(tWH tWL) 45.5 62.5 41.6 Unit
Output Enable Output Disable Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control
Notes: Switching Test Circuit test conditions. These parameters 100% tested, calculated initial characterization time design modified where frequency affected. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
PALCE20V8H-15/25 Q-15/25 (Com'l)
2-173
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current -40°C +85°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Industrial Devices Temperature (TA) Operating Free -40°C +85°C Supply Voltage (VCC) with Respect Ground +4.5 +5.5
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current Test Conditions -3.2 -100 -100 -150 Unit
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note (Note (Note VOUT (Note VOUT (Note VOUT (Note Outputs Open (IOUT Max,
Notes: These absolute values with respect device ground overshoots system and/or tester noise included. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
2-174
PALCE20V8H-15/25, Q-20/25 (Ind)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note
Parameter Symbol Maximum Frequency (Note Parameter Description Input Feedback Combinatorial Output Setup Time from Input Feedback Clock Hold Time Clock Output Clock Width HIGH External Feedback Internal Feedback (fCNT) Feedback tPZX tPXZ Output Enable Output Disable Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control 1/(tS tCO) 1/(tS tCF) (Note 1/(tWH tWL) 45.5 62.5 41.6 45.4 50.0 41.6 Unit
fMAX
Notes: Switching Test Circuit test conditions. These parameters 100% tested, calculated initial characterization time design modified where frequency affected. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
PALCE20V8H-15/25, Q-20/25 (Ind)
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SWITCHING WAVEFORMS
Input Feedback Input Feedback Combinatorial Output
16491D-7
Clock
Registered Output
16491D-8
Combinatorial Output
Registered Output
Clock
16491D-9
Input Output 0.5V 0.5V
16491D-10
Clock Width
Input Output Disable/Enable
tPXZ Output 0.5V 0.5V tPZX
16491D-11
Output Disable/Enable
Notes: Input pulse amplitude Input rise fall times typical.
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PALCE20V8 Family
SWITCHING WAVEFORMS
WAVEFORM
INPUTS Must Steady Change from Change from Don't Care, Change Permitted Does Apply
OUTPUTS Will Steady Will Changing from Will Changing from Changing, State Unknown Center Line HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
Output
Switching Test Circuit
Commercial Specification tPD, tPZX, tPXZ, Closed Open Closed Open Closed
16491D-12
Measured Output Value
H-5:
PALCE20V8 Family
2-177
TYPICAL CHARACTERISTICS 25°C
20V8H-5
20V8H-7 (mA) 20V8H-10 20V8H-15/25
20V8Q-10 20V8Q-15/25
16491D-13
Frequency (MHz)
Frequency
selected "typical" pattern utilized device resources. Half macrocells were programmed registered, other half were programmed combinatorial. Half available product terms were used each macrocell. vector, half outputs were switching. utilizing device, midpoint defined ICC. From this midpoint, designer scale graphs down estimate requirements particular design.
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PALCE20V8 Family
ENDURANCE CHARACTERISTICS
PALCE20V8 manufactured using AMD's advanced electrically erasable process. This technology
uses cell replace fuse link used bipolar parts. result, device erased reprogrammed-a feature which allows 100% testing factory.
Endurance Characteristics
Symbol Parameter Pattern Data Retention Time Reprogramming Cycles Test Conditions Storage Temperature Operating Temperature Normal Programming Conditions Unit Years Years Cycles
PALCE20V8 Family
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ROBUSTNESS FEATURES
PALCE20V8X-X/5 have some unique features that make them extremely robust, especially when operating high-speed design environments. Pull-up resistors inputs pins cause unconnected pins default known state. Input clamping circuitry limits negative overshoot, eliminating possibility false clocking
caused subsequent ringing. special noise filter makes programming circuitry completely insensitive positive overshoot that pulse width less than about versions. Selected devices also being retrofitted with these robustness features. chart below device listings.
INPUT/OUTPUT EQUIVALENT SCHEMATICS SELECTED VERSION SELECTED VERSIONS*
Protection Clamping
Programming Pins only
Programming Voltage Detection
Positive Overshoot Filter
Programming Circuitry
Typical Input
Provides Protection Clamping Preload Circuitry Feedback Input
Typical Output
16491D-14
Device PALCE20V8H-10 PALCE20V8H-15 PALCE20V8Q-15 PALCE20V8H-25 PALCE20V8Q-25
Letter
Topside Marking: CMOS PLDs marked package following manner: PALCEXXXX Datecode numbers) characters)- -(Rev Letter) Letter separated spaces.
2-180
PALCE20V8 Family
INPUT/OUTPUT EQUIVALENT SCHEMATICS SELECTED VERSIONS*
Protection
Input
Preload Circuitry
Feedback Input
16491D-15
Device PALCE20V8H-10 PALCE20V8H-15 PALCE20V8Q-15 PALCE20V8H-25 PALCE20V8Q-25
Letter
Topside Marking: CMOS PLDs marked package following manner: PALCEXXX Datecode numbers) characters)- -(Rev Letter) Letter separated spaces.
PALCE20V8 Family
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POWER-UP RESET
PALCE20V8 been designed with capability reset during system power-up. Following power-up, flip-flops will reset LOW. output state will HIGH independent logic polarity. This feature provides extra flexibility designer especially valuable simplifying state machine initialization. timing diagram parameter table shown below.
Parameter Symbol Parameter Description Power-Up Reset Time Input Feedback Setup Time Clock Width
synchronous operation power-up reset wide range ways rise steady state, conditions required insure valid power-up reset. These conditions are:
rise must monotonic. Following reset, clock input must driven
from HIGH until applicable input feedback setup times met.
1000 Switching Characteristics Unit
Power
Registered Output
Clock
16491D-16
Power-Up Reset Waveforms
2-182
PALCE20V8 Family
TYPICAL THERMAL CHARACTERISTICS Devices (PALCE20V8H-10/4)
Measured 25°C ambient. These parameters tested.
Parameter Symbol Parameter Description Thermal impedance, junction case Thermal impedance, junction ambient Thermal impedance, junction ambient with flow lfpm lfpm lfpm lfpm SKINNYDIP PLCC Unit °C/W °C/W °C/W °C/W °C/W °C/W
Devices (PALCE20V8H-7/5)
Measured 25°C ambient. These parameters tested.
Parameter Symbol Parameter Description Thermal impedance, junction case Thermal impedance, junction ambient Thermal impedance, junction ambient with flow lfpm lfpm lfpm lfpm SKINNYDIP PLCC Unit °C/W °C/W °C/W °C/W °C/W °C/W
Plastic Considerations data listed plastic reference only recommended calculating junction temperatures. heat-flow paths plastic-encapsulated devices complex, making measurement relative specific location package surface. Tests indicate this measurement reference point directly below die-attach area bottom center package. Furthermore, tests packages performed constant-temperature bath, keeping package surface constant temperature. Therefore, measurements only used similar environment.
PALCE20V8 Family
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COM'L:
IND: -15/25
PALCE22V10Z Family
Zero-Power 24-Pin CMOS Versatile Device
DISTINCTIVE CHARACTERISTICS
Zero-power CMOS technology standby current fast first-access propagation delay fMAX (external) Unused product term disable reduced power consumption Available Industrial operating range -40°C +85°C +4.5 +5.5 HCT-compatible inputs outputs Electrically-erasable technology provides reconfigurable logic full testability
Advanced Micro Devices
macrocells programmable registered combinatorial, active high active match application needs Varied product term distribution allows product terms output complex functions Global asynchronous reset synchronous preset initialization Power-up reset initialization register preload testability Extensive third-party software programmer support through FusionPLD partners 24-pin SKINNYDIP, 28-pin PLCC, 24-pin SOIC packages save space
GENERAL DESCRIPTION
PALCE22V10Z advanced device built with zero-power, high-speed, electrically-erasable CMOS technology. provides user-programmable logic replacing conventional zero-power CMOS SSI/MSI gates flip-flops reduced chip count. PALCE22V10Z provides zero standby power high speed. maximum standby current, PALCE22V10Z allows battery powered operation extended period. ZPALdevice implements familiar Boolean logic transfer function, products. device programmable array driving fixed array. array programmed create custom product terms, while array sums selected terms outputs. product terms connected fixed array with varied distribution from to16 across outputs (see Block Diagram). products feeds output macrocell. Each macrocell programmed registered combinatorial, active high active low. output configuration determined bits controlling multiplexers each macrocell. AMD's FusionPLD program allows PALCE22V10Z designs implemented using wide variety popular industry-standard design tools. working closely with FusionPLD partners, certifies that tools provide accurate, quality support. ensuring that thirdparty tools available, costs lowered because designer does have complete tools each device. FusionPLD program also greatly reduces design time since designer tool that already installed familiar. Please refer Software Reference Guide Compliers certified development systems, Programmer Reference Guide approved programmers.
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Publication# 15700 Rev. Issue Date: February 1996
Amendment
BLOCK DIAGRAM
CLK/I0
PROGRAMMABLE ARRAY 132)
RESET
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL PRESET
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9 15700E-1
CONNECTION DIAGRAMS View SKINNYDIP/SOIC
CLK/I0 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
PLCC
CLK/I0 I/O9 I/O8 I/O0 I/O1 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2
15700E-3
15700E-2
Note: marked orientation.
DESCRIPTION
Clock Ground Input Input/Output Connect Supply Voltage
PALCE22V10Z Family
2-245
ORDERING INFORMATION Commercial Industrial Products
programmable logic products commercial industrial applications available with several ordering options. order number (Valid Combination) formed combination these elements:
FAMILY TYPE Programmable Array Logic TECHNOLOGY CMOS Electrically Erasable NUMBER ARRAY INPUTS OUTPUT TYPE Versatile NUMBER OUTPUTS POWER Zero Power standby)
OPERATING CONDITIONS Commercial (0°C +75°C) Industrial (-40°C +85°C) PACKAGE TYPE 24-Pin Plastic SKINNYDIP (PD3024) 28-Pin Plastic Leaded Chip Carrier 028) 24-Pin Plastic Gull-Wing Small Outline Package SPEED
Valid Combinations PALCE22V10Z-15 PALCE22V10Z-25
Valid Combinations Valid Combinations lists configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations, check newly released combinations.
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PALCE22V10Z Family
FUNCTIONAL DESCRIPTION
PALCE22V10Z zero-power version PALCE22V10. architectural features PALCE22V10. addition, PALCE22V10Z zero standby power unused product term disable. PALCE22V10Z allows systems engineer implement design on-chip, programming cells configure gates within device, according desired logic function. Complex interconnections between gates, which previously required time-consuming layout, lifted from board placed silicon, where they easily modified during prototyping production. Product terms with connections opened assume logical HIGH state; product terms connected both true complement single input assume logical state. PALCE22V10Z inputs macrocells. macrocell (Figure allows four potential output configurations; registered output combinatorial I/O, active high active (see Figure configuration choice made according user's design specification corresponding programming configuration bits Multiplexer controls connected ground through programmable bit, selecting path through multiplexer. Erasing disconnects control line from floats (1), selecting path.
device produced with cell link each input gate array, connections selectively removed applying appropriate voltages circuit. Utilizing easily-implemented programming algorithm, these products rapidly programmed customized pattern.
Variable Input/Output Ratio
PALCE22V10Z twelve dedicated input lines, each macrocell output pin. Buffers device inputs have complementary outputs provide user-programmable input signal polarity. Unused input pins should tied GND.
Registered Output Configuration
Each macrocell PALCE22V10Z includes D-type flip-flop data storage synchronization. flipflop loaded LOW-to-HIGH transition clock input. registered configuration array feedback from flip-flop.
Combinatorial Configuration
macrocell configured combinatorial selecting multiplexer path that bypasses flip-flop combinatorial configuration feedback from pin.
Output Configuration Registered/Active Registered/Active High Combinatorial/Active Combinatorial/Active High I/On
Programmed Erased (charged)
15700E-4
Figure Output Logic Macrocell
PALCE22V10Z Family
2-247
Registered/Active Registered/Active High Combinatorial/Active High
15700E-5
Combinatorial/Active
Figure Macrocell Configuration Options
Programmable Three-State Outputs
Each output three-state output buffer with threestate control. product term controls buffer, allowing enable disable function product device inputs output feedback. combinatorial output provides bidirectional pin, configured dedicated input buffer always disabled.
Preset/Reset
initialization, PALCE22V10Z additional Preset Reset product terms. These terms connected registered outputs. When Synchronous Preset (SP) product term asserted high, output registers will loaded with HIGH next LOW-toHIGH clock transition. When Asynchronous Reset (AR) product term asserted high, output registers will immediately loaded with independent clock. Note that preset reset control flip-flop, output pin. output level determined output polarity selected.
Programmable Output Polarity
polarity each macrocell output active high active low, either match output signal needs reduce product terms. Programmable polarity allows Boolean expressions written their most compact form (true inverted), output still desired polarity. also save "DeMorganizing" efforts. Selection controlled programmable output macrocell, affects both registered combinatorial outputs. Selection automatic, based design specification definitions. definition output equation have same polarity, output programmed active high
Zero-Standby Power Mode
PALCE22V10Z features zero-standby power mode. When none inputs switch extended period (typically ns), PALCE22V10Z will into standby mode, shutting down most internal circuitry. current will almost zero (ICC µA). outputs will maintain states held before device went into standby mode.
2-248
PALCE22V10Z Family
When input switches, internal circuitry fully enabled power consumption returns normal. This feature results considerable power savings operation medium frequencies. This savings illustrated frequency graph.
Security
After programming verification, PALCE22V10Z design secured programming security bit. Once programmed, this defeats readback internal programmed pattern device programmer, securing proprietary designs from competitors. When security programmed, array will read every erased, preload will disabled. only erased conjunction with erasure entire pattern.
Product-Term Disable
programmed PALCE22V10Z, product terms that used disabled. Power from these product terms that they draw current. shown frequency graph, product-term disabling results considerable power savings. This savings greater higher frequencies. Further hints minimizing power consumption found Application Note "Minimizing Power Consumption with Zero-Power PLDs."
Programming Erasing
PALCE22V10Z programmed standard logic programmers. also erased reset previously configured device back virgin state. Erasure automatically performed programming hardware. special erase operation required.
Power-Up Reset
flip-flops power-up logic predictable system initialization. Outputs PALCE22V10Z will depend programmed output polarity. rise must monotonic reset delay time 1000 maximum.
Quality Testability
PALCE22V10Z offers very high level built-in quality. erasability CMOS PALCE22V10Z allows direct testing device array guarantee 100% programming functional yields.
Register Preload
registers PALCE22V10Z preloaded from output pins facilitate functional testing complex state machine designs. This feature allows direct loading arbitrary states, making unnecessary cycle through long test vector sequences reach desired state. addition, transitions from illegal states verified loading illegal states observing proper recovery.
Technology
high-speed PALCE22V10Z fabricated with AMD's advanced electrically-erasable (EE) CMOS process. array connections formed with proven cells. Inputs outputs designed compatible with devices. This technology provides strong input-clamp diodes, output slew-rate control, grounded substrate clean switching.
PALCE22V10Z Family
2-249
LOGIC DIAGRAM SKINNYDIP (PLCC) Pinouts
CLK/I
(28)
(27)
(26)
(25)
(24)
(23)
(21)
(20)
(19)
(10)
(18)
(11)
(17)
(12) (13)
(16)
(14)
15700E-6
2-250
PALCE22V10Z Family
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output -0.5 Voltage Static Discharge Voltage 2001 Latchup Current -40°C +85°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Industrial Devices Operating Case Temperature (TC) -40°C +85°C Supply Voltage (VCC) with Respect Ground +4.5 +5.5
Operating Ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified
Parameter Symbol Parameter Description Output HIGH Voltage Test Conditions Output Voltage IOZH Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH IOZL Off-State Output Leakage Current Output Short-Circuit Current Supply Current Guaranteed Input Logical HIGH Voltage Inputs (Notes Guaranteed Input Logical Voltage Inputs (Notes VCC, (Note (Note VOUT VCC, (Note VOUT (Note VOUT (Note Outputs Open (IOUT -150 3.84 VCC- 0.33 Unit
Notes: These absolute values with respect device ground overshoots system tester noise included. Represents worst case standards, allowing compatibility with either. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
PALCE22V10Z-15 (Ind)
2-251
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Condition VOUT 25°C Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note
Parameter Symbol tARW tARR tSPR Parameter Description Input Feedback Combinatorial Output Setup Time from Input, Feedback Clock Hold Time Clock Output Asynchronous Reset Registered Output Asynchronous Reset Width Asynchronous Reset Recovery Time Synchronous Preset Recovery Time Clock Width HIGH External Feedback Maximum Frequency Internal Feedback (fCNT) (Notes Feedback 1/(tS tCO) 1/(tS tCF) 1/(tWH tWL) 58.8 62.5 Unit
fMAX
Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control
Notes: Switching Test Circuit test conditions. These parameters 100% tested, evaluated initial characterization time design modified where frequency affected. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
2-252
PALCE22V10Z-15 (Ind)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current -40°C +85°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits impl
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