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Efficient Arithmetic Designs With Cypress CPLDs
This application note intended provide designers with some insight into efficient means implementing arithmetic functions Cypress CPLDs. Additionally this application note will discuss variety implementations pros cons associated with each. importance selecting proper implementation your application significantly improve chance that your design will meet your design requirements. Although there great deal information about arithmetic designs, this application note seeks fill void detailed explanation their implementation Cypress CPLDs. Throughout this application note, phrase "Cypress CPLD" will used refer interchangeably members both FLASH370iand Ultra37000complex programmable logic device (CPLD) families. designer many alternatives when selecting arithmetic implementations given design. decision final choice typically based issues like resource availability, speed operation modularity. Creating designs view target device's architecture will definitely yield better results than implementing generic design same device. discussion this application note addresses arithmetic algorithms, design methodologies implementations tailored features resources offered FLASH370i Ultra37000 families CPLDs. These specialized arithmetic designs achieve balanced tradeoff between speed area requirements given application. this application note user offered wide variety algorithms implementations from which choose. This variety provides designer with flexibility choose model best suited target application. This choice absolutely necessary since design requirements constraints vary from application application. This discussion assumes that designer good feel features resources available FLASH370i Ultra37000 families CPLDs. implementation details design tradeoffs building adders, subtracters, equality ADD: 1-Bit Full Adder Pass) magnitude comparators addressed this application note. Examples shown VHDL. Since Warpautomatically uses these design modules during VHDL synthesis, intent this application note allow designer visualize implement arithmetic functions CPLDs. This application note assumes that reader good grasp fundamentals VHDL. Some (library parameterized modules) elements CPLDs provided Warp software built using concepts final implementations discussed here. This provides user with excellent opportunity choose best algorithm implementation tailored target application. Additionally since Warp automatically infers these modules, this application note will provide user with better understanding their design synthesized. Also this application note will provide some insight times when designer might want intervene personally control Warp's synthesis process.
Adders
addition operands most common operation most arithmetic units. two-operand adder commonly used performing additions subtractions. also used when executing complex arithmetic functions like multiplication division. ADD: 1-Bit Full Adder basic component used adding operands called Full Adder. full adder element will henceforth referred `ADD' component. block diagram functionality shown Figure operands added Carry-in component. Carry-out from component. VHDL code describing functionality component shown here. This design takes pass through Logic (AND-OR) array into Cypress CPLD. component instantiated VHDL code shown exactly same functionality shown Figure
(Basic building block)
Functionality:
Figure Block Diagram Functionality Full Adder
Cypress Semiconductor Corporation
3901 North First Street
Jose
95134
408-943-2600 July 1998
Efficient Arithmetic Designs With Cypress CPLDs
This VHDL code implements full adder component called within package called MATHPKG
LIBRARY IEEE; IEEE.STD_LOGIC_1164.ALL; PACKAGE mathpkg COMPONENT PORT (CI: STD_LOGIC; INSTD_LOGIC; SUM: STD_LOGIC; STD_LOGIC); COMPONENT; mathpkg; LIBRARY IEEE; IEEE.STD_LOGIC_1164.ALL; ENTITY PORT (CI: STD_LOGIC; STD_LOGIC; SUM: STD_LOGIC; STD_LOGIC); add; ARCHITECTURE archadd
BEGIN CI);
archadd;
RADD12: 12-Bit Ripple Carry Adder n-bit two-operand ripple carry adder built using components. input bits available adder same time. However carries have propagate from position MSB. other words, need wait until carries ripple through components claim that outputs correct. Because this rippling effect, adder referred Ripple Carry Adder. This simplest form adding operands. uses least amount area compared other implementations but, negative side, slowest implementation. This typically implementation provided with synthesis tool when recognizes operator VHDL code. block diagram 12-bit Ripple Carry Adder (RADD12) shown Figure VHDL code describing functionality RADD12 component shown here. This design takes passes through logic array into Cypress CPLD. outputs component produced first pass. outputs succeeding components produced with every alternate pass through logic array. Each pass through logic array time penalty associated with -This VHDL code describes implementation generic ripple carry adder.
LIBRARY IEEE; IEEE.STD_LOGIC_1164.ALL; WORK.MATHPKG.ALL; ENTITY rippleadd12 PORT (CI: STD_LOGIC; A11, A10, STD_LOGIC;
Efficient Arithmetic Designs With Cypress CPLDs
RADD12:
12-Bit Ripple-Carry-Adder Passes)
Figure Block Diagram 12-Bit Ripple Carry Adder B11, B10, STD_LOGIC; SUM11, SUM10, SUM9, SUM8, SUM7, SUM6, SUM5, SUM4, SUM3, SUM2, SUM1, SUM0 STD_LOGIC; STD_LOGIC); rippleadd12;
ARCHITECTURE archripple12add rippleadd12 SIGNAL C10, STD_LOGIC; attribute synthesis_off C10, signal true; BEGIN
i10: i11: i12:
PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT
MAP(CI,A0,B0,SUM0,C1); MAP(C1,A1,B1,SUM1,C2); MAP(C2,A2,B2,SUM2,C3); MAP(C3,A3,B3,SUM3,C4); MAP(C4,A4,B4,SUM4,C5); MAP(C5,A5,B5,SUM5,C6); MAP(C6,A6,B6,SUM6,C7); MAP(C7,A7,B7,SUM7,C8); MAP(C8,A8,B8,SUM8,C9); MAP(C9,A9,B9,SUM9,C10); MAP(C10,A10,B10,SUM10,C11); MAP(C11,A11,B11,SUM11,CO);
archripple12add;
need `synthesis_off' attribute used VHDL code will discussed later.
Efficient Arithmetic Designs With Cypress CPLDs
ADD2WC: 2-Bit Adder with Carry-Out concept component extended create 2-bit adder which takes 2-bit operands with carry-in produces 2-bit carry-out outputs. This component will referred ADD2WC (2-bit adder with carry-out). This also takes just pass through logic array yield results. block diagram ADD2WC shown Figure operands added Carry-in component. Sums Carry-outs from component.
ADD2WC: 2-Bit Adder Pass) A1,A0 B1,B0
ADD2WC
SUM1,SUM0 Figure 2-Bit Full Adder with Carry-Out VHDL code describing functionality ADD2WC component shown here. This design takes pass through logic array into Cypress CPLD.
-VHDL code describing 2-bit adder with carry-out. LIBRARY IEEE; IEEE.STD_LOGIC_1164.ALL; PACKAGE add2wc_pkg COMPONENT add2wc PORT( STD_LOGIC; A1,A0: STD_LOGIC; B1,B0: STD_LOGIC; SUM1,SUM0 STD_LOGIC; STD_LOGIC); COMPONENT; add2wc_pkg; LIBRARY IEEE; IEEE.STD_LOGIC_1164.ALL; ENTITY add2wc PORT STD_LOGIC; A1,A0: STD_LOGIC; B1,B0: STD_LOGIC; SUM1,SUM0 STD_LOGIC; STD_LOGIC); add2wc; ARCHITECTURE archadd2wc add2wc BEGIN
SUM0 SUM1 ((A0 CI)); B1);
archadd2wc;
concept ADD2WC extended describe ADD2NC component. ADD2NC component cut-down version ADD2WC component, does have carry-out. VHDL code block diagram ADD2NC component easy extrapolate shown here. R2ADD12: 12-Bit Ripple Carry Adder using ADD2WC Basic Block 12-bit adder using ADD2WC component shown here. This adder takes passes produce results, opposed passes needed 12-bit adder using component. outputs ADD2WC component produced first pass. outputs succeeding
Efficient Arithmetic Designs With Cypress CPLDs
ADD2WC components produced with every alternate pass through logic array. number macrocells used this scheme less than RADD12, product term count higher. comparison different schemes present-
later. block diagram R2ADD12 shown Figure VHDL code describing functionality also attached.
R2ADD12: 12-Bit Adder using ADD2WC Passes) A7,A6 B7,B6 A5,A4 B5,B4 A3,A2 B3,B2
A1,A0 B1,B0
ADD2WC
ADD2WC
ADD2WC
ADD2WC
SUM7,SUM6
SUM5,SUM4
SUM3,SUM2
SUM1,SUM0
A11,A10 B11,B10
A9,A8 B9,B8
ADD2WC
ADD2WC
SUM11,SUM10
SUM9,SUM8
Figure Block Diagram 12-Bit Ripple Carry Adder Using 2-Bit Adders 12-bit Ripple carry adder built using ADD2WC element basic building block
LIBRARY IEEE; IEEE.STD_LOGIC_1164.ALL; WORK.ADD2WC.ALL; ENTITY add12 PORT STD_LOGIC; STD_LOGIC; STD_LOGIC; SUM3,SUM2,SUM1,SUM0 STD_LOGIC; STD_LOGIC); add12; ARCHITECTURE archadd12 add12 SIGNAL STD_LOGIC; attribute synthesis_off signal true;
BEGIN add2wc add2wc add2wc add2wc add2wc add2wc
PORT PORT PORT PORT PORT PORT
(SUM2). This takes more than product terms (PTs) takes passes through logic array produce result. other results, including carry-out, take less than take just pass produce results. control sum-splitting functionality SUM2, intermediate carry created assigned node. then used create functionality SUM2. Note that
archadd12; ADD3WC: 3-Bit Ripple Carry Adder There another could implement n-bit ripple carry adder targeting Cypress CPLDs. implement n-bit adder using 3-bit group adder (ADD3WC) opposed 2-bit group adder (ADD2WC). problem with 3-bit group adder sum-splitting functionality
Efficient Arithmetic Designs With Cypress CPLDs
functionality takes less than generated first pass, carry rippling faster. This makes this component faster building block. This scheme still takes passes create functionality SUM2, without getting sum-split. resource utilization 12-bit adder using 3-bit group adder presented later. block diagram ADD3WC component shown Figure
ADD3WC:
3-Bit Adder Passes) A2.0 B2.0
ADD3WC
SUM2.0
Figure 3-Bit Full Adder with Carry-Out 3-Bit Adder with Carry-out
LIBRARY IEEE; IEEE.STD_LOGIC_1164.ALL; PACKAGE add3wc_pkg COMPONENT add3wC PORT BIT; A2,A1,A0: BIT; B2,B1,B0: BIT; SUM2,SUM1,SUM0 BIT; BIT); COMPONENT; add3wc_pkg; LIBRARY IEEE; IEEE.STD_LOGIC_1164.ALL; ENTITY add3wc PORT STD_LOGIC; A2,A1,A0: STD_LOGIC; B2,B1,B0: STD_LOGIC; SUM2,SUM1,SUM0 STD_LOGIC; STD_LOGIC); add3wc; ARCHITECTURE archadd3wc add3wc SIGNAL STD_LOGIC; attribute synthesis_off signal true;
BEGIN SUM0 SUM1 ((A0 CI)); SUM2 B1);
((A1 B2)) ((A0 B2)) B2));
archadd3wc;
Function synthesis_off Attribute synthesis_off attribute causes signal made into factoring point logic equations keeps signal from being minimized during optimization. attribute useful following reasons: gives user control over which equations sub-expressions need factored into node.
Efficient Arithmetic Designs With Cypress CPLDs
helps cutting down compile time designs that have `signal redirection' (signals getting inverted/reassigned other signals). This attribute provides Logic optimizer better control over optimization process reducing number signals needs deal with. provides better results designs where signal with large functionality being used many other signals. left alone, fitter would collapse internal signals (which desirable many cases) drive design's resource requirements beyond available limits. using synthesis_off attribute, user assign commonly-used signal node bring down resource utilization. side effect using synthesis_off attribute that design will take extra pass through array achieve same functionality. extra pass required anyway, more than required. This attribute only recommended combinatorial signals. Registered signals assigned node natural factoring synthesis_off attribute these signals redundant. This attribute associated with signals declared both VHDL schematics. `BUF' component also used schematics VHDL achieve same results synthesis_off attribute. Please refer Warp Synthesis manual more details. Carry-Lookahead Principle predominant delay adders carry propagation. carry-lookahead principle aims minimizing this delay. carry equations each position adder given Ci+1 carry generated whenever both carry propagated whenever either `1'. Generate term: Propagate term: Note: Bi), `OR' easier implement than `XOR' CPLDs. Rewriting equation Ci+1, Ci+1 Writing equations 4-bit carry-lookahead adder:
further speed addition providing carry-lookahead over groups addition internal lookahead within group. define group-generated carry group-propagated carry group size follows: carry-out group) generated internally carry-in group) propagated internally produce carry-out group). boolean equations these carries are:
group-generated group-propagated carries several groups used generate group carry-ins manner similar single-bit carry-ins. selection group size plays important role obtaining best possible implementation carry-lookahead adder CPLD. Some different possible implementations 12-bit carry-lookahead adder shown Figure
XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX
Adder split into groups
Adder split into groups
Adder split into groups
Figure Some Possible Implementations 12-Bit Carry-Lookahead Adder number passes each these implementations take number product terms (PTs) macrocells (MCs) used vary each scheme (see Table "Comparison Resource Utilization Different Schemes Building 12-Bit Adder" section). Each scheme advantage over other. user needs judiciously choose between different schemes based application, bit-size, CPLD chosen architectural constraints. number passes taken through logic direct representation total time taken producing final results. Each extra pass results time penalty. rule follow "The smaller number passes through logic array, faster your application runs." implementation 12-bit carry-lookahead adder with different group-sizes presented next. FC2ADD12: 12-Bit Full Carry-Lookahead Adder Using Group-Size Bits Cypress CPLD access each macrocell. functionality signal that more than sum-split into multiple MCs. number utilized signals that sum-split large undesirable option. With 2-bit group-size implementation accommodate entire functionality 32-bit full carry-lookahead adder without signals getting sum-split. scheme takes maximum three passes through logic array adder sizes bits generate outputs.
where Bi). values generated single pass through array. carry-in positions computed second pass through array, based upon values various generated first pass. generalized carry-lookahead equation compute different carry-in signals shown here: Ci+1 Gi-1) Pi-1 i-1) Pi-1
Efficient Arithmetic Designs With Cypress CPLDs
various values SUM1, SUM0, generated first pass. other intermediate carries generated second pass various results generated third pass. point note that value produced second pass, even though various outputs generated third pass only. FC2ADD12: A7,A6 B7,B6 12-Bit Fast Carry Adder Passes) A5,A4 B5,B4
This makes component cascadable modular. Refer Table details resource utilization different 12-bit adder implementations. FC2ADD12 built using ADD2WC ADD2NC basic building blocks. block diagram FC2ADD12 shown Figure VHDL code design also presented.
A3,A2
B3,B2
A1,A0
B1,B0
ADD2NC
ADD2NC
ADD2NC
ADD2WC
SUM7,SUM6
SUM5,SUM4 Carry-lookahead Unit
SUM3,SUM2
SUM1,SUM0
A11,A10 B11,B10 ADD2NC ADD2NC A9,A8 B9,B8
SUM11,SUM10
SUM9,SUM8
Figure 12-Bit Full Carry-Lookahead Adder Using ADD2WC ADD2NC 12-bit Full carry-lookahead adder built using ADD2WC ADD2NC -elements
LIBRARY IEEE; IEEE.STD_LOGIC_1164.ALL; WORK.ADD2WC.ALL; WORK.ADD2NC.ALL; ENTITY fc2add12 PORT STD_LOGIC; STD_LOGIC; STD_LOGIC; SUM3,SUM2,SUM1,SUM0 STD_LOGIC; STD_LOGIC); fc2add12; ARCHITECTURE archfc2add12 fc2add12 SIGNAL STD_LOGIC; SIGNAL E1,E2,E3,E4,E5 STD_LOGIC; SIGNAL R1,R2,R3,R4,R5 STD_LOGIC; attribute synthesis_off E1,E2,E3,E4,E5 signal true; attribute synthesis_off R1,R2,R3,R4,R5 signal true; attribute synthesis_off signal true;
BEGIN add2wc PORT
Efficient Arithmetic Designs With Cypress CPLDs
add2nc add2nc add2nc add2nc add2nc
PORT PORT PORT PORT PORT
MAP(C2,A3,A2,B3,B2,SUM3,SUM2); MAP(C4,A5,A4,B5,B4,SUM5,SUM4); MAP(C6,A7,A6,B7,B6,SUM7,SUM6); MAP(C8,A9,A8,B9,B8,SUM9,SUM8);
((A3 B2)); B2); R1); ((A5 B4)); B4); ((E1 R1)) R2); ((A7 B6)); B6); ((E2 ((E1 R1)) R2)) R3); ((A9 B8)); B8); ((E3 ((E2 ((E1 R1)) R2)) R3)) R4); (A11 B11) ((A11 B11) (A10 B10)); (A11 B11) (A10 B10); ((E4 ((E3 ((E2 ((E1 R1)) R2)) R3)) R4)) R5);
archfc2add12;
FC3ADD12: A11.9 B11.9 12-Bit Fast Carry Adder Passes) A8.6 B8.6 A5.3 B5.3 A2.0 B2.0
ADD3WC SUM11.9
ADD3NC
ADD3NC
ADD3NC
SUM8.6
SUM5.3
SUM2.0
Carry-Lookahead Unit Figure 12-Bit Full Carry-Lookahead Adder using ADD3WC ADD3NC FC3ADD12: 12-Bit Full Carry-Lookahead Adder using Group-Size Bits This very similar FC2ADD12, differing group-size adder used basic building block. basic building blocks this scheme ADD3WC ADD3NC components. VHDL code attached block diagram Figure illustrate design. This scheme takes four passes through logic array yield results. generated first pass. intermediate carries generated second pass. carries internal group generated third pass final outputs fourth pass.
different approach, generated ADD3WC opposed Carry-lookahead unit. This results being generated third pass opposed second pass. VHDL code clearly indicates manner which model built. some bit-sizes, given that 3-bit group-size odd-numbered, designer will have choose non-modular structure building adder. example, 32-bit adder cannot built using just ADD3NCs built using ADD3NCs ADD2NC. designer needs choose final implementation based constraints application.
Efficient Arithmetic Designs With Cypress CPLDs
-12-Bit Fast carry-Lookahead adder with 3-bit groups
LIBRARY IEEE; IEEE.STD_LOGIC_1164.ALL; WORK.ADD3WC.ALL; WORK.ADD3NC.ALL; ENTITY fc3add12 PORT STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; SUM2,SUM1,SUM0 STD_LOGIC); fc3add12; ARCHITECTURE fc3add12arch fc3add12 SIGNAL SIGNAL SIGNAL
E1,E2,E3 STD_LOGIC; R1,R2,R3 STD_LOGIC; C3,C6,C9 STD_LOGIC;
attribute synthesis_off C3,C6,C9 signal true; attribute synthesis_off E1,E2,E3 signal true; attribute synthesis_off R1,R2,R3 signal true; BEGIN
add3nc PORT add3nc PORT add3nc PORT add3wc PORT ((A1 B2)) ((A0 B2)); B0);
CI); ((A4 B5)) ((A3 B5)); B3);
CI); ((A7 B8)) ((A6 B8)); B6);
CI);
fc3add12arch;
Efficient Arithmetic Designs With Cypress CPLDs
FC4ADD12: 12-Bit Full Carry-Lookahead Adder using Group-Size Bits This very similar FC2ADD12 and, again, differs group-size adder used basic building block. basic building block this scheme ADD4NC component. ADD4NC component built using combination ADD2WC ADD2NC same order. This component replicated create adder desired size. very last stage, ADD2WCs used instead
ADD2WC ADD2NC. VHDL code attached block diagram Figure illustrate design's functionality. This scheme takes four passes through logic array yield results. various generated first pass, values second pass, outputs from ADD2WCs third pass, outputs from ADD2NC fourth pass. Note that value generated second pass. This scheme uses fewer more than previously mentioned schemes. resource utilization this model shown Table
FC4ADD12: A7,A6 B7,B6
12-Bit Fast Carry Adder Passes) A5,A4 B5,B4 A3,A2 B3,B2 A1,A0 B1,B0
ADD2NC
ADD2WC
ADD2NC
ADD2WC
SUM7,SUM6
SUM5,SUM4
SUM3,SUM2
SUM1,SUM0
Carry-Lookahead Unit A11,A10 B11,B10 A9,A8 B9,B8
ADD4NC ADD2WC ADD2WC
SUM11,SUM10
SUM9,SUM8
Figure 12-Bit Full Carry-Lookahead Adder using ADD4NC 12-bit Full carry-lookahead adder built using ADD2WC ADD2NC -elements. ADD2WC ADD2NC elements part ADD4NC -same order
LIBRARY IEEE; IEEE.STD_LOGIC_1164.ALL; WORK.ADD2WC.ALL; WORK.ADD2NC.ALL; ENTITY fc4add12 PORT STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; SUM2,SUM1,SUM0 STD_LOGIC); fc4add12; ARCHITECTURE fc4add12arch fc4add12 SIGNAL E1,E2 STD_LOGIC; SIGNAL R1,R2 STD_LOGIC; SIGNAL C2,C4,C6,C8,C10 STD_LOGIC;
Efficient Arithmetic Designs With Cypress CPLDs
attribute synthesis_off C2,C4,C6,C8,C10 signal true; attribute synthesis_off E1,E2 signal true; attribute synthesis_off R1,R2 signal true;
BEGIN add2wc PORT add2nc PORT MAP(C2,A3,A2,B3,B2,SUM3,SUM2); add2wc PORT add2nc PORT MAP(C6,A7,A6,B7,B6,SUM7,SUM6); add2wc PORT add2wc PORT ((A2 B3)) ((A1 B3)) ((A0 B3)); B0); CI); ((A6 B7)) ((A5 B7)) ((A4 B7)); B4); CI); fc4add12arch; referred `SUB' component. block diagram functionality shown Figure (minuend) (subtrahend) operands subtracted Borrow-in component. Bout Difference Borrow-out from component. VHDL code describing functionality component shown here. This design takes pass through logic array into Cypress CPLD. component instantiated VHDL code exact same functionality shown Figure
Subtracters
Subtracters just modified form adders. discussion presented adders easily extended subtracters. given sized adder subtracter, resource utilization exactly same respects. SUB: 1-Bit Full Subtracter basic component used subtracting operands called Full subtracter. full subtracter element will
SUB:
1-Bit Full Subtracter Pass)
(Basic building block)
Bout Functionality:
(NOT Bin) Bout (NOT (NOT
Figure Block Diagram Functionality Full Subtracter This VHDL code implements element
LIBRARY IEEE; IEEE.STD_LOGIC_1164.ALL; PACKAGE mathpkg COMPONENT PORT (BIN: STD_LOGIC;
Efficient Arithmetic Designs With Cypress CPLDs
STD_LOGIC; DIF: STD_LOGIC; BOUT: STD_LOGIC); COMPONENT; mathpkg;
LIBRARY IEEE; IEEE.STD_LOGIC_1164.ALL; ENTITY PORT (Bin: STD_LOGIC; STD_LOGIC; DIF: STD_LOGIC; Bout: STD_LOGIC); sub; ARCHITECTURE archsub
BEGIN (NOT Bin); Bout (not Bin) ((not Bin);
archsub;
SUB2WB: 2-Bit Subtracter with Borrow-Out structure 2-bit group subtracter (SUB2WB) very similar that ADD2WC shown here. This component used building block build larger sized subtracters, exactly like ADD2WC used build larger sized adders. block diagram SUB2WB shown Figure corresponding VHDL code used describe functionality SUB2WB also attached. case ADD2WC, functionality SUB2WB realized pass through logic array. SUB2: 2-Bit Adder Pass) A1,A0 B1,B0
SUB2WB
Bout
DIF1,DIF0
Figure Block Diagram 2-Bit Subtracter with Borrow-Out
LIBRARY IEEE; IEEE.STD_LOGIC_1164.ALL; PACKAGE sub2wb_pkg COMPONENT sub2wb PORT( STD_LOGIC; A1,A0: STD_LOGIC; B1,B0: STD_LOGIC; DIF1,DIF0 STD_LOGIC; Bout: STD_LOGIC); COMPONENT; sub2wb_pkg; ENTITY sub2wb PORT (Bin STD_LOGIC; A1,A0: STD_LOGIC; B1,B0: STD_LOGIC; DIF1,DIF0 STD_LOGIC; Bout: STD_LOGIC); sub2wb; ARCHITECTURE archsub2wb sub2wb BEGIN
DIF0 (NOT Bin); DIF1 (NOT ((NOT (NOT Bin) Bin)));
Efficient Arithmetic Designs With Cypress CPLDs
Bout
(NOT (NOT (NOT B1);
archsub2wb;
FB2SUB12: 12-Bit Full Borrow-Lookahead Subtracter using 2-Bit Subtracters mentioned before that build equivalent subtracter models adder models discussed earlier. functionality implementation FB2SUB12 (subtracter equivalent FC2ADD12) shown here example. implementation possible subtracter elements discussed this application note, since concept involved building them identical that adders. FBSUB12: A7,A6 B7,B6 block diagram FB2SUB12 very similar that adder element FC2ADD12 shown Figure FB2SUB12 built using basic elements SUB2WB SUB2NC (2-bit subtracter with borrow-out). This takes three passes through logic array. values various generated first pass, intermediate carries (borrows) second pass, various DIFs third pass. Note that value generated second pass. VHDL code FB2SUB12 also shown.
12-Bit Fast Borrow Subtracter Passes) A5,A4 B5,B4 A3,A2 B3,B2 A1,A0 B1,B0
SUB2NC
SUB2NC
SUB2NC
SUB2WB
DIF7,DIF6
DIF5,DIF4 Borrow-Lookahead Unit
DIF3,DIF2
DIF1,DIF0
Bout A11,A10 B11,B10 A9,A8 B9,B8
SUB2NC
SUB2NC
DIF11,DIF10
DIF9,DIF8
Figure 12-Bit Fast Borrow Subtracter Built using SUB2WB SUB2NC 12-bit Full borrow-lookahead subtracter built using SUB2WC -SUB2NC elements
LIBRARY IEEE; IEEE.STD_LOGIC_1164.ALL; WORK.SUB2WB.ALL; WORK.SUB2NC.ALL; ENTITY fb2sub12 PORT (Bin STD_LOGIC; STD_LOGIC; STD_LOGIC; DIF3,DIF2,DIF1,DIF0 STD_LOGIC;
Efficient Arithmetic Designs With Cypress CPLDs
Bout: STD_LOGIC); fb2sub12;
ARCHITECTURE archfb2sb12 fb2sub12 SIGNAL STD_LOGIC; SIGNAL E1,E2,E3,E4,E5 STD_LOGIC; SIGNAL R1,R2,R3,R4,R5 STD_LOGIC;
-The internal carries referred distinguish between -borrow-out's operands attribute synthesis_off E1,E2,E3,E4,E5 signal true; attribute synthesis_off R1,R2,R3,R4,R5 signal true; attribute synthesis_off signal true; BEGIN sub2wb sub2nc sub2nc sub2nc sub2nc sub2nc
PORT PORT PORT PORT PORT PORT
MAP(C2,A3,A2,B3,B2,DIF3,DIF2); MAP(C4,A5,A4,B5,B4,DIF5,DIF4); MAP(C6,A7,A6,B7,B6,DIF7,DIF6); MAP(C8,A9,A8,B9,B8,DIF9,DIF8);
(NOT ((NOT (NOT B2)); (NOT (NOT B2); R1); (NOT ((NOT (NOT B4)); (NOT (NOT B4); ((E1 R1)) R2); (NOT ((NOT (NOT B6)); (NOT (NOT B6); ((E2 ((E1 R1)) R2)) R3); (NOT ((NOT (NOT B8)); (NOT (NOT B8); ((E3 ((E2 ((E1 R1)) R2)) R3)) R4); (NOT B11) ((NOT B11) (NOT B10)); (NOT B11) (NOT B10); Bouy ((E4 ((E3 ((E2 ((E1 R1)) R2)) R3)) R4)) R5);
archfb2sub12;
Table Comparison Different 12-Bit Adder Schemes Resource used used passes R1ADD12 R2ADD12 R3ADD12 FC2ADD12 FC3ADD12 FC4ADD12
Efficient Arithmetic Designs With Cypress CPLDs
Comparison Resource Utilization Different Schemes Building 12-Bit Adder
comparison chart showing resource utilization different models that used building 12-bit adder shown Table This table summarizes some issues that have been presented discussion far. Some comparisons comments from charts listed here: Ripple Carry Adders given group-size, number passes taken yield results dependent size adder being built. group-size increases, number passes taken through logic array (n/k) passes final stage, where size adder group size. example, R2ADD12 takes (12/2) passes yield desired result. R3ADD12 (ripple carry adder built using 3-bit groups) scheme, value within 3-bit group produced only second pass through array. This, however, does affect 12-bit adder yielding results passes (12/3) expected. This possible because carry-out from 3-bit group produced first pass. implementation ADD3WC discussed detail earlier. This solution very desirable solution most applications that small sized adders. R1ADD12 uses fewer more among different versions ripple-carry adders. opposite case R3ADD12. R2ADD12 provides intermediate solution between extremes. macrocell count R1ADD12 reduced from attribute `synthesis_off' used even-numbered carries only. number passes also improved from This pushes product term count from 138. either case, none equations must split. This fact, R2ADD12. designer choose implementation that best chooses application. R4ADD12 (ripple carry adder built using 4-bit groups) viable solution, since carry-out from 4-bit groups would take passes generated. This results implementation that takes passes yield results opposed expected three passes. This solution inefficient considered. Carry-Lookahead Adders given group-size, number passes taken yield results largely independent size adder being
built. This biggest advantage with carry-lookahead adders. group generates (Es) group propagates (Rs) generated first pass carry-ins groups second pass through logic array. outputs generated third fourth pass, depending group-size being used. FC2ADD12 takes three passes complete, four passes FC3ADD12 FC4ADD12. number passes remains same 32-bit versions adder. Similar ripple carry adders, FC2ADD12 uses fewer more among different versions carry-lookahead adders. opposite case FC4ADD12. FC3ADD12 provides intermediate solution between extremes. FC5ADD12 (carry-lookahead adder built using 5-bit groups) viable solution, since extra number number passes taken through logic array justify usage. design also modular difficult deal with. designer can, however, extend discussion presented build FC5ADD12 model application demands This, however, would extreme case presented. Summary Comparing ripple carry carry-lookahead adders, evident that ripple carry adders area efficient have poor speed performance. carry-lookahead adders other hand faster utilize more resources. Given different choices, user choose which scheme best suited application.
Large-Sized Adders/Subtracters
Table discusses resource utilization 24-bit 32-bit adders using 2-bit, 3-bit, 4-bit group-sizes with carry/borrow-lookahead principle. previous sections, different implementation strategies VHDL code 12-bit full-carry-lookahead adder were shown example. VHDL code most variations 32-bit implementations presented here space constraints. code isprovided, however, part tutorial section Warp VHDL compiler. Figure illustrates three schemes used implementing 24-bit adder. VHDL code 24-bit carry-lookahead adder with 4-bit group size shown here example. code other models very similar easily extrapolated.
Table Comparison Different 24-Bit 32-Bit Adder Schemes. Resource used used passes FC2ADD24 FC3ADD24 FC4ADD24 FC2ADD32 FC3ADD32 FC4ADD32
Efficient Arithmetic Designs With Cypress CPLDs
Adder split into groups
Adder split into groups
Adder split into groups
Figure Three Different Carry-Lookahead Schemes Implement 24-Bit Adder -24-bit Fast Carry lookahead adder with 4-bit groups
LIBRARY IEEE; IEEE.STD_LOGIC_1164.ALL; work.add2wc_pkg.all; work.add2nc_pkg.all; ENTITY fc4add24 PORT
STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC);
fc4add24; ARCHITECTURE fc4add24arch fc4add24 SIGNAL SIGNAL SIGNAL
E1,E2,E3,E4,E5 STD_LOGIC; R1,R2,R3,R4,R5 STD_LOGIC; STD_LOGIC;
attribute synthesis_off signal true; attribute synthesis_off E1,E2,E3,E4,E5 signal true; attribute synthesis_off R1,R2,R3,R4,R5 signal true;
BEGIN add2wc PORT (CI,A1,A0,B1,B0,SUM1,SUM0,C2); add2nc PORT (C2,A3,A2,B3,B2,SUM3,SUM2); add2wc PORT (C4,A5,A4,B5,B4,SUM5,SUM4,C6); add2nc PORT (C6,A7,A6,B7,B6,SUM7,SUM6); add2wc PORT (C8,A9,A8,B9,B8,SUM9,SUM8,C10); add2nc PORT add2wc PORT add2nc PORT add2wc PORT i10: add2nc PORT i11: add2wc PORT i12: add2wc PORT ((A2 B3)) ((A1 B3)) ((A0 B3));
Efficient Arithmetic Designs With Cypress CPLDs
B0); CI); ((A6 B7)) ((A5 B7)) ((A4 B7)); B4); CI); (A11 B11) ((A10 B10) (A11 B11)) ((A9 (A10 B10) (A11 B11)) ((A8 (A10 B10) (A11 B11)); (A11 B11) (A10 B10) B8); CI);
(A15 B15) ((A14 B14) (A15 B15)) ((A13 B13) (A14 B14) (A15 B15)) ((A12 B12) (A13 B13) (A14 B14) (A15 B15)); (A15 B15) (A14 B14) (A13 B13) (A12 B12); CI); (A19 B19) ((A18 B18) (A19 B19)) ((A17 B17) (A18 B18) (A19 B19)) ((A16 B16) (A17 B17) (A18 B18) (A19 B19)); (A19 B19) (A18 B18) (A17 B17) (A16 B16); CI);
fc4add24arch;
Equality Comparators
Equality comparators used compare value operands. Equality comparators built using Exclusive-OR gate building block. bit-wise comparison data streams done using gates each individual results OR-ed together obtain final result. EQCOMP4: 4-Bit Equality Comparator EQCOMP4 4-bit equality compare element. model described ((A3 B0)) This implementation takes PTs. Figure shows block diagram EQCOMP4. NEQCOMP4 4-bit non-equality comparator. EQCOMP4 implemented inverted version NEQCOMP4. NEQCOMP4 element takes EQCOMP4 takes PTs. Cypress CPLD polarity control macrocell create
EQCOMP4 element using NEQCOMP4 element, resulting implementation with reduced product term count.
A3.0 NEQCOMP4 B3.0 EQCOMP4 Figure Block Diagram 4-Bit Equality Compare equality comparator sizes greater than takes more than produce result takes passes, since Cypress CPLD architecture takes maximum into macrocell. EQCOMP24: 24-Bit Equality Comparator EQCOMP24 uses three EQCOMP8s parallel combines results three components produce result. This takes passes through logic array, MCs,
Efficient Arithmetic Designs With Cypress CPLDs
PTs. block diagram this model shown Figure A7.0 B7.0 EQCOMP8
parators provide information signal greater than (>), less than another signal same length. MAGCOMP8: 8-Bit Magnitude Comparator This generic implementation magnitude comparator does bit-wise comparison, similar that equality comparison. However, case magnitude comparator results bit-wise comparison retained passed onto succeeding bits. This passage information continues tends increase resource utilization design exponentially. VHDL implementation 8-bit magnitude comparator shown here. design takes fits passes through logic array. block diagram MAGCOMP8 shown Figure A7.0
A15.8 EQCOMP8 B15.8
A23.16 EQCOMP8 B23.16 Figure Block Diagram 24-Bit Equality Compare
MAGCOMP8 B7.0
Magnitude Comparators
Magnitude comparators also widely used industry comparing values operands. magnitude com- Flattened version Magnitude comparator
Figure Block Diagram 8-Bit Magnitude Compare
LIBRARY IEEE; IEEE.STD_LOGIC_1164.ALL; work.std_arith.all; ENTITY magcomp PORT STD_LOGIC_VECTOR(7 DOWNTO STD_LOGIC); magcomp; ARCHITECTURE magarch magcomp
BEGIN WHEN ELSE '0';
magarch;
fully flattened implementation magnitude comparator bits would take implement. however, recommended fully-flattened version magnitude comparator bit-size greater than bits. This ensure that there sum-splitting involved equations. There other means achieve better results best scheme presented next. FB2MGCMP8: 8-Bit Borrow-Lookahead Magnitude Comparator block diagram 8-bit magnitude compare shown Figure A7.0 FB2MGCMP8 B7.0 Figure Block Diagram 8-Bit Magnitude Compare This scheme uses different approach compare magnitudes binary vectors. example, scheme illustrated 8-bit magnitude comparator. bits vectors A[7:0] B[7:0] called respectively. Similarly, bits referred respectively. vector greater than BL). evident from equations Figure that magnitude comparison binary vectors done evaluating values generate functions MSHalf (most significant half) LSHalf (least significant half) vectors propagate function MSHalf. This scheme stripped down version borrow-lookahead scheme used build fast subtracters. this implementation need determine values generate propagate functions vectors need produce difference results. borrow-out signal determines output magnitude comparison. borrow-out then else This scheme allows fast efficient means magnitude comparisons. Magnitude Comparators bits
Efficient Arithmetic Designs With Cypress CPLDs
A[7:0] B[7:0]
((AM BL))
XXXXXXXX XXXXXXXX >BM) (AM/=BM) >BL)
Figure Vector Magnitude Comparison Equations built produce result just passes. number used also substantially less than `flattened' implementation magnitude comparators. discussion presented earlier group-sizes also extended here. group-size over which propagate generate functions generated varied cases design takes passes produce desired result. various values generated first pass value borrow-out second pass. However, there trade-off between number used among different group-sizes chosen. comparison between these different implementations discussed later. number used implement (propagate) function halved `OR' gates used instead `XOR' gates. This mentioned earlier discussion carry-lookahead. This extension makes implementation borrow-lookahead magnitude comparator fast efficient. Comparison Implementations 12-Bit Magnitude Compare different implementations 12-bit magnitude comparator shown here. first implementation extension MAGCOMP4. second implementation uses borrow-lookahead scheme built using borrow-lookahead over group-size bits. This comparison illustrates advantage using FB2MGCMP12 over simple MAGCOMP12. Cypress CPLDs. MAGCOMP12 with synthesis_off attribute intermediate signals uses unique PTs, very slow takes passes through array. A11.0 MAGCOMP12 B11.0
Figure Block Diagram 12-Bit Magnitude Compare block diagram FB2MGCMP12 shown Figure VHDL code this design also shown here. This design takes just passes through array uses unique PTs. various values generated first pass value borrow-out second pass. Each uses output takes PTs. This clearly much better implementation than MAGCOMP12.
A11.0 FB2MGCMP12 B11.0
block diagram MAGCOMP12 shown Figure Figure Block Diagram 12-Bit flattened version MAGCOMP12 takes (212 PTs. Magnitude Compare with Borrow-Lookahead This large amount logic will into -The borrow-lookahead principle using 2-bit groups used build this -element
LIBRARY IEEE; IEEE.STD_LOGIC_1164.ALL; ENTITY fb2mgcmp12 PORT STD_LOGIC; STD_LOGIC; MAG: STD_LOGIC); fb2mgcmp12; ARCHITECTURE archfb2mgcmp12 fb2mgcmp12 SIGNAL E0,E1,E2,E3,E4,E5 SIGNAL R0,R1,R2,R3,R4,R5
STD_LOGIC; STD_LOGIC;
Efficient Arithmetic Designs With Cypress CPLDs
SIGNAL STD_LOGIC; attribute synthesis_off E0,E1,E2,E3,E4,E5 signal true; attribute synthesis_off R0,R1,R2,R3,R4,R5 signal true;
BEGIN (NOT ((NOT (NOT B0)); (NOT (NOT B0); (NOT ((NOT (NOT B2)); (NOT (NOT B2); (NOT ((NOT (NOT B4)); (NOT (NOT B4); (NOT ((NOT (NOT B6)); (NOT (NOT B6); (NOT ((NOT (NOT B8)); (NOT (NOT B8); (NOT B11) ((NOT B11) (NOT B10)); (NOT B11) (NOT B10);
E0);
WHEN '1') ELSE '0'; -MAG
archfb2mgcmp12;
comparison between 4-bit group sized implementation 12-bit magnitude comparator based borrow-lookahead scheme shown Table mentioned before, number passes through logic array same group-bit-sizes. number used vary shown table. user wide choice needs choose right group-size depending application. Table Comparison 12-Bit Magnitude Compare between Different Group-Sizes. Group-Bit-Size passes Figure Block Diagram 12-Bit Borrow-Lookahead Three-Output Magnitude Compare There ways which Borrow-lookahead principle used achieve functionality three-output comparator. passes each, then third pass using results from This uses PTs. EQCOMP12 required this model built using three EQCOMP4s similar block diagram shown Figure EQCOMP12 also built using four EQCOMPs, EQCOMP6s, FB2EQMCMP12: 12-Bit Borrow-Lookahead Three-Output Magnitude Comparator Using 2-Bit Groups This model combines concepts discussed magnitude comparator section into design. This uses borrow-lookahead, 2-bit groups, also produces three outputs. block diagram this model shown Figure
A11.0 FB2EQMGCMP12 B11.0
Three-Output Comparators
discussion magnitude comparators been restricted values less than greater than equal only. discussion this section talks about producing three outputs, namely `<', `='.
Efficient Arithmetic Designs With Cypress CPLDs
EQCOMP8 EQCOMP4 other combination. long EQCOMP model chosen does sum-split, value EQCOMP12 realized passes using PTs. passes generate three outputs. this implementation required create value second required
obtain value value also produced passes along with This scheme uses PTs. first scheme area efficient, takes three passes though logic array generate final results. VHDL implementation first scheme presented here. very easy extrapolate code second scheme.
-This VHDL code describes implementation 3-output magnitude -comparator. borrow-lookahead principle using 2-bit groups used build this element
LIBRARY IEEE; IEEE.STD_LOGIC_1164.ALL; ENTITY fb2eqmgcmp12 PORT STD_LOGIC; STD_LOGIC; EQ,LT,GT: STD_LOGIC); fb2eqmgcmp12; ARCHITECTURE archfb2eqmgcmp12 fb2mgeqcmp12 SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL
E0,E1,E2,E3,E4,E5 STD_LOGIC; R0,R1,R2,R3,R4,R5 STD_LOGIC; STD_LOGIC; INT1, INT2, INT3: STD_LOGIC; STD_LOGIC;
attribute synthesis_off E0,E1,E2,E3,E4,E5 signal true; attribute synthesis_off R0,R1,R2,R3,R4,R5 signal true; attribute synthesis_off INT1, INT2, INT3 signal true;
BEGIN (NOT ((NOT (NOT B0)); (NOT (NOT B0); (NOT (NOT (NOT (NOT
((NOT (NOT B2)); (NOT B2); ((NOT (NOT B4)); (NOT B4);
(NOT ((NOT (NOT B6)); (NOT (NOT B6); (NOT ((NOT (NOT B8)); (NOT (NOT B8); (NOT B11) ((NOT B11) (NOT B10)); (NOT B11) (NOT B10);
R1);
WHEN '1') ELSE '0';
Efficient Arithmetic Designs With Cypress CPLDs
WHEN ELSE '0'; B11; B10; INT1 (X11 X8); INT2 X4); INT3 X0); (INT1 INT2 INT3);
archfb2eqmgcmp12;
Summary
number arithmetic elements frequently used various applications were presented this application note. underlying concepts final implementations these models were also presented. Designs created with understanding target architecture always perform better than generic designs. elements available Warp geared towards obtaining best performance, both speed area, CPLDs. concepts implementations presented this application note used build various elements. Understanding this application note will enable user understand elements better exploit their availability best possible manner. CPLDs very popular with programmable logic industry widely used applications, PCs, Motherboards, Data Communication equipment, Multimedia, Instrumenta-
tion, etc. They have many advantages over other programmable logic devices. advantages listed here: Ease use-Simple extension AND-OR structure small PLDs like 22V10 Predictable timing model fanout penalty High system speed shelf availability Cost effective These advantages make CPLDs ideal platform implement high-performance arithmetic circuits cost-effective manner. With background provided this application note, designer should able create algorithm implementation arithmetic application.
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Cypress Semiconductor Corporation, 1998. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.

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