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Modular Embedded DRAM Core Concept 0.24 Technology
Konrad SIEMENS Semiconductor Group Balanstr. 81617 Germany
Copyright 1998 IEEE. Published Proceedings MTDT `98, August 1998 Jose, California. Personal this material permitted. However, permission reprint republish this material advertising promotional purposes creating collective works resale redistribution servers lists, reuse copyrighted component this work other works, must obtained from IEEE. Contact: Manager, Copyrights Permissions IEEE Service Center Hoes Lane P.O. 1331 Piscataway, 08855 1331, Telephone: Intl. 3966
Modular Embedded DRAM Core Concept 0.24 Technology
Konrad SIEMENS Semiconductor Group Balanstr. 81617 Germany
Abstract
development embedded DRAMs important step ahead processor-memory performance need memory architectures with high data bandwidths. this paper, motivation development embedded DRAMs shown, followed introduction advantages, disadvantages, applications market shares embedded systems. main part paper description SIEMENS Modular Embedded DRAM Core Concept, that allows customer large number degrees freedom customizing special embedded DRAM application.
using logic technology logic part chip benefits from fast transistors, because high saturation current memory cannot realized with cell. This means relatively high area penalty. this case embedded system compete against classical printed circuit board (PCB) solution terms silicon area, large amount memory required. other hand very compact logic design possible because high number metalization levels. DRAM technology allows creation embedded DRAMs with very leakage currents, speed logic transistors cannot achieved this case. other hand DRAM technology allows design embedded systems with Mbits DRAM more. This impossible with logic technology because would lead tremendously large chip areas. disadvantages against logic technologies partly compensated introduction additional metalization layers, which allow design very compact logic structures. speed transistors increased decreasing gate oxide thickness channel length relative commodity DRAM process.
Introduction
evolution integrated circuits technologies processing logic devices dynamic memory devices have diverged because different requirements these circuits. Logic devices need very fast transistors because complexity logic structures, e.g. processors. This achieved extremely thin gate oxides. these oxides cannot used DRAM technology because they lead high leakage currents thus short retention times. This means that DRAMs have thicker gate oxides than logic devices short switching times logic transistor DRAM cell transistor. Because irregular organisation logic circuits logic technology needs higher number metalization layers than DRAM technology using regular structures memories. Embedded systems, consisting logic embedded DRAM, developed from directions:
SIEMENS advanced 0.24 DRAM trench technology experience processing high quality DRAMs high volumes. Because focus market embedded systems with DRAM capacity several Mbits, usage DRAM technology best fits customers` requirements. When used embedded DRAMs, trench capacitor superior normal stacked capacitor,
cause planar trench cell array induces step transition periphery whereas stack cell array results this step, which causes critical thinning metal lines reduces resolution lithography. Additionally trench cell less susceptible noise other disturbance than stacked cell, because trench cell lies deeply buried substrate.
integration several devices same substrate allows cost reduction packaging, because only package fewer total number interface pins needed. using embedded systems lower chipcount results saving board space.
Motivation Embedded DRAM
last years increasing observed between processor DRAM speed: performance processors increased year contrast only improvement performance commodity DRAMs. Several cache structures where introduced partially compensate this performance expense increased latency, which turn limited performance many applications. integration logic circuit sufficient amount dynamic memory same substrate offers possibility lowering this performance because following advantages [1]: on-chip memory interface embedded DRAM allows replacement large off-chip drivers (OCD) small on-chip drivers. This results decreased capacitive loads, power consumption heat loss. Because interface between memory logic needs OCDs pads, higher clock frequency applied memory. wire length interface embedded system optimized every application. This results lower propagation delays enhancement noise immunity. commodity DRAM every data data word needs pin. Because area aspects there limitation that directly results limitation word width. Embedded DRAMs need each databit, much higher word widths possible. SIEMENS embedded DRAM concept word width bits memory macro supported. customer needs special memory size application rely memories available DRAM market. using embedded DRAM memory organisations memory sizes that available commodity DRAMs.
spite these advantages there still some challenges disadvantages that should mentioned: integration logic DRAM can`t mastered without adjustment technology already descriped introduction. this eDRAM technology libraries must developed characterized, macros have ported sometimes design flow adapted. Although embedded memory decreased power consumption, power consumption whole chip increase. This have effect DRAM retention time increasing junction temperature devices. Because every data accessible external known test concepts commodity DRAMs cannot applied embedded DRAM. Therefore special eDRAM test concept developed. customer decided embedded system cannot later expand on-chip memory size.
market embedded DRAM growing very fast estimated rise from 1997 2001. following four market segments currently largest applications eDRAM: market graphics accelerator chips laptops other portable devices. this segment advantages high performance power dissipation features. market hard disk drive controllers. This segment does benefit much from high data bandwidth graphics market exploits system costs. market printer controllers. similiar requirements hard disk drive market. market network switching. This high market embedded DRAM: very large
memories with Mbits widths with bits needed operation networks.
State
Since volume manufacturing embedded DRAM new, only companies have introduced embedded DRAM concepts. shown above, main market eDRAM product categories with very short development times life cycles, where customized memory cores needed. Because development dynamic memory even cut-down from existing design last nearly long life cycle dedicated product, company afford start with development after customer request. Therefore most companies offering embedded DRAM concepts provide certain number tailored DRAM cores with different, fixed parameters like memory size, page length, word width redundancy capability. customer need embedded DRAM special application must choose between available cores take that best fits needs.
blocks that needed interface perform DRAM functionality: column decoder, secondary sense amplifier, data multiplexer, column redundancy fuses, data I/O, address input, test interface power supply module. construction memory core depends application customer`s requirements. First must know general operating conditions embedded DRAM: size memory, page length, data word width, latency mode, clock frequency memory organisation. core concept supports multi bank operation mode with four independent banks memory module, where memory module concatenated stack memory blocks with shared interface. this memory module 1Mbit building blocks stacked above each other. Because power consumption aspects, maximum number memory blocks, that activated parallel, 1Mbit memory block pagelength kbits, maximum page length, that achieved parallel activation, kbit. More than blocks activated parallel expense extra power supply module.
Configuration Configuration Mbit DRAM Configuration Mbit DRAM
SIEMENS decided choose completely different approach developed modular embedded DRAM core concept 0.24 DRAM trench technology. concept lets customers realize tailored solutions very short time, with uncompromising quality standard DRAMs. This achieved, because eDRAM core concept large number degrees freedom customer choose from.
Bank
Mbit DRAM
Mbit DRAM
Mbit DRAM
Interface
Interface
Interface
Figure Examples Embedded DRAM cores
Modularity flexibility
modular embedded DRAM core concept based idea toolbox. this toolbox parts available that needed form customer specific embedded DRAM core. main part Mbit memory block containing cells, wordlines bitlines, that needed memory array, additionally whole path with decoder, wordline drivers word redundancy steering circuits this memory block. Based this building block creation memories with Mbit supported with memory granularity Mbit. other parts toolbox building Figure shows three different memory configurations. Each them memory size Mbit. Configuration consists bank, where only memory block activated time. activated memory block appears greyed-out figure. This activation results page length kbit. Configuration consists bank, this bank memory blocks activated parallel. this example page length kbits available expense higher activation current. Configuration consists banks. every bank only memory block activated time. Basically this results page length kbit. activating bank then bank page length
Bank
Mbit DRAM
Mbit DRAM
Bank
Mbit DRAM
Mbit DRAM
Mbit DRAM
Mbit DRAM
Bank
SIEMENS Modular Embedded DRAM Core Concept
Mbit DRAM
kbit possible. customer decide addressing whether wants operate DRAM core high power mode power mode. word width delivered interface bit. activating memory modules parallel maximum data word width possible. customer needs small memory with high data word width expand word width memory module using interfaces parallel only memory module shown figure This does mean that wide interface double area interface needed, because some circuits, notably column decoder test interface, needed only once both interfaces.
Redundancy
redundancy performance needed eDRAM core depends application memory size. instance, graphics applications have less stringent error requirements less powerful redundancy than needed program memory high-end applications. redundancy concept embedded DRAM core concept offers row- column redundancy, that configured wide ranges adapted application. this area penalty redundancy tailored customer`s requirements. Every Mbit building block fixed number redundant word line clusters. Depending wanted redundancy capability, size spare word line cluster chosen from three different versions. redundant clusters repair defective word lines both same memory block other memory blocks. capability this interblock word redundancy depends memory size activation scheme core increased expense some additional space area local sense amplifiers. column redundancy based flexible approach, that developed modular DRAM applications. allows expand redundancy performance customer`s needs uses available redundant cells more efficient than conventional concepts. Because patent evaluation reasons further information cannot presented.
Mbit DRAM Mbit DRAM Mbit DRAM Mbit DRAM Mbit DRAM Mbit DRAM Mbit DRAM Mbit DRAM
Interface Interface
Test concept
SIEMENS offers embedded DRAM quality that meets high quality standards commodity DRAMs. provide this, SIEMENS developed special embedded DRAM test concept, based onchip integration test controller, which programmed external automated test equipment (ATE), which able apply test patterns memory. Because every data accessible external pin, read data compressed afterwards evaluated ATE. Figure shows diagram embedded DRAM test concept [2]. customer choose between supported test modes. direct access provides same functionality commodity DRAMs used fail generation, yield analysis redundancy calculation. Therefore multiplexers registers implemented available number external pins.
Figure Embedded DRAM with interface core concept offers programmable latency stages latency latency mode embedded DRAM clocked with MHz, depending memory size. memory module with interface wordwidth achieves data rates 10.6 Gbit/s page mode. combining four memory modules shown figure with total data word width bit, maximum data rate 84.8 Gbit/s page mode achieved. Because finished building blocks only takes days compose layout eDRAM macro create other views, that requested customer.
Test Controller also provides built-in-logic support algorithmic test pattern generation (ATPG) expected value comparison. This test mode needed package tests normal logic without memory test option. Additionally built-in-logic also provides built-in power-on self test burn-in capabilities.
dram_test
Applications
SIEMENS nearly years experience developing embedded DRAMs, starting with (picture picture) device applications 1989. This first embedded DRAM application produced Mbit technology. figure chip photo embedded device shown, that dedicated speech recognition applications. This chip designed 1997 0.35µm DRAM technology included Mbit DRAM, core, SRAM.
Customer Logic ASIC
data,
data Test Controller
Embedded DRAM Core
Figure Embedded DRAM Test Concept with Test Controller Test Controller always presents same hardware regardless internal core configuration allows reuse test software with only small modifications. wafer test, memory tester logic tester with memory test option required, whereas package test logic tester taken.
eDRAM
customized logic
C163
Figure photo integrated hard-diskdrive controller with Mbit eDRAM eDRAM customized logic eDRAM Figure figure show photos integrated hard-disk-drive controllers. These devices produced 0.35 technology include Mbit respectively 1.875 Mbit embedded DRAM addition other components, that required controller operation [3],[4].
SRAM
Conclusion
this paper modular embedded DRAM core concept 0.24 DRAM technology been introduced. modularity flexibility this approach allow design customized embedded DRAM cores very short time. core concept performs creation embedded DRAMs with memory size Mbit supports large number memory organisations
Figure photo embedded chip voice applications
memory activation schemes. innovative redundancy concept permits adaption redundancy capability application keeps area penalty low. arrive equivalent quality known from commodity DRAMs, special test concept based on-chip integration test controller developed implemented.
comparison pros cons embedded DRAMs, inspection embedded DRAM market introduction some applications embedded DRAMs show wide range market potential this modular embedded DRAM core concept.
Acknowledgements
author wants thank colleagues from SIEMENS memory division development group.
References
Wehn, Hein. Embedded DRAM Architectural Trade-Offs. Design, Automation Test Europe 1998, Paris. McConnell, Richter. Test Concept Embedded DRAM Cores. IEEE TECS Testing Embedded Core-based Systems, Washington, November 5-6, 1997. Embedded DRAMs ihre Anwendung. Fachbericht, Fachtagung Hannover, 1998. Born, Steurich. Smaller, better, faster. What`s Electronics, Europe, 1998.
eDRAM
Figure photo integrated hard-diskdrive controller with 1.875 Mbit eDRAM
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