COP888GW 8-Bit Microcontroller with Pulse Train Generators Capture Mod
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COP888GW 8-Bit Microcontroller with Pulse Train Generators Capture Modules
COP888GW 8-Bit Microcontroller with Pulse Train Generators Capture Modules
General Description
COP888 family microcontrollers uses 8-bit single chip core architecture fabricated with National Semiconductor's M2CMOSprocess technology. COP888GW member this expandable 8-bit core processor family microcontrollers. fully static part, fabricated using double-metal silicon gate microCMOS technology. Features include 8-bit memory mapped architecture, MICROWIRE/PLUSserial I/O, 16-bit timer/counters supporting three modes (Processor Independent generation, External Event counter Input Capture mode capabilities), four independent 16-bit pulse train generators with 16-bit prescalers, independent 16-bit input capture modules with 8-bit prescalers, multiply divide functions, full duplex UART, power savings modes (HALT IDLE), both with multi-sourced wake up/interrupt capability. This multi-sourced interrupt capability also used independent HALT IDLE modes. Each software selectable configurations. devices operate over voltage range 2.5V-6V. High throughput achieved with efficient, regular instruction operating maximum instruction rate. device emissions. radiated emissions achieved gradual turn-on output drivers internal filters chip logic crystal oscillator. device available 68-pin PLCC package. Multi-Input Wake-Up (MIWU) with optional interrupts MICROWIRE/PLUSserial
Features
Memory mapped Software selectable options TRI-STATE Output, Push-Pull Output, Weak Pull-Up Input, High Impedance Input) Schmitt trigger inputs port Package: 68-pin PLCC
CPU/Instruction Features
instruction cycle time Fourteen multi-source vectored interrupts servicing: External Interrupt with selectable edge Idle Timer Timers (each with interrupts) MICROWIRE/PLUS Multi-Input Wake-Up Software Trap UART Capture Timers Counters (one vector four counters) Default (default interrupt) Versatile easy-to-use instruction 8-bit Stack Pointer (stack RAM) 8-bit register indirect data memory pointers
Features
16-bit input capture modules with 8-bit prescalers Four Pulse Train Generators with 16-bit prescalers Full duplex UART 16-bit timers, each with 16-bit registers supporting: Processor independent mode External event counter mode Input capture mode Quiet design (low radiated emissions) kbytes on-board bytes on-board
Fully Static CMOS
power saving modes: HALT IDLE current drain (typically Single supply operation: 2.5V-5.5V Temperature range: -40°C +85°C
Development Support
Emulation device Real time emulation full program debug offered MetaLink's Development System
Additional Peripheral Features
Idle Timer
TRI-STATE registered trademark National Semiconductor Corporation. M2CMOSTM, MICROWIRE/PLUSTM, COPSTM, MICROWIREand WATCHDOGare trademarks National Semiconductor Corporation. PC-AT PC/XT registered trademarks International Business Machines Corporation. iceMASTERis trademark MetaLink Corporation.
2000 National Semiconductor Corporation
DS012065
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COP888GW
Block Diagram
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FIGURE COP888GW Block Diagram
Connection Diagram
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View Order Number COP888GW-XXX/V Package Number V68A
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COP888GW
Absolute Maximum Ratings (Note
SuppIy Voltage (VCC) Voltage Total Current into (Source) -0.3V +0.3V
Total Current (Sink) Storage Temperature Range
-65°C +150°C
Note Absolute maximum ratings indicate limits beyond which damage device occur. electrical specifications ensured when operating device absolute maximum ratings.
Electrical Characteristics
COP888GW: -40°C 85°C unless otherwise specified Parameter Operating Voltage Power Supply Ripple (Note Supply Current (Note HALT Current (Note IDLE Current Input Levels (VIH, VIL) RESET Logic High Logic Other Inputs Logic High Logic Hi-Z Input Leakage Input Pullup Current Port Input Hysteresis Output Current Levels Outputs Source Sink Others Source (Weak Pull-Up Mode) Source (Push-Pull Mode) Sink (Push-Pull Mode) TRI-STATE Leakage Allowable Sink/Source Current Outputs (Sink) others Maximum Input Current without Latchup (Notes Retention Voltage, (Note Input Capacitance Load Capacitance Rise Fall Time (min) (Note (Note 1000 Room Temp 2.7V 2.5V, 1.8V 3.3V 2.5V, 1.8V 0.4V 2.5V, 0.4V 6.0V -2.5 -0.4 -0.2 -100 3.3V 2.5V, 1.8V 2.5V, 0.4V -0.4 -0.2 (Note 0.05 -250 0.35 2.5V 2.5V, Peak-to-Peak ConditIons UnIts
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COP888GW
Electrical Characteristics
COP888GW: -40°C 85°C unless otherwise specified Parameter Instruction Cycle Time (tc) Crystal, Resonator Ceramic Clock Duty Cycle (Note Rise Time (Note Fall Time (Note Inputs tSETUP tHOLD Output Propagation Delay (Note tPD1, tPD0 Others MICROWIRESetup Time (tUWS) (Note MICROWIRE Hold Time (tUWH) (Note MICROWIRE Output Propagation Delay (tUPD) Input Pulse Width (Note Interrupt Input High Time Interrupt Input Time Timer Input High Time Timer Input Time Capture Timer High Time Capture Timer Time Reset Pause Width
Note Maximum rate voltage change defined. Note Supply current measured after running 2000 cydes with square wave input, open, inputs rails outputs open. Note HALT mode will stop from oscillatng. Test conditions: inputs tied VCC, port I/O's configured outputs programmed driving load; outputs programmed driving load. Parameter refers HALT mode entered setting Port data register. Part will pull during HALT crystal clock mode. Note Pins RESET designed with high voltage input network. These pins allow input voltages greater than pins will have sink current when biased voltages greater than (the pins have source current when biased voltage below VCC.) effective resistance (typical). These pins will latch voltage pins must limited less than volts. WARNING: Voltages excess volts will cause damage pins. This warning excludes transients. Note Condition parameter valid only part HALT mode. Note Parameter characterized tested. Note Instruction Cycle Time Note output propagation delay referenced instruction cycle where output change occurs.
Conditions 2.5V Clock Clock 2.5V 2.5V 2.2k, 2.5V 2.5V
Units
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FIGURE MICROWIRE/PLUS Timing
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COP888GW
Electrical Characteristics
(Continued)
Typical Performance Characteristics
Port Source Current Port Sink Current
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Ports C/G/L/E/F Source Current
Ports C/G/L/E/F Sink Current
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Ports C/G/L/E/F Weak Pull-Up Source Current
Dynamic
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Idle
HALT
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COP888GW
Descriptions
power supply pins. pins must connected. clock input. This comes from generated oscillator, crystal oscillator conjunction with CKO). Oscillator Description section. RESET master reset input. Reset description section. device contains five bidirectional 8-bit ports where each individual independently configured input (Schmitt trigger inputs ports output TRI-STATE under program control. Three data memory address locations allocated each these ports. Each port associated 8-bit memory mapped registers, CONFIGURATION register output DATA register. memory mapped address also reserved input pins each port. (See memory various addresses associated with ports.) Figure shows port configurations. DATA CONFIGURATION registers allow each port individually configured under software control shown below: Configuration Register Data Register Hi-Z Input (TRI-STATE Output) Input with Weak Pull-Up Push-Pull Zero Output Push-Pull Output Port Set-Up
PORT 8-bit port. L-pins have Schmitt triggers inputs. Port supports Multi-Input Wake eight pins. used UART external clock. used UART transmit receive. used timer input functions T2B. used capture timer input functions CAP1 CAP2. Port following alternate features: MIWU MIWU MIWU MIWU MIWU MIWU MIWU CAP1 MIWU CAP2 Port 8-bit port with pins (G0-G5), input (G6), dedicated output (G7). Pins G0-G6 have Schmitt Triggers their inputs. serves dedicated output clock output. There registers associated with Port, data register configuration register. Therefore, each bits (G0-G5) individually configured under software control.
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COP888GW
Descriptions
(Continued)
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FIGURE Port Configurations Since input only dedicated clock output pin, associated bits data configuration registers used special purpose functions outlined below. Reading data bits will return zeros. Note that chip will placed HALT mode writing Port Data Register. Similarly chip will placed IDLE mode writing Port Data Register. Writing Port Configuration Register enables MICROWIRE/PLUS operate with alternate phase clock. Config Reg. Used Alternate Data Reg. HALT IDLE memory (RAM). Both have their separate addressing space with separate address buses. architecture, though based Harvard architecture, permits transfer data from RAM. REGISTERS 8-bit addition, subtraction, logical shift operation instruction (tc) cycle time. There registers: 8-bit Aocumulator Register 15-bit Program Counter Register upper bits program counter (PC) lower bits program counter (PC) 8-bit address pointer, which optionally post auto incremented decremented. 8-bit alternate address pointer, which optionally post auto incremented decremented. 8-bit stack pointer, which points subroutine/ interrupt stack RAM). initialized address with reset. 8-bit Data Segment Address Register used extend Iower haIf address range into data segments bytes each. registers memory mapped with exception AccumuIator Program Counter (PC). PROGRAM MEMORY program memory consists 16384 bytes ROM. These bytes hoId program instructions constant data (data tables LAID instruction, jump vectors instruction, interrupt vectors instruction). program memory addressed 15-bit program counter (PC). interrupts devices Vector program memory location Hex. DATA MEMORY data memory address space includes on-chip data registers, registers (Configuration, Data Pin), control registers, MICROWIRE/PLUS shift register, various registers, counters associated with timers (with exception IDLE timer). Data memory addressed directly instruction indirectly pointers register.
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Port following alternate features: INTR (ExternaI Interrupt Input) (Timer Capture Input) (Timer I/O) (MICROWIRE Serial Data Output) (MICROWIRE SeriaI Clock) (MICROWIRE Serial Data Input) Port following dedicated functions: OsciIlator dedicated output Ports 8-bit ports. Port 8-bit port. following alternate features: (Output counter1, PuIse Train Generator) (Output counter2, Pulse Train Generator) (Output counter3, PuIse Train Generator) (Output counter4, Pulse Train Generator) Port eight-bit Hi-Z input port. Port 8-bit output port that preset high when RESET goes Iow. user more port outputs (except together order higher drive.
Functional Description
architecture device modified Harvard architecture. With Harvard architecture, control store program memory (ROM) separated from data store
COP888GW
Functional Description
(Continued)
data memory consists bytes RAM. Sixteen bytes mapped "registers" addresses Hex. These registers loaded immediately, also decremented tested with DRSZ (decrement register skip zero) instruction. memory pointer registers memory mapped into this space address locations respectively, with other registers being available general usage.
Note: contents undefined upon power-up.
Data Memory Segment Extension
Data memory address used memory mapped location Data Segment Address Register (S). data store memory either addressed directly single-byte address within instruction, indirectly relative reference pointers (each contains single-byte address). This single-byte address allows addressing range locations from hex. upper this single-byte address divides data store memory into separate sections outlined previously. With exception register memory from address locations 00F0 00FF, memory memory mapped with upper single-byte address being equal zero. This allows upper single-byte address determine whether base address range (from 0000 00FF) extended. this upper equals (representing address range 0080 00FF), then address extension does take place. Alternatively, this upper equals zero, then data segment extension register used extend base address range (from 0000 007F) from XX00 XX7F, where represents bits from register. Thus 128-byte data segment extensions located from addresses 0100 017F data segment 0200 027F data segment etc., FF00 FF7F data segment 255. base address range from 0000 007F represents data segment
Figure illustrates register data memory extension used extending lower half base address range hex) into data segments bytes each, with total addressing range kbytes from XX00 XX7F. This organization allows total data segments 128-bytes each with additional upper base segment bytes. Furthermore, addressing modes availabIe data segments. register must changed under program control move from data segment (128 bytes) another. However, upper base segment (containing memory registers, registers, controI registers, etc.) always available regardless contents register, since upper base segment (address range 0080 00FF) independent data segment extension. instructions that utilize stack pointer (SP) always reference stack part base segment (Segment regardless contents register. register changed these instructions. Consequently, stack (used with subroutine linkage interrupts) always located base segment. stack pointer will initialized point data memory location 006F result reset. bytes contained base segment split between Iower upper base segments. first bytes resident from address 0000 006F Iower base segment, while remaining bytes represent data memory registers located addresses 00F0 00FF upper base segment. located upper sixteen addresses (0070 007F) lower base segment. Additional beyond these initial bytes, however, will always memory mapped groups bytes less) data segment address extensions (XX00 XX7F) lower base segment. additional bytes this device memory mapped address locations 0100 017F° 0200 027F, 0300 037F hex.
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COP888GW
Data Memory Segment Extension
(Continued)
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Note Reads ones.
FIGURE Organization
Reset
This device enters reset state immediately upon detecting logic RESET pin. RESET must held minimum instruction cycle guarantee valid reset. During power-up initialization, user must insure that RESET held until this device within specified voltage. circuit RESET with delay times (5x) greater than power supply rise time recommended. When RESET input goes low, ports initialized immediately, with observed delay being only propagation delay. When RESET goes high, this device comes reset state synchronously. This device will running within instruction cycles RESET going high. RESET also used exit this device from HALT mode. Some registers reset known state, whereas other registers "unchanged" reset. When controller goes into reset state while performing write operation these registers that "unchanged" reset, register value will become unknown (i.e. unchanged). This because write operation terminated prematurely reset results become uncertain. These registers locations unchanged reset only they written when controller resets. following initializations occur with RESET Port Port Port Port Port TRI-STATE TRI-STATE TRI-STATE TRI-STATE TRI-STATE
Port HIGH CLEARED PSW, CNTRL ICNTRL registers: CLEARED SIOR: UNAFFECTED after RESET with power already applied RANDOM after RESET power-on T1CNTRL: CLEARED T2CNTRL: CLEARED TxRA, TxRB: RANDOM CCMR1, CCMR2: CLEARED CM1PSC, CM1CRL, CM1CRH, CM2PSC, CM2CRL, CM2CRH: UNAFFECTED after RESET with power already applied RANDOM after RESET power-on CCR1 CCR2: CLEARED CxPRH, CxPRL, CxCTH, CxCTL: UNAFFECTED after RESET with clock option (power already applied) RANDOM after RESET power-on PSR, ENUR ENUI: CLEARED ENU: CLEARED except (TBMT) Accumulator, Timer Timer RANDOM after RESET with crystal clock option (power already applied) RANDOM after RESET power-on MDCR: CLEARED MDR1, MDR2, MDR3, MDR4, MDR5: RANDOM WKEN, WKEDG: CLEARED
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COP888GW
Reset
(Continued)
(pF)
(pF) 30-36
Freq (MHz) 0.455
Conditions
WKPND: RANDOM Register: CLEARED (Stack Pointer): Loaded with Pointers: UNAFFECTED after RESET with power already applied RANDOM after RESET power-on RAM: UNAFFECTED after RESET with power already applied RANDOM after RESET power-on external network shown Figure should used ensure that RESET held until power supply chip stabilizes.
100-150
Control Registers
CNTRL Register (Address X'00EE) Timer1 (T1) MICROWIRE/PLUS control register contains following bits: Select MICROWIRE/PLUS clock divide IEDG External interrupt edge polarity select Rising edge, Falling edge) MSEL Selects MICROWIRE/PLUS signals respectively T1C0 Timer Start/Stop control timer modes Underflow Interrupt Pending Flag timer mode T1C1 Timer mode control T1C2 Timer mode control T1C3 Timer mode control
T1C3 T1C2 T1C1 T1C0 MSEL IEDG
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POWER SUPPLY RISE TIME
FIGURE Recommended Reset Circuit
Oscillator Circuits
chip driven clock input input which between MHz. output clock (crystal configuration), input frequency divided down produce instruction cycle clock (tc).
Figure shows Crystal diagram
Register (Address X'00EF) register contains following select bits: GIobaI interrupt enable (enables interrupts) EXEN EnabIe externaI interrupt BUSY MICROWIRE/PLUS busy shifting flag EXPND ExternaI interrupt pending T1ENA Timer Interrupt Enable Timer Underflow Input capture edge T1PNDA Timer Interrupt Pending Flag (Autoreload mode Underflow Mode capture edge mode Carry FIag Half Carry Flag
T1PNDA T1ENA EXPND BUSY EXEN
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FIGURE Crystal Diagram CRYSTAL OSCILLATOR connected make closed loop crystal resonator) controlled oscillator.
Half-Carry fIag aIso affected instructions that affect Carry fIag. (Set Carry) (Reset Carry) instructions wilI respectiveIy clear both carry flags. addition instructions, ADC, SUBC, instructions affect Carry Half Carry fIags. ICNTRL Register (Address X'00E8) ICNTRL register contains foIlowing bits: T1ENB Timer Interrupt Enable Input capture edge T1PNDB Timer Interrupt Pending Flag capture edge µWEN EnabIe MICROWIRE/PLUS interrupt µWPND MICROWIRE/PLUS interrupt pending T0EN Timer Interrupt Enable (Bit toggle) T0PND Timer Interrupt pending
Table shows component values required various standard crystal values.
TABLE CrystaI Oscillator Configuration, 25°C (pF) (pF) 30-36 Freq (MHz) Conditions
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COP888GW
Control Registers
LPEN could used flag
Unused LPEN T0PND T0EN
(Continued)
Port Interrupt Enable (Multi-Input Wake Interrupt)
WPND
T1PNDB
T1ENB
T2CNTRL Register (Address X'00C6) T2CNTRL register contains following bits: T2ENB Timer Interrupt Enable Input capture edge T2PNDB Timer Interrupt Pending Flag capture edge T2ENA Timer Interrupt Enable Timer Underflow Input capture edge T2PNDA Timer Interrupt Pending Flag (Auto reload mode Underflow mode capture edge mode T2C0 Timer Start/Stop control timer modes Timer Underflow Interrupt Pending Flag timer mode T2C1 Timer mode control T2C2 Timer mode control T2C3 Timer mode control
T2C3 T2C2 T2C1 T2C0 T2PNDA T2ENA T2PNDB T2ENB
Each timer block consists 16-bit timer, supporting 16-bit autoreload/capture registers, RxB. Each timer block pins associated with TxB. supports required timer block, while input timer block. powerful flexible timer block allows device easily perform timer functions with minimal software overhead. timer block three operating modes: Processor Independent mode, External Event Counter mode, Input Capture mode. control bits TxC3, TxC2, TxC1 allow selection different modes operation. Mode Processor Independent Mode name suggests, this mode allows device generate signal with very minimal user intervention. user only define parameters signal time time). Once begun, timer block will continuously generate signal completely independent microcontroller. user software services timer block only when parameters require updating. this mode timer counts down fixed rate Upon every underflow timer alternately reloaded with contents supporting registers, RxB. very first underflow timer causes timer reload from register RxA. Subsequent underflows cause timer reloaded from registers alternately beginning with register RxB. Timer control bits, TxC3, TxC2 TxC1 timer mode operation.
Timers
device contains very versatile timers (T0, T2). timers associated autoreload/capture registers power containing random data. TIMER (IDLE TIMER) device supports applications that require maintaining reaI time power with IDLE mode. This IDLE mode support furnished IDLE timer which 16-bit timer. Timer runs continuously fixed rate instruction cycle cIock, user cannot read write IDLE Timer which count down timer. Timer supports following functions:
Exit Idle Mode (See Idle Mode description) Start delay HALT mode IDLE Timer generate interrupt when thirteenth toggIes. This toggle Iatched into T0PND pending flag, wiIl occur every maximum clock frequency µs). control flag T0EN allows interrupt from thirteenth Timer enabled disabIed. Setting T0EN will enable interrupt, while resetting will disable interrupt.
TIMER TIMER device powerful timer/counter blocks, associated features functioning timer block described referring timer block Since timer blocks, identical, comments equally applicable either timer blocks.
Figure shows block diagram timer mode. underfIows programmed toggle output pin. underfIows also programmed generate interrupts. UnderfIows from timer alternately latched into pending flags, TxPNDA TxPNDB. user must reset these pending fIags under software control. control enabIe fIags, TxENA TxENB, alIow interrupts from timer underflow enabled disabled. Setting timer enable flag TxENA wilI cause interrupt when timer underflow causes register reloaded into timer. Setting timer enable flag TxENB will cause interrupt when timer underflow causes register reloaded into timer. Resetting timer enable flags will disable associated interrupts. Either both timer underflow interrupts enabled. This gives user flexibility interrupting once period either rising falling edge output. Alternatively, user choose interrupt both edges output.
Mode ExternaI Event Counter Mode This mode quite similar processor independent mode described above. main difference that timer, cIocked input signal from pin. timer control bits, TxC3, TxC2 TxC1 allow timer clocked either positive negative edge from pin. Underflows from timer Iatched into TxPNDA pending flag. Setting TxENA control flag will cause interrupt when timer underflows.
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COP888GW
Timers
(Continued)
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FIGURE Timer Mode
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FIGURE Timer External Event Counter Mode
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COP888GW
Timers
(Continued)
this mode input used independent positive edge sensitive interrupt input TxENB control flag set. occurrence positive edge input latched into TxPNDB flag.
trigger conditions also programmed generate interrupts. occurrence specified trigger condition pins will respectively Iatched into pending flags, TxPNDA TxPNDB. control flag TxENA allows interrupt either enabled disabled. Setting TxENA flag enables interrupts generated when selected trigger condition occurs pin. Similarly, flag TxENB controls interrupts from pin. Underflows from timer also programmed generate interrupts. Underflows latched into timer TxC0 pending flag (the TxC0 control serves timer underflow interrupt pending flag Input Capture mode). Consequently, TxC0 control should reset when entering Input Capture mode. timer underflow interrupt enabled with TxENA control flag. When interrupt occurs Input Capture mode, user must check both TxPNDA TxC0 pending flags order determine whether input capture timer underflow both) caused interrupt.
Figure shows block diagram timer External Event Counter mode.
Note: output available this mode since being used counter input clock.
Mode Input Capture Mode device precisely measure external frequencies time external events placing timer block, input capture mode. this mode, timer constantly running fixed rate. registers, RxB, capture registers. Each register acts conjunction with pin. register acts conjunction with register acts conjunction with pin. timer value gets copied over into register when trigger event occurs corresponding pin. Control bits, TxC3, TxC2 TxC1, allow trigger events specified either positive negative edge. trigger condition each input specified independently.
Figure shows block diagram timer Input Capture mode.
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FIGURE Timer Input Capture Mode TIMER CONTROL FLAGS timers have identical control structures. control bits their functions summarized below. TxC0 Timer Start/Stop controI Modes (Processor Independent External Event Counter), where Start, Stop Timer UnderfIow Interrupt Pending Flag Mode (Input Capture) TxPNDA Timer Interrupt Pending Flag TxPNDB Timer Interrupt Pending Flag TxENA Timer Interrupt Enable FIag TxENB Timer Interrupt Enable Flag Timer Interrupt EnabIed Timer Interrupt Disabled TxC3 Timer mode controI TxC2 Timer mode control TxC1 Timer mode controI timer mode controI bits (TxC3, TxC2 TxC1) detailed beIow:
Capture Timer
This device contains independent capture timers, Capture Timer Capture Timer Each capture timer contains 8-bit programmable prescaler register, 16-bit down counter, 16-bit input capture register, capture edge select Iogic. 16-bit down counter clocked specific frequency determined value loaded into prnscaler register. selected positive negative edge transition capture input causes contents down counter latched into capture register. values captured registers reflect eIapsed time between positive negative transitions capture input. time between positive negative edge pulse width) measured selected capture edge switched after first edge captured. Each capture timer
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COP888GW
Capture Timer
(Continued)
Figure shows capture timer block diagram.
stopped/started under software control, each capture timer configured interrupt microcontroller underflow input capture. TABLE Timer Mode Control TxC3 TxC2 TxC1 Timer Mode MODE (External Event Counter) MODE (External Event Counter) MODE (PWM) Toggle MODE (PWM) Toggle MODE (Capture) Captures: Positive Edge Positive Edge MODE (Capture) Captures: Positive Edge Negative Edge MODE (Capture) Captures: Negative Edge Positive Edge MODE (Capture) Captures: Negative Edge Negative Edge Negative Edge Timer Underflow Negative Edge Negative Edge Timer Underflow Positive Edge Positive Edge Timer Underflow Negative Edge Interrupt Source Timer Underflow Timer Underflow Autoreload Autoreload Positive Edge Timer Underflow Interrupt Source Positive Edge Positive Edge Autoreload Autoreload Positive Edge Timer Counts Positive Edge Negative Edge
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FIGURE Capture Timer Block Diagram
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COP888GW
Capture Timer
(Continued)
FUNCTIONAL DESCRIPTION capture timer used determine time between events, where event simply selected edge transition capture input. resolution time measurement dependent frequency which down counter clocked. vaIue Ioaded into prescaler controls this frequency. prescaIer clocked CKI, while down counter clocked every underfIow prescaler. This means prescaIer simpIy divides cIock before into down counter. prescaler register must Ioaded with vaIue corresponding divisor needed produce desired down counter clock. appropriate prescaler vaIue determined using following equation: Down Counter Clock Frequency CKI/(CMxPSC capture input signaI configuring port associated with capture timer input. edge seIect capture input then reset according desired transition. configured input, appropriate externaI transition will cause capture. configured output, toggling data register wiIl cause capture. interrupts used, capture timer interrupt pending bits cIeared capture timer interrupt enable set. Both interrupt sources, down counter underflow input capture edge, enabled/disabled with same CMxIEN bit. must also enable interrupts. interrupt signals from capture timers gated single 16-bit interrupt vector located addresses 0xE6 0xE7. capture timer started writing capture timer start/stop bit. Setting this also enables port capture input capture timer. internal prescaler loaded with contents prescaler register, begins counting down. Setting start/stop also loads down counter with 0FFFF Hex. prescaler clocked CKI. underflow prescaler decrements 16-bit down counter, reloads value from prescaler register into prescaler. Each additional underflow prescaler decrements down counter, reloads prescaler from prescaler register. selected edge transition input capture occurs, contents down counter immediately latched into capture register, down counter re-initialized 0FFFF Hex, capture input pending flag set. prescaler counter loaded. order input transition guaranteed recognized, signal capture input must have pulse width high pulse width least period.) interrupts enabled, capture timer generates interrupt. prescaler down counter continue operate until reset condition occurs capture timer start/stop reset. user must process capture interrupts faster than capture input frequency, otherwise input captures lost erroneous values read. down counter underflows (changes state from 0000 FFFF) before capture input detected, underflow interrupt pending flag set. interrupts enabled, capture timer generates interrupt. capture timer stopped time under software control resetting capture timer start/stop bit. capture occur before start/stop physically cIeared, fully asynchronous nature input capture signal. user must ensure that software handles this situation correctly. user wishes process this capture interrupts being used, capture timer
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registers shown block diagram include those Capture Timer (CM1), well capture timer control register. These registers read/writable (with exception capture registers, which read-only) accessed through data memory address/data bus. registers designated CM1PSC Capture Timer Prescaler (8-bit) CM1CRL Capture Timer Capture Register (Low-byte), read-only CM1CRH Capture Timer Capture Register (High-byte), read-only CM2PSC Capture Timer Prescaler (8-bit) CM2CRL Capture Timer Capture Register (Low-byte), read-only CM2CRH Capture Timer Capture Register (High-byte), read-only CCMR1 Control Register Capture Timer CCMR2 Control Register Capture Timer CONTROL REGISTER BITS control bits Capture Timer (CM1) Capture Timer (CM2) contained CCMR1 CCMR2. CCMR1 Register Bits are: CM1RUN start/stop control start; stop) CM1IEN interrupt enable control enable IRQ) CM1IP1 interrupt pending underflowed) CM1IP2 interrupt pending captured) CM1EC Select active edge capture rising, falling) CM1CM1 test mode control special test path test mode. This reserved during normal operation, must never one.) interrupt pending bits must reset software. CCMR2 Register Bits are: CM2RUN start/stop control start; 0=stop) CM2IEN interrupt enable control enable IRQ) CM2IP1 interrupt pending (1=CM2 underflowed) CM2IP2 interrupt pending (1=CM2 captured) CM2EC Select active edge capture rising, falling) CM2CM2 test mode control speciaI test path test mode. This reserved during normal operation, must never one.) interrupt pending bits must reset software. unused unused unused unused
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Capture Timer
(Continued)
Configure corresponding Port bits inputs edge control bits CMxEC Reset CMxIP1 (CMxIP1 Reset CMxIP2 (CMxIP2 Load 8-bit prescaler register CMxPSC with desired value (from 255) CMxIEN interrupts used) Global Interrupt Enable (GIE) interrupts used) CMxRUN start capture timer
interrupts should disabIed prior stopping timer. interrupts being used, user should poll capture timer pending bits after stopping timer. user wishes ignore this capture interrupts being used, capture timer interrupt service routine should check that timer still running prior processing capture interrupts. user polling pending flags, these flags should cleared after timer stopped. contents prescaler down counter remain unchanged while capture timer stopped. capture edge detect logic disabled, capture takes place even external capture signal occurs. capture timer restarted under software control writing start/stop bit. This causes prescaler down counter re-initialized. prescaler loaded from prescaler register, down counter loaded with 0FFFF Hex. RESET STATE reset signal applied counter block during normal operation following effects:
WARNING order avoid erroneous interrupts, capture timer interrupts must disabled prior setting/resetting capture edge control bits (CMxEC). addition, after selecting interrupt edge, pending flags must reset before capture interrupts enabled re-enabled. initialization sequence outlined above followed each time user aIters edge control bits, user guaranteed avoid erroneous interrupts.
CM1PSC, CMICRL, CM1CRH, CM2PSC, CM2CRL CM2CRH unaffected. power-on, contents these registers undefined.) bi-directional port pins initialized during reset HI-Z inputs. Setting start/stop bits connects pins capture timers. INITIALIZATION user should perform following initialization prior starting capture timer: Reset CMxRUN
Clear CCMR1 register Clear CCMR2 register
Pulse Train Generators
This device contains four independent pulse train generators. Each individual generator controlled corresponding 16-bit counter. Each counter 16-bit prescaler 16-bit count register. Each counter configured output selected number duty cycle pulses. contents prescaler determine width output pulses, value count register determines number pulses. Each counter stopped/started under software control, each counter configured interrupt microcontroller underflow.
Figure shows pulse train generator block diagram.
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FIGURE Pulse Train Generator Block Diagram
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COP888GW
Pulse Train Generators
(Continued)
C4Bit
IPND
C3
IPND
four 8-bit registers shown each individual counter block diagram constitute 16-bit prescaler 16-bit count register. These registers read/writable accessed through data memory address/data bus. registers designated CxPRL Low-byte Prescaler CxPRH High-byte Prescaler CxCTL Low-byte Count Register CxCTH High-byte Count Register CONTROL REGISTER BITS control bits Counter Counter contained CCR1 register. CCR1 Register bits are: C1RUN COUNTER1 start/stop control start; stop) C1IEN COUNTER1 interrupt enable control enable IRQ) C1IPND COUNTER1 interrupt pending counter underflowed) C1COUNTER1 test mode control (1=special test path test mode. This reserved during normal operation, must never one.) C2RUN COUNTER2 start/stop control start; stop) C2IEN COUNTER2 interrupt enable control enable IRQ) C2IPND COUNTER2 interrupt pending =counter underflowed) C2COUNTER2 test mode control (1=special test path. This reserved during normal operation, must never one.) interrupt pending bits must reset software.
C2Bit IPND C1C1 IPND
interrupt pending bits must reset software. FUNCTIONAL DESCRIPTION pulse train generator used produce series output pulses given width. high/low time pulse determined contents prescaler. number pulses series determined contents count register. prescaler loaded with value corresponding desired width output pulse (tw). high time time output signal each equal therefore output signal produced duty cycle period equal appropriate prescaler value determined using following equation: [(PRH 256) Since both 8-bit registers, this equation allows maximum 65536 minimum internal prescaler automatically loaded from when counter start/stop set. count register loaded with value corresponding desired number output pulses. appropriate count value calculated with following equation: Number Pulses port associated with counter signal configured software output, preset desired start logic level. interrupts used, counter interrupt pending cleared interrupt enable set. must also enable interrupts. interrupt signals from four counters gated single interrupt vector located addresses 0xF0-0xF1. counter started writing counter start/ stop bit. This resets divide-by-2 counter which produces clock signal counter register from prescaler underflow (See Figure 11). also reloads internal prescaler starts prescaler counting down next rising edge prescaler clocked rising edge ensure synchronization. Each subsequent rising edge causes prescaler decremented. When prescaler underflows, UFL1 generated (see Figure 12). This signal causes port toggle. addition, internal prescaler reloaded with value from registers. Each additional underflow prescaler causes port toggle reloads internal prescaler. Every second underflow prescaler generates signal UFL2. (UFL2 occurs half frequency UFL1, once output pulse.) This signal, UFL2, decrements count register. Therefore, count registers decremented once output pulse. underflow counter register produces signal UFL3. This signal stops counter resetting counter start/stop bit, sets counter interrupt pending flag. counter interrupt enabled, interrupt occurs. counter stopped time under software control resetting counter start/stop bit. contents count register output associated port frozen. counter restarted under software control setting start/stop bit. internal prescaler automatically reloaded from when counter start/stop set, therefore full width pulse will generated before output toggled. user also choose
control bits Counter Counter contained CCR2 register. CCR2 Register bits are: C3RUN COUNTER3 start stop control =start; stop) COUNTER3 interrupt enable control enable IRQ) C3IPND COUNTER3 interrupt pending (1=counter underflowed) C3COUNTER3 test mode control (1=special test path. This reserved during normal operation, must never one.) C4RUN COUNTER4 start/stop control start; stop) C4IEN COUNTER4 interrupt enable control enable IRQ) C4IPND COUNTER4 interrupt pending =counter underflowed C4COUNTER4 test mode control =special test path. This reserved during normal operation, must never one.) C3IEN
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COP888GW
Pulse Train Generators
(Continued)
alter logic level port before restarting. This done initializing associated port data register bit. counter underflow occur before start/stop physically cleared software. user must ensure that software handles this situation correctly. user wishes process this underflow interrupts being used, counter interrupts should disabled prior stopping timer. interrupts being used, user should poll counter pending bits after stopping timer. user wishes ignore this underflow interrupts being used, counter interrupt should disabled prior stopping timer. user polling pending flags, these flags should cleared after timer stopped. default level output high (associated port data register "1") counter stopped during level, level becomes default level. software must reinitialize port high level before restarting necessary. programmer also have adjust counter value (See Figure 12). RESET STATE reset signal applied pulse train generator block during normal operation following effects:
Divide-by-2 counter reset bi-directional port pins initialized during reset HI-Z inputs. appropriate bits must initialized outputs, order route Counter signals port pins.
INITIALIZATION user should perform following initialization prior starting counter: Load register Load register Load register Load register Reset CxIPND CxIEN interrupt used) Configure associated port output used) Global Interrupt Enable (GIE) interrupt used) CxRUN start counter
Multiply/Divide
This device contains multiply/divide block. This block supports byte bytes bytes result) multiply bytes/ bytes bytes result) divide operation. multiply divide operation executed setting control bits located multiply/divide control register. multiply divide operands must placed into appropriate memory mapped locations before operation initiated.
Counting stops immediately Interrupt enable reset zero Counter start/stop reset zero Interrupt pending reset zero Test mode controI reset zero PRL, PRH, unaffected power-on reset, contents prescaler count register undefined.)
DS012065-13
FIGURE Timing Diagram PRL=1, PRH=0, CTL=3, CTH=0
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Multiply/Divide
Register Name (Address) MDR1 (xx98) MDR2 (xx99) MDR3 (xx9A) MDR4 (xx9B) MDR5 (xx9C)
(Continued) TABLE Multiply/Divide Registers Multiplication Assignment Before Operation Unused Multiplier After Operation Unchanged byte result Middle byte result High byte result Unchanged Division Assignment Before Operation byte dividend Middle byte dividend High byte dividend byte divisor High byte divisor After Operation byte result High byte result Undefined byte divisor High byte divisor
byte multiplicand High byte multiplicand
CONTROL REGISTER BITS Multiply/Divide control register (MDCR) located address xx9D. following assignments: MULT Start Multiplication Operation start) Start Division Operation start) DIVOVF Division Overflow result division greater than bits user attempted divide zero; error) Rsvd Rsvd Rsvd Rsvd Rsvd After appropriate registers loaded, MULT start bits user start multiply divide operation. division operation priority, both bits simultaneously. MULT bits BOTH automatically cleared hardware divide multiply operation. Each division operation causes DIVOVF flag set/reset appropriate. DIVOVF flag cleared following multiplication operation. DIVOVF read-only bit. MULT bits read/writable. Bits MDCR should used, MULT operations will change their values. MULTIPLY/DIVIDE OPERATION multiply operation, muItiplicand placed addresses xx9B xx9C. multiplier placed address xx99. divide operation, dividend placed addresses xx98 xx9A divisor placed addresses xx9B xx9C. both operations, operands interpreted unsigned values. divide multiply operation started setting appropriate MDCR bit. both MULT bits set, microcontroller performs divide operation. (The user required read clear DIVOVF error prior beginning multiply/divide operation. This ignored during subsequent operations. However, next divide operation will overwrite error flag appropriate, next multiply operation will clear it.) multiply operation requires instruction cycle complete. divide operation requires instruction cycles complete. divide zero division which produces overflow requires only instruction cycle execute. MDR1 through MDR5 registers MDCR register read from written during multiply divide operation. attempt write into these registers will ignored. attempt read these registers will return undefined data. result multiply placed addresses xx99-xx9B. result divide placed addresses xx98-xx99. division zero attempted resulting quotient divide operation more than bits long, then DIVOVF
multiply/divide control register. dividend divisor left unchanged. divide operation always causes DIVOVF flag reset appropriate. DIVOVF flag cleared following multiply operation. RESET STATE reset signal applied device during normal operation following affects: MDCR cleared, operation progress stopped. MDR1 through MDR5 undefined.
MULT
Power Save Modes
device offers user power save modes operation: HALT IDLE. HALT mode, microcontroller activities stopped. IDLE mode, on-board oscillator circuitry timer active other microcontroller activities stopped. either mode, on-board RAM, registers, states, timers (with exception unaltered. HALT MODE device placed HALT mode writing HALT flag data bit). microcontroller activities, including clock timers, stopped. HALT mode, power requirements device minimal applied voltage (VCC) decreased 2.0V) without altering state machine. device supports different ways exiting HALT mode. first method exiting HALT mode with Multi-Input Wakeup feature port. second method exiting HALT mode pulling RESET low. Since crystal ceramic resonator selected oscillator, Wakeup signal allowed start chip running immediately since crystal oscillators ceramic resonators have delayed start time reach full amplitude frequency stability. IDLE timer used generate fixed deIay ensure that oscilIator indeed stabilized before allowing instruction execution. this case, upon detecting valid Wakeup signal, only oscillator circuitry enabled. IDLE timer loaded with value clocked with instruction cycle clock. clock derived dividing oscillator clock down factor Schmitt trigger following inverter chip ensures that IDLE timer clocked only when oscillator sufficiently large amplitude meet Schmitt trigger specifications. This Schmitt trigger part oscillator closed loop. startup timeout from IDLE timer enables clock signals routed rest chip.
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Power Save Modes
(Continued)
devices have mask options associated with HALT mode. first mask option enables HALT mode feature, while second mask option disables HALT mode. With HALT mode enable mask option, device will enter exit HALT mode described above. With HALT disable mask option, device cannot placed HALT mode (writing HALT flag will have effect, HALT flag will remain "0"). IDLE MODE device placed IDLE mode writing IDLE flag data bit). this mode, activities, except associated on-board oscillator circuitry IDLE Timer stopped. with HALT mode, device returned normal operation with reset, with Multi-Input Wake from Port. Alternately, microcontroller resumes normal operation from IDLE mode when thirteenth (representing 4.096 internal clock frequency MHz, IDLE Timer toggles. This toggle condition thirteenth IDLE Timer latched into T0PND pending flag. user option being interrupted with transition thirteenth IDLE Timer interrupt enabled disabled T0EN control bit. Setting T0EN flag enables interrupt vice versa.
user enter IDLE mode with Timer interrupt enabled. this case, when T0PND gets set, device will first execute Timer interrupt service routine then return instruction following "Enter Idle Mode" instruction. Alternatively, user enter IDLE mode with IDLE Timer interrupt disabled. this case, device will resume normal operation with instruction immediately following "Enter IDLE Mode" instruction.
Note: necessary program instructions following both HALT mode IDLE mode instructions. These instructions necessary allow clock resynchronization following HALT IDLE modes.
Multi-Input Wakeup
Multi-Input Wake feature used return (wake device from either HALT IDLE modes. Alternately Multi-Input Wake Up/Interrupt feature also used generate edge selectable external interrupts.
Figure shows Multi-Input Wake logic.
DS012065-15
FIGURE Multi-Input Wake Logic Multi-Input Wake feature utilizes Port. user selects which particular port combination Port bits) will cause device exit HALT IDLE modes. selection done through register WKEN. register WKEN 8-bit read/write register, which contains control every port bit. Setting particular WKEN enables Wake from associated port pin. user select whether trigger condition selected Port going either positive edge (low high transition) negative edge (high transition).
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Multi-Input Wakeup
(Continued)
This selection made register WKEDG, which 8-bit control register with assigned each Port pin. Setting control will select trigger condition negative edge that particular Port pin. Resetting selects trigger condition positive edge. Changing edge select entails several steps order avoid Wake condition result edge change. First, associated WKEN should reset, followed edge select change WKEDG. Next, associated WKPND should cleared, followed associated WKEN being reenabled. example serve clarify this procedure. Suppose wish change edge select from positive (low going high) negative (high going low) Port where previously been enabled input interrupt. program would follows: RBIT WKEN SBIT WKEDG RBIT WKPND SB1T WKEN port bits have been used outputs then changed inputs with Multi-Input Wake Up/lnterrupt, safety procedure should also followed avoid wakeup conditions. After selected port bits have been changed from output input before associated WKEN bits enabled, associated edge select bits WKEDG should reset desired edge selects, followed associated WKPND bits being cleared, This same procedure should used following reset, since port inputs left floating result reset. occurrence selected trigger condition Multi-Input Wake latched into pending register called WKPND. respective bits WKPND register will occurrence selected trigger edge corresponding Port pin. user responsibility clearing these pending flags. Since WKPND pending register occurrence selected wake conditions, device will enter HALT mode Wake both enabled pending. Consequently, user must clear pending flags before attempting enter HALT mode. WKEN, WKPND WKEDG read/write registers, cleared reset. PORT INTERRUPTS Port provides user with additional eight fully selectable, edge sensitive interrupts which vectored into same service subroutine.
interrupt from Port shares logic with wake circuitry. register WKEN allows interrupts from Port individually enabled disabled. register WKEDG specifies trigger condition either positive negative edge. Finally, register WKPND latches pending trigger conditions. (Global Interrupt Enable) enables interrupt function. control flag, LPEN, functions global interrupt enable Port interrupts. Setting LPEN flag will enable interrupts vice versa. separate global pending flag needed since register WKPND adequate. Since Port also used waking device HALT lDLE modes, user elect exit HALT IDLE modes either with without interrupt enabled. elects disable interrupt, then device will restart execution from instruction immediately following instruction that placed microcontroller HALT IDLE modes. other case, device will first execute interrupt service routine then revert normal operation. (See HALT MODE clock option wake information.)
UART
device contains full-duplex software programmable UART. UART (Figure consists transmit shift register, receive shift register seven addressable registers, follows: transmit buffer register (TBUF), receiver buffer register (RBUF), UART control status register (ENU), UART receive control status register (ENUR), UART interrupt clock source register (ENUI), prescaler select register (PSR) baud (BAUD) register. register contains flags transmit receive functions; this register also determines length data frame bits), value ninth transmission, parity selection bits. ENUR register flags framing, data overrun parity errors while UART receiving. Other functions ENUR register include saving ninth received data frame, enabling disabling UART's attention mode operation providing additional receiver/transmitter status information RCVG XMTG bits. determination internal external clock source done ENUI register, well selecting number stop bits enabling disabling transmit receive interrupts. control flag this register also select UART mode operation: asynchronous synchronous.
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UART
(Continued)
DS012065-16
FIGURE UART Block Diagram UART CONTROL STATUS REGISTERS operation UART programmed through three registers: ENU, ENUR ENUI. function individual bits these registers follows: ENU-UART Control Status Register (Address 0BA)
PSEL1 XBIT9/ PSEL0 CHL1 CHL0 RBFL TBMT
DESCRIPTION UART REGISTER BITS UART CONTROL STATUS REGISTER TBMT: This when UART transfers byte data from TBUF register into TSFT register transmission. automatically reset when software writes into TBUF register. RBFL: This when UART received complete character copied into RBUF register. automatically reset when software reads character from RBUF. ERR: This global UART error flag which gets combination errors (DOE, occur. CHL1, CHL0: These bits select character frame format. Parity included generated/verified hardware. CHL1 CHL0 frame contains eight data bits. CHL1 CHL0 frame continues seven data bits. CHL1 CHL0 frame continues nine data bits. CHL1 CHL0 Loopback Mode selected. Transmitter output internally looped back receiver input. Nine framing format used. XBIT9/PSEL0: Programs ninth transmission when UART operating with nine data bits frame. seven eight data bits frame, this conjunction with PSEL1 selects parity. PSEL1, PSEL0: Parity select bits. PSEL1 PSEL0 Parity Parity enabled) PSEL1 PSEL1 Parity Parity enabled) PSEL1 PSEL0 Mark(1) Parity enabled) PSEL1 PSEL1 Space(0) Parity enabled)
ENUR-UART Receive Control Status Register (Address 0BB)
SPARE 0RW* RBlT9 ATTN XMTG RCVG
ENUI-UART Interrupt Clock Source Register (Address 0BC)
STP2 STP78 ETDX SSEL XRCLK XTCLK
used. cleared reset. reset. read-only; cannot written software. read/write. cleared read; when read software one, cleared automatically. Writing does affect state.
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UART
(Continued)
PEN: This enables/disables Parity 8-bit modes only). Parity disabled. Parity enabled.
simulate line break generation, software should reset ETDX output logic zero through Port data configuration registers. STP78: This program last Stop 7/8th length. STP2: This programs number Stop bits transmitted. STP2 Stop transmitted. STP2 Stop bits transmitted.
ENUR UART RECEIVE CONTROL STATUS REGISTER RCVG: This high whenever framing error occurs goes when goes high. XMTG: This indicate that UART transmitting. gets reset last frame (end last Stop bit). ATTN: ATTENTION Mode enabled while this set. This cleared automatically receiving character with data nine set. RBIT9: Contains ninth data received when UART operating with nine data bits frame. SPARE: Reserved future use. Flags Parity Error. Indicates Parity Error been detected since last time ENUR register read. Indicates occurrence Parity Error. Flags Framing Error. Indicates Framing Error been detected since last time ENUR register read. Indicates occurrence Framing Error. DOE: Flags Data Overrun Error. Indicates Data Overrun Error been detected since last time ENUR register read. Indicates occurrence Data Overrun Error. ENUI UART INTERRUPT CLOCK SOURCE REGISTER ETI: This enables/disables interrupt from transmitter section. Interrupt from transmitter disabled. Interrupt from transmitter enabled. ERI: This enables/disables interrupt from receiver section. Interrupt from receiver disabled. Interrupt from receiver enabled. XTCLK: This selects clock source transmitter section. XTCLK clock source selected through BAUD registers. XTCLK Signal (L1) used clock. XRCLK: This selects clock source receiver section. XRCLK clock source selected through BAUD registers. XRCLK Signal (L1) used clock. SSEL: UART mode select. SSEL Asynchronous Mode. SSEL Synchronous Mode. ETDX: (UART Transmit Pin) alternate function assigned Port selected setting ETDX bit.
Associated Pins
Data transmitted received pin. alternate function assigned Port selected setting ETDX ENUI register) one. inherent function Port requiring setup. baud rate clock UART generated on-chip, taken from external source. Port (CKX) external clock pin. either input output, determined Port Configuration Data registers (Bit input, accepts clock signal which selected drive transmitter and/or receiver. output, presents internal Baud Rate Generator output.
UART Operation
UART modes operation: asynchronous mode synchronous mode. ASYNCHRONOUS MODE This mode selected resetting SSEL ENUI register) zero. input frequency UART times baud rate. TSFT TBUF registers double-buffer data transmission. While TSFT shifting current character pin, TBUF register loaded software with next byte transmitted. When TSFT finishes transmitting current character contents TBUF transferred TSFT register Transmit Buffer Empty Flag (TBMT register) set. TBMT flag automatically reset UART when software loads character into TBUF register. There also XMTG which indicate that UART transmitting. This gets reset last frame (end last Stop bit). TBUF read/write register. RSFT RBUF registers double-buffer data being received. UART receiver continually monitors signal level detect beginning Start bit. Upon sensing this level, waits half time samples again. still low, receiver considers this valid Start bit, remaining bits character frame each sampled single time, mid-bit position. Serial data input shifted into RSFT register. Upon receiving complete character, contents RSFT register copied into RBUF register Received Buffer Full Flag (RBFL) set. RBFL automatically reset when software reads character from RBUF register. RBUF read only register. There also RCVG which high when framing error occurs goes once goes high. TBMT, XMTG, RBFL RCVG read only bits.
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UART Operation
SYNCHRONOUS MODE
(Continued)
this mode data transferred synchronously with clock. Data transmitted rising edge received falling edge synchronous clock. This mode selected setting SSEL ENUI register. input frequency UART same baud rate. When external clock input selected pin, data transmit receive performed synchronously with this clock through TDX/RDX pins. data transmit receive selected with clock output, device generates synchronous clock output pin. internal baud rate generator used produce synchronous clock. Data transmit receive performed synchronously with this clock. FRAMING FORMATS UART supports several serial framing formats (Figure 15). format selected using control bits ENU, ENUR ENUI registers.
first format (1,1a, data transmission (CHL0 CHL1 consists Start bit, seven Data bits (excluding parity) 7/8, Stop bits. applications using parity, parity generated verified hardware. second format (CHL0 CHL1 consists Start bit, eight Data bits (excluding parity) 7/8, Stop bits. Parity generated verified hardware. third format transmission (CHL0 CHL1 consists Start bit, nine Data bits 7/8, Stop bits. This format also supports UART "ATTENTION" feature. When operating this format, eight bits TBUF RBUF used data. ninth data transmitted received using bits ENUR registers, called XBIT9 RBIT9. RBIT9 read only bit. Parity generated verified this mode.
DS012065-17
FIGURE Framing Formats above framing formats, last Stop programmed 7/8th length. Stop bits selected 7/8th (selected), second Stop will 7/8th length. parity enabled/disabled located register. Parity selected 8-bit modes only. parwww.national.com
enabled (PEN parity selection then performed PSEL0 PSEL1 bits located register. Note that XBIT9/PSEL0 located register serves mutually exclusive functions. This programs ninth transmission when UART operating
COP888GW
UART Operation
(Continued)
with nine data bits frame. There parity selection this framing format. other framing formats XBIT9 needed PSEL0 used conjunction with PSEL1 select parity. frame formats receiver differ from transmitter number Stop bits required. receiver only requires Stop frame, regardless setting Stop selection bits control register. Note that implicit assumption made full duplex UART operation that framing formats same transmitter receiver. UART INTERRUPTS UART capable generating interrupts. Interrupts generated Receive Buffer Full Transmit Buffer Empty. Both interrupts have individual interrupt vectors. bytes program memory space reserved each interrupt vector. vectors located addresses 0xEC 0xEF program memory space. interrupts individually enabled disabled using Enable Transmit Interrupt (ETl) Enable Receive Interrupt (ERl) bits ENUI register.
interrupt from Transmitter pending, remains pending, long both TBMT bits set. remove this interrupt, software must either clear write TBUF register (thus clearing TBMT bit). interrupt from receiver pending, remains pending, long both RBFL bits set. remove this interrupt, software must either clear read from RBUF register (thus clearing RBFL bit).
Baud Clock Generation
clock inputs transmitter receiver sections UART individually selected come either from external source (port from source selected BAUD registers. Internally, basic baud clock created from oscillator frequency through two-stage divider chain consisting 1-16 (increments 0.5) prescaler 11-bit binary counter (Figure 16). divide factors specified through read/write registers shown Figure Note that 11-bit Baud Rate Divisor spills over into Prescaler Select Register (PSR). cleared upon reset.
DS012065-18
FIGURE UART BAUD Clock Generation
DS012065-19
FIGURE UART BAUD Clock Divisor Registers
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Baud Clock Generation
(Continued)
TABLE Prescaler Factors Prescaler Select 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Prescaler Factor CLOCK 10.5 11.5 12.5 13.5 14.5 15.5
shown Table Prescaler Factor corresponds CLOCK. This condition UART power down mode where UART clock turned power saving purpose. user must also turn UART clock when different baud rate chosen. correspondences between 5-bit Prescaler Select Prescaler factors shown Table There many ways calculate divisor factors, particularly effective method would achieve 1.8432 frequency coming first stage. 1.8432 prescaler output then used drive software programmable baud rate counter create clock following baud rates: 110, 134.5, 150, 300, 600, 1200, 1800, 2400, 3600, 4800, 7200, 9600, 19200 38400 (Table Other baud rates created using appropriate divisors. clock then divided provide rate serial shift registers transmitter receivers. TABLE Baud Rate Divisors (1.8432 PrescaIer Output) Baud Rate (110.03) 134.5 (134.58) 1200 1800 2400 3600 4800 7200 9600 19200 38400 Baud Rate Divisor (N-1) 1046
Note entries Table assume prescaIer output 1.8432 MHz. asynchronous mode baud rate could high 625k.
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Baud Clock Generation
4.608/1.8432
(Continued)
example, considering Asynchronous Mode clock 4.608 MHz, prescaler factor selected entry available Table 1.8432 prescaler output then used with proper Baud Rate Divisor (Table obtain different baud rates. baud rate 19200 e.g., entry Table value from Table Baud Rate Divisor) Baud Rate 1.8432 MHz/(16 19200 divide performed because asynchronous mode, input frequency UART times baud rate. equation calculate baud rates given below. actual Baud Rate found from: Fc/(16 Where: Baud Rate frequency Baud Rate Divisor (Table Prescaler Divide Factor selected value Prescaler Select Register (Table
Note: Synchronous Mode, divisor replaced two.
idle timer (T0) generates fixed (256 delay ensure that oscillator indeed stabilized before allowing device execute code. user consider this delay when data transfer expected immediately after exiting HALT mode.
Diagnostic
Bits CHARL0 CHARL1 register provide Ioopback feature diagnostic testing UART. When these bits one, following occur: receiver input (RDX) internally connected transmitter output (TDX); output Transmitter Shift Register "looped back" into Receive Shift Register input. this mode, data that transmitted immediately received. This feature allows processor verify transmit receive data paths UART. Note that framing format this mode nine format; Start bit, nine data bits, 7/8, Stop bits. Parity generated verified this mode.
Attention Mode
UART Receiver section supports alternate mode operation, referred ATTENTION Mode. This mode operation selected ATTN ENUR register. data format transmission must also selected having nine Data bits either 7/8, Stop bits. ATTENTION mode operation intended networking device with other processors. Typically such environments messages consists device addresses, indicating which several destinations should receive them, actual data. This Mode supports scheme which addresses flagged having ninth data field ninth reset zero byte Data byte. While ATTENTION mode, UART monitors communication flow, ignores characters until address character received. Upon receiving address character, UART signals that character ready setting RBFL flag, which turn interrupts processor UART Receiver interrupts enabled. ATTN also cleared automatically this point, that data characters well address characters recognized. Software examines contents RBUF responds deciding either accept subsequent data stream leaving ATTN reset) wait until next address character seen setting ATTN again). Operation UART Transmitter affected selection this Mode. value ninth transmitted programmed setting XBIT9 appropriately. value ninth received obtained reading RBIT9. Since this located ENUR register where error flags reside, operation will reset error flags.
Example: Asynchronous Mode: Crystal Frequency Desired baud rate 9600 Using above equation calculated first. 106)/(16 9600) 32.552 32.552 divided each Prescaler Factor (Table obtain value closest integer. This factor happens 6.5). 32.552/6.5 5.008 programmed value (from Table should Using above values calculated 106)/(16 6.5) 9615.384 error (9615.385 9600)/9600 0.16
Effect HALT/IDLE
UART logic reinitialized when either HALT IDLE modes entered. This reinitialization sets TBMT flag resets read only bits UART control status registers. Read/Write bits remain unchanged. Transmit Buffer (TBUF) affected, Transmit Shift register (TSFT) bits one. receiver registers RBUF RSFT affected. device will exit from HALT/IDLE modes when Start character detected (L3) pin. This feature obtained using Multi-Input Wakeup scheme provided device. Before entering HALT IDLE modes user program must select Wakeup source pin. This selection done setting WKEN (Wakeup Enable) register. Wakeup trigger condition then selected high transition. This done WKEDG register (Bit "one"). device halted crystal oscillator used, Wake signal will start chip running immediately because finite start time requirement crystal oscillator.
Interrupts
devices supports vectored interrupt scheme. supports total fourteen interrupt sources. Table lists possible device interrupt sources, their arbitration rankings memory locations reserved interrupt vector each source. bytes program memory space reserved each interrupt source. interrupt sources except software interrupt maskable. Each maskable interrupts have Enable more Pending bits. maskable interrupt active associated enable pending bits
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Interrupts
(Continued)
set. interrupt active, then processor will interrupted soon ready start executing instruction except above conditions happen during Software Trap service routine. This exception described Software Trap sub-section. interruption process accomplished with INTR instruction (opcode 00), which jammed inside Instruction Register replaces opcode about executed. following steps performed every interrupt: (Global Interrupt Enable) reset. address instruction about executed pushed into stack. (Program Counter) branches address 00FF. This procedure takes cycles execute. this time, since other maskable interrupts disabled. user free whatever context switching required saving context machine stack with PUSH instructions. user would then program (Vector Interrupt Select) instruction order branch interrupt service routine highest priority interrupt enabled pending time VIS. Note that this necessarily interrupt that caused branch address location 00FF prior context switching.
Thus, interrupt with higher rank than which caused interruption becomes active before decision which interrupt service made VIS, then interrupt with higher rank will override lower ones will acknowledged. lower priority interrupt(s) still pending, however, will cause another interrupt immediately following completion interrupt service routine associated with higher priority interrupt just serviced. This lower priority interrupt will occur immediately following RETI (Return from Interrupt) instruction interrupt service routine just completed. Inside interrupt service routine, associated pending cleared software. RETI (Return from Interrupt) instruction interrupt service routine will (Global Interrupt Enable) bit, allowing processor interrupted again another interrupt active pending. instruction looks active interrupts time executed performs indirect jump beginning service routine with highest rank. addresses different interrupt service routines, called vectors, chosen user stored table starting 01E0 (assuming that located between 00FF 01DF). vectors 15-bit wide therefore occupy locations.
TABLE Interrupt Vector Table ARBITRATION RANKING Highest (10) (11) (12) (13) (14) (15) (16) Lowest Software Reserved External Timer Timer Timer Microwire/PIus Counters UART UART Timer Timer Capture Timer Unused Port L/Wakeup Default Reserved Receive Transmit T2A/Underflow Underflow T1A/Underflow Busy SOURCE DESCRIPTION VECTOR (Note ADDRESS (Hi-Low Byte) 0yFE-0yFF 0yFC-0yFD 0yFA-0yFB 0yF8-0yF9 0yF6-0yF7 0yF4-0yF5 0yF2-0yF3 0yF0-0yF1 0yEE-0yEF 0yEC-0yED 0yEA-0yEB 0yE8-0yE9 0yE6-0yE7 0yE4-0yE5 0yE2-0yE3 0yE0-0yE1
Note variable which represents block. vector table must located same 256-byte block except located last address block, this case, table must next block.
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Interrupts
(Continued)
vector table must located same 256-byte block (0y00 0yFF) except located last address block. this case, table must next block. vector table cannot inserted first 256-byte block vector maskable interrupt with lowest rank located 0yE0 (Hi-Order byte) 0yE1 (Lo-Order byte) forth increasing rank number. vector maskable interrupt with highest rank located 0yFA (Hi-Order byte) 0yFB (Lo-Order byte). Software Trap highest rank vector located 0yFE 0yFF. accident, gets executed interrupt active, then (Program Counter) will branch vector located 0yE0-0yE1. Warning: Default interrupt handler routine must present. minimum, this handler should confirm that cleared (this indicates that interrupt sequence been taken), take care required housekeeping, restore context return. Some sort Warm Restart procedure should implemented. These events occur without error part system designer programmer.
Note: There always possibility interrupt occurring during instruction which attempting reset other interrupt enable bit. this occurs when single cycle instruction being used
reset interrupt enable bit, interrupt enable will reset interrupt still occur. This because interrupt processing started same time interrupt being reset. avoid this scenario, user should always two-, three- four-cycle instruction reset interrupt enable bits.
Figure shows Interrupt block diagram.
SOFTWARE TRAP Software Trap (ST) special kind non-maskable interrupt which occurs when INTR instruction (used acknowledge interrupts) fetched from placed inside instruction register. This happen when pointing beyond available address space when stack over-popped. When occurs, user re-initialize stack pointer recovery procedure (similar reset, necessarily containing same initialization procedures) before restarting. occurrence latched into pending bit. affected pending (not accessible user) used inhibit other interrupts direct program service routine with instruction. RPND instruction used clear software interrupt pending bit. This pending also cleared reset. highest rank among interrupts. Nothing (except another interrupt being serviced.
DS012065-20
FIGURE Interrupt Block Diagram
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COP888GW
Detection Illegal Conditions
device detect various illegal conditions resulting from coding errors, transient noise, power supply voltage drops, runaway programs, etc. Reading undefined gets zeroes. opcode software interrupt program fetches instructions from undefined ROM, this will force software interrupt, thus signaling that illegal condition occurred. subroutine stack grows down each call (jump subroutine), interrupt, PUSH, grows each return POP. stack pointer initialized location during reset. Consequently, there more returns than calls, stack pointer will point addresses (which undefined RAM). Undefined from addresses (Segment (Segment other segments (i.e., Segments etc.) read 1's, which turn will cause program return address 7FFF Hex. This undefined location instruction fetched (all 0's) from this location will generate software interrupt signaling illegal condition. Thus, chip detect following illegal conditions: Executing from undefined Over "POP"ing stack having more returns than calls. When software interrupt occurs, user re-initialize stack pointer recovery procedure before restarting (this recovery program probably similar that following reset, might contain same program initialization procedures). recovery program should reset software interrupt pending using RPND instruction.
vice interface with National Semiconductor's MICROWIRE peripherals (i.e., converters, display drivers, E2PROMs etc.) with other microcontrollers which support MICROWIRE interface. consists 8-bit serial shift register (SIO) with serial data input (SI), serial data output (SO) serial shift clock (SK). Figure shows block diagram MICROWIRE/PLUS logic. shift clock selected from either internal source external source. Operating MlCROWIRE/PLUS arrangement with internal clock source called Master mode operation. Similarly, operating MICROWIRE/ PLUS arrangement with external shift clock called Slave mode operation. CNTRL register used configure control MICROWIRE/PLUS mode. MICROWIRE/PLUS, MSEL CNTRL register one. master mode, clock rate selected bits, SL1, CNTRL register. Table details different clock rates that selected. TABLE MICROWIRE/PLUS Master Mode Clock Select Period
Where instruction cycle clock
MICROWIRE/PLUS
MICROWIRE/PLUS serial synchronous communications interface. MICROWIRE/PLUS capability enables
DS012065-21
FIGURE MICROWIRE/PLUS Block Diagram
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COP888GW
MICROWIRE/PLUS
(Continued)
TABLE MICROWIRE Mode Settings
(SO) Config. (SK) Config. Fun. TRISTATE TRlSTATE Fun. Int. Int. Ext. Ext. MICROWIRE/PLUS Master MICROWlRE/PLUS Master MlCROWlRE/PLUS Slave MICROWlRE/PLUS Slave Operation
MICROWIRE/PLUS OPERATION Setting BUSY register causes MICROWIRE/PLUS start shifting data. gets reset when eight data bits have been shifted. user reset BUSY software allow less than bits shift. enabled, interrupt generated when eight data bits have been shifted. device enter MICROWIRE/PLUS mode either Master Slave. Figure shows devices, microcontrollers several peripherals interconnected using MICROWIRE/PLUS arrangements. Warning: register should only loaded when clock low. Loading register while clock high will resuIt undefined data register. clock normally when shifting. Setting BUSY flag when input clock high MICROWIRE/PLUS slave mode cause current clock shift register narrow. safety, BUSY flag should only when input clock low. MICROWIRE/PLUS Master Mode Operation MICROWIRE/PLUS Master mode operation shift clock (SK) generated internally device. MICROWIRE Master always initiates data exchanges. MSEL CNTRL register must enable functions onto Port. pins must also selected outputs setting appropriate bits Port configuration register. Table VIII summarizes settings required Master mode operation. MICROWIRE/PLUS Slave Mode Operation MICROWIRE/PLUS Slave mode operation clock generated external source. Setting MSEL CNTRL register enables functions onto Port. must selected input selected output setting resetting appropriate bits Port configuration register. Table VIII summarizes settings required enter Slave mode operation.
This table assumes that control flag MSEL set. user must BUSY flag immediately upon entering Slave mode. This will ensure that data bits sent Master will shifted properly. After eight clock pulses BUSY flag will cleared sequence repeated. Alternate Phase Operation device allows either normal clock alternate phase clock shift data register. both modes normally low. normal mode data shifted rising edge clock data shifted falling edge clock. register shifted each falling edge clock. alternate phase operation, data shifted falling edge clock shifted rising edge clock. control flag, SKSEL, allows either normal clock alternate clock selected. Resetting SKSEL causes MICROWIRE/PLUS logic clocked from normal signal. Setting SKSEL flag selects alternate clock. SKSEL mapped into configuration bit. SKSEL flag will power reset condition, selecting normal signal.
DS012065-22
FIGURE MICROWIRE/PLUS Application
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COP888GW
Memory
RAM, ports registers (except mapped into data memory address space. ADDRESS S/ADD 0000 006F 0070 007F xx80 xx8F xx90 xx91 xx92 xx93 xx94 xx95 xx96 xx97 xx98 xx99 xx9A xx9B xx9C xx9D xx9E xx9F xxA0 xxA1 xxA2 xxA3 xxA4 xxA5 xxA6 xxA7 xxA8 xxA9 xxAA xxAB xxAC xxAD xxAE xxAF xxB0 xxB1 xxB2 xxB3 xxB4 xxB5 xxB6 xxB7 xxB8 xxB9 On-Chip Bytes Unused Address Space (reads 1's) Unused Address Space (reads undefined data) Port Data Register Port Configuration Register Port Input Pins (read only) Reserved Port Data Register Port Configuration Register Port Input Pins (read only) Reserved Dividend Result Byte (MDR1) Dividend/Multiplier Result Byte (MDR2) Dividend/Result Byte Undefined (MDR3) Divisor/Multiplicand Result Byte (MDR4) Divisor Multiplicand Byte(MDR5) MuItiply/Divide Control Register (MDCR) Counter Control Register (CCR1) Counter Control Register (CCR2) Counter Prescaler Lower Byte (C1PRL) Counter Prescaler Upper Byte (C1PRH) Counter Count Register Lower Byte (C1CTL) Counter Count Register Upper Byte (C1CTH) Counter Prescaler Lower Byte (C2PRL) Counter Prescaler Upper Byte (C2PRH) Counter Count Register Lower Byte (C2CTL) Counter Count Register Upper Byte (C2CTH) Counter Prescaler Lower Byte (C3PRL) Counter Prescaler Upper Byte (C3PRH) Counter Count Register Lower Byte (C3CTL) Counter Count Register Upper Byte (C3CTH) Counter Prescaler Lower Byte (C4PRL) Counter Prescaler Upper Byte (C4PRH) Counter Count Register Lower Byte (C4CTL) Counter Count Register Upper Byte (C4CTH) Capture Timer Prescaler Register (CM1 PSC) Capture Timer Lower Byte (CM1CRL) Read-Only Capture Timer Upper Byte (CM1CRH) Read-Only Capture Timer Prescaler Register (CM2PSC) Capture Timer Lower Byte (CM2CRL) Read-Only Capture Timer Upper Byte (CM2CRH) Read-Only Capture Timer Control Register (CCMR1) Capture Timer Control Register (CCMR2) UART Transmit Buffer (TBUF) UART Receive Buffer (RBUF) CONTENTS
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COP888GW
Memory
(Continued) ADDRESS S/ADD CONTENTS UART Control Status Register (ENU) UART Receive Control Status Register (ENUR) UART Interrupt Clock Source Register (ENUI) UART Baud Register (BAUD) UART Prescaler Select Register (PSR) Reserved UART Timer Lower Byte Timer Upper Byte Timer Autoload Register T2RA Lower Byte Timer Autoload Register T2RA Upper Byte Timer Autoload Register T2RB Lower Byte Timer Autoload Register T2RB Upper Byte Timer Control Register Reserved MIWU Edge Select Register (WKEDG) MlWU Enable Register (WKEN) MlWU Pending Register (WKPND) Reserved Reserved Reserved Port Data Register Port Configuration Register Port Input Pins (Read Only) Reserved Port Port Data Register Port Configuration Register Port Input Pins (Read Only) Port Input Pins (Read Only) Port Data Register Port Configuration Register Port Input Pins (Read Only) Reserved Port Port Reserved Port Reserved Control Registers Timer Autoload Register T1RB Lower Byte Timer Autoload Register T1RB Upper Byte ICNTRL Register MICROWIRE Shift Register Timer Lower Byte Timer Upper Byte Timer Autoload Register T1RA Lower Byte Timer Autoload Register T1RA Upper Byte CNTRL Control Register Register On-chip Mapped Registers Register Register
xxBA xxBB xxBC xxBD xxBE xxBF xxC0 xxC1 xxC2 xxC3 xxC4 xxC5 xxC6 xxC7 xxC8 xxC9 xxCA xxCB xxCC xxCD xxCF xxD0 xxD1 xxD2 xxD3 xxD4 xxD5 xxD6 xxD7 xxD8 xxD9 xxDA xxDB xxDC xxDD xxDF xxE0 xxE5 xxE6 xxE7 xxE8 xxE9 xxEA xxEB xxEC xxED xxEE xxEF xxF0 xxFB xxFC xxFD
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COP888GW
Memory
(Continued) ADDRESS S/ADD CONTENTS Register Register Chip Bytes (384 Bytes)
xxFE xxFF 0100 017F 0200 027F 0300 037F
Reading memory locations 0070H-007FH (Segment will return ones. Reading unused memory locations between 0080H-00F0 (Segment will return undefined data. Reading memory locations from other segments (i.e., segment segment etc.) will return ones.
ADDRESSING MODES There addressing modes, operand addressing four transfer control. OPERAND ADDRESSING MODES Register Indirect This "normal" addressing mode. operand data memory addressed pointer pointer. Register Indirect (with auto post Increment decrement pointer) This addressing mode used with instructions. operand data memory addressed pointer pointer. This register indirect mode that automatically post increments decrements register after executing instruction. Direct instruction contains 8-bit address field that directly points data memory operand. ImmedIate instruction contains 8-bit immediate field operand. Short Immediate This addressing mode used with Load Immediate instruction. instruction contains 4-bit immediate field operand. Indirect This addressing mode used with LAID instruction. contents accumuiator used partial address (lower bits accessing data operand from program memory. TRANSFER CONTROL ADDRESSING MODES Relative This mode used instruction, with instruction field being added program counter program location. range from allow 1-byte relative jump implemented instruction). There "pages" when using since bits used. Absolute This mode used with instructions, with instruction field bits replacing lower bits program counter (PC). This allows jumping location current program memory segment.
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Absolute Long This mode used with JMPL JSRL instructions, with instruction field bits replacing entire bits program counter (PC). This allows jumping location program memory space. Indirect This mode used with instruction. contents accumulator used partial address (lower bits accessing location program memory. contents this program memory location serve partial address (lower bits jump next instruction.
Note: special case Indirect Transfer Control addressing mode, where double byte vector associated with interrupt transferred from adjacent addresses program memory into program counter (PC) order jump associated interrupt service routine.
Instruction
Register Symbol Definition Registers 8-Bit Accumulator Register 8-Bit Address Register 8-Bit Address Register 8-Bit Stack Pointer Register 15-Bit Program Counter Register Upper Bits Lower Bits Register Carry Register Half Carry Register Global Interrupt Enable Interrupt Vector Upper Byte Interrupt Vector Lower Byte
COP888GW
Instruction
Meml
(Continued) Symbols
Symbols 8-Bit Immediate Data Register Memory: Addresses (Includes Number Loaded with Exchanged with
Memory Indirectly Addressed Register Memory Indirectly Addressed Register Direct Addressed Memory Direct Addressed Memory Direct Addressed Memory Immediate Data
INSTRUCTION SUBC ANDSZ IFEQ IFEQ IFNE IFGT lFBNE DRSZ SBIT RBIT lFBIT RPND LAID DCOR SWAP A,Mem A,[X] A,Meml A,[X] Mem, Reg, ],lmm A,MemI A,Meml A,Meml A,Meml A,lmm A,Meml A,Meml MD,lmm A,Meml A,Meml A,Meml with Carry Subtract with Carry Logical Logical lmmed., Skip Zero Logical Logical EXclusive EQual EQual Equal Greater Than Equal Decrement Reg., Skip Zero Reset Reset PeNDing Flag EXchange with Memory EXchange with Memory LoaD with Memory LoaD with Memory LoaD with Immed. LoaD Memory Immed. LoaD Register Memory Immed. EXchange with Memory EXchange with Memory LoaD with Memory LoaD with Memory LoaD Memory lmmed. CLeaR INCrement DECrement Load InDirect from Decimal CORrect Rotate Right thru Rotate Left thru SWAP nibbles Reset
MemI MemI Carry, Half Carry MemI Carry, Half Carry MemI Skip next Imm) MemI MemI Compare lmm, next Compare Meml, next Meml Compare Meml, next Meml Compare Meml, next Meml next lower bits RegReg Skip bit, (bit immediate) bit, true next instruction Reset Software Interrupt Pending Flag AMem A[X] MemI A[X] MemImm RegImm A[B], A[X], [B], [X], [B]Imm, (PU, ABCD correction (follows ADC, SUBC) A7.A4A3.A0 true, next instruction
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#,Mem #,Mem #,Mem
COP888GW
Instruction
IFNC PUSH JMPL JSRL RETSK RETI INTR Addr. Addr. Disp. Addr. Addr
(Continued) true, next instruction [SP] [SP] [VU], [VL] PCii bits, 32k) PC9.0 bits) PCPC +32, except [SP] [SP] PC9.0 (PU, [SP], [SP], skip next instruction [SP], [SP]
stack into PUSH onto stack Vector Interrupt Service Routine Jump absolute Long Jump absolute Jump relative short Jump SubRoutine Long Jump SubRoutine Jump InDirect RETurn from subroutine RETurn SKip RETurn from Interrupt Generate Interrupt OPeration
Instruction Execution Time
Most instructions single byte (with immediate addressing mode instructions taking bytes). Most single byte instructions take cycle time execute. Skipped instructions require number cycles skipped, where equals number bytes skipped instruction opcode. BYTES CYCLES INSTRUCTION table details. Bytes Cycles InstructIon following table shows number bytes cycles each instruction format byte/cycle. Arithmetic Logic Instructions SUBC IFEQ IFGT IFBNE DRSZ SBIT RBIT lFBIT RPND Direct Immed. Instructions Using CLRA INCA DECA LAID DCORA RRCA RLCA SWAPA IFNC PUSHA POPA ANDSZ
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COP888GW
Instruction Execution Time
Transfer Control Instructions
(Continued)
JMPL JSRL RETSK RETI INTR Memory Transfer Instructions Register Indirect (Note (Note Mem, Reg, IFEQ
Note
Direct
Immed.
Register Indirect Auto Incr. Decr. [B+, [X+,
Memory location addressed directly.
Mask Options
mask programmable options shown below. options programmed same time pattern submission. OPTION CLOCK CONFIGURATION Crystal Oscillator (CKI/10) (CKO) clock generator output crystal/resonator with being clock input OPTION HALT Enable HALT mode Disable HALT mode OPTION BONDING OPTIONS Pins PLCC chip driven clock input input which between MHz. output clock clock option been selected). input frequency divided down produce instruction cycle clock (1/tc).
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COP888GW
Opcode Table
Upper Nibble DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ
IFNE A,[B] A,[X+] A,[X-] Md,#i A,[X] A,[B] JSRL A,Md [B],#i B,#i JMPL A,Md POPA RETSK RETI A,[B-] [B-],#i DECA A,[B+] [B+],#i INCA SBIT 2,[B] SBIT 3,[B] SBIT 4,[B] SBIT 5,[B] SBIT 6,[B] SBIT 7,[B]
IFEQ Md,#i
IFNE A,#i
SBIT 1,[B]
RBIT 1,[B] RBIT 2,[B] RBIT 3,[B] RBIT 4,[B] RBIT 5,[B] RBIT 6,[B] RBIT 7,[B]
x900-x9FF IFBNE IFBNE IFBNE IFBNE IFBNE IFBNE
x900-x9FF
JP-5
JP-21
0FA,#i
JP+27 xA00-xAFF xA00-xAFF JP+28 xB00-xBFF xB00-xBFF JP+29 xC00-xCFF xC00-xCFF JP+30 xD00-xDFF xD00-xDFF JP+31 xE00-xEFF xE00-xEFF xF00-xFFF xF00-xFFF JP+32
JP+11 JP+12
JP+13 JP+14 JP+15 JP+16
JP-4
JP-20
0FB,#i
JP-3
JP-19
0FC,#i
JP-2
JP-18
0FD,#i
JP-1
JP-17
0FE,#i
JP-0
JP-16
0FF,#i
where, immediate data directly addressed memory location unused opcode
Lower Nibble RBIT 0,[B] IFBNE IFBNE x800-x8FF x800-x8FF JP+25 JP+26 JP+9 JP+10
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RRCA A,[B+] A,[B-] LAID A,[B] A,#i IFNC SBIT 0,[B] A,[B] IFBIT PUSHA 7,[B] A,#i A,[B] IFBIT DCORA 6,[B] IFBNE IFBNE A,#i A,[B] IFBIT SWAPA 5,[B] B,#0A IFBNE A,#i A,[B] IFBIT 4,[B] CLRA B,#0B IFBNE x400-x4FF x500-x5FF x600-x6FF x700-x7FF IFGT A,#i IFGT A,[B] B,0C IFBNE x300-x3FF IFBIT 3,[B]
SUBC A,#i IFEQ A,#i IFEQ A,[B] B,0D IFBNE x200-x2FF IFBIT 2,[B]
A,#i SUBC A,[B] B,0E x200-x2FF x300-x3FF x400-x4FF x500-x5FF x600-x6FF x700-x7FF IFBNE x100-x1FF x100-x1FF IFBIT 1,[B]
A,[B] IFBIT ANDSZ 0,[B] A,#i B,0F IFBNE x000-x0FF x000-x0FF JP+17 JP+18 JP+19 JP+20 JP+21 JP+22 JP+23 JP+24
INTR JP+2 JP+3 JP+4 JP+5 JP+6 JP+7 JP+8
JP-15
JP-31
0F0,
JP-14 A,[X+] A,[X-] RPND A,[X]
JP-30
0F1,#i
JP-13
JP-29
0F2,#i
JP-12
JP-28
0F3,#i
Note: opcode also opcode IFBIT,#iA.
JP-11
JP-27
0F4,#i
JP-10
JP-26
0F5,#i
JP-9
JP-25
0F6,#i
JP-8 RLCA A,#i
JP-24
0F7,#i
JP-7
JP-23
0F8,#i
JP-6
JP-22
0F9,#i
COP888GW
Development Support
SUMMARY
iceMASTER: IM-COP8/400 Full feature in-circuit emulation COP8 products. full COP8 Basic Feature Family device package specific probes available. COP8 Debug Module: Moderate cost in-circuit emulation development programming unit. COP8 Evaluation Programming Unit: EPU-COP888GG cost In-circuit simulation development programming unit. Assembler: COP8-DEV-IBMA. installable cross development Assembler, Linker, Librarian Utility Software Development Tool Kit. Compiler: COP8C. installable cross development Software Tool Kit. OTP/EPROM Programmer Support: Covering needs from engineering prototype, pilot production full production environments.
Full frame synchronous trace memory. Address, instruction, unspecified, circuit connectable trace lines. Display source (e.g., source), assembly mixed. full hardware configurable break, trace trace control, pass count increment events. Tool integrated interactive symbolic debugger supports both assembler (COFF) Compiler (.COD) linked object formats. Real time peformance profiling analysis; selectable bucket definition. Watch windows, content updated automatically each execution break. Instruction instruction memory/register changes displayed source window when single step operation. Single base unit debugger software reconfigurable support entire COP8 family; only probe personality needs change. Debugger software processor customized, reconfigured from master model file. Processor specific symbolic display registers level assignments, configured from master model file. Halt/Idle mode notification. On-line HELP customized specific processor using master model file. Includes copy COP8-DEV-IBMA assembler linker SDK.
iceMASTER (IM) IN-CIRCUIT EMULATION iceMASTER IM-COP8/400 full feature, based, in-circuit emulation tool developed marketed MetaLink Corporation support whole COP8 family products. National resale vendor these products. Figure configuration. iceMASTER IM-COP8/400 with device specific COP8 Probe provides rich feature developing, testing maintaining product:
Order Information Base Unit IM-COP8/400-1 IM-COP8/400-2 iceMASTER Probe MHW-888GW68PWPC PLCC iceMASTER base unit, 110V power supply iceMASTER base unit, 220V power supply
Real-time in-circuit emulation; full 2.4V-5.5V operation range, full DC-10 clock. Chip options programmable jumper selectable. Direct connection application board package compatible socket surface mount assembly. Full kbytes loadable programming space that overlays (replaces) on-chip EPROM. On-chip blocks used directly recreated probe necessary.
DS012065-31
FIGURE COP8 iceMASTER Environment
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COP888GW
Development Support
iceMASTER DEBUG MODULE (DM)
(Continued)
Instruction instruction memory/register changes displayed when single step operation. Debugger software processor customized, reconfigured from master model file. Processor specific symbolic display registers level assignments, configured from master model file. Halt/Idle mode notification. Programming menu supports full product line programmable EPROM COP8 products. Program data taken directly from overlay RAM. Programming PLCC PLCC parts requires external programming adapters. Includes wallmount power supply. On-board generator from input connection external supply supported. Requires VPPlevel adjustment family programming specification (correct level provided on-screen pop-down display). On-line HELP customized specific processor using master model file. Includes copy COP8-DEV-IBMA assembler linker SDK.
iceMASTER Debug Module based, combination in-circuit emulation tool COP8 based OTP/EPROM programming tool developed marketed MetaLink Corporation support whole COP8 family products. National resale vendor these products. Figure configuration. iceMASTER Debug Module moderate cost development tool. capability in-circuit emulation specific COP8 microcontroller addition serves programming tool COP8 EPROM product families. Summary features follows:
Real-time in-circuit emulation; full operating voltage range operation, full DC-10 clock. processor pins cabled application development board with package compatible cable socket surface mount assembly. Full kbytes loadable programming space that overlays (replaces) on-chip EPROM. On-chip blocks used directly recreated necessary. frames synchronous trace memory. display source source), assembly mixed. most recent history prior break available trace memory. Configured break points; uses INTR instruction which modestly intrusive. Software only supported features selectable. Tool integrated interactive symbolic debugger supports both assembler (COFF) Compiler (.COD) linked object formats.
Order Information Debug Module Unit COP8-DM/888GW Cable Adapters DM-COP8/68P PLCC
DS012065-32
FIGURE COP8-DM Environment
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COP888GW
Development Support
(Continued)
BITS data type extension. Register declaration #pragma with direct level definitions. language support interrupt routines. Expert system, rule based code generation optimization. Performs consistency checks against architectural definitions target COP8 device. Generates program memory code. Supports linking compiled object COP8 assembled object formats. Global optimization linked code. Symbolic debug load format fully source level supported MetaLink debugger.
COP8 ASSEMBLER/LINKER SOFTWARE DEVELOPMENT TOOL National Semiconductor offers relocateable COP8 macro cross assembler, linker, librarian utility software development tool kit. Features summarized follows:
Basic Feature Family instruction "device" type. Nested macro capability. Extensive assembler directives. Supported PC/DOS platform. Generates National standard COFF output files. Integrated Linker Librarian. Integrated utilities generate code file outputs. DUMPCOFF utility. This product integrated part MetaLink tools development kit, fully supported MetaLink debugger. ordered separately bundled with MetaLink products additional cost.
Order-Information Assembler COP8-DEV-IBMA Assembler installable 3.5" PC/DOS Floppy Disk Drive format. Periodic upgrades most recent version available National's Internet. COP8 COMPILER Compiler developed marketed Byte Craft Limited. COP8C compiler fully integrated development tool specifically designed support compact embedded configuration COP8 family products. Features summarized follows:
SINGLE CHIP OTP/EMULATOR SUPPORT COP8 family supported single chip emulators. detailed information refer emulator specific datasheet emulator selection table below: Emulator Ordering Information Device Number Clock Option COP87L88GWV-XE Crystal/ HALT PLCC COP888GW Package Emulates
INDUSTRY WIDE OTP/EPROM PROGRAMMING SUPPORT Programming support, addition MetaLink development tools, provided full range independent approved vendors meet needs from engineering laboratory full production.
ANSI with some restrictions extensions that optimize development COP8 embedded application.
Approved List Manufacturer Microsystems Data North America (800) 225-2102 (713) 688-4600 Fax: (713) 688-0920 (800) 426-1045 (206) 881-6444 Fax: (206) 882-1043 HI-LO Technology MetaLink (510) 623-8860 (800) 624-8949 (919) 430-7915 (800) 638-2423 (602) 926-0797 Fax: (602) 693-0681 Systems General Needhams (916) 924-8037 Fax: (916) 924-8065 (408) 263-6667 +41-1-9450300 +886-2-917-3005 Fax: +886-2-911-1283 Call Asia +44-1226-767404 Fax: 0-1226-370-434 +49-80 9156 96-0 Fax: +49-80 9123 +852-737-1800 +886-2-764-0215 Fax: +886-2-756-6403 +44-0734-440011 Call North America +49-8152-4183 +49-8856-932616 +852-234-16611 +852-2710-8121 Europe Asia
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COP888GW
Development Support
AVAILABLE LITERATURE
(Continued)
DIAL-A-HELPER Standard Modem Modem: CANADA/U.S.: EUROPE: Baud: Set-Up: (800) NSC-MICRO (800) 672-6427 (+49) 0-8141-351332 14.4k Length: 8-Bit Parity: None Stop Bit: Hours, Days
more information, please COP8 Basic Family User's Manual, Literature Number 620895, COP8 Feature Family User's Manual, Literature Number 620897 National's Family 8-bit Microcontrollers COP8 Selection Guide, Literature Number 630009. DIAL-A-HELPER SERVICE Dial-A-Helper service provided Microcontroller Applications group. Dial-A-Helper Electronic Information System that accessed Bulletin Board System (BBS) data modem, site Internet standard client application site Internet using standard Internet browser such Netscape Mosaic. Dial-A-Helper system provides access automated information storage retrieval system. system capabilities include MESSAGE SECTION (electronic mail, when accessed BBS) communications from Microcontroller Applications Group FILE SECTION which consists several file areas where valuable application software utilities could found.
Operation:
DIAL-A-HELPER nscmicro.nsc.com user: anonymous password: username @yourhost.site.domain
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COP888GW
Development Support
ftp://nscmicro.nsc.com
(Continued)
CUSTOMER RESPONSE CENTER Complete product information technical support available from National's customer response centers.
CANADA/ U.S.: EUROPE: Tel: email: email: Deutsch English Italiano JAPAN: S.E. ASIA: Tel: Beijing Shanghai Hong Kong Korea Malaysia Singapore Taiwan AUSTRALIA: INDIA: Tel: Tel: Tel: Tel: Tel: Tel: Tel: Tel: Tel: Tel: Tel: Tel: Tel: (800) 272-9959 support@tevm2.nsc.com europe.support@nsc.com 180-530 180-532 180-532 180-534 +81-043-299-2309 (+86) 10-6856-8601 (+86) 21-6415-4092 (+852) 2737-1600 (+82) 2-3771-6909 (+60-4) 644-9061 (+65) 255-2226 +886-2-521-3288 (+61) 3-9558-9999 (+91) 80-559-9467
DIAL-A-HELPER WorldWide Browser
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COP888GW 8-Bit Microcontroller with Pulse Train Generators Capture Modules
Physical Dimensions
inches (millimeters) unless otherwise noted
68-Lead Molded Plastic Chip Carrier Order Number COP888GW-XXX/V Package Number V68A
LIFE SUPPORT POLICY NATIONAL'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT GENERAL COUNSEL NATIONAL SEMICONDUCTOR CORPORATION. used herein: Life support devices systems devices systems which, intended surgical implant into body, support sustain life, whose failure perform when properly used accordance with instructions provided labeling, reasonably expected result significant injury user.
National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: 180-530 Email: europe.support@nsc.com Deutsch Tel: 9508 6208 English Tel: 2171 Tel: 8790
critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness.
National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com
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National does assume responsibility circuitry described, circuit patent licenses implied National reserves right time without notice change said circuitry specifications.
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