Distinguishing Features Programmable pulse shaper meet cross-conn
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M28335 Twelve Port T3/E3/STS-1 Line Interface Unit
Distinguishing Features
Programmable pulse shaper meet cross-connect pulse masks (ANSI T1.102-1993) SRAM-like 8-bit parallel microprocessor interface Serial Peripheral Interface (SPI) support Meets jitter tolerance jitter generation specifications Bellcore GR499, GR253, ETSI TBR24 Alarms coding violation loss signal Full diagnostic loopback capability Uses minimum external components Compliant with ITU-T G.703 ETSI TBR24 Independent power-down mode channel Easily interfaced T3/E3 framer (CX28342/3/4/6/8 CX28365) Selectable B3ZS/HDB3 encoding/decoding Superior input receiver sensitivity (<25 peak) Transmit monitor inputs faulty transmit shorted output Programmable RLOS threshold
M28335 12-channel, T3/E3/STS-1 Line Interface Unit (LIU). configured Parallel, Serial (SPI) microprocessor interface through hardware control pins. Each channel includes independent receive equalizer that requires user configuration. Additionally, each channel programmable transmit pulse shaper that ensure that transmit pulse meets pulse mask requirement digital cross-connect. M28335 achieves typical reach 1275 feet when working DS3/E3 rates, allowing designers greater margin flexibility design high performance system solutions. M28335 provides user economies scale Metro-optical Access Switch applications where STS-1 channels aggregated into OC12/OC48 connection single line card. Significant elimination external components achieved including twelve independent transceivers package. line interface reduced coupling transformers, termination resistors, supply bypass capacitors.
XOE1 LBO1 E3MODE1 PDB1 TPOS TNEG TCLK TAIS Monitor TMONP TMONM TXMON TMONTST REFCLK
PDATA NDATA
Functional Block Diagram
PDATA/ NDATA Encoder TCLK Pulse Shaper Line Driver TLINEP TLINEM/N
Physical Characteristics
580-ball, TBGA package Single power supply temperature range V-tolerant pins digital pins
RLOOP1 LLOOP1
Data
RPOS RNEG RCLK RLOS
ENDECDIS1
Decoder
Clock/ DATCLK Data RLOSMAX RLOSTHR Recovery RLOSMDIS
Receiver
RLINEP RLINEM/N REQH1
Applications
Digital cross-connect systems High-end routers Multi-service Aswitches Optical add-drop multiplexers Metro-optical Access Switches
ALOS
BDATA/PORTMODE[1:8] BADD/PORTMODE[9:12] BOE~/LMODE0 BWR~/LMODE1 BCS~/GRLOOP BINTR~ SDIN SDOUT
Control Latches/ Command DEMUX
ENCDECDIS[1:12] LBO[1:12] PD~[1:12] RLOOP[1:12] LLOOP[1:12] REQH[1:12] E3[1:12] XOE[1:12] RLOSMAX[1:12] RLOSMDIS[1:12]
500020_030
28335-DSH-001-B
Mindspeed Technologies
February 2003
Ordering Information
Model Number Direct: M28335-13 Distributors: M28335EBGC Package 580-pin TBGA Description Twelve Port T3/E3/STS-1 Operating Temperature
Revision History
Revision
Level
Advance Advance Advance Advance Preliminary Preliminary Preliminary
Date
February 2001 2001 October 2001 December 2001 2002 2002 August 2002 Initial release.
Description
Changed document number from 101487B 500020B. Added number information M28335 Definitions table. Misc. updates. Updated register RLOS information. Added definition. Incorporated Errata document number 500297C. Improved description device. Added diagrams. General corrections. Corrected diagrams; minor updates. Corrected BMODE settings Table descriptions. Updated electrical characteristics. Corrected distance setting Section 3.3. Removed multidevice transmit monitor connection diagram. General corrections. Corrected transmit operation during loopback. Fixed transmit pulse mask, Figure 2-7. Added requirement that hard reset performed after power-up serial modes. Added DS3/E3 STS-1 electrical characteristics tables. Updated design considerations. Added power sequencing requirements between VDD. General corrections. Assigned document number released 28335-DSH-001-B.
Released
February 2003
2002, 2003 Mindspeed TechnologiesTM, Conexant Business
rights reserved. Information this document provided connection with Mindspeed Technologies ("Mindspeed") products. These materials provided Mindspeed service customers used informational purposes only. Mindspeed assumes responsibility errors omissions these materials. Mindspeed make changes specifications product descriptions time, without notice. Mindspeed makes commitment update information shall have responsibility whatsoever conflicts incompatibilities arising from future changes specifications product descriptions. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Mindspeed's Terms Conditions Sale such products, Mindspeed assumes liability whatsoever. THESE MATERIALS PROVIDED WITHOUT WARRANTY KIND, EITHER EXPRESS IMPLIED, RELATING SALE AND/OR MINDSPEED PRODUCTS INCLUDING LIABILITY WARRANTIES RELATING FITNESS PARTICULAR PURPOSE, CONSEQUENTIAL INCIDENTAL DAMAGES, MERCHANTABILITY, INFRINGEMENT PATENT, COPYRIGHT OTHER INTELLECTUAL PROPERTY RIGHT. MINDSPEED FURTHER DOES WARRANT ACCURACY COMPLETENESS INFORMATION, TEXT, GRAPHICS OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. MINDSPEED SHALL LIABLE SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES LOST PROFITS, WHICH RESULT FROM THESE MATERIALS. Mindspeed products intended medical, lifesaving life sustaining applications. Mindspeed customers using selling Mindspeed products such applications their risk agree fully indemnify Mindspeed damages resulting from such improper sale. following trademarks Conexant Systems, Inc.: Mindspeed TechnologiesTM, Mindspeedlogo, "Build First"TM. Product names services listed this publication identification purposes only, trademarks third parties. Third-party brands names property their respective owners. additional disclaimer information, please consult Mindspeed Technologies Legal Information posted www.mindspeed.com which incorporated reference.
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28335-DSH-001-B
M28335 Evaluation Module (EVM)
NRZTX DATA NRZRX DATA
B3ZS/HDB3 analog B3ZS/HDB3 analog
M28335
NRZTX DATA CH12 NRZRX DATA Loss Signal Code Violation
B3ZS/HDB3 analog CH12 B3ZS/HDB3 analog Clock Input Control
101487_002
28335-DSH-001-B
Mindspeed Technologies
28335-DSH-001-B
Mindspeed Technologies
Contents
Figures Tables
Assignments Logic Diagrams 1-19
Description.
Functional Description.
Overview Configuration Control 2.2.1 Hardware Mode. 2.2.2 Mode 2.2.3 Serial Mode. Transmitter 2.3.1 B3ZS/HDB3 Encoder 2.3.2 Pulse Shaper 2.3.3 Line Driver 2.3.3.1 Transmit Pulse Mask Templates 2.3.4 Alarm Indication Signal (AIS) Generator 2-10 2.3.5 Transmit Monitor Block. 2-12 2.3.6 Jitter Generation (Intrinsic) 2-12 Receiver. 2-13 2.4.1 Receive Sensitivity 2-13 2.4.2 AGC/VGA Block 2-13 2.4.3 Receive Equalizer 2-13 2.4.4 Clock Recovery Circuit 2-14 2.4.5 Loss Signal (LOS) Detector 2-14 2.4.6 B3ZS/HDB3 Decoder With Bipolar Violation Detector 2-14 2.4.7 Data Squelching 2-15 Jitter Tolerance 2-16 2.5.1 Jitter Transfer 2-18
28335-DSH-001-B
Mindspeed Technologies
M28335 Data Sheet
Additional M28335 Functions 2.6.1 Bias Generator 2.6.2 External Reset 2.6.3 Power-On Reset (POR) 2.6.4 Interrupt 2.6.5 Loopback Multiplexers (MUXes) Mechanical Specifications 2.7.1 Moisture Sensitivity Electrical/Thermal Characteristics 2.8.1 Absolute Maximum Ratings 2.8.2 Ratings 2.8.3 Recommended Operating Conditions 2.8.4 Characteristics. 2.8.5 Electrical Characteristics 2.8.6 Electrical Characteristics 2.8.7 STS-1 Electrical Characteristics 2.8.8 Characteristics.
2-19 2-19 2-19 2-19 2-20 2-20 2-22 2-23 2-24 2-24 2-24 2-24 2-25 2-26 2-26 2-26 2-27
Registers
Address Global Register 0x0-Global Control Register (GC) Port Registers 0x1-0xC-Portn Control Register (PCn) Alarm Registers. 0x10-RLOS Alarm Register (RALMR1) 0x11-RLOS Alarm Register (RALMR2) 0x12-TLOS Alarm Register (TALMR1) 0x13-TLOS Alarm Register (TALMR2) Interrupt Status Registers 0x14-RLOS Interrupt Status Register (RISR1) 0x15-RLOS Interrupt Status Register (RISR2) 0x16-TLOS Interrupt Status Register (TISR1) 0x17-TLOS Interrupt Status Register (TISR2) Interrupt Enable Registers 0x18-RLOS Interrupt Enable Register (RIER1) 0x19-RLOS Interrupt Enable Register (RIER2) 0x1A-TLOS Interrupt Enable Register (TIER1) 0x1B-TLOS Interrupt Enable Register (TIER2) RLOS Threshold Control Registers 0x0D-RMTR1 (RLOS Threshold Register 0x0E-RMTR2 (RLOS Threshold Register 0x0F-RMTR3 (RLOS Threshold Register RLOS Data Squelch Disable Registers. 0x1C-RDR1 (RLOS Disable Register 0x1D-RDR2 (RLOS Disable Register
Mindspeed Technologies
28335-DSH-001-B
M28335 Data Sheet
Applications.
Line Interface Example Interface Example CX28365 Mode Interface Example CX28365 Hardware Mode Serial Mode Interface Example Design Considerations M28335 4.5.1 Power Supply Ground Plane. 4.5.2 Component Placement 4.5.2.1 RBIAS Resistor 4.5.2.2 Decoupling 4.5.2.3 Termination Resistors Capacitors. 4.5.3 Impedance Matching. 4.5.4 Other Passive Parts. 4.5.5 IBIS Models 4.5.6 Recommended Vendors
Applicable Standards Power Sequencing
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M28335 Data Sheet
viii
Mindspeed Technologies
28335-DSH-001-B
Figures
Figure 1-1. Figure 1-2. Figure 1-3. Figure 1-4. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 2-6. Figure 2-7. Figure 2-8. Figure 2-9. Figure 2-10. Figure 2-11. Figure 2-12. Figure 2-13. Figure 2-14. Figure 2-15. Figure 2-16. Figure 2-17. Figure 2-18. Figure 2-19. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure B-1. Figure B-2.
Bottom View M28335 Hardware Mode Logic Diagram 1-19 Mode Logic Diagram 1-20 Serial Mode Logic Diagram 1-21 Typical Application Single M28335 Channel Device Serial Port Signals Pulse Shaper Pulse Power Measurement Points Transmit Pulse Mask Rates Transmit Pulse Mask STS-1 Rates Transmit Pulse Mask Rate 2-10 Signal 2-11 Direct Connection Monitor Signal Transmit Signal 2-12 Minimum Jitter Tolerance Requirement 2-17 Maximum Jitter Transfer Curve Requirement 2-18 Remote Loopback Diagram 2-21 Local Loopback Diagram 2-21 M28335 Mechanical Drawing TBGA)-Dimensions 2-22 Timing Diagram 2-27 Mode Read Timing 2-28 Mode Write Timing 2-29 Serial Mode Register Read (see Note below) 2-30 Serial Mode Register Write (see Note below) 2-30 Line Interface Example Interface CX28365 Mode Interface CX28365 Hardware Mode Serial Mode Interface Example TX/RX Terminations Power sequence VDD. Power-down sequence VDD.
28335-DSH-001-B
Mindspeed Technologies
Figures
M28335 Data Sheet
Mindspeed Technologies
28335-DSH-001-B
Tables
Table 1-1. Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 2-7. Table 2-8. Table 2-9. Table 2-10. Table 2-11. Table 2-12. Table 2-13. Table 2-14. Table 2-15. Table 2-16. Table 2-17. Table 3-1.
M28335 Definitions Redefinition Port Configuration Hardware Mode Transmit Template Specifications STS-1 Transmit Template Specifications Receiver Sensitivity (Length Cable) DS3/E3/STS-1. 2-13 RLOS Threshold Control Bits 2-14 Absolute Maximum Ratings 2-24 Ratings 2-24 Recommended Operating Conditions. 2-25 Characteristics 2-25 Receiver Characteristics 2-26 Receiver Characteristics 2-26 STS-1 Receiver Characteristics 2-26 Characteristics (Logic Timing) 2-27 Mode Timing-Read Cycles 2-28 Mode Timing-Write Cycles 2-29 Serial Mode Timing 2-30 Register Address
28335-DSH-001-B
Mindspeed Technologies
Tables
M28335 Data Sheet
Mindspeed Technologies
28335-DSH-001-B
Description
Assignments
M28335 packaged 580-ball TBGA package. Figure illustrates complete view ballout, seen from bottom.
Figure 1-1. Bottom View M28335
BOTTOM VIEW
28335-DSH-001-B
Mindspeed Technologies
Description
M28335 Data Sheet
Table lists M28335 descriptions. Input/Output (I/O) column coded follows: Input Output Bidirectional Power
NOTE:
digital inputs outputs contain pull-down resistors.
When channel disabled, receive transmit analog circuitry powers down. Analog inputs (RLINE) ignored analog outputs (TLINE) high impedance. Digital inputs powered-down channel still active, ignored. Overall noise device lowered driving digital inputs powered-down channel.
NOTE:
When channel reverted from power-down normal operation, TLINE pins impedance ground driven more than forward-bias diode voltage (0.7 below ground. Additionally, driving TLINE, forward-bias diode voltage above pin, creates impedance path from TLINE pin. Otherwise, TLINE pins high impedance.
Mindspeed Technologies
28335-DSH-001-B
M28335 Data Sheet
Description
Table 1-1. M28335 Definitions Signal Name Description Coaxial Line Pins
AF33 AF34 AC32 AC33 RLINE1P RLINE1M RLINE2P RLINE2M RLINE3P RLINE3M RLINE4P RLINE4M RLINE5P RLINE5M RLINE6P RLINE6M RLINE7P RLINE7M RLINE8P RLINE8M RLINE9P RLINE9M RLINE10P RLINE10M RLINE11P RLINE11M RLINE12P RLINE12M positive receive data negative receive data positive receive data negative receive data positive receive data negative receive data positive receive data negative receive data positive receive data negative receive data positive receive data negative receive data positive receive data negative receive data positive receive data negative receive data positive receive data negative receive data positive receive data negative receive data positive receive data negative receive data positive receive data negative receive data Differential inputs each channel from respective receive coax line. expects balanced differential inputs, usually achieved using transformer. inputs internally biased
I/O/P
Notes
28335-DSH-001-B
Mindspeed Technologies
Description
M28335 Data Sheet
Table 1-1. M28335 Definitions
AG31 AG32 AD31 AD32 AA31 AA32
Signal Name
TLINE1P TLINE1M TLINE2P TLINE2M TLINE3P TLINE3M TLINE4P TLINE4M TLINE5P TLINE5M TLINE6P TLINE6M TLINE7P TLINE7M TLINE8P TLINE8M TLINE9P TLINE9M TLINE10P TLINE10M TLINE11P TLINE11M TLINE12P TLINE12M
Description
positive transmit data negative transmit data positive transmit data negative transmit data positive transmit data negative transmit data positive transmit data negative transmit data positive transmit data negative transmit data positive transmit data negative transmit data positive transmit data negative transmit data positive transmit data negative transmit data positive transmit data negative transmit data positive transmit data negative transmit data positive transmit data negative transmit data positive transmit data negative transmit data
I/O/P
Notes
Differential, coax-driver balanced outputs pulse-shaped B3ZS/HDB3 encoded waveforms each channel. These pins should connected primary side transformer through backmatch resistors.
Mindspeed Technologies
28335-DSH-001-B
M28335 Data Sheet
Description
Table 1-1. M28335 Definitions Signal Name Description Digital Data Pins
AN27 AM27 AL23 AP24 AN20 AM20 AM10 AL10 AM14 AL14 AP27 AM23 AP20 AP10 AN14 RPOS1/RNRZ1 RNEG1/RLCV1 RPOS2/RNRZ2 RNEG2/RLCV2 RPOS3/RNRZ3 RNEG3/RLCV3 RPOS4/RNRZ4 RNEG4/RLCV4 RPOS5/RNRZ5 RNEG5/RLCV5 RPOS6/RNRZ6 RNEG6/RLCV6 RPOS7/RNRZ7 RNEG7/RLCV7 RPOS8/RNRZ8 RNEG8/RLCV8 RPOS9/RNRZ9 RNEG9/RLCV9 receive positive rail data receive negative rail line code violation receive positive rail data receive negative rail line code violation receive positive rail data receive negative rail line code violation receive positive rail data receive negative rail line code violation receive positive rail data receive negative rail line code violation receive positive rail data receive negative rail line code violation receive positive rail data receive negative rail line code violation receive positive rail data receive negative rail line code violation receive positive rail data receive negative rail line code violation Recovered clock each channel receiver, intended strobing corresponding RDAT into following framer logic. When ENDECDIS these outputs decoded data (RNRZ) line code violation (RLCV). line code violation indicated when RLCV notes ENDECDIS Section 2.3.1. Resynchronized receive data intended strobed corresponding RCLK. When ENDECDIS these outputs positive negative data (RPOS RNEG).
I/O/P
Notes
RPOS10/RNRZ10 receive positive rail data RNEG10/RLCV10 receive negative rail line code violation
RPOS11/RNRZ11 receive positive rail data RNEG11/RLCV11 receive negative rail line code violation
RPOS12/RNRZ12 receive positive rail data RNEG12/RLCV12 RCLK1 RCLK2 RCLK3 RCLK4 RCLK5 RCLK6 RCLK7 RCLK8 RCLK9 RCLK10 RCLK11 RCLK12 receive negative rail line code violation Receive Clock Receive Clock Receive Clock Receive Clock Receive Clock Receive Clock Receive Clock Receive Clock Receive Clock Receive Clock Ch10 Receive Clock Ch11 Receive Clock Ch12
28335-DSH-001-B
Mindspeed Technologies
Description
M28335 Data Sheet
Table 1-1. M28335 Definitions
AP25 AM25 AL21 AP22 AN18 AM18 AP12 AN12 AL16 AM16 AL24 AM21 AP18 AL13 AP16
Signal Name
TPOS1 TNEG1/NC1 TPOS2 TNEG2/NC2 TPOS3 TNEG3/NC3 TPOS4 TNEG4/NC4 TPOS5 TNEG5/NC5 TPOS6 TNEG6/NC6 TPOS7 TNEG7/NC7 TPOS8 TNEG8/NC8 TPOS9 TNEG9/NC9 TPOS10 TNEG10/NC10 TPOS11 TNEG11/NC11 TPOS12 TNEG12/NC12 TCLK1 TCLK2 TCLK3 TCLK4 TCLK5 TCLK6 TCLK7 TCLK8 TCLK9 TCLK10 TCLK11 TCLK12
Description
transmit Positive rail data transmit negative rail connect data transmit Positive rail data transmit negative rail connect data transmit Positive rail data transmit negative rail connect data transmit Positive rail data transmit negative rail connect data transmit Positive rail data transmit negative rail connect data transmit Positive rail data transmit negative rail connect data transmit Positive rail data transmit negative rail connect data transmit Positive rail data transmit negative rail connect data transmit Positive rail data transmit negative rail connect data transmit Positive rail data transmit negative rail connect data transmit Positive rail data transmit negative rail connect data transmit Positive rail data transmit negative rail connect data Transmit Clock Transmit Clock Transmit Clock Transmit Clock Transmit Clock Transmit Clock Transmit Clock Transmit Clock Transmit Clock Transmit Clock Transmit Clock Transmit Clock
I/O/P
Notes
Synchronized transmit data intended strobed corresponding TCLK. When ENDECDIS these inputs expected positive negative data (TPOS TNEG). When ENDECDIS these inputs expected uncoded data (TNRZ) connects (NC). notes ENDECDIS Section 2.3.1.
Transmit clock input strobing with transmit data into M28335.
Mindspeed Technologies
28335-DSH-001-B
M28335 Data Sheet
Description
Table 1-1. M28335 Definitions
AM26 AN23 AL19 AM11 AL15
Signal Name
RLOS1 RLOS2 RLOS3 RLOS4 RLOS5 RLOS6 RLOS7 RLOS8 RLOS9 RLOS10 RLOS11 RLOS12
Description
Loss Signal Loss Signal Loss Signal Loss Signal Loss Signal Loss Signal Loss Signal Loss Signal Loss Signal Loss Signal Loss Signal Loss Signal
I/O/P
Notes
Loss Signal (LOS) indication each channel, determined insufficient pulse density. Signal loss detected when RLOS Loss signal will asserted deasserted under conditions discussed Section 2.4.5.
Control Signal
AN24 AP21 AP17 AP13 AL17 TAIS1 TAIS2 TAIS3 TAIS4 TAIS5 TAIS6 TAIS7 TAIS8 TAIS9 TAIS10 TAIS11 TAIS12 Transmit mode enable Transmit mode enable Transmit mode enable Transmit mode enable Transmit mode enable Transmit mode enable Transmit mode enable Transmit mode enable Transmit mode enable Transmit mode enable Transmit mode enable Transmit mode enable Transmission Alarm Indication Signal (AIS) given channel. Replace transmit data with signal. form supported alternating (+1, Transmit overwrites data during local loopback. mode enabled mode disabled
28335-DSH-001-B
Mindspeed Technologies
Description
M28335 Data Sheet
Table 1-1. M28335 Definitions Signal Name Description I/O/P Notes
Mode/Hardware Mode/Serial Mode Control Signals
BDATA0 /PORTMODE1 /SDOUT BDATA1 /PORTMODE2 /SDIN BDATA2 /PORTMODE3 BDATA3 /PORTMODE4 BDATA4 /PORTMODE5 BDATA5 /PORTMODE6 BDATA6 /PORTMODE7 BDATA7 /PORTMODE8 BADD0 /PORTMODE9 BADD1 /PORTMODE10 BADD2 /PORTMODE11 BADD3 /PORTMODE12 BADDR4 /TMONTST Data 0/PORTMODE1/SDOUT Hardware mode (Pins BMODE[1:0] 00), pins defined PORTMODE[8:1], which select configurations Port[8:1]. mode (Pins BMODE[1:0] 10), pins defined eight bidirectional used transferring data from internal registers which configurations ports. Serial mode (Pins BMODE[1:0] 11), SDIN serial data input from Serial Master device. Serial mode (Pins BMODE[1:0] 11), SDOUT serial data output Serial Master device.
Data 1/PORTMODE2/SDIN
Data 2/PORTMODE3 Data 3/PORTMODE4 Data 4/PORTMODE5 Data 5/PORTMODE6 Data 6/PORTMODE7 Data 7/PORTMODE8 Address 0/PORTMODE9 Address 1/PORTMODE10 Address 2/PORTMODE11 Address 3/PORTMODE12 Address 4/TX Monitor Test
Hardware mode (Pins BMODE[1:0] 00), pins defined PORTMODE[12:9] which select configurations Port[12:9]. mode (Pins BMODE[1:0] 10), pins defined four address lines identify internal register read/write data transfer cycle.
Hardware mode (Pins BMODE[1:0] 00), defined monitor test which, when driven high, asserts TLOS outputs. This used test board level functionality downstream from TLOS outputs. mode (Pins BMODE[1:0] 10), defined address internal register access. Hardware mode (Pins BMODE[1:0] 00), defined pins LMODE0 LMODE1 which common control lines together with PORTMODEx lines control configuration individual ports. mode (Pins BMODE[1:0] 10), indicates write cycle when low.
BWR~/LMODE1
Data Write Strobe /LMODE1
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28335-DSH-001-B
M28335 Data Sheet
Description
Table 1-1. M28335 Definitions
Signal Name
BOE~/LMODE0 /SCLK
Description
Data Output Enable /LMODE0
I/O/P
Notes
Hardware mode (Pins BMODE[1:0] 00), defined pins LMODE0 LMODE1 which common control lines together with PORTMODEx lines control configuration individual ports. mode (Pins BMODE[1:0] 10), enables BDATA output during read operation when active low. When high, BDATA[7:0] high impedance state. serial mode (Pins BMODE[1:0] 11), SCLK serial clock input from serial master device.
BCS~/GRLOOP
Chip select /GRLOOP
Hardware mode (Pins BMODE[1:0] 00), defined GRLOOP (global remote loopback). twelve ports placed remote loopback when this tied high. normal operations, GRLOOP should tied low. mode (Pins BMODE[1:0] 10), serves chip select. enables read/write operation when active low. When high, ends current read/write cycle returns BDATA[7:0] high impedance state.
BMODE0 BMODE1
Mode select Mode select
Mode Select pins control device configuration mode follows: BMODE1 BMODE0 Mode Operation Hardware Mode Reserved (for factory test) Mode Serial Mode Hardware mode (Pins BMODE[1:0] 00), control signals redefined configuration each channel determined associated dedicated PORTMODE pins. mode (pins BMODE[1:0] 10), internal registers that control operation each port accessed through SRAMlike parallel port. Serial mode (pins BMODE[1:0] 11), Control signals redefined support SPI.
BINTR~
Interrupt
Open drain active output signifies more pending alarm condition detected INTEN (bit address set.
28335-DSH-001-B
Mindspeed Technologies
Description
M28335 Data Sheet
Table 1-1. M28335 Definitions Signal Name Description Miscellaneous
AN26 AL22 AM19 AN11 AM15 AN29 REFCLK1 REFCLK2 REFCLK3 REFCLK4 REFCLK5 REFCLK6 REFCLK7 REFCLK8 REFCLK9 REFCLK10 REFCLK11 REFCLK12 RBIASA RBIASB RBIASC RBIASD RESET Reference Clock Reference Clock Reference Clock Reference Clock Reference Clock Reference Clock Reference Clock Reference Clock Reference Clock Reference Clock Reference Clock Reference Clock Bias Resistor Bias Resistor Bias Resistor Bias Resistor Reset Global Power Down Asynchronous reset (reset entire device). Power down (Static testing). Power down disable Power down active Four 12.1 resistors tied from each these pins ground provide current reference.(2) Reference clock from off-chip. clock should following with rates tolerance: rate (34.368 MHz) rate (44.736 MHz) STS-1 rate (51.84 MHz) clock rate should correspond mode operation chosen channel.
I/O/P
Notes
1-10
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28335-DSH-001-B
M28335 Data Sheet
Description
Table 1-1. M28335 Definitions
AH32 AG33 AE34 AD33 AB32 AA34 AL25 AM22 AL18 AM12 AP15
Signal Name
TMON1P TMON1M TMON2P TMON2M TMON3P TMON3M TMON4P TMON4M TMON5P TMON5M TMON6P TMON6M TMON7P TMON7M TMON8P TMON8M TMON9P TMON9M TMON10P TMON10M TMON11P TMON11M TMON12P TMON12M TLOS1 TLOS2 TLOS3 TLOS4 TLOS5 TLOS6 TLOS7 TLOS8 TLOS9 TLOS10 TLOS11 TLOS12
Description
transmit monitor positive input transmit monitor negative input transmit monitor positive input transmit monitor negative input transmit monitor positive input transmit monitor negative input transmit monitor positive input transmit monitor negative input transmit monitor positive input transmit monitor negative input transmit monitor positive input transmit monitor negative input transmit monitor positive input transmit monitor negative input transmit monitor positive input transmit monitor negative input transmit monitor positive input transmit monitor negative input transmit monitor positive input transmit monitor negative input transmit monitor positive input transmit monitor negative input transmit monitor positive input transmit monitor negative input loss signal output loss signal output loss signal output loss signal output loss signal output loss signal output loss signal output loss signal output loss signal output loss signal output loss signal output loss signal output
I/O/P
Notes
Transmit monitor input pins normally tied their respective transmit line outputs, i.e., (TMON1P TLINE1P TMON1M TLINE1M). Loss signal outputs active high when monitor inputs detect signal TCLK periods. monitor test asserts TLOS outputs when TMONTST high. This used test board level functionality downstream from TLOS outputs.
28335-DSH-001-B
Mindspeed Technologies
1-11
Description
M28335 Data Sheet
Table 1-1. M28335 Definitions
C28, AP28, AN6, D28, AL27, AP6,
Signal Name
FAC_TEST Test pins.
Description
I/O/P
Notes
factory test, leave unconnected.
Power/Ground
AF31 AD34 AH31 AE32 AB31 TVDD1 TVDD2 TVDD3 TVDD4 TVDD5 TVDD6 TVDD7 TVDD8 TVDD9 TVDD10 TVDD11 TVDD12 TVSS1 TVSS2 TVSS3 TVSS4 TVSS5 TVSS6 TVSS7 TVSS8 TVSS9 TVSS10 TVSS11 TVSS12 Power Power Power Power Power Power Power Power Power Power Power Power Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground pins transmit circuitry channel. Power pins transmit circuitry channel (3.3
1-12
Mindspeed Technologies
28335-DSH-001-B
M28335 Data Sheet
Description
Table 1-1. M28335 Definitions
AF32 AC31 AE31 AC34 AM28
Signal Name
RVDD1 RVDD2 RVDD3 RVDD4 RVDD5 RVDD6 RVDD7 RVDD8 RVDD9 RVDD10 RVDD11 RVDD12 RVSS1 RVSS2 RVSS3 RVSS4 RVSS5 RVSS6 RVSS7 RVSS8 RVSS9 RVSS10 RVSS11 RVSS12 VGGA VGGB VGGC VGGD Power Power Power Power Power Power Power Power Power Power Power Power Ground Ground Ground Ground Ground Ground Ground Ground Ground
Description
I/O/P
Notes
Power pins receive circuitry channel (3.3 Connect power.
Ground pins receive circuitry channel. Connect ground.
Ground Ground Ground V/3.3
V/3.3 pin(1) V/3.3 pin(1) V/3.3 pin(1)
supply V-tolerant, digital diodes. static power drawn from pin.
28335-DSH-001-B
Mindspeed Technologies
1-13
Description
M28335 Data Sheet
Table 1-1. M28335 Definitions Signal Name
Power
Description
I/O/P
Notes
Connect power.
E10, DVDD E14, E18, E22, E26, F30, K30, P30, V30, AA5, AB30, AE5, AF30, AJ5, AK4, AK9, AK13, AK17, AK21, AK25, AK29, AL30
1-14
Mindspeed Technologies
28335-DSH-001-B
M28335 Data Sheet
Description
Table 1-1. M28335 Definitions Signal Name Description
Ground
I/O/P
Connect ground.
Notes
A13, A18, A22, A28, A30, A31, A32, A33, A34, B10, B11, B13, B16, B17, B19, B22, B25, B28, B29, B30, B31, B32, B33, B34, C10, C12, C17, C18, C26, C30, C31, C32, C33, C34, D15, D17, D18, D19, D24, D29, D30, D31, D32, D33, D34, E11, E12, E13, E15, E16, E17, E19, E20, E21, E23, E24, E25, E27, E28, E29, E30, E31, E32, E33, F32, G30, G32, G33, G34,
(List continued next page.)
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1-15
Description
M28335 Data Sheet
Table 1-1. M28335 Definitions Signal Name Description
Ground
I/O/P
Connect ground.
Notes
H30, J30, J34, K33, K34, L30, L31, L33, M30, M31, N30, N33, P33, R30, T30, T33, U30, W30, W31, W33, Y30, AA30, AA33, AB1, AB2, AB5, AB33, AB34, AC2, AC5, AC30, AD4, AD5, AD30, AE2, AE30, AE33, AF5, AG1, AG5, AG30, AG34, AH1, AH2, AH5, AH30, AH33, AH34, AJ3, AJ4, AJ30, AJ31, AJ32, AJ33, AJ34, AK1, AK2, AK3,
(List continued next page.)
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M28335 Data Sheet
Description
Table 1-1. M28335 Definitions Signal Name Description
Ground
I/O/P
Connect ground.
Notes
AK5, AK6, AK7, AK8, AK10, AK11, AK12, AK14, AK15, AK16, AK18, AK19, AK20, AK22, AK23, AK24, AK26, AK27, AK28, AK30, AK31, AK32, AK33, AK34, AL1, AL2, AL3, AL4, AL5, AL11, AL12, AL20, AL26, AL28, AL29, AL31, AL32, AL33, AL34, AM1, AM2, AM3, AM4, AM5, AM13, AM17, AM24, AM29, AM30, AM31, AM32, AM33, AM34, AN1, AN2, AN3, AN4, AN5, AN7, AN10, AN13,
(List continued next page.)
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Description
M28335 Data Sheet
Table 1-1. M28335 Definitions Signal Name Description
Ground
I/O/P
Connect ground.
Notes
AN15, AN16, AN17, AN19, AN21, AN22, AN25, AN28, AN30, AN31, AN32, AN33, AN34, AP1, AP2, AP3, AP4, AP5, AP9, AP11, AP14, AP19, AP23, AP26, AP29, AP30, AP31, AP32, AP33, AP34
NOTES:
This should connected all-3.3 design. Placing capacitor from this ground result instabilities.
GENERAL NOTE: digital input pins contain pull-down resistor from input GND.
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M28335 Data Sheet
Description
Logic Diagrams
Figure 1-2. Hardware Mode Logic Diagram
Port Mode Line Mode Global Remote Loopback Monitor Test
PORTMODE[1:12] LMODE[0:1] GRLOOP TMONTST BMODE1 BMODE0
Hardware Mode Configuration
Postive Receive Data Negative Receive Data RLINE[1:12]P RLINE[1:12]M RPOS[1:12]/RNRZ[1:12] NPOS[1:12]/RLCV[1:12] RCLK[1:12] RLOS[1:12] Receive Positive Rail/NRZ Data Receive Negative Rail/Line Code Violation Receive Clock Receive Loss Data
Receiver
Transmit Positive Rail/NRZ data Trasmit Negative Rail/NC Transmit Monitor Postive Input Transmit Monitor Negative Input Transmit Clock Transmit mode Enable
TPOS[1:12] TNEG[1:12]/NC[1:12] TMON[1:12]P TMON[1:12]M TCLK[1:12] Transmitter TAIS[1:12] REFCLK[1:12] RESET
TLINE[1:12]P TLINE[1:12]M TLOS[1:12]
Positive Transmit Data Negative Transmit Data Transmit Loss Data
Reference Clock Reset Global Power Down
RBIASA RBAISB RBAISC RBAISD
Bias Resistor Bias Resistor Bias Resistor Bias Resistor
Miscellaneous
Input, Output, Programmable I/O; controls located
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Description
M28335 Data Sheet
Figure 1-3. Mode Logic Diagram
Data Address Chip Select Data Write Strobe Data Output Enable
BDATA[0:7] BADD[0:4] BCS~ BWR~ BOE~ BMODE1 BMODE0
BINTR~
Interrupt
Mode Interface
RPOS[1:12]/RNRZ[1:12] NPOS[1:12]/RLCV[1:12] RCLK[1:12] RLOS[1:12] Receive Positive Rail/NRZ Data Receive Negative Rail/Line Code Violation Receive Clock Receive Loss Data
Postive Receive Data Negative Receive Data
RLINE[1:12]P RLINE[1:12]M
Receiver
Transmit Positive Rail/NRZ data Trasmit Negative Rail/NC Transmit Monitor Postive Input Transmit Monitor Negative Input Transmit Clock Transmit mode Enable
TPOS[1:12] TNEG[1:12]/NC[1:12] TMON[1:12]P TMON[1:12]M TCLK[1:12] Transmitter TAIS[1:12] REFCLK[1:12] RESET
TLINE[1:12]P TLINE[1:12]M TLOS[1:12]
Positive Transmit Data Negative Transmit Data Transmit Loss Data
Reference Clock Reset Global Power Down
RBIASA RBAISB RBAISC RBAISD
Bias Resistor Bias Resistor Bias Resistor Bias Resistor
Miscellaneous
Input, Output, Programmable I/O; controls located
500020_032
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M28335 Data Sheet
Description
Figure 1-4. Serial Mode Logic Diagram
Chip Select Serial Clock Serial Data
BCS~ SCLK SDIN
SDOUT BINTR~
Serial Data Output Interrupt
BMODE1 BMODE0
Serial Peripheral Interface
Postive Receive Data Negative Receive Data RLINE[1:12]P RLINE[1:12]M RPOS[1:12]/RNRZ[1:12] NPOS[1:12]/RLCV[1:12] RCLK[1:12] RLOS[1:12] Receive Positive Rail/NRZ Data Receive Negative Rail/Line Code Violation Receive Clock Receive Loss Data
Receiver
Transmit Positive Rail/NRZ data Trasmit Negative Rail/NC Transmit Monitor Postive Input Transmit Monitor Negative Input Transmit Clock Transmit mode Enable
TPOS[1:12] TNEG[1:12]/NC[1:12] TMON[1:12]P TMON[1:12]M TCLK[1:12] TAIS[1:12] Transmitter REFCLK[1:12] RESET
TLINE[1:12]P TLINE[1:12]M TLOS[1:12]
Positive Transmit Data Negative Transmit Data Transmit Loss Data
Reference Clock Reset Global Power Down
RBIASA RBAISB RBAISC RBAISD
Bias Resistor Bias Resistor Bias Resistor Bias Resistor
Miscellaneous
Input, Output, Programmable I/O; controls located
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Description
M28335 Data Sheet
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Functional Description
Overview
M28335 12-port E3/DS3/STS-1 Line Interface Unit (LIU). physical layer interface between data framer other terminal-side equipment) electrical cable used data transmission. M28335 consists independent data transceivers that operate over type 734/728 coaxial cable rates 34.368 Mbps (E3), 44.736 Mbps (DS3), 51.84 Mbps (STS-1). transmit side takes already-encoded dual rail input encodes into B3ZS (for DS3/STS-1) HDB3 (for analog waveforms transmitted over coaxial cable. receiver side takes attenuated distorted analog receive signal equalizes, slices, resynchronizes signal before decoding output sending nondecoded dual rail. architecture M28335 includes following internal functions each channel: Transmitter: B3ZS/HDB3 encoder pulse shaper line driver Alarm Indication Signal (AIS) insertion transmit monitor Receiver: receive sensitivity Automatic Gain Control (AGC) receive equalizer Clock Recovery circuit Loss Signal (LOS) detector B3ZS/HDB3 decoder with bipolar violation detector data squelching Additional Functions: bias generator power-on reset loopback MUXes
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Mindspeed Technologies
Functional Description
M28335 Data Sheet
addition, each channel ability perform remote local loopbacks. Figure illustrates typical application using M28335 channel. Each port controlled configured mode through parallel port hardware mode through dedicated pins. M28335 used data transceiver over coaxial cable that feet long feet from DSX) on-premise environment within public private networks that these data rates.
Figure 2-1. Typical Application Single M28335 Channel
0-450 COAX (type 734/728)
0-450 COAX (type 734/728)
0-450 COAX (type 734/728)
0-450 COAX (type 734/728)
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M28335 Data Sheet
Functional Description
2.2.1
Configuration Control
Hardware Mode
When BMODE pins tied connected, device operates Hardware mode where control signals redefined configuration each channel determined associated dedicated PORTMODE pins. redefinition listed Table 2-1.
Table 2-1. Redefinition
Hardware Mode (BMODE
PORTMODE1 PORTMODE2 PORTMODE3 PORTMODE4 PORTMODE5 PORTMODE6 PORTMODE7 PORTMODE8 PORTMODE9 PORTMODE10 PORTMODE11 PORTMODE12 TMONTST LMODE0 LMODE1 GRLOOP
Mode (BMODE
BDATA0 BDATA1 BDATA2 BDATA3 BDATA4 BDATA5 BDATA6 BDATA7 BADD0 BADD1 BADD2 BADD3 BADD4 BOE~ BWR~ BCS~
Serial Mode (BMODE
SDOUT SDIN SCLK BCS~
28335-DSH-001-B
Mindspeed Technologies
Functional Description
M28335 Data Sheet
Pins LMODE0 LMODE1 common control lines. Together with PORTMODEx lines, they control configuration individual ports. device decodes three lines sets internal registers that determine configuration port according Table 2-2.
Table 2-2. Port Configuration Hardware Mode Pins PORTMODEn
Internal Registers Description E3MODE
LMODE[1:0]
REQH
ENDECDIS
DS3/STS-1, square receive pulse (low eq), encode/decode DS3/STS-1, normal receive pulse (high eq), encode/decode DS3/STS-1, square receive pulse (low eq), encode/decode DS3/STS-1, normal receive pulse (high encode/decode off, mode, encode/decode DS3/STS-1, normal receive pulse (high eq), encode/decode mode, encode/decode (same DS3, square, encode/decode off, off) DS3/STS-1, normal receive pulse (high encode/decode off,
Group Controls Global (GRLOOP) controls remote loopback. When GRLOOP tied high, twelve ports placed remote loopback. normal operations, GRLOOP should tied low.
NOTE:
real-time status alarm signals RLOS TLOS available dedicated output pins regardless BMODE state read/write cycle.
2.2.2
Mode
When BMODE1 tied high BMODE0 tied low, device operates mode. mode, internal registers that control operation each port accessed through SRAM like parallel port. redefinition follows: BDATA[7:0] BADDR[4:0] BWR~ BOE~ BCS~ Eight-bit bidirectional data Five-bit address Write strobe BDATA output enable BDATA chip select
Chapter definition internal registers.
Mindspeed Technologies
28335-DSH-001-B
M28335 Data Sheet
Functional Description
2.2.3
Serial Mode
M28335 supports Serial Peripheral Interface (SPI) device control configuration. four-wire, slave interface which allows host processor framer with compatible master serial port communicate with device. This interface allows host control query M28335 status writing reading internal registers. 8-bit register written SDIN read from SDOUT clock rate determined SCLK. serial port enabled pulling chip select pin, active (low) during read write cycles. Figure serial peripheral interface port signals. serial interface uses 16-bit process each write read operation. During write read operation, 8-bit control word consisting read/write control 7-bit register address (A[6:0], where A[4:0] used with always zero), transmitted SDIN pin. operation write operation (R/W 8-bit register data (D[7:0]) byte follows address SDIN pin. This data received M28335 stored addressed register. operation read operation (R/W M28335 outputs addressed register contents SDOUT pin. signal input SDIN sampled SCLK falling edge, data output SDOUT changes SCLK rising edge.
Figure 2-2. Device Serial Port Signals
Read Timing
SCLK
SDIN
Address/Control Byte SDOUT
Register Data Byte
Write Timing
SCLK
SDIN
Address/Control Byte SDOUT
Register Data Byte
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Mindspeed Technologies
Functional Description
M28335 Data Sheet
Transmitter
This section describes detailed operation various blocks M28335 transmitter.
2.3.1
B3ZS/HDB3 Encoder
ENDECDIS E3MODE pins configure encoder mode. When ENDECDIS encoder receiving non-encoded Nonreturn Zero (NRZ) data TNRZ (TPOS) alone, Connect (NC) (TNEG) ignored. data encoded into representation three-level B3ZS (E3MODE HDB3 (E3MODE signal before going pulse shaper form binary signals representing positive negative three-level pulses. When ENDECDIS encoder disabled. encoder passes already-encoded data over TPOS (TNRZ) TNEG (NC) pulse shaper. transmit digital data clocked into chip rising TCLK edge, which must equal symbol rate (line rate). small delay added data provides certain amount negative data hold time.
2.3.2
Pulse Shaper
pulse shaper converts digital (clocked) positive negative pulses into single analog three-level Alternate Mark Inversion (AMI) pulse. pulses Return Zero (RZ) format, meaning that positive negative pulses have duration first half symbol period. rate (E3MODE pulse full-amplitude, square-shaped pulse with very little slope.
Figure 2-3. Pulse Shaper
Mode Pulse Pulse
Pulse Shaper Line Driver
500020_010
DS3/STS-1 rates, pulse-shaper block shapes transmit waveform reduces high-frequency energy content. This ensures that transmit pulse template cross-connect block, which follows 0-450 feet transmit-side coaxial cable.
Mindspeed Technologies
28335-DSH-001-B
M28335 Data Sheet
Functional Description
2.3.3
Line Driver
differential line driver takes shaped transmit waveform, increases proper level, drives into transmit magnetics. external discrete backmatching resistors provide line matching. driver presented with approximately differential load. Driver gain accounts gain loss back-matching resistors. Figure illustrates Pulse/Power template measurement points various data rates.
Figure 2-4. Pulse Power Measurement Points
Pulse/Power Template STS-1
0-450 COAX (type 734/728)
0-450 COAX (type 734/728)
Pulse/Power Template
0-450 COAX (type 734/728)
0-450 COAX (type 734/728)
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Functional Description
M28335 Data Sheet
2.3.3.1
Transmit Pulse Mask Templates
Figure 2-5, Figure 2-6, Figure illustrate transmit pulse masks DS3, STS-1, rates respectively.
Figure 2-5. Transmit Pulse Mask Rates
Transmit Pulse Mask Rates
Normalized Pulse Amplitude
-0.2
-1.0 -0.5
Normalized Symbol Time
Table 2-3. Transmit Template Specifications Time Axis Range (UI) Upper Curve
-0.85 -0.68 -0.68 0.36 0.36 0.03 0.03 2)(1 0.34)]} 0.08 0.407 -1.84(T 0.36)
Normalized Amplitude Equation
Lower Curve
-0.85 -0.36 -0.36 0.36 0.36 -0.03 -0.03 2)(1 0.18)]} -0.03
Mindspeed Technologies
28335-DSH-001-B
M28335 Data Sheet
Functional Description
Figure 2-6. Transmit Pulse Mask STS-1 Rates
Transmit Pulse Mask STS-1 Rates
Normalized Pulse Amplitude
-0.2
-1.0 -0.5
Normalized Symbol Time
Table 2-4. STS-1 Transmit Template Specifications Time Axis Range Upper Curve
-0.85 -0.68 -0.68 0.26 0.26 0.03 0.03 2)(1 0.34)]} 0.61 -2.4(T 0.26)
Normalized Amplitude Equation
Lower Curve
-0.85 -0.36 -0.36 0.36 0.36 -0.03 -0.03 2)(1 0.18)]} -0.03
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Mindspeed Technologies
Functional Description
M28335 Data Sheet
Figure 2-7. Transmit Pulse Mask Rate
Volts 8.65 12.1 14.55
24.5 29.1 Time
500118a_1
2.3.4
Alarm Indication Signal (AIS) Generator
When TAIS asserted, replaces transmit data TPOS TNEG. type signal (all supported. three-level signal form, this continuously alternating positive negative pulse stream, transmit data were continuous string logical Figure illustrates signal. TAIS same data latency data pins used replace single symbols within data stream. When encoder disabled (ENDECDIS TAIS mode maintains proper phase, based polarity last received. signal follows same path data during local loopback, does affect remote loopback operation.
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M28335 Data Sheet
Functional Description
Figure 2-8. Signal
POSITIVE PULSE
NEGATIVE PULSE
TLINEP (output voltage)
TLINEN (output voltage)
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Functional Description
M28335 Data Sheet
2.3.5
Transmit Monitor Block
transmit monitor inputs (TMONP TMONM) designed monitor line driver outputs (TLINEP TLINEM) pulses, assert Loss Signal (TLOS) indictor when output pulse been detected TCLK periods. After TLOS asserted, will deassert until pulse again detected. transmit monitor independent function which TMONP TMONM must externally connected TLINEP TLINEM, respectively. transmit monitor logic does require external hardware between transmit signal monitor input. This illustrated Figure 2-9.
Figure 2-9.Direct Connection Monitor Signal Transmit Signal
TMONP TLINEP Transformer TLINEM TMONM
NOTE:
order transmit monitor logic port operate, transmit clock (TCLK) that port must clocked.
special (TMONTST) available testing board-level functionality downstream from TLOS outputs. When TMONTST high, asserts TLOS channel outputs. TLOS outputs active high when monitor inputs detect signal.
2.3.6
Jitter Generation (Intrinsic)
M28335 meets jitter generation requirements various rates with large margins, with condition that input transmit clock (TCLK) jitter-free. Data rates jitter generation requirements defined these three documents:
rate-ETSI TBR24, ITU-T G.823 (section 3.1.2) rate-Bellcore Telcordia GR499, AT&T Accunet TR54014, ITU-T G.824 STS-1 rate-Bellcore Telcordia GR253
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M28335 Data Sheet
Functional Description
2.4.1
Receiver
This section describes detailed operation blocks M28335 receiver.
Receive Sensitivity
receiver recovers data from coaxial cable that attenuated frequency-dependent characteristics cable. addition, receiver compensates flat loss (across frequencies) various electrical components variation transmitted signal power. M28335 recover data cable distances shown Table when cable characteristics attenuation consistent with ANSI T1.102-1993, Annex Figure C.2. This approximates characteristics AT&T type 734/728 cable; almost same attenuation characteristics achieved one-half length AT&T type cable.
Table 2-5. Receiver Sensitivity (Length Cable) DS3/E3/STS-1 Mode
STS-1
1275 1275 1200
Units
Feet Feet Feet
2.4.2
AGC/VGA Block
Variable Gain Amplifier (VGA) receives input signal from coaxial cable. supplies flat gain (independent frequency) make various flat losses transmission channel loss one-half symbol rate that cannot made equalizer. gain controlled feedback loop which senses amplitude equalizer output, acts amplitude servo optimal slicing.
2.4.3
Receive Equalizer
receive equalizer receives differential signal from boosts high frequency content signal reduce intersymbol interference (ISI) point that correct decisions made slicer with minimum jitter recovered data. REQH when high (REQH boosts amount equalization receive side LIU. DS3/STS-1 pulses require greater amount equalization then standard pulses. REQH therefore normally high (REQH standard DS3/STS-1 pulses. cases where square-shaped DS3/STS-1 pulse (that does meet DS3/STS1 standards) transmitted receiver REQH (REQH mode, REQH should always (REQH prevent overequalization.
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Functional Description
M28335 Data Sheet
2.4.4
Clock Recovery Circuit
clock recovery circuit PLL) extracts embedded clock from sliced data provides retimed data decoder (data mode). Upon startup (after internal reset deasserted), uses reference clock (REFCLK, running symbol rate) phase-frequency detector lock correct data rate (reference mode). During reference mode, data outputs squelched (set kept reference mode until valid input detected.
2.4.5
Loss Signal (LOS) Detector
RLOS detector circuitry consists functional blocks: analog section digital section. analog section consists high-speed, low-offset comparators used amplitude qualification. digital section qualifies pulse stream density 0-run length. analog section, bits control declare clear levels each channel (see Table 2-6). digital section asserts RLOS when valid pulses (per analog section described above) have been received REFCLKs. digital block clears RLOS when valid pulse density exceeds 20.3% with consecutive during 128-symbol period. RLOS detector always monitors cable-side inputs. detector affected state remote local looping. each channel, (RLOS Disable), used decide RLOS should disable data squelching. RLOS Data Squelch Disable registers Section 3.8.
Table 2-6. RLOS Threshold Control Bits
Action
RLOS Cleared RLOS Declared
Vpk(mV)
Typical Vpk(mV)
Vpk(mV)
RLOS Cleared RLOS Declared
RLOS Cleared RLOS Declared
Reserved
GENERAL NOTE: Hysteresis
2.4.6
B3ZS/HDB3 Decoder With Bipolar Violation Detector
M28335 device, when ENDECDIS (encoder/decoder enabled), decoder takes output from clock recovery circuit decodes data (HDB3 B3ZS) into single retimed data signal. data signal then sent M28335 RNRZ (RPOS) pin. detected Line Code Violations (LCV) sent over
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M28335 Data Sheet
Functional Description
corresponding RLCV (RNEG) pin. RLCV asserted symbol period time violation appears output (RNRZ). following shows data sequence criteria LCV; violations indicated bold text. valid bipolar pulse indicated bipolar violation (non-alternating positive negative) pulse indicated Excessive zeros: (HDB3) (B3ZS). These violations passed data RNRZ pin. Bipolar violation: (i.e., HDB3) (B3ZS HDB3). These violations passed data RNRZ pin. Coding violation: (HDB3) (B3ZS) with even number since last valid substitution (follows coding rule). These violations passed data RNRZ pin. even/odd counter (used count number between will count bipolar violation coding violation valid substitution resets counter. When ENDECDIS decoder disabled, retimed slicer outputs sent over RPOS (RNRZ) RNEG (RLCV) pins. These outputs then decoded Framer other downstream device. LCVs detected this mode operation. decoder configurable either: mode using HDB3 coding (E3MODE DS3/STS-1 mode using B3ZS coding (E3MODE receiver digital data outputs centered rising edge RCLK (see Section 2.8.8).
2.4.7
Data Squelching
counter receiver counts number consecutive symbol periods without valid data pulse. When more counted, receiver assumes lost signal resets itself regain signal. While receiver reacquiring signal, clock recovery block locks reference clock, data squelching achieved forcing data bits data squelching true both dual rail mode. When input signal been properly amplified equalized, clock recovery then switches incoming data.
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Functional Description
M28335 Data Sheet
Jitter Tolerance
M28335 receiver tolerate specified amount high-frequency jitter received signal while providing error-free operation (generally defined 10-9). specifications (illustrated Figure 2-10) jitter tolerance discussed following documents: rate-ITU-T G.823 ETSI TBR24 contain frequency masks input jitter tolerance.
NOTE: meet jitter transfer requirements loop-timed operation, external jitter attenuator required. jitter attenuator lessens jitter from receive clock.
rate-Bellcore GR499 specifies jitter tolerance frequency masks Category Category interfaces. STS-1 rate-Bellcore GR253 specifies jitter tolerance.
STS-1 jitter tolerance differs from requirements only Category interfaces.
NOTE:
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M28335 Data Sheet
Functional Description
Figure 2-10. Minimum Jitter Tolerance Requirement
Rate
Input Jitter Amplitude
Jitter Frequency
STS-1 Rates
STS-1 Category Category
Input Jitter Amplitude
Jitter Frequency
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Functional Description
M28335 Data Sheet
2.5.1
Jitter Transfer
receiver must meet certain jitter transfer specifications between input output jitter function frequency. These specifications only intended with jitter attenuator. Because M28335 does contain jitter attenuator, must supplied externally. reference purposes, specifications discussed following documents illustrated Figure 2-11. rate-Assume same DS3. rate-Bellcore GR499, section 7.3.2 figures 7-3, 7-4, 7-5, defines describes jitter transfer. STS-1 rate-Bellcore GR253, section 5.6.2.1, defines describes jitter transfer STS-1 rate.
Figure 2-11. Maximum Jitter Transfer Curve Requirement
Jitter Gain -19.9
STS-1 Category Category Category (Note: slopes dB/decade)
Jitter Frequency
500020_017
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M28335 Data Sheet
Functional Description
2.6.1
Additional M28335 Functions
Bias Generator
four RBIAS resistors used convert internal current references into accurate voltage references used internal voltage biasing. RBIAS resistors ensure that internal voltage references kept within tight tolerance. 12.1 external resistors from RBIAS pins ground specified have tolerance ±1%. This ensures tight control internal voltage references.
NOTE:
Refer Section 4.5.2 RBIAS resistor placement.
2.6.2
External Reset
hardware mode, system cannot guarantee valid REFCLK frequency input during power-on reset (POR) cycle, M28335 requires assertion external reset signal (RESET) after power-up. Valid frequencies REFCLK (44.736 ppm), (34.368 ppm) STS-1 (51.84 ppm). serial mode, external reset should always performed after power-up.
2.6.3
Power-On Reset (POR)
circuit provided device initialize resettable digital logic analog control lines used hardware mode operation (Registers, interrupt, status used bus/serial mode operation require external reset after power-up). circuit uses fixed timer (~1µs) deassert itself soon power supply voltage reaches minimum level When minimum supply voltage reached (see Table 2-9), REFCLK input counted clocks before internal reset deasserted. this time receiver block attempts frequency lock onto valid incoming REFCLK input. After frequency lock achieved, receiver attempts phase lock onto valid RLINE receive signal.
NOTE:
valid REFCLK input present when releases internal reset, receiver block unable lock RLINE receive signal. common some types crystal oscillators oscillate lower fundamental frequency crystal oscillator supply reached minimum operational voltage.
NOTE:
external reset should always performed after power-up when using device serial mode.
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Functional Description
M28335 Data Sheet
2.6.4
Interrupt
Each RLOS TLOS signal goes dedicated edge-detector, whose output stored flip-flop Each interrupt dedicated enable register with which specific interrupt sources activated. interrupt register outputs ORed together generate global interrupt value, which read Global register Global Interrupt signal also enable register Global register, which activates routing global interrupt interrupt pin. Interrupt Status register contents read through parallel serial interface. read interrupt register should clear register, should leave others untouched.
2.6.5
Loopback Multiplexers (MUXes)
loopback MUXes channel M28335 allow local loopback (terminal framer side), remote loopback (cable side), both. RLOS signal monitors cable inputs irrespective loopback. Remote Loopback (RLOOP) controlled Portn Control register. RLOOP, receive data (retimed after clock recovery decoded) loops back into pulse shaper place transmit data. Additionally, this data sent RPOS, RNEG, RCLK pins. Local Loopback (LLOOP) controlled Portn Control register. LLOOP, transmit data loops back immediately from encoder output decoder input place received data. Additionally, this data sent TLINEP TLINEM/N pins.
NOTE: During transmit operation, data local loopback will overwritten with pattern. operation does affect remote loopback.
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M28335 Data Sheet
Functional Description
Figure 2-12. Remote Loopback Diagram
XOE1 LBO1 E3MODE1 PDB1 TPOS TNEG TCLK TAIS Monitor TMONP TMONM TXMON TMONTST REFCLK
PDATA NDATA Clock/ DATCLK Data RLOSMAX RLOSTHR Recovery RLOSMDIS
Encoder
PDATA/ NDATA
Pulse Shaper
Line Driver
TLINEP TLINEM/N
TCLK
RLOOP1 LLOOP1
Data
RPOS RNEG RCLK RLOS
ENDECDIS1
Receiver
Decoder
RLINEP RLINEM/N REQH1
ALOS
Figure 2-13. Local Loopback Diagram
XOE1 LBO1 E3MODE1 PDB1 TPOS TNEG TCLK TAIS Monitor TMONP TMONM TXMON TMONTST REFCLK
PDATA NDATA Clock/ DATCLK Data RLOSMAX RLOSTHR Recovery RLOSMDIS
Encoder
PDATA/ NDATA
Pulse Shaper
Line Driver
TLINEP TLINEM/N
TCLK
RLOOP1 LLOOP1
Data
RPOS RNEG RCLK RLOS
ENDECDIS1
Receiver
Decoder
RLINEP RLINEM/N REQH1
ALOS
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Functional Description
M28335 Data Sheet
Mechanical Specifications
Figure 2-14. M28335 Mechanical Drawing TBGA)-Dimensions
0.10 Corner Reference Mark
0.35 Chamfer Places) DETAIL
BOTTOM VIEW VIEW DETAIL
SIDE VIEW DIMENSIONAL REFERENCES MIN. NOM. MAX. 1.25 1.40 1.55 0.40 0.50 0.60 34.80 35.00 35.20 33.00 (BSC.) 34.80 35.00 33.00 (BSC.) 0.63 0.90 0.15 0.25 1.00 TYP. 0.35 0.15
500020_018a
00.30 00.10
REF.
35.20
DETAIL
0.50 0.85
0.75 0.95
DETAIL
NOTES FOLLOWING PAGE
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M28335 Data Sheet
Functional Description
Notes Figure 2-14 previous page: dimensions millimeters. represents basic solder ball grid pitch. represents basic solder ball matrix size, symbol maximum number balls after depopulating. measured maximum solder ball diameter after reflow parallel primary datum Dimension "aaa" measured parallel primary datum Primary datum
seating plane defined spherical
crowns solder balls. Package surface shall black oxide. Cavity depth varies with thickness. Substrate material base copper. Bilateral tolerance zone applied each side package body. degree 0.35 chamfer corner identification. Encapsulant size vary with size. Refer ASME Y14.5M-1994 standard dimensioning tolerance.
2.7.1
Moisture Sensitivity
device meets moisture sensitivity level (MSL)
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Mindspeed Technologies
2-23
Functional Description
M28335 Data Sheet
2.8.1
Electrical/Thermal Characteristics
Absolute Maximum Ratings
Table 2-7. Absolute Maximum Ratings Symbol
DVDD/ RVDD/ TVDD/ TVSOL
Parameter
Power supply voltage
-0.3
Unit
Voltage signal Storage temperature Vapor phase soldering temperature min.) Ambient operating temperature Thermal resistance (Junction-Ambient) Thermal resistance (Junction-Case) Maximum Case Temperature Junction temperature
-1.0
°C/W °C/W
GENERAL NOTE:
Stresses above those listed absolute maximum ratings cause permanent damage device. This stress rating only, functional operation device these other conditions beyond those indicated other sections this document implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
2.8.2
Ratings
Testing Method-The devices were subjected events rated voltage with both positive negative polarities relative each other supply domain device. given then curve-traced detect leaky shorted diodes. criterion passing three devices that withstand voltage without leaky pins functional failures.
Table 2-8. Ratings Model
Human Body Charged Device
Observed Minimum
2,500
2.8.3
Recommended Operating Conditions
Table lists various operating conditions, power supplies, bias resistor.
2-24
Mindspeed Technologies
28335-DSH-001-B
M28335 Data Sheet
Functional Description
Table 2-9. Recommended Operating Conditions Parameter
Power supply voltage voltage(1,
Conditions
DVDD, RVDD, TVDD RBIAS GND;
3.135 3.135 11.98
12.1
3.465 12.22
Unit
External bias resistor
FOOTNOTE:
With logic input, should tied With logic input, should tied must equal greater than power supply voltage (DVDD, RVDD, TVDD). must sequenced with respect (DVDD, RVDD, TVDD) discussed Appendix
2.8.4
Characteristics
Table 2-10. Characteristics Parameter
high threshold threshold high threshold threshold ILEAK (digital inputs outputs) ILEAK (RLINExP, RLINExM,
TLINExP, TLINExM)
Conditions
Digital inputs Digital inputs Digital outputs, Digital outputs, digital
-0.3 -270
3.72 3.52 3.15
4.00 3.86 3.65
Unit
ILEAK (TMONxP, TMONxM) Input capacitance Load capacitance Power dissipation (total chip) Digital inputs Digital outputs STS1
GENERAL NOTE:
digital inputs V-compliant when VGG=5V. These inputs diode protected pin. Additionally, digital inputs contain pull-down resistors. digital outputs also V-compliant when VGG=5V. However, these outputs will drive will they accept external pull-ups. Power dissipation pattern with ports active.
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Mindspeed Technologies
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Functional Description
M28335 Data Sheet
2.8.5
Electrical Characteristics
Table 2-11. Receiver Characteristics Parameter
Receiver Sensitivity Intrinsic Jitter (all "1's" pattern) Remote Loopback Jitter Tolerance Jitter Frequency Jitter Tolerance Jitter Frequency Jitter Tolerance Jitter Frequency Jitter Tolerance Jitter Frequency (Cat Limited test equipment capabilities.
1275 0.005 >64* >64*
Unit
Feet
2.8.6
Electrical Characteristics
Table 2-12. Receiver Characteristics Parameter
Receiver Sensitivity (length cable) Interference Margin Intrinsic Jitter (all "1's" pattern) Remote Loopback Jitter Tolerance Jitter Frequency Jitter Tolerance Jitter Frequency Jitter Tolerance Jitter Frequency Jitter Tolerance Jitter Frequency Limited test equipment capabilities.
1275
Unit
Feet
0.010 >64* >64*
2.8.7
STS-1 Electrical Characteristics
Table 2-13. STS-1 Receiver Characteristics Parameter
Receiver Sensitivity Intrinsic Jitter (all "1's" pattern) Remote Loopback Jitter Tolerance Jitter Frequency Jitter Tolerance Jitter Frequency Jitter Tolerance Jitter Frequency Jitter Tolerance Jitter Frequency Limited test equipment capabilities.
1200 0.005 >64* >64*
Unit
Feet
2-26
Mindspeed Technologies
28335-DSH-001-B
M28335 Data Sheet
Functional Description
2.8.8
Characteristics
Table 2-14. Characteristics (Logic Timing) Parameter
Tosym, Tisym RCLK TCLK Clock Duty Cycle DS-3 STS-1 Towidth/Tosym, RCLK Tiwidth/Tisym, TCLK Tiwidth/Tisym, REFCLK TPOS/TNRZ, TNEG, TAIS TPOS/TNRZ, TNEG, TAIS
Conditions
29.10 22.35 19.29
Unit
3.50 2.50
Todelay Tisetup Tihold Trise Tfall
GENERAL NOTE:
2.22 1.28
description applies DS3, STS-1 clock rates other parameters such pulse width, set-up time, hold time, duty cycle. timing diagram, illustrated Figure 2-15, describes logical relationship between various clock data signals, parameter values.
Figure 2-15. Timing Diagram
Tosym
DATA OUTPUTS
RCLK
Towidth
Tfall RPOS/RNRZ, RNEG/RLCV
Trise
Todelay
Tisym
DATA INPUTS
TCLK Tiwidth
Tisetup TPOS/TNRZ, TNEG, TAIS,
Tihold
Don't Care
Valid Data
Don't Care
500020_020 07-24-02
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Mindspeed Technologies
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Functional Description
M28335 Data Sheet
Table 2-15. Mode Timing-Read Cycles Parameter
TAZD tdis tpwh tpwl Address valid data valid Address hold after BCS~ BOE~ rising edge BCS~ BOE~ falling edge BDATA drive BDATA hold after BCS~ BOE~ rising edge BCS~ BOE~ high time BCS~ BOE~ time
Description
Figure 2-16. Mode Read Timing
tAZD BADDR[4:0] Address Read Data
tdis
BDATA[7:0]
BWR~ tpwh BCS~ BOE~
500020_026
tpwl
2-28
Mindspeed Technologies
28335-DSH-001-B
M28335 Data Sheet
Functional Description
Table 2-16. Mode Timing-Write Cycles Parameter
tpwh tpwl
Description
Address setup before BCS~ BWR~ rising edge Address hold after BCS~ BWR~ rising edge Data setup before BCS~ BWR~ rising edge Data hold after BCS~ BWR~ rising edge BCS~ BWR~ high time BCS~ &BWR~ time
Type
Figure 2-17. Mode Write Timing
tAZD BADDR[4:0] Address BDATA[7:0] tpwh BCS~ BWR~ BOE~ tpwl Write Data
(high)
500020_027
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Mindspeed Technologies
2-29
Functional Description
M28335 Data Sheet
Table 2-17. Serial Mode Timing Symbol
Tcssu PWsch PWscl Tsisu Tsihf Tvsif Tsiz PWcsi Tcsur
Parameter
BCS~ set-up time SCLK rising edge Pulse width SCLK high Pulse width SCLK SCLK rising edge set-up time SCLK rising edge hold time SCLK falling edge valid time BCS~ inactive three-state Pulse width BCS~ inactive SCLK rising edge BCS~ hold time
Unit
Figure 2-18. Serial Mode Register Read (see Note below)
PWcsi BCS~ Tcssu SCLK Tsihf Tsisu Write
PWsch PWscl
Tcsur
SDIN
50020_038A
Figure 2-19. Serial Mode Register Write (see Note below)
PWcsi BCS~ Tcssu SCLK Tsihf Tsisu Read
PWscl PWsch
SDIN
Address
Tvsif SDOUT
Read Data
Tsiz
50020_037
NOTE:
Serial mode, BDATA1/PORTMODE2/SDIN configured SDIN BDATA0/PORTMODE1/SDOUT configured SDOUT BOE~/LMODE0/SCLK configured SCLK
2-30
Mindspeed Technologies
28335-DSH-001-B
Registers
Address
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 00x9 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19
Address
Name
PC10 PC11 PC12 RMTR1 RMTR2 RMTR3 RALM1 RALM2 TALM1 TALM2 RISR1 RISR2 TISR1 TISR2 RIER1 RIER2
Table 3-1. Register Address Map(1 Description
Global Control Register Port1 Control Register Port2 Control Register Port3 Control Register Port4 Control Register Port5 Control Register Port6 Control Register Port7 Control Register Port8 Control Register Port9 Control Register Port10 Control Register Port11 Control Register Port12 Control Register RLOS Max/Threshold Register RLOS Max/Threshold Register RLOS Max/Threshold Register RLOS Alarm Register RLOS Alarm Register TLOS Alarm Register TLOS Alarm Register RLOS Interrupt Status Register RLOS Interrupt Status Register TLOS Interrupt Status Register TLOS Interrupt Status Register RLOS Interrupt Enable Register RLOS Interrupt Enable Register
Default
0x00 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x00 0x00 0x00 0x00 0x00
28335-DSH-001-B
Mindspeed Technologies
Registers
M28335 Data Sheet
Table 3-1. Register Address Map(2 Address
0x1A 0x1B 0x1C 0x1D
Name
TIER1 TIER2 RDR1 RDR2
Description
TLOS Interrupt Enable Register TLOS Interrupt Enable Register RLOS Data Squelch Disable Register RLOS Data Squelch Disable Register
Default
0x00 0x00 0x00 0x00
Global Register
0x0-Global Control Register (GC)
Name Default
BINTR
BINTR
Reserved
TMONTST
INTEN
RESET
Interrupt Status alarm interrupt pending more alarm interrupt pending
NOTE: BINTR different from hardware BINTR~ because BINTR~ masked INTEN bit.
RESERVED
Reserved This reserved internal testing should kept normal operation. Monitor Test Normal operation TLOS Asserts TLOS outputs; this used test board-level functionality downstream from TLOS outputs Interrupt Enable Open drain BINTR~ held inactive BINTR propagates BINTR~ pin.
NOTE: BINTR~ active low.
TMONTST
INTEN
RESET
Software reset Setting software reset initializes resettable digital logic analog control lines. register bits, except reset bit, will initialized default state. device will stay reset until reset cleared.
NOTE: Performing hardware reset reset will clear software reset bit.
Mindspeed Technologies
28335-DSH-001-B
M28335 Data Sheet
Registers
Port Registers
0x1-0xC-Portn Control Register (PCn)
Name Default
ENDECDIS
ENCDECDIS
RLOOP
LLOOP
REQH
Encoder/Decoder Disable Device accepts data TNRZ (TPOS) outputs decoded single-ended data RNRZ (RPOS) Device accepts bipolar AMI/B3ZS/HDB3 data TPOS/TNEG outputs receive bipolar data RPOS/RNEG Line Build Line Build disabled (used transmit cable lengths feet) Line Build enabled (used transmit cable lengths feet) Port Power-down Transmitter receiver this port disabled. alarms (RLOS TLOS) from powered down port will read back loss signal). interrupt will generated while port powered down. interrupts enabled, interrupt will generated during port power down (PD~ transitions from high low) there loss signal port while port being powered down. Similarly interrupt will also generated during power (PD~ transitions from high) there loss signal port while port being powered Normal operation Remote Loopback Normal operation Remote Loopback enabled this port Local Loop Back Normal operation Local Loopback enabled this port Receive Equalizer High Receive Equalizer forced gain. Used mode operation correctly receive square pulses. Used normal operation. This setting recommended mode over-equalize received signal. Mode DS3/STS-1 mode mode Transmit Output Enable Transmit output disabled Transmit output enabled
RLOOP
LLOOP
REQH
28335-DSH-001-B
Mindspeed Technologies
Registers
M28335 Data Sheet
Alarm Registers
Alarm Registers provide real time status Receive Loss Signal (RLOS) alarms Transmit Loss Signal (TLOS) alarms.
0x10-RLOS Alarm Register (RALMR1)
Name
RALMn
RALM8
RALM7
RALM6
RALM5
RALM4
RALM3
RALM2
RALM1
Receive Loss Signal Alarm status Loss Signal Loss Signal Alarm
0x11-RLOS Alarm Register (RALMR2)
Name
RALMn
RALM12
RALM11
RALM10
RALM9
Receive Loss Signal Alarm status Loss Signal Loss Signal Alarm
0x12-TLOS Alarm Register (TALMR1)
Name
TALMn
TALM8
TALM7
TALM6
TALM5
TALM4
TALM3
TALM2
TALM1
Transmit Loss Signal Alarm status Loss Signal Loss Signal Alarm
0x13-TLOS Alarm Register (TALMR2)
Name
TALMn
TALM12
TALM11
TALM10
TALM9
Transmit Loss Signal Alarm status Loss Signal Loss Signal Alarm
Mindspeed Technologies
28335-DSH-001-B
M28335 Data Sheet
Registers
Interrupt Status Registers
appropriate Loss Signal (RLOS/TLOS) interrupt status when corresponding loss signal alarm (goes from inactive active) cleared (goes from active inactive). interrupt status bits cleared when register read.
0x14-RLOS Interrupt Status Register (RISR1)
Name
RISn
RIS8
RIS7
RIS6
RIS5
RIS4
RIS3
RIS2
RIS1
Receive Loss Signal (RLOS) Interrupt status RLOS interrupt pending RLOS interrupt pending
0x15-RLOS Interrupt Status Register (RISR2)
Name
RISn
RIS12
RIS11
RIS10
RIS9
RLOS Interrupt status RLOS interrupt pending RLOS interrupt pending
0x16-TLOS Interrupt Status Register (TISR1)
Name
TISn
TIS8
TIS7
TIS6
TIS5
TIS4
TIS3
TIS2
TIS1
Transmit Loss Signal (TLOS) Interrupt status TLOS interrupt pending TLOS interrupt pending
0x17-TLOS Interrupt Status Register (TISR2)
Name
TISn
TIS12
TIS11
TIS10
TIS9
TLOS Interrupt status TLOS interrupt pending TLOS interrupt pending
28335-DSH-001-B
Mindspeed Technologies
Registers
M28335 Data Sheet
Interrupt Enable Registers
Setting appropriate RLOS/TLOS Interrupt Enable will allow corresponding interrupt status register propagate BINTR Global Control Register. INTEN Global Control Register, BINTR will propagate BINTR~ pin.
0x18-RLOS Interrupt Enable Register (RIER1)
Name Default
RIEn
RIE8
RIE7
RIE6
RIE5
RIE4
RIE3
RIE2
RIE1
RLOS Interrupt enable RLOS interrupt disabled RLOS interrupt enabled
0x19-RLOS Interrupt Enable Register (RIER2)
Name Default
RIEn
RIE12
RIE11
RIE10
RIE9
RLOS Interrupt enable RLOS interrupt disabled RLOS interrupt enabled
0x1A-TLOS Interrupt Enable Register (TIER1)
Name Default
TIEn
TIE8
TIE7
TIE6
TIE5
TIE4
TIE3
TIE2
TIE1
TLOS Interrupt enable TLOS interrupt disabled TLOS interrupt enabled
0x1B-TLOS Interrupt Enable Register (TIER2)
Name Default
TIEn
TIE12
TIE11
TIE10
TIE9
TLOS Interrupt enable TLOS interrupt disabled TLOS interrupt enabled
Mindspeed Technologies
28335-DSH-001-B
M28335 Data Sheet
Registers
RLOS Threshold Control Registers
0x0D-RMTR1 (RLOS Threshold Register
Name Default
RMn&RTn
RLOS Maximum RLOS Threshold Table RLOS threshold control bits.
0x0E-RMTR2 (RLOS Threshold Register
Name Default
RMn&RTn
RLOS Maximum RLOS Threshold Table RLOS threshold control bits.
0x0F-RMTR3 (RLOS Threshold Register
Name Default
RMn&RTn
RM12
RT12
RM11
RT11
RM10
RT10
RLOS Maximum RLOS Threshold Table RLOS threshold control bits.
28335-DSH-001-B
Mindspeed Technologies
Registers
M28335 Data Sheet
RLOS Data Squelch Disable Registers
0x1C-RDR1 (RLOS Disable Register
Name Default
RLOS disable RLOS auto data squelch enabled RLOS data squelch disabled
0x1D-RDR2 (RLOS Disable Register
Name Default
RD12
RD11
RD10
RLOS disable RLOS auto data squelch enabled RLOS data squelch disabled
Mindspeed Technologies
28335-DSH-001-B
Applications
M28335 used variety applications.
Line Interface Example
Figure illustrates example line being terminated M28335. data clock extracted passed framer chip further data manipulation user interface. important employ high-frequency design techniques printed board layout.
Figure 4-1. Line Interface Example
M28335
TPOS TNEG TCLK TMONP TLINEP TLINEN TMONM 37.4 0.01µF Type 728, 734, Type 728, 734,
Framer
Channel
RPOS RNEG RCLK RLINEP RLINEN
37.4
Only Channel Shown
GENERAL NOTE:
500020_025
transformers part number T3001 from Pulse Technology. Recommended Vendors, Section 4.5.6. TMONP TMONM denoted dotted lines.
28335-DSH-001-B
Mindspeed Technologies
Applications
M28335 Data Sheet
Interface Example CX28365 Mode
M28335 interfaced CX28365 T3/E3 Framer Cell Delineator without glue logic illustrated Figure 4-2. M28335 configured mode provide more flexible control. line Framer/ Delineator OutPort2 configured provide "Chip-Select" M28335. line InPort1 Framer/Delineator configured interrupt input receive interrupt from M28335. BADD BDATA M28335 located processor address data respectively. TLOS RLOS status accessed through M28335's internal registers. TLOS RLOS hardware status from M28335 used drive LEDs provide real-time display status lines, they used further status processing.
Figure 4-2. Interface CX28365 Mode
M28335 M28335 T3/E3/STS-1 T3/E3/STS-1
BDATA[7:0]
Processor Data
CX28365 M28365 T3/E3 Framer T3/E3 Framer Cell Delineator Cell Delineator
MData[7:0]
Processor Address
BADD[4:0]
Processor Control
MAddr[12:0]
BWR~ BOE~
MWR~ MOE~
BCS~ BINTR~
OutPort2[0] InPort1[0]
BMODE1 BMODE0
Note: BMODE0 internal pulldown. left disconnected grounded.
500020_036
Mindspeed Technologies
28335-DSH-001-B
M28335 Data Sheet
Applications
Interface Example CX28365 Hardware Mode
M28335 interfaced CX28365 T3/E3 Framer Cell Delineator hardware mode illustrated Figure 4-3. OutPort1 Framer/ Delineator configured output control twelve PORTMODE lines M28335. Three OutPort2 lines Framer/Delineator configured output handle global remote loop back chip-wide mode controls. InPort1 InPort2 configured input monitor RLOS TLOS from M28335.
Figure 4-3. Interface CX28365 Hardware Mode
M28335 CX28335 T3/E3/STS-1 T3/E3/STS-1
PORTMODE1 PORTMODE2 PORTMODE3 PORTMODE4 PORTMODE5 PORTMODE6 PORTMODE7 PORTMODE8 PORTMODE9 PORTMODE10 PORTMODE11 PORTMODE12 LMODE0 LMODE1 GRLOOP
CX28365 CX28365 T3/E3 Framer T3/E3 Framer Cell Delineator Cell Delineator
OutPort1[0] OutPort1[1] OutPort1[2] OutPort1[3] OutPort1[4] OutPort1[5] OutPort1[6] OutPort1[7] OutPort1[8] OutPort1[9] OutPort1[10] OutPort1[11] OutPort2[0] OutPort2[1] OutPort2[2] InPort1[11:0] InPort2[11:0]
BMODE0 BMODE1
RLOS[11:0] TLOS[11:0]
Note: BMODE0 internal pulldown. left disconnected grounded.
500020_035
28335-DSH-001-B
Mindspeed Technologies
Applications
M28335 Data Sheet
Serial Mode Interface Example
M28335 interfaced microprocessor microcontroller that supports Serial Peripheral Interface (SPI) shown Figure 4-4. microprocessor/ microcontroller working master. generates SPICLK that shifts data from M28335 SDOUT Master Slave (SPIMISO) shifts data M28335 SDIN through Master Out, Slave (SPIMOSI) pin. microprocessor/microcontroller also provides chip-select function receives interrupt from M28335.
Figure 4-4. Serial Mode Interface Example
M28335 M28335 T3/E3/STS-1 T3/E3/STS-1
Microprocessor/ Microprocessor/ Controller Controller
SCLK SDIN SDOUT BCS~ BINTR~
SPICLK SPIMOSI SPIMISO CHIP_SELECT INTERRUPT
BMODE1 BMODE0
500020_034
Mindspeed Technologies
28335-DSH-001-B
M28335 Data Sheet
Applications
Design Considerations M28335
M28335 mixed signal 12-port device operating frequencies 51.84 MHz. This calls careful design layout. Some design considerations outlined below.
4.5.1
Power Supply Ground Plane
single power plane with bulk capacitors (typically distributed throughout board will mitigate most power rail-related voltage transients. bulk capacitor should also placed where power enters board. Because this M28335 BGA, routing decoupling capacitors power pins very difficult. recommended that that decoupling capacitors only routed directly power they placed within inch pin. Decoupling capacitors should dispersed around outside chip side underneath chip bottom side board. recommended that 0.01 0.001 decoupling capacitors used. three values required each pin, values should dispersed uniformly filter different frequencies noise. tantalum capacitors should placed four corners chip. continuous ground plane best minimize ground impedance. Most ground noise produced return currents power supply transients during switching. This effect minimized reducing ground plane impedance.
4.5.2
4.5.2.1
Component Placement
RBIAS Resistor
important keep RBAIS pins quiet, noise coupled these pins affect internal references. RBIAS resistors should placed close possible RBIAS pins digital signals should routed near pins resistors. Additionally, would wise guard pin, resistor, traces with ground vias.
4.5.2.2
Decoupling
recommended that decoupled with 0.01 0.001 capacitors. These capacitors should placed close pin.
4.5.2.3
Termination Resistors Capacitors
termination resistors capacitors receive RLINE pins should placed close receiver input chip possible. series resistors transmit TLINE pins should also placed close transmitter output pins possible, less priority then RLINE.
28335-DSH-001-B
Mindspeed Technologies
Applications
M28335 Data Sheet
Figure 4-5. TX/RX Terminations
TMONP TLINEP
Transformer
TLINEM TMONM RLINEP 0.01 From Transformer 37.4 37.4
RLINEM
4.5.3
Impedance Matching
critical that both transmit receive traces around transformers matching resistors kept minimum length that trace impedance matched ohms. transmit signals should routed both differentially single ended. Between device transformer signals should routed differentially. signals should routed single ended between transformer connector. receive signals should routed differentially between transformers either differentially single ended from transformers connectors, depending application. application requires ground termination recommended that signals routed single ended. application does require ground termination, then signals routed differentially. route signals differentially, signal pair (positive negative) should coupled should surrounded solid power/ground planes (buried strip line) coupled power/ground plane (microstrip). Buried strip line recommended internal layers while microstrip line used signals routed surface layers. There should discontinuity planes during path signal traces. Single ended signals should coupled between power/ground planes inner layers coupled power/ground plane outer layers. There should discontinuities power/ground planes over trace path. Impedance discontinuities occur when signal passes through vias travels between layers. recommended minimize number vias layers that transmit/receive signals travel through design.
Mindspeed Technologies
28335-DSH-001-B
M28335 Data Sheet
Applications
4.5.4
Other Passive Parts
Mindspeed recommends transformers coupling connectors device. M28335 uses Pulse Tx3051 transformer) devices handle channels. recommended that tantalum capacitor used where power enters board.
4.5.5
IBIS Models
IBIS (Input/Output Buffer Interface Specification) models M28335 available from Mindspeed's site (www.Mindspeed.com).
4.5.6
Recommended Vendors
Product: Transformers Product: Crystals Crystek Corp. 12730 Commonwealth Drive Fort Myers, 33913 800-237-3061 941-561-1025 sales@crystek.com www.crystek.com
America Address:
Tel: Fax: Northern Asia
Pulse Corporate Office 12220 World Trade Drive Diego, 92128 858-674-8100 858-674-8262 Pulse 3F-4, Sec. Hsin Road Hsi-Chih Tapei Hsien, Taiwan R.O.C. 886-2-26980228 886-2-26980948 Pulse Huxley Road Surrey Research Park Guildford, Surrey United Kingdom 44-1483-401700 44-1483-401701
Tel: Fax: E-mail: site:
Tel: Northern Europe
Tel: Fax:
28335-DSH-001-B
Mindspeed Technologies
Applications
M28335 Data Sheet
Mindspeed Technologies
28335-DSH-001-B
Appendix Applicable Standards
applicable standards documents follows:
ANSI T1.102-1993 (DS3 STS-1 standard) ANSI T1.404a-1996 (DS3 metallic interface) Recommendation G.703 (DS3 standard) Recommendation G.823 G.824 (jitter wander) Bellcore GR499, Issue 12/89 (formerly TR-TSY-000499) (DS3 STS-1 requirements) Bellcore GR253, Issue 12/91 (formerly TA-NWT-000253) (STS-1 requirements jitter) Bellcore TR-TSY-000191, Issue 5/86 (AIS LOS) ETSI TBR24 TBR25 terminal equipment interface) ETSI standard) AT&T Technical Reference TR54014, 1992 (Accunet Interface Specification DS-3 jitter only)
28335-DSH-001-B
Mindspeed Technologies
Applicable Standards
M28335 Data Sheet
Mindspeed Technologies
28335-DSH-001-B
Appendix Power Sequencing
When operated power-up power-down sequencing (DVDD, RVDD, TVDD) must conform diagrams below (See note below). seen, must higher than 3.6V lower than 0.5V
NOTE:
exceed 10%) short durations less than must never less than more than 0.5V.
Figure B-1. Power sequence VDD.
VGGmax
3.6V Max. 3.6V Max. 0.5V Max. 3.6V Max. 0.5V Max. 3.6V Max.
VGGmin
5.5V Max.
Time
Figure B-2. Power-down sequence VDD.
VGGmax
3.6V Max.
VGGmin
5.5V Max. 0.5V Max.
3.6V Max. 3.6V Max. 3.6V Max. 0.5V Max.
Time
28335-DSH-001-B
Mindspeed Technologies
Power Sequencing
M28335 Data Sheet
Mindspeed Technologies
28335-DSH-001-B
www.mindspeed.com (949) 579-3000 Headquarters Newport Beach 4000 MacArthur Blvd., East Tower Newport Beach, 92660
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