UM012811-0904 ZiLOG Worldwide Headquarters Race Street Jose, 9512
|
|
|
Top Searches for this datasheet
UM012811-0904
ZiLOG Worldwide Headquarters Race Street Jose, 95126-3432 Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com
This publication subject replacement later edition. determine whether later edition exists, request copies publications, contact:
ZiLOG Worldwide Headquarters Race Street Jose, 95126-3432 Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com
Document Disclaimer
ZiLOG registered trademark ZiLOG Inc. United States other countries. other products and/or service names mentioned herein trademarks companies with which they associated. ©2004 ZiLOG, Inc. rights reserved. Information this publication concerning devices, applications, technology described intended suggest possible uses superseded. ZiLOG, INC. DOES ASSUME LIABILITY PROVIDE REPRESENTATION ACCURACY INFORMATION, DEVICES, TECHNOLOGY DESCRIBED THIS DOCUMENT. ZiLOG ALSO DOES ASSUME LIABILITY INTELLECTUAL PROPERTY INFRINGEMENT RELATED MANNER INFORMATION, DEVICES, TECHNOLOGY DESCRIBED HEREIN OTHERWISE. Devices sold ZiLOG, Inc. covered warranty limitation liability provisions appearing ZiLOG, Inc. Terms Conditions Sale. ZiLOG, Inc. makes warranty merchantability fitness purpose Except with express written approval ZiLOG, information, devices, technology critical components life support systems authorized. licenses conveyed, implicitly otherwise, this document under intellectual property rights.
UM012811-0904
Discliamer
Table Contents
Table Contents List Figures List Tables Manual Objectives Architectural Overview Features Processor Description Fetch Unit Instruction State Machine Program Counter CONTROL REGISTERS Compatibility Overview Assembly Language Compatibility Instructions Relocation Control Registers Stack Pointer Compatibility Reset Compatibility Interrupt Compatibility Address Space Introduction Register File Program Memory Data Memory Stacks Addressing Modes Introduction Register Addressing Indirect Register Addressing (IR) Indexed Addressing Direct Addressing (DA) Relative Addressing (RA) Immediate Data Addressing (IM)
UM012811-0904
Table Contents
Interrupts. Introduction Interrupt Enable Disable Interrupt Priority Vectored Interrupt Processing Nesting Vectored Interrupts Polled Interrupt Processing Software Interrupt Generation Illegal Instruction Traps. Description Instruction Summary. Assembly Language Programming Introduction Assembly Language Syntax Instruction Notation Instruction Classes Instruction Summary Instruction Description Opcode Maps Opcodes Listed Numerically Assembly Object Code Example Index.
UM012811-0904
Table Contents
List Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Block Diagram Flags Register Register File Organization Working Register Addressing Example 16-Bit Register Pair Addressing Addressing Example Stack Operations Register Addressing Using 12-Bit Addresses Register Addressing Using 8-Bit Addresses Register Addressing Using 4-Bit Addresses Indirect Register Addressing Register File Indirect Register Addressing Program Data Memory Indexed Register Addressing Direct Addressing Relative Addressing Immediate Data Addressing Effects Interrupt Stack Interrupt Vectoring Program Memory Example Example Instruction Description Operand Description BTJNZ Operand Description BTJZ Operand Description Opcode Cell Description
UM012811-0904
List Figures
List Tables
Table Control Registers Table Condition Codes Table Function Instructions Table Extended Addressing Instructions Table Instructions with Opcodes Table Control Registers Table Program Memory Example Table Assembly Language Syntax Example Table Assembly Language Syntax Example Table Notational Shorthand Table Additional Symbols Table Arithmetic Instructions Table Manipulation Instructions Table Block Transfer Instructions Table Control Instructions Table Logical Instructions Table Load Instructions Table Program Control Instructions Table Rotate Shift Instructions Table Instruction Summary Table Operation Instruction Table Opcode Abbreviations Table Instructions Sorted Opcode Table Assembly Object Code Example
UM012811-0904
List Tables
Manual Objectives
This user manual describes architecture instruction CPU.
About This Manual
ZiLOG recommends that user read understand everything this manual before setting using product. However, recognize that there different styles learning. Therefore, have designed this manual used either procedural manual reference guide important data.
Intended Audience
This document written ZiLOG customers experienced working with microprocessors writing assembly code compilers.
Manual Organization
User Manual divided into sections; each section details specific topic about product. Architectural Overview Presents overview CPU's features benefits, description architecture. Compatibility Provides information users familiar with programming ZiLOG's classic planning existing code with CPU. Address Space Describes three address spaces accessible Register File, Program Memory, Data Memory.
UM012811-0904
Manual Objectives
viii
Addressing Modes Details CPU's addressing modes:
Register Indirect Register (IR) Indexed Direct (DA) Relative (RA) Immediate Data (IM) Extended Register (ER)
Interrupts Describes operation response interrupt requests from either internal peripherals external devices. Illegal Instruction Traps Describes consequences executing undefined opcodes. Instruction Summary Lists assembly language instructions, including mnemonic definitions summary User Manual instruction set. Opcode Maps Presents detailed diagram each opcode table. Opcodes Listed Numerically Provides easy reference locating instructions their opcode. Sample Program Listing sample program shows instructions, using many available memory modes, will translate into object code after assembly.
Manual Conventions
following assumptions conventions adopted provide clarity ease use: Courier Typeface Commands, code lines fragments, bits, equations, hexadecimal addresses, various executable items distinguished from general text Courier typeface.
UM012811-0904
Manual Objectives
Where font indicated, Index, name entity presented upper case.
Example: FLAGS[1] smrf.
Hexadecimal Values Hexadecimal values designated uppercase appear Courier typeface.
Example: F8H.
Brackets square brackets, indicate register bus.
Example: register R1[7:0], 8-bit register, R1[7] most significant bit, R1[0] least significant bit.
Braces curly braces, indicate single register created concatenating some combination smaller registers, buses, individual bits.
Example: 12-bit register address {0H, RP[7:4], R1[3:0]} composed 4-bit hexadecimal value (0H) 4-bit register values taken from Register Pointer (RP) Working Register most significant nibble (4-bit value) 12-bit register, R1[3:0] least significant nibble 12-bit register.
Parentheses parentheses, indicate indirect register address lookup.
Example: (R1) memory location referenced address contained Working Register
Parentheses/Bracket Combinations parentheses, indicate indirect register address lookup square brackets, indicate register bus.
Example: assume PC[15:0] contains value 1234h. (PC[15:0]) then refers contents memory location address 1234h.
Words Set, Reset Clear word implies that register condition contains logical word reset clear implies that register condition contains logical When either these terms followed number, word logical included; however, implied.
UM012811-0904
Manual Objectives
Notation Bits Similar Registers field bits within register designated Register[n:n].
Example: ADDR[15:0] refers bits through Address.
Terms LSB, MSB, lsb, this document, terms MSB, when appearing upper case, mean least significant byte most significant byte, respectively. lowercase forms, msb, mean least significant most significant bit, respectively. Initial Uppercase Letters Initial uppercase letters designate settings, modes, conditions general text.
Example Stop mode. Example receiver forces line Low. Master generate Stop condition abort transfer.
Uppercase Letters uppercase letters designates names states commands.
Example considered BUSY after Start condition. Example START command triggers processing initialization sequence.
Numbering Bits numbered from where indicates total number bits. example, bits register numbered from
Safeguards
important that users understand following safety terms, which defined here. Caution: Indicates procedure file become corrupted user does follow directions.
Trademarks
trademarks ZiLOG, Inc.
UM012811-0904
Manual Objectives
Architectural Overview
FEATURES
ZiLOG's latest 8-bit central processing unit (CPU) designed meet continuing demand faster more code-efficient microcontrollers. executes superset original instruction set. features include:
Direct register-to-register architecture allows each register function accumulator. This improves execution time decreases required program memory. Software stack allows much greater depth subroutine calls interrupts than hardware stacks. Compatible with assembly instruction set. Expanded internal Register File allows access 4KB. instructions improve execution efficiency code developed using higher-level programming languages including Pipelined instruction fetch execution
PROCESSOR DESCRIPTION
contains major functional blocks Fetch Unit Execution Unit. Execution Unit further subdivided into Instruction State Machine, Program Counter, Control Registers, Arithmetic Logic Unit (ALU). Figure illustrates architecture.
UM012811-0904
Architectural Overview
Fetch Unit
Instruction State Machine
Program Counter
Control Registers
Arithmetic Logic Unit
Figure Block Diagram
FETCH UNIT
Fetch Unit controls memory interface. primary function fetch opcodes operands from memory. Fetch Unit also fetches interrupt vectors reads writes memory Program Data Memory. Fetch Unit performs partial decoding opcode determine number bytes fetch operation. Fetch Unit operation sequence follows: Fetch opcode Determine operand size (number bytes) Fetch operands Present opcode operands Instruction State Machine. Fetch Unit pipelined operates semi-independently from rest CPU.
INSTRUCTION STATE MACHINE
Instruction State Machine controller Execution Unit. After initial operation decode Fetch Unit, Instruction State Machine takes over completes instruction. Instruction State Machine performs register read write operations generates addresses.
UM012811-0904
Architectural Overview
Instruction Cycle Time
instruction cycle times vary from instruction instruction, allowing higher performance given specific clock speed. Minimum instruction execution time standard instructions clock cycles (only instruction executes single cycle). Because variation number bytes required different instructions, delay cycles occur between instructions. Delay cycles added time number bytes next instruction exceeds number clock cycles current instruction takes execute. example, executes 2-cycle instruction while fetching 3-byte instruction, delay cycle occurs because Fetch Unit only cycles fetch three bytes. Execution Unit idle during delay cycle.
PROGRAM COUNTER
Program Counter contains 16-bit counter 16-bit adder. Program Counter monitors address current memory address calculates next memory address. Program Counter increments automatically according number bytes fetched Fetch Unit. 16-bit adder increments handles Program Counter jumps relative addressing.
CONTROL REGISTERS
contains four control registers that mapped into Register File address space. These four control registers are:
Stack Pointer High Byte Stack Pointer Byte Register Pointer Flags
register access (4096) bytes register space. products, upper bytes reserved control CPU, on-chip peripherals, ports. control registers always located addresses from FFCH FFFH listed Table page
UM012811-0904
Architectural Overview
Table Control Registers Register Mnemonic FLAGS Address (Hex)
Register Description Flags Register Pointer Stack Pointer High Byte Stack Pointer Byte
Stack Pointer Registers
allows user relocate stack within Register File. stack located addresses from 000H EFFH. 12-bit Stack Pointer value given {SPH[3:0], SPL[7:0]}. Stack Pointer 12-bit increment/decrement capability stack operations, allowing Stack Pointer operate over more than page (256-byte boundary) Register File. Stack Pointer register values undefined after Reset.
Register Pointer
Register Pointer contains address information current Working Register Group Register File Page. Page Pointer lower 4-bits Register Pointer, RP[3:0], points current Page. There sixteen 256-byte Pages available. Working Register Group Pointer upper bits Register Pointer, RP[7:4], points sixteen 16-byte Working Register Groups. There Working Register Groups page. more information Register File, please refer section`'Address Space" page
Flags Register
Flags Register contains status information regarding most recent arithmetic, logical, manipulation rotate shift operation. Flags Register contains bits status information that cleared operations. Four bits tested with conditional jump instructions. flags cannot tested used Binary-Coded Decimal (BCD) arithmetic. remaining bits, User Flags F2), available general-purpose status bits. User Flags unaffected arithmetic operations must cleared instructions. User Flags cannot used with conditional Jumps. They undefined initial power-up unaffected Reset. Figure illustrates flags their positions Flags Register.
UM012811-0904
Architectural Overview
Flags Register User Flags Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag
Figure Flags Register
Interrupts, Software Trap (TRAP) instruction, Illegal Instruction Traps write value Flags Register stack. Executing Interrupt Return (IRET) instruction restores value saved stack into Flags Register. Carry Flag Carry flag when result arithmetic operation generates carry borrow into most significant (Bit data. Otherwise, Carry flag Some rotate shift instructions also affect Carry flag. There three instructions available directly changing value Carry Flag:
Complement Carry Flag (CCF) Reset Carry Flag (RCF) Carry Flag (SCF)
Zero Flag arithmetic logical operations, Zero flag result Otherwise, Zero flag result testing bits register 00H, Zero flag otherwise, Zero flag Also, result rotate shift operation 00H, Zero flag otherwise, Zero flag Sign Flag Sign flag stores value most-significant result following arithmetic, logical, rotate shift operation. signed numbers, uses binary two's complement represent data perform arithmetic operations.
UM012811-0904
Architectural Overview
most significant position (Bit identifies positive number; therefore, Sign flag also most significant position (Bit identifies negative number; therefore, Sign flag also Overflow Flag signed arithmetic, rotate shift operations, Overflow flag when result greater than maximum possible number (>127) less than minimum possible number (<-128) that represented with 8-bits two's complement form. Overflow flag overflow occurs. Following logical operations, Overflow flag Following addition operations, Overflow flag when operands have same sign, result opposite sign. Following subtraction operations, Overflow flag operands opposite sign sign result same sign source. Following rotation operations, Overflow flag sign destination operand changed during rotation. Decimal Adjust Flag Decimal Adjust flag used Binary-Coded Decimal (BCD) arithmetic operations. Because algorithm correcting operations different addition subtraction, this flag specifies type instruction that last executed, enabling subsequent decimal adjust (DA) operation. Normally, Decimal Adjust flag cannot used test condition. After subtraction, Decimal Adjust flag Following addition, Half Carry Flag Half Carry flag when addition generates carry from subtraction generates borrow from instruction converts binary result previous addition subtraction into correct result using Half Carry flag. case Decimal Adjust flag, user does normally access this flag directly.
Condition Codes
flags control operation conditional jump instructions. Sixteen frequently useful functions flag settings encoded 4-bit field called condition code (cc), which forms Bits first opcode conditional jump instructions. Table summarizes condition codes. Some binary condition codes created using more than assembly code mnemonic. result flag test operation determines conditional jump executes.
UM012811-0904
Architectural Overview
Table Condition Codes Assembly Mnemonic Definition Always False Less Than Less Than Equal Unsigned Less Than Equal Overflow Minus Zero Equal Carry Unsigned Less Than
Binary 0000 0001 0010 0011 0100 0101 0110 0110 0111 0111 1000 1001 1010 1011 1100 1101 1110 1110 1111 1111
Flag Test Operation
blank) Always True Greater Than Equal Greater Than Unsigned Greater Than Overflow Plus Non-Zero Equal Carry
Unsigned Greater Than Equal
Arithmetic Logic Unit
Arithmetic Logic Unit (ALU) performs arithmetic logical operations data. arithmetic operations include addition, subtraction, multiplication. logical functions include binary logic operations, shifting, rotation.
Byte Ordering
multi-byte data, stores most significant byte lowest memory address. example, value stored 2-byte (16-bit) number Register
UM012811-0904
Architectural Overview
Pair 122H 123H. value stored 0001H. most-significant byte (00H) stored lowest memory address 122H. least-significant byte (01H) stored higher memory address 123H. This ordering multi-byte data often referred "big endian".
UM012811-0904
Architectural Overview
Compatibility
OVERVIEW
extension improvement ZiLOG's popular, easy-to-use, powerful architecture. Users have experience programming will have difficulty adapting CPU. users will appreciate instructions that improve execution programs developed high-level programming languages such
ASSEMBLY LANGUAGE COMPATIBILITY
executes assembly language instructions other than (WatchDog Timer Enable During HALT Mode opcode 4FH). Users with existing assembly code easily compile their code CPU. assembler available download from www.zilog.com.
INSTRUCTIONS
features many instructions increase processor efficiency allow access expanded Register File. There classes instructions available Function instructions Extended Addressing instructions.
Function Instructions
Table lists instructions that provide functionality.
Table Function Instructions Mnemonic ABCLR BSET BSWAP Instruction Description Atomic Execution Clear Clear Break Swap
UM012811-0904
Compatibility
Table Function Instructions (Continued) Mnemonic BTJNZ BTJZ LDCI MULT TRAP Instruction Description Test Jump Test Jump Non-Zero Test Jump Zero Compare with Carry Load Constant Load Constant Auto-Increment Addresses Load Effective Address 8-bit 8-bit multiply with 16-bit result Shift Right Logical Software Trap
Extended Addressing Instructions
Extended Addressing instructions allow data movement between Register File pages. These instructions allow generation 12-bit address direct access register value Register File address space. Table lists Extended Addressing instructions
Table Extended Addressing Instructions Mnemonic ADCX ADDX ANDX CPCX LDWX POPX PUSHX SBCX SUBX Instruction Description with Carry using Extended Addressing using Extended Addressing Logical using Extended Addressing Compare with Carry using Extended Addressing Compare using Extended Addressing Load Word using Extended Addressing Load using Extended Addressing Logical using Extended Addressing using Extended Addressing Push using Extended Addressing Subtract with Carry using Extended Addressing Subtract using Extended Addressing
UM012811-0904
Compatibility
Table Extended Addressing Instructions (Continued) Mnemonic TCMX XORX Instruction Description Test Complement Under Mask using Extended Addressing Test Under Mask using Extended Addressing Logical using Extended Addressing
Alternate Function Opcode
accommodate instructions, opcode refers second opcode map. pre-pended opcode select alternate functions available second opcode map. CPC, CPCX, SRL, LDWX PUSH (immediate) instructions this second opcode map. Users writing assembly language code employ CPC, CPCX, SRL, LDWX PUSH (immediate) instructions directly. assembler automatically inserts opcode necessary.
Moved Instructions
Some existing instructions have been moved opcodes CPU. Table lists these moved instruction.
Table Instructions with Opcodes Instruction IRR1 Opcode (Hex) Opcode (Hex)
Removed Instructions
instruction types have been removed from opcode they subsets instruction (opcode using Escaped mode addressing. CPU, these instructions used opcodes through through F9H. assembler continues support these instructions. Refer Address Modes chapter instruction description more information. (Watch-Dog Timer Enable During HALT Mode) instruction also been removed. information regarding Watch-Dog Timer, refer Product Specification specific device.
UM012811-0904
Compatibility
RELOCATION CONTROL REGISTERS
four control registers within have addresses take advantage larger Register File. Stack Pointer High Byte Registers Stack Pointer Byte (SPL) resides address FFFH Register File. Stack Pointer High Byte (SPH) resides address FFEH. Register Pointer Register Pointer (RP) resides address FFDH Register File. Flags Register Flags Register (FLAGS) resides address FFCH Register File.
STACK POINTER COMPATIBILITY
stack pointer 12-bits length given {SPH[3:0], SPL[7:0]}. This change allows origin stack placed address from 000H EFFH where general-purpose registers available. Refer device-specific Product Specification available Register File addresses. stack pointer operations occur within Register File address space.
RESET COMPATIBILITY
Unlike which uses fixed reset address 00CH, uses vectored reset. Program Memory stores RESET vector addresses 0002H 0003H (most significant byte 0002H least significant byte 0003H). When reset fetches RESET vector addresses 0002H 0003H. writes RESET factor Program Counter. executes code Program Counter address.
INTERRUPT COMPATIBILITY
interrupt table resides starting address 0008H Program Memory accommodate increased number interrupts available with CPU.
UM012811-0904
Compatibility
Address Space
INTRODUCTION
access three distinct address spaces:
Register File contains addresses general-purpose registers CPU, peripheral, port control registers. Program Memory contains addresses memory locations having executable code and/or data. Data Memory contains addresses memory locations that hold data only.
REGISTER FILE
supports maximum 4096 consecutive bytes (registers) Register File. Register File composed sections control registers general-purpose registers. upper bytes reserved control CPU, on-chip peripherals, ports. These registers always located addresses from F00H FFFH. When instructions execute, registers read from when defined sources written when defined destinations. architecture allows general-purpose registers function accumulators, address pointers, index registers, stack areas, scratch memory. Some products contain Register File that less than maximum 4096 bytes. products with less than 4096B Register File, reading from unavailable Register File addresses returns undefined value. Writing unavailable Register File addresses produces effect. Refer device-specific Product Specification determine number registers available Register File well descriptions peripheral control registers.
Control Registers
Within registers reserved control, there four control registers that always same register addresses. These four control registers (see Table Stack Pointer High Byte, Stack Pointer Byte, Register Pointer Flags registers. more information operation control registers, please refer Architectural Overview chapter.
UM012811-0904
Address Space
Table Control Registers Register Mnemonic FLAGS Address (Hex)
Register Description Flags Register Pointer Stack Pointer High Byte Stack Pointer Byte
General-Purpose Registers
Other than upper registers reserved control functions, other available addresses within Register File available general-purpose use. Refer device-specific Product Specification determine addresses available.
Register File Organization
Register File accessed 4096 byte linear address space using 12-bit addressing mode, sixteen 256-byte Register Pages using 8-bit addressing mode, sixteen 16-byte Working Register Groups Register Page using 4-bit addressing mode. Figure illustrates organization Register File. Attempts read unavailable Register File addresses return undefined value. Attempts write unavailable Register File addresses produce effect.
UM012811-0904
Address Space
256B Pages FFFH 4096B Linear Addressable Register File 000H
Working Register Groups Page
Working Registers Group
Figure Register File Organization
Linear Addressing Register File Using 12-bit linear addressing, directly access 8-bit registers 16bit register pairs within 4096B Register File. instructions that support 12-bit addressing allow direct register access most registers without requiring change value Register Pointer (RP). accommodate increase register address space relative architecture, Extended Addressing instructions have been added allow easier register access across page boundaries. Page Mode Addressing Register File Page mode, Register File divided into sixteen 256-Byte register Pages. current page determined Page Pointer value, RP[3:0]. Registers accessed Direct, Indirect, Indexed Addressing using 8-bit addresses. full 12-bit address given {RP[3:0], Address[7:0]}. registers current page referenced
UM012811-0904
Address Space
modified instruction that uses 8-bit addressing. change different page, Register Pointer (SRP) instruction change value Register Pointer. (Load instructions, LDX, also used require more bytes code space). Working Register Addressing Register File Each Register File page logically divided into Working Register Groups registers each. Working Registers within each Working Register Group accessible using 4-bit addressing. high nibble Register Pointer (RP) contains base address active Working Register Group, referred Working Group Pointer. When accessing Working Registers, 4-bit address Working Register combined within Page Pointer Working Group Pointer form full 12-bit address {RP[3:0], RP[7:4], Address[3:0]}. Figure illustrates this operation.
Register Pointer
Working Group
Page
Working Register 4-bit Address
Full 12-bit Register Address (376H)
Figure Working Register Addressing Example
Because Working Registers typically specified using fewer operand bytes, there fewer bytes code needed, which reduces execution time. addition, when processing interrupts changing tasks, Register Pointer speeds context switching. Register Pointer (SRP) instruction sets contents Register Pointer. 16-bit Register Pairs Register data accessed 16-bit word using Register Pairs. this case, most significant byte (MSB) data stored even numbered register, while least significant byte (LSB) stored next higher numbered register (see Figure Address register pair using address MSB.
UM012811-0904
Address Space
Rn+1
Even Address Figure 16-Bit Register Pair Addressing
Addressing Many instructions allow access individual bits within registers. Figure illustrates instruction R15, MASK clear individual bit.
MASK
R15,
Clear Working Register
Figure Addressing Example
Register File Precautions
Some control registers within Register File provide Read-Only Write-Only access. When accessing these Read-Only Write-Only registers, insure that instructions attempt read from Write-Only register conversely, write Read-Only register. determine which control registers allow either Read-Only Write-Only access, refer device-specific Product Specification.
PROGRAM MEMORY
access 64KB (65,536 bytes) Program Memory. Program Memory provides storage both executable program code data. each product within family, block Program Memory beginning address 0000H reserved option bits, Reset vector, Watch-Dog Timer time-out vector, Illegal Instruction Trap vector, Interrupt vectors. rest Program Memory stores code
UM012811-0904
Address Space
data. Program Memory accessed using opcode fetches, operand fetches, LDC/ LDCI instructions. Table provides example Program Memory product with 64KB Program Memory interrupt vectors.
Table Program Memory Example Program Memory Address (Hex) 0000-0001 0002-0003 0004-0005 0006-0007 0008-0027 0028-FFFF
Description Option Bits RESET Vector Watch-Dog Timer Vector Illegal Instruction Trap Vector Interrupt Vectors Program code data
Individual products containing support varying amounts Program Memory. Refer device-specific Product Specification your product determine amount Program Memory available. Attempts read execute from unavailable Program Memory addresses return FFH. Attempts write unavailable Program Memory addresses produce effect.
DATA MEMORY
addition Register File Program Memory, also accesses maximum 64KB (65,536 bytes) Data Memory. Data Memory space provides data storage only. Opcode operand fetches cannot executed this space. Access obtained LDEI instructions. Valid addresses Data Memory from 0000H FFFFH. Individual products containing support varying amounts Data Memory. Refer device-specific Product Specification your product determine amount Data Memory available. Attempts read unavailable Data Memory addresses returns FFH. Attempts write unavailable Data Memory addresses produce effect.
STACKS
Stack operations occur general-purpose registers Register File. Register Pair FFEH FFFH form 16-bit Stack Pointer (SP) used stack operations. Stack Pointer holds current stack address. Stack Pointer must always point section Register File that does cause user program data overwritten. Even linear program code that employ stack Call and/or Inter-
UM012811-0904
Address Space
rupt routines, Stack Pointer must prepare possible Illegal Instruction Traps. stack address decrements prior PUSH operation increments after operation. stack address always points data stored stack. stack return stack interrupts CALL TRAP instructions. also employed data stack. During CALL instruction, contents Program Counter saved stack. Program Counter restored during execution Return (RET). Interrupts Traps (either TRAP instruction Illegal Instruction Trap) save contents Program Counter Flags Register stack. Interrupt Return (IRET) instruction restores them. Figure illustrates contents Stack location Stack Pointer following Call, Interrupt Trap operations.
PC[7:0] PC[7:0] Stack PC[15:8] Stack PC[15:8] Flags
Stack Contents After Call Instruction Figure Stack Operations
Stack Contents After Interrupt Trap
overflow underflow occur when stack address incremented decremented beyond available address space. programmer must prevent this occurrence unpredictable operation will result.
UM012811-0904
Address Space
Addressing Modes
INTRODUCTION
provides addressing modes:
Register Indirect Register (IR) Indexed Direct (DA) Relative (RA) Immediate Data (IM)
With exception immediate data condition codes, operands expressed either Register File, Program Memory, Data Memory addresses. Registers 12-bit addresses range 000H-FFFH. Program Memory Data Memory 16-bit addresses (register pairs) range 0000H-FFFFH. Register pairs designate 16-bit values memory addresses. Working Register Pairs 4-bit addresses must specified even-numbered address range Register Pairs 8-bit addresses must specified even-numbered address range 254. following definitions Addressing Modes, 'register' imply Register, Register Pair, Working Register, Working Register pair, depending context. Refer device-specific Product Specification details Program, Data, Register File memory types address ranges available.
REGISTER ADDRESSING Register Addressing Using 12-Bit Addresses
Extended register addressing used directly access register Register File. 12-bit address supplied operands. There types extended mode instructions: Register Register operations Immediate Register operations. Figure illustrates Register addressing using 12-bit addresses.
UM012811-0904
Addressing Modes
Program Memory 12-bit address dst[11:0] dst[7:0] 12-bit Addresses (dst, src) {src[3:0}, dst[11:8]} src[11:4] Three Operand Instruction (Example)
Register File
Destination Register
Opcode 12-bit address src[11:0]
Source Register
Figure Register Addressing Using 12-Bit Addresses
Register Addressing Using 8-Bit Addresses
Registers Register Pairs accessed using 8-bit addresses supplied operands. registers current Register File Page accessed using 8bit addressing. upper 4-bits 12-bit address provided Page Pointer, RP[3:0]. full 12-bit address given {RP[3:0], Address[7:0]}. Figure illustrates using 8-bit addressing, destination and/or source address specified corresponds register Register File.
UM012811-0904
Addressing Modes
Program Memory
Register File
8-bit Address (dst) Operand Instruction (Example)
12-bit address {RP[3:0], dst[7:0]} dst[7:0]
Destination Register
Opcode
Figure Register Addressing Using 8-Bit Addresses
Register Addressing Using 4-Bit Addresses
Working Registers Working Register Pairs accessed using 4-bit addresses supplied operands. With 4-bit Addressing, destination and/or source addresses point possible Working Registers within current Working Register Group. This 4-bit address combined with Page Pointer, RP[3:0], Working Group Pointer, RP[7:4], form actual 12-bit address Register File. full 12-bit address given {RP[3:0], RP[7:4], Address[3:0]}. Figure illustrates 4-bit addressing Register File.
UM012811-0904
Addressing Modes
Program Memory
Register File
12-bit address {RP[3:0], RP[7:4], dst[3:0]} 4-bit Addresses (dst, src) Operand Instruction (Example) {dst[3:0], src[3:0]} Opcode Destination Register
12-bit address {RP[3:0], RP[7:4], src[3:0]}
Source Register
Figure Register Addressing Using 4-Bit Addresses
Escaped Mode Addressing
Escaped Mode Addressing with 8-bit Addresses Using Escaped Mode Addressing 12-bit addresses specify Working Register. high nibble 8-bit address (1110b), Working Register inferred. example, Working Register (CH) desired destination operand, 8-bit address operand opcode. access Registers with addresses EFH, either Working Group Pointer, RP[7:4], indirect addressing. Escaped Mode Addressing with 12-bit Addresses Using Escaped Mode Addressing, address mode source destination specify Working Register with 4-bit addressing. high byte source destination address (11101110B), Working Register inferred. example, operand EE3H selects Working Register full 12bit address given {RP[3:0], RP[7:4], 3H}. access Registers Page (addresses E00H EFFH), Page Pointer, RP[3:0], Working Group Pointer, RP[7:4], desired Working Group.
UM012811-0904
Addressing Modes
INDIRECT REGISTER ADDRESSING (IR)
Indirect Register Addressing Mode, contents specified Register provide address illustrated Figures Depending upon instruction selected, specified Register contents point Register File, Program Memory, Data Memory location. When accessing Program Memory Data Memory, Register Pairs Working Register Pairs hold 16-bit addresses.
Program Memory Register File Register contains 8-bit address (addr[7:0]) Destination Register 12-bit address {RP[3:0], addr[7:0]} Value used execution Addressing Modes
8-bit Address (dst) Operand Instruction (Example)
12-bit address {RP[3:0], dst[7:0]} dst[7:0]
Opcode
Figure Indirect Register Addressing Register File
UM012811-0904
Program Memory
Register File
8-bit Address (dst) Operand Instruction (Example)
12-bit address {RP[3:0], dst[7:0]} dst[7:0]
Destination Register Destination Register
Register Pair contains 8-bit address {addr[15:8], addr[7:0]}
Opcode 16-bit address {addr[15:8], addr[7:0]} Addressing Modes
Program Data Memory
Value used execution
Figure Indirect Register Addressing Program Data Memory
INDEXED ADDRESSING
Indexed Address consists 8-bit address contained Working Register offset 8-bit Signed Index value. Figure illustrates Indexed Addressing.
UM012811-0904
Program Memory 12-bit address {RP[3:0], RP[7:4], dst[3:0]} Index 4-bit Address (dst, src) Operand Instruction (Example) {dst[3:0], src[3:0]} Opcode Source Value
Register File
Destination Register Source Register
12-bit address {RP[3:0], Source Value Index}
Value used execution
Figure Indexed Register Addressing
DIRECT ADDRESSING (DA)
Figure depicts Direct Addressing mode.This instruction specifies address next instruction executed. Only Jump Call (CALL) instructions Direct Addressing. 16-bit Direct Address written Program Counter.
UM012811-0904
Addressing Modes
8-bit value written Desitnation Register
Program Memory
DA[7:0] 16-bit Direct Address DA[15:8] Operand Instruction (Example) DA[15:0] written Program Counter
Opcode
16-bit Program Memory address DA[15:0]
Next Opcode
Figure Direct Addressing
RELATIVE ADDRESSING (RA)
Figure illustrates Relative Addressing mode. instruction specifies two's complement signed displacement range -128 +127. This instruction, added contents Program Counter, obtains address next instruction executed. Prior addition operation, Program Counter contains address instruction immediately following current relative addressing instruction. DJNZ instructions only instructions that this mode.
UM012811-0904
Addressing Modes
Program Memory
16-bit Program Memory address PC[15:0] 8-bit Value -128 +127 Operand Instruction (Example)
Next Opcode PC[15:0] Jump Displacement Opcode Jump taken, PC[15:0] PC[15:0] d[7:0]
16-bit Program Memory address PC[15:0] d[7:0]
Next Opcode Jump
Figure Relative Addressing
IMMEDIATE DATA ADDRESSING (IM)
Immediate data considered "addressing mode" this discussion. only addressing mode that does indicate register memory address operand. operand value used instruction value supplied operand field itself. Because immediate operand part instruction, always located Program Memory address space (see Figure 16).
UM012811-0904
Addressing Modes
Program Memory
Register File
Immediate Data Operand Instruction (Example)
8-bit data written Destination
Destination Register 12-bit address {RP[3:0], dst[7:0]}
Opcode
Figure Immediate Data Addressing
UM012811-0904
Addressing Modes
Interrupts
INTRODUCTION
Interrupt requests (IRQs) allow peripheral devices suspend operation force start interrupt service routine (ISR). interrupt service routine exchanges data, status information, control information between interrupting peripheral. When service routine finishes, returns previous operation. supports both vectored-and polled-interrupt handling. Interrupts generated from internal peripherals, external devices through port pins, software. Interrupt Controller prioritizes handles individual interrupt requests before passing them CPU. interrupt sources trigger conditions device dependent. Refer device-specific Product Specification determine available interrupt sources (internal external), triggering edge options, exact programming details.
INTERRUPT ENABLE DISABLE
Interrupts globally enabled disabled executing Enable Interrupts (EI) Disable Interrupts (DI) instructions, respectively. These instructions affect global interrupt enable control Interrupt Controller. Enable disable individual interrupts using control registers Interrupt Controller. Refer device-specific Product Specification information Interrupt Controller.
INTERRUPT PRIORITY
Interrupt Controller prioritizes interrupts. Refer device-specific Product Specification information Interrupt Controller.
VECTORED INTERRUPT PROCESSING
Each interrupt assigned vector. When interrupt occurs, control passes interrupt service routine pointed interrupt's vector location Program Memory. sequence events vectored interrupt follows:
UM012811-0904
Interrupts
Push byte Program Counter, PC[7:0], stack. Push high byte Program Counter, PC[15:8], stack. Push Flags Register stack. Fetch High Byte Interrupt Vector Fetch Byte Interrupt Vector Branch Interrupt Service Routine specified Interrupt Vector Figure illustrates effect vectored interrupts Stack Pointer contents stack. Figure provides example Program Memory during interrupt operation. example Figure Interrupt Vector located address 0014H Program Memory. 2-byte Interrupt Vector, stored Program Memory addresses 0014H 0015H, loaded into Program Counter. Execution Interrupt Service Routine begins Program Memory address 4567H, stored Interrupt Vector.
Stack Pointer Stack Before Interrupt Stack Pointer Stack After Interrupt
Stack Pointer
Stack
Stack Pointer PC[7:0] PC[15:8] Flags[7:0]
Figure Effects Interrupt Stack
UM012811-0904
Interrupts
Program Memory Address
Program Memory
4567H
Interrupt Service Routine Origin
Vector Selected Interrupt Controller
0015H 0014H
Vector[7:0] Vector[15:8]
Interrupt Vector Table
Figure Interrupt Vectoring Program Memory Example
NESTING VECTORED INTERRUPTS
Vectored interrupt nesting allows higher priority requests interrupt lower priority request. initiate vectored interrupt nesting, perform following steps during interrupt service routine: Push Interrupt Control Interrupt Enable Register information stack. Load Interrupt Enable Register information with masks disable lower priority interrupts. Execute instruction enable interrupts. Proceed with interrupt service routine processing. After processing complete, execute instruction disable interrupts. Restore Interrupt Control Interrupt Enable Register information from stack. Execute IRET instruction return from interrupt service routine.
UM012811-0904
Interrupts
POLLED INTERRUPT PROCESSING
Polled interrupt processing supported individually disabling interrupts polled. initiate polled processing, check interrupt bits interest Interrupt Request Register(s) using Test Under Mask (TM) similar test instruction. perform software call branch interrupt service routine. Write service routine service request, reset Interrupt Request Interrupt Request Register, return branch back main program. example polling routine follows: IRQ1, #0010000B NEXT CALL SERVICE NEXT: Other program code here SERVICE: Service routine code here IRQ1, #1101111B Process interrupt request Clear interrupt request IRQ1 Return address following CALL Test interrupt request IRQ1 interrupt request, NEXT interrupt request, interrupt service routine.
Refer device-specific Product Specification information Interrupt Request Registers.
SOFTWARE INTERRUPT GENERATION
generates Software Interrupts writing Interrupt Request Registers Register File. Interrupt Controller handle these software interrupts same manner hardware-generated interrupt requests. generate Software Interrupt, write desired interrupt request selected Interrupt Request Register. example, following instruction IRQ1, #0010000B writes Interrupt Request Register this interrupt enabled there higher priority pending interrupt requests, program control transfers interrupt service routine specified corresponding Interrupt Vector. more information Interrupt Controller Interrupt Request Registers, refer device-specific Product Specification.
UM012811-0904
Interrupts
Illegal Instruction Traps
Description
instruction does cover possible sequences binary values. Binary values sequences which operation defined illegal instructions. When fetches these illegal instructions, performs Illegal Instruction Trap operation. Illegal Instruction Trap functions similarly TRAP instruction (object code 03H). Flags Program Counter pushed stack. When Program Counter detects illegal instruction does increment. Program Counter value that pushed onto stack points illegal instruction. most significant byte (MSB) Illegal Instruction Trap Vector stored Program Memory address 0006H. least significant byte (LSB) Illegal Instruction Trap Vector stored Program Memory address 0007H. 16-bit Illegal Instruction Trap Vector replaces value Program Counter (PC). Program execution resumes from value Program Counter. Caution: IRET instruction must performed following Illegal Instruction Trap service routine. Because stack contains Program Counter value illegal instruction, IRET instruction returns code execution this illegal instruction.
Symbolic Operation Illegal Instruction Trap
Flags Vector
Linear Programs that Employ Stack
Stack Pointer must point section Register File that does overwrite user program data. Even linear program code that employ stack Call and/or Interrupt routines, Stack Pointer prepare possible Illegal Instruction Traps.
UM012811-0904
Illegal Instruction Traps
Instruction Summary
ASSEMBLY LANGUAGE PROGRAMMING INTRODUCTION
assembly language enables writing application program without concern about actual memory addresses machine instruction formats. program written assembly language called source program. Assembly language uses symbolic addresses identify memory locations. also allows mnemonic codes (opcodes operands) represent instructions themselves. opcodes identify instruction while operands represent memory locations, registers, immediate data values. Each assembly language program consists series symbolic commands, called statements. Each statement contains labels, operations, operands comments. Labels assigned particular instruction step source program. label identifies that step program entry point other instructions. assembly language also includes assembler directives that supplement machine instruction. assembler directives, pseudo-ops, translated into machine instruction. pseudo-ops interpreted directives that control assist assembly process. assembler processes source program obtain machine language program called object code. executes object code. example segment assembly language program detailed following example. Assembly Language Source Program Example
START START:
Everything after semicolon comment. label called "START". first instruction START) this example causes program execution jump point within program where START label occurs. Load (LD) instruction with operands. first operand, Working Register destination. second operand, Working Register source. contents written into Another Load (LD) instruction with operands. first operand, Extended Mode Register Address 234H, identifies destination. second operand, Immediate Data
234H, #%01
UM012811-0904
Instruction Summary
value 01H, source. value written into Register address 234H.
ASSEMBLY LANGUAGE SYNTAX
proper instruction execution, assembly language syntax requires that operands written `destination, source'. After assembly, object code usually places operands order 'source, destination', ordering opcode-dependent. following instruction examples illustrate format some basic assembly instructions resulting object code produced assembler. This binary format must followed users that prefer manual program coding intend implement their assembler. Example contents Registers added result stored 43H, assembly syntax resulting object code
Table Assembly Language Syntax Example Assembly Language Code Object Code 43H, (ADD dst, src) (OPC src, dst)
Example general, when instruction format requires 8-bit register address, that address specify register location range 0-255 using Escaped Mode Addressing, Working Register R0-R15. contents Register Working Register added result stored 43H, assembly syntax resulting object code
Table Assembly Language Syntax Example Assembly Language Code Object Code 43H, (ADD dst, src) (OPC src, dst)
device-specific Product Specification determine exact register file range available. register file size varies, depending device type.
INSTRUCTION NOTATION
Instruction Summary Description sections, operands, condition codes, status flags, address modes represented notational shorthand that Table describes.
UM012811-0904
Instruction Summary
Table Notational Shorthand Notation Description Condition Code Direct Address Extended Addressing Register Immediate Data Indirect Working Register Indirect Register Indirect Working Register Pair Indirect Register Pair Polarity Working Register Register Relative Address Operand Range Addrs #Data @Reg @RRp @Reg represents value from (000B 111B). Condition Codes overview Flags Register section Architectural Overview chapter. Addrs. represents number range 0000H FFFFH Reg. represents number range 000H FFFH Data number between Reg. represents number range Reg. represents even number range Polarity single binary value either Reg. represents number range represents index range +127 -128 which offset relative address next instruction Reg. represents even number range Vector represents number range register register pair indexed offset signed Index value (#Index) +127 -128 range.
Vector
Working Register Pair Register Pair Vector Address Indexed
#Vector #Index
Table contains additional symbols that used throughout Instruction Summary Instruction Description sections.
UM012811-0904
Instruction Summary
Table Additional Symbols Symbol FLAGS Definition Destination Operand Source Operand Indirect Address Prefix Carry Flag Stack Pointer Program Counter Flags Register Register Pointer Immediate Operand Prefix Binary Number Suffix Hexadecimal Number Prefix Hexadecimal Number Suffix
arrow indicates assignment value. example, indicates source data added destination data result stored destination location.
INSTRUCTION CLASSES
instructions divided functionally into following groups:
Arithmetic Manipulation Block Transfer Control Load Logical Program Control Rotate Shift
UM012811-0904
Instruction Summary
Tables through contain instructions belonging each group number operands required each instruction. Some instructions appear more than table these instructions considered subset more than category. Within these tables, source operand identified 'src', destination operand 'dst' condition code 'cc'.
Table Arithmetic Instructions Mnemonic ADCX ADDX CPCX DECW INCW MULT SBCX SUBX Operands dst, dst, dst, dst, dst, dst, dst, dst, dst, dst, dst, dst, Instruction with Carry with Carry using Extended Addressing using Extended Addressing Compare Compare with Carry Compare with Carry using Extended Addressing Compare using Extended Addressing Decimal Adjust Decrement Decrement Word Increment Increment Word Multiply Subtract with Carry Subtract with Carry using Extended Addressing Subtract Subtract using Extended Addressing
Table Manipulation Instructions Mnemonic BCLR BSET Operands bit, bit, bit, Instruction Clear Clear
UM012811-0904
Instruction Summary
Table Manipulation Instructions (Continued) Mnemonic BSWAP TCMX Operands dst, dst, dst, dst, Instruction Swap Complement Carry Flag Reset Carry Flag Carry Flag Test Complement Under Mask Test Complement Under Mask using Extended Addressing Test Under Mask Test Under Mask using Extended Addressing
Table Block Transfer Instructions Mnemonic LDCI LDEI Operands dst, dst, Instruction Load Constant to/from Program Memory Auto-Increment Addresses Load External Data to/from Data Memory Auto-Increment Addresses
Table Control Instructions Mnemonic ACCF HALT STOP Operands Instruction Atomic Execution Complement Carry Flag Disable Interrupts Enable Interrupts Halt Mode Operation Reset Carry Flag Carry Flag Register Pointer Stop Mode Watch-Dog Timer Refresh
UM012811-0904
Instruction Summary
Table Load Instructions Mnemonic LDCI LDEI LDWX POPX PUSH PUSHX Operands Instruction dst, dst, dst, dst, dst, dst, dst, Clear Load Load Constant to/from Program Memory Load Constant to/from Program Memory Auto-Increment Addresses Load External Data to/from Data Memory Load External Data to/from Data Memory Auto-Increment Addresses Load Word using Extended Addressing Load using Extended Addressing
dst, X(src) Load Effective Address using Extended Addressing Push Push using Extended Addressing
Table Logical Instructions Mnemonic Operands Instruction ANDX XORX dst, dst, dst, dst, dst, dst, Logical Logical using Extended Addressing Complement Logical Logical using Extended Addressing Logical Exclusive Logical Exclusive using Extended Addressing
UM012811-0904
Instruction Summary
Table Program Control Instructions Mnemonic BTJNZ BTJZ CALL DJNZ IRET TRAP Operands Instruction On-Chip Debugger Break
bit, src, Test Jump bit, src, bit, src, dst, dst, vector Test Jump Non-Zero Test Jump Zero Call Procedure Decrement Jump Non-Zero Interrupt Return Jump Jump Conditional Jump Relative Jump Relative Conditional Return Software Trap
Table Rotate Shift Instructions Mnemonic BSWAP SWAP Operands Instruction Swap Rotate Left Rotate Left through Carry Rotate Right Rotate Right through Carry Shift Right Arithmetic Shift Right Logical Swap Nibbles
UM012811-0904
Instruction Summary
INSTRUCTION SUMMARY
Table summarizes instructions. table identifies addressing modes employed instruction, effect upon Flags register, number clock cycles required instruction fetch, number clock cycles required instruction execution.
Table Instruction Summary Assembly Mnemonic dst, Address Mode Symbolic Operation ADCX dst, dst, ADDX dst, Flags Notation: Opcode(s) (Hex) Reset Flags Fetch Instr. Cycles Cycles
Value function result operation. Unaffected Undefined Carry Flag
UM012811-0904
Instruction Summary
Table Instruction Summary (Continued) Assembly Mnemonic dst, Address Mode Symbolic Operation ANDX dst, ABlock interrupt requests during execution next instructions dst[bit] dst[bit] Debugger Break dst[bit] dst[7:0] dst[0:7] Opcode(s) (Hex) Flags Fetch Instr. Cycles Cycles
BCLR bit, bit, BSET bit, BSWAP
bit, src, src[bit] BTJNZ bit, src, src[bit] BTJZ bit, src, src[bit]
CALL
Flags Notation:
Value function result operation. Unaffected Undefined Carry Flag
Reset
UM012811-0904
Instruction Summary
Table Instruction Summary (Continued) Assembly Mnemonic Address Mode Symbolic Operation ~dst dst, dst, CPCX dst, dst, DA(dst) Flags Notation: Opcode(s) (Hex) Reset Flags Fetch Instr. Cycles Cycles
Value function result operation. Unaffected Undefined Carry Flag
UM012811-0904
Instruction Summary
Table Instruction Summary (Continued) Assembly Mnemonic DECW Address Mode Symbolic Operation DJNZ dst, Disable Interrupts IRQCTL[7] Enable Interrupts IRQCTL[7] Halt Mode INCW FLAGS IRQCTL[7] Flags Notation: true true IRET Opcode(s) (Hex) 0A-FA Flags Fetch Instr. Cycles Cycles
HALT
0E-FE
0D-FD 0B-FB
Value function result operation. Unaffected Undefined Carry Flag
Reset
UM012811-0904
Instruction Summary
Table Instruction Summary (Continued) Assembly Mnemonic dst, Address Mode Symbolic Operation X(r) dst, LDCI dst, rr+1 rr+1 LDEI dst, X(r) Opcode(s) (Hex) 0C-FC 1FE8 Flags Fetch Instr. Cycles Cycles
dst,
LDWX dst, Flags Notation:
Value function result operation. Unaffected Undefined Carry Flag
Reset
UM012811-0904
Instruction Summary
Table Instruction Summary (Continued) Assembly Mnemonic dst, Address Mode Symbolic Operation X(rr) dst, X(src) dst[15:0] dst[15:8] dst[7:0] operation dst, Flags Notation: MULT dst, X(rr) X(r) X(rr) Opcode(s) (Hex) Reset Flags Fetch Instr. Cycles Cycles
Value function result operation. Unaffected Undefined Carry Flag
UM012811-0904
Instruction Summary
Table Instruction Summary (Continued) Assembly Mnemonic Address Mode Symbolic Operation PUSHX
Opcode(s) (Hex) 1F70
Flags
Fetch Instr. Cycles Cycles
POPX PUSH
Flags Notation:
Value function result operation. Unaffected Undefined Carry Flag
Reset
UM012811-0904
Instruction Summary
Table Instruction Summary (Continued) Assembly Mnemonic dst, Address Mode Symbolic Operation SBCX dst,
Opcode(s) (Hex)
Flags
Fetch Instr. Cycles Cycles
STOP dst,
Stop Mode
SUBX dst,
Flags Notation:
Value function result operation. Unaffected Undefined Carry Flag
Reset
UM012811-0904
Instruction Summary
Table Instruction Summary (Continued) Assembly Mnemonic SWAP Address Mode Symbolic Operation dst[7:4] dst[3:0] dst, (NOT dst) TCMX dst, (NOT dst) dst, dst, FLAGS @Vector TRAP Vector Vector Opcode(s) (Hex) Flags Fetch Instr. Cycles Cycles
Flags Notation:
Value function result operation. Unaffected Undefined Carry Flag
Reset
UM012811-0904
Instruction Summary
Table Instruction Summary (Continued) Assembly Mnemonic dst, Address Mode Symbolic Operation XORX dst, Flags Notation: Opcode(s) (Hex) Reset Flags Fetch Instr. Cycles Cycles
Value function result operation. Unaffected Undefined Carry Flag
UM012811-0904
Instruction Summary
Instruction Description
following pages provide detailed descriptions assembly language instructions available with CPU. instruction available with superset original instruction set. instruction descriptions following pages organized alphabetically mnemonic. Figure illustrates example layout instruction pages that follow.
Mnemonic
Description Simplified description assembly coding
Operation Symbolic description operation performed Description Detailed description instruction operation. Flags Information Flags affected instruction operation. Attributes Table providing information assembly coding, opcode value, operand ordering. Escaped Mode Addressing Description Escaped Mode addressing applicable this instruction. Example
simple code example using instruction.
Figure Example Instruction Description
UM012811-0904
Instruction Description
with Carry dst,
Operation Description source operand Carry flag added destination operand. Two'scomplement addition performed. stored destination operand. contents source operand affected. multiple-precision (multi-byte) arithmetic, this instruction permits carry from addition low-order byte operations carried into addition high-order bytes. Flags
there carry from reset otherwise. result zero; reset otherwise. result negative; reset otherwise. arithmetic overflow occurs; reset otherwise. Reset there carry from result; reset otherwise.
UM012811-0904
Instruction Description
Attributes
Mnemonic Destination, Source @R1, Opcode (Hex) Operand {r1, {r1, Operand Operand
Escaped Mode Addressing Using Escaped Mode Addressing, address modes specify Working Register. high nibble source destination address (1110B), Working Register inferred. example, Working Register (CH) desired destination operand, destination operand opcode. access Registers with addresses EFH, either Working Group Pointer, RP[7:4], indirect addressing. Examples
Working Register contains value 16H, Carry flag Working Register contains value 20H, statement: Object Code: leaves value Working Register clears flags.
Working Register contains value 16H, Carry flag set, Working Register contains value 20H, Register contains value 11H, statement: R15, @R10 Object Code: leaves value Working Register clears flags.
Register contains value 2EH, Carry flag set, Register contains value 1BH, statement: 34H, Object Code: leaves value Register 34H, sets flag clears flags.
UM012811-0904
Instruction Description
Using Escaped Mode Addressing, Working Register contains value 2EH, Carry flag set, Register contains value 1BH, statement: E4H, Object Code: leaves value Working Register sets flag, clears flags.
Using Escaped Mode Addressing, Register contains value 82H, Carry flag set, Working Register contains value 10H, Register contains value 01H, statement: 4BH, Object Code: leaves value Register 4BH, sets flag clears flags.
Register contains value 2AH, Carry flag set, statement: 6CH, #03H Object Code: leaves value Register clears flags.
Register contains value 5FH, Register contains value 4CH, Carry flag set, statement: @D4H, #02H Object Code: leaves value Register clears flags.
UM012811-0904
Instruction Description
ADCX
with Carry using Extended Addressing ADCX dst,
Operation Description source operand Carry flag destination operand. Perform two'scomplement addition. Store destination operand. contents source operand affected. multiple-precision (multi-byte) arithmetic, this instruction permits carry from addition low-order byte operations carried into addition high-order bytes. destination source operands 12-bit addresses access address Register File. Flags
there carry from reset otherwise. result zero; reset otherwise. result negative; reset otherwise. arithmetic overflow occurs; reset otherwise. Reset there carry from result; reset otherwise.
Attributes
Mnemonic Destination, Source ADCX ADCX ER1, ER1, Opcode (Hex) Operand ER2[11:4] Operand {0H, ER1[11:8]} Operand ER1[7:0] {ER2[3:0], ER1[11:8]} ER1[7:0]
Escaped Mode Addressing Using Escaped Mode Addressing, address mode source destination specify Working Register with 4-bit addressing. high byte source destination address (11101110B), Working Register inferred. example, operand EE3H selects Working Register full 12bit address given {RP[3:0], RP[7:4], 3H}. access Registers Page (addresses E00H EFFH), Page Pointer, RP[3:0], Working Group Pointer, RP[7:4], desired Working Group.
UM012811-0904
Instruction Description
Examples
Register 634H contains value 2EH, Carry flag set, Register B12H contains value 1BH, statement: ADCX 634H, B12H Object Code: leaves value Register 634H, sets flag clears flags. Using Escaped Mode Addressing, Working Register contains value 2EH, Carry flag set, Register B12H contains value 1BH, statement: ADCX EE4H, B12H Object Code: leaves value Working Register sets flag clears flags.
Register 46CH contains value 2AH, Carry flag set, statement: ADCX 46CH, #03H Object Code: leaves value Register 46CH clears flags.
UM012811-0904
Instruction Description
dst,
Operation Description source operand destination operand. Perform two's-complement addition. Store destination operand. contents source operand affected. Flags
there carry from reset otherwise. result zero; reset otherwise. result negative; reset otherwise. arithmetic overflow occurs; reset otherwise. Reset there carry from result; reset otherwise.
Attributes
Mnemonic Destination, Source @R1, Opcode (Hex) Operand {r1, {r1, Operand Operand
Escaped Mode Addressing Using Escaped Mode Addressing, address modes specify Working Register. high nibble source destination address (1110B), Working Register inferred. example, Working Register (CH) desired destination operand, destination operand opcode. access Registers with addresses EFH, either Working Group Pointer, RP[7:4], indirect addressing.
UM012811-0904
Instruction Description
Examples
Working Register contains value Working Register contains value 20H, statement: Object Code: leaves value Working Register clears flags.
Working Register contains value 16H, Working Register contains 20H, Register contains value 11H, statement: R15, @R10 Object Code: leaves value Working Register clears flags.
Register contains value Register contains value 1BH, statement: 34H, Object Code: leaves value Register 34H, sets flag clears flags.
Using Escaped Mode Addressing, Register contains value 82H, Working Register contains value 10H, Register contains value 01H, statement: 4BH, Object Code: leaves value Register 4BH, sets flag clears flags.
Register contains value 2AH, statement: 6CH, #03H Object Code: leaves value Register flags clear.
Register contains value Register contains value 4CH, statement: @D4H, #02H Object Code: leaves value Register clears flags.
UM012811-0904
Instruction Description
ADDX
using Extended Addressing ADDX dst,
Operation Description source operand added destination operand. Two's-complement addition performed. stored destination operand. contents source operand affected. Flags
there carry from reset otherwise. result zero; reset otherwise. result negative; reset otherwise. arithmetic overflow occurs; reset otherwise. Reset there carry from result; reset otherwise.
Attributes
Mnemonic Destination, Source ADDX ADDX ER1, ER1, Opcode (Hex) Operand ER2[11:4] Operand {0H, ER1[11:8]} Operand ER1[7:0] {ER2[3:0], ER1[11:8]} ER1[7:0]
Escaped Mode Addressing Using Escaped Mode Addressing, address mode source destination specifies Working Register with 4-bit addressing. high byte source destination address (11101110B), Working Register inferred. example, operand EE3H selects Working Register full 12bit address given {RP[3:0], RP[7:4], 3H}. access Registers Page (addresses E00H EFFH), Page Pointer, RP[3:0], Working Group Pointer, RP[7:4], desired Working Group.
UM012811-0904
Instruction Description
Examples
Register 634H contains value Register B12H contains value 1BH, statement: ADDX 634H, B12H Object Code: leaves value Register 634H, sets flag clears flags.
Using Escaped Mode Addressing, Working Register contains value Register B12H contains value 1BH, statement: ADDX EE4H, B12H Object Code: leaves value Working Register sets flag clears flags.
Register 46CH contains value statement: ADDX 46CH, #03H Object Code: leaves value Register 46CH clears flags.
UM012811-0904
Instruction Description
Logical dst,
Operation Description source operand logically AND'ed with destination operand. operation stores when corresponding bits operands both otherwise operation stores destination operand stores result. contents source unaffected. Flags
Unaffected. result zero; reset otherwise. result set; reset otherwise. Reset Unaffected. Unaffected.
Attributes
Mnemonic Destination, Source @R1, Opcode (Hex) Operand {r1, {r1, Operand Operand
Escaped Mode Addressing Using Escaped Mode Addressing, address modes specify Working Register. high nibble source destination address (1110B), Working Register inferred. example, Working Register (CH) desired destination operand, destination operand opcode. access Registers with addresses EFH, either Working Group Pointer, RP[7:4], indirect addressing.
UM012811-0904
Instruction Description
Examples
Working Register contains value (00111000B) Working Register contains value (10001101B), statement: Object Code: leaves value (00001000B) Working Register clears flags.
Working Register contains value (11111001B), Working Register contains value 7BH, Register contains value (01101010B), statement: @R13 Object Code: leaves value (01101000B) Working Register clears flags.
Register contains value (11110101B) Register contains value (00001010), statement: 3AH, Object Code: leaves value (00000000B) Register 3AH, sets flag clears flags.
Using Escaped Mode Addressing, Working Register contains value (11110000B), Register contains value 3AH, Register contains value (01111111B), statement: @45H Object Code: leaves value (01110000B) Working Register clears flags.
Register contains value (11110111B), statement: 7AH, #F0H Object Code: leaves value (11110000B) Register 7AH, sets flag clears flags.
Using Escaped Mode Addressing, Working Register contains value Register contains value (11101100B), statement: @R3, #05H Object Code:
UM012811-0904
Instruction Description
leaves value (00000100B) Register clears flags.
UM012811-0904
Instruction Description
ANDX
Logical using Extended Addressing ANDX dst,
Operation Description source operand AND'ed with destination operand. operation stores when corresponding bits operands both otherwise this operation stores destination operand stores result. contents source operand unaffected. Flags
Unaffected. result zero; reset otherwise. result negative; reset otherwise. Reset Unaffected. Unaffected.
Attributes
Mnemonic Destination, Source ANDX ANDX ER1, ER1, Opcode (Hex) Operand ER2[11:4] Operand {0H, ER1[11:8]} Operand ER1[7:0] {ER2[3:0], ER1[11:8]} ER1[7:0]
Escaped Mode Addressing Using Escaped Mode Addressing, address mode source destination specify Working Register with 4-bit addressing. high byte source destination address (11101110B), Working Register inferred. example, operand EE3H selects Working Register full 12bit address given {RP[3:0], RP[7:4], 3H}. access Registers Page (addresses E00H EFFH), Page Pointer, RP[3:0], Working Group Pointer, RP[7:4], desired Working Group.
UM012811-0904
Instruction Description
Examples
Register 93AH contains value (11110101B) Register 142H contains value (00001010), statement: ANDX 93AH, 142H Object Code: leaves value (00000000B) Register 93AH, sets flag, flags clear.
Register D7AH contains value (11110111B), statement: ANDX D7AH, #F0H Object Code: leaves value (11110000B) Register 7AH, sets flag clears flags.
UM012811-0904
Instruction Description
AAtomic Execution A
Operation Blocks interrupt requests during execution next 3instructions. Description Atomic instruction forces execute next instructions single block (i.e. atom) operations. During execution these next instructions, interrupts requests prevented. This allows operations performed multi-byte registers memory locations that could changed used interrupts DMA. example potential Ainstruction during adjustment multibyte stack pointer value. Flags
Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. Unaffected.
Attributes
Mnemonic Destination, Source Byte Byte Byte Byte
UM012811-0904
Instruction Description
BCLR
Clear BCLR bit,
Operation dst[bit] Description selected destination operand other bits unaffected. Flags
Unaffected. result zero; reset otherwise. result negative; reset otherwise. Reset Unaffected. Unaffected.
Attributes
Mnemonic BCLR Bit, Destination bit, Opcode (Hex) Operand {0B, bit, Operand Operand
Example
Working Register contains value (00111000B), statement: BCLR Object Code: leaves value (00101000B) Working Register clears flag.
UM012811-0904
Instruction Description
Set/Reset bit,
Operation dst[bit] Description selected destination operand binary value other bits unaffected. Flags
Unaffected. result zero; reset otherwise. result negative; reset otherwise. Reset Unaffected. Unaffected.
Attributes
Mnemonic Polarity, Bit, Destination bit, Opcode (Hex) Operand bit, Operand Operand
Example
Working Register contains value (00111000B), statement: Object Code: leaves value (00101000B) Working Register clears flag.
Working Register contains value (00111000B), statement: Object Code: leaves value (00111010B) Working Register clears flag.
UM012811-0904
Instruction Description
On-Chip Debugger Break
Operation None. Description Executes on-chip debugger break this address. Refer device-specific Product Specification information regarding on-chip debugger. Flags
Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. Unaffected.
Attributes
Mnemonic Destination, Source Opcode (Hex) Operand Operand Operand
UM012811-0904
Instruction Description
BSET
BSET bit,
Operation dst[bit] Description selected destination operand other bits unaffected. Flags
Unaffected. result zero; reset otherwise. result negative; reset otherwise. Reset Unaffected. Unaffected.
Attributes
Mnemonic BSET Bit, Destination bit, Opcode (Hex) Operand {1B, bit, Operand Operand
Example
Working Register contains value (00111000B), statement: BSET Object Code: leaves value (00111010B) Working Register clears flag.
UM012811-0904
Instruction Description
BSWAP
Swap BSWAP
Operation dst[7:0] dst[0:7] Description contents Register flipped: dst[7] dst[0] dst[6] dst[1] dst[5] dst[2] dst[4] dst[3] Flags
Undefined. result zero; reset otherwise. result negative; reset otherwise. Reset Unaffected. Unaffected.
Attributes
Mnemonic BSWAP Destination Opcode (Hex) Operand Operand Operand
Escaped Mode Addressing Using Escaped Mode Addressing, address mode specifies Working Register. destination address prefixed (1110B), Working Register inferred. example, Working Register (CH) desired destination operand, destination operand opcode. access Registers with addresses EFH, either Working Group Pointer, RP[7:4], indirect addressing. Example
Register contains value (01010011B), statement: BSWAP Object Code:
UM012811-0904
Instruction Description
leaves value (11001010B) Register sets flag clears flag. flag undefined.
UM012811-0904
Instruction Description
Test Jump bit, src,
Operation src[bit] where jump offset, calculated assembler from Program Counter (PC) value Destination Address (DA). Description selected source operand register pointed source operand compared with flag bit. source equal polarity signed displacement added Program Counter, which causes jump. displacement value from -128 +127. This instruction tests only single position. Multiple bits cannot tested simultaneously.
Figure Operand Description Position Tested Polarity Decimal Binary Operand[3:0] Binary 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Hexadecimal
UM012811-0904
Instruction Description
Flags
Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. Unaffected.
Attributes
Mnemonic Polarity, Bit, Source, Address Opcode (Hex) bit, bit, @r2, Operand bit[2:0], bit[2:0], Operand Operand
Examples
Working Register contains value (00100000B), instruction that begins following code segment:
Assembly Code NEXT HALT NEXT: Object Code This label assembled, used assembler identify destination address (the address next instruction).
does cause Program Counter jump occur because Working Register fails test next instruction executed after HALT instruction. flags unaffected.
Working Register contains value (00100000B), instruction that begins following code segment:
Assembly Code NEXT HALT Object Code
UM012811-0904
Instruction Description
Assembly Code NEXT NEXT:
Object Code This label assembled, used assembler identify destination address (the address next instruction).
causes Program Counter jump occur because Working Register passes test next instruction executed after instruction. assembler automatically calculates desired displacement value 01H, allowing Program Counter skip byte HALT instruction jump NEXT label that identifies instruction address. flags unaffected.
UM012811-0904
Instruction Description
BTJNZ
Test Jump Non-Zero BTJNZ bit, src,
Operation src[bit] where jump offset, calculated assembler from Program Counter (PC) value Destination Address (DA). Description selected source operand register pointed source operand compared with logical selected signed destination displacement added Program Counter, that causes jump. displacement value from -128 +127. This instruction tests only single position. Multiple bits cannot tested simultaneously.
Figure BTJNZ Operand Description Position Tested Decimal Binary Operand[3:0] Binary 1000 1001 1010 1011 1100 1101 1110 1111 Hexadecimal
UM012811-0904
Instruction Description
Flags
Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. Unaffected.
Attributes
Mnemonic BTJNZ BTJNZ Bit, Source, Address Opcode (Hex) bit, bit, @r2, Operand {1B, bit, {1B, bit, Operand Operand
Examples
Working Register contains value (00100000B), BTJNZ instruction that begins following code segment:
Assembly Code BTJNZ NEXT HALT NEXT:
Object Code This label assembled, used assembler identify destination address (the address next instruction).
causes Program Counter jump occur because Working Register passes test next instruction executed after BTJNZ instruction. assembler automatically calculates desired displacement value 01H, allowing Program Counter skip byte HALT instruction jump NEXT label that identifies instruction address. flags unaffected.
Working Register contains value (00100000B), BTJNZ instruction that begins following code segment:
UM012811-0904
Instruction Description
Assembly Code BTJNZ NEXT HALT NEXT:
Object Code This label assembled, used assembler identify destination address (the address next instruction).
does cause Program Counter jump occur because Working Register fails test next instruction executed after BTJNZ HALT instruction. flags unaffected.
UM012811-0904
Instruction Description
BTJZ
Test Jump Zero BTJZ bit, src,
Operation src[bit] where jump offset, calculated assembler from Program Counter (PC) value Destination Address (DA). Description selected source operand register pointed source operand compared with logical selected signed destination displacement added Program Counter, that causes jump. displacement value from +127. This instruction tests only single position. Multiple bits cannot tested simultaneously.
Figure BTJZ Operand Description Position Tested Decimal Binary Operand[3:0] Binary 0000 0001 0010 0011 0100 0101 0110 0111 Hexadecimal
UM012811-0904
Instruction Description
Flags
Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. Unaffected.
Attributes
Mnemonic BTJZ BTJZ Bit, Source, Address Opcode (Hex) bit, bit, @r2, Operand bit, bit, Operand Operand
Examples
Working Register contains value (00100000B), BTJZ instruction that begins following code segment:
Assembly Code BTJZ NEXT HALT NEXT:
Object Code This label assembled, used assembler identify destination address (the address next instruction).
causes Program Counter jump occur because Working Register passes test next instruction executed after instruction. assembler automatically calculates desired displacement value allow Program Counter skip byte HALT instruction jump NEXT label that identifies instruction address. flags unaffected.
Working Register contains value (00100000B), BTJZ instruction that begins following code segment:
UM012811-0904
Instruction Description
Assembly Code BTJZ NEXT HALT NEXT:
Object Code This label assembled, used assembler identify destination address (the address next instruction).
does cause Program Counter jump occur because Working Register fails test next instruction executed after BTJZ HALT instruction. flags unaffected.
UM012811-0904
Instruction Description
CALL
CALL Procedure CALL
Operation Description Stack Pointer decrements two, current contents Program Counter, which address first instruction following CALL instruction, pushed onto stack specified destination address then loaded into Program Counter. Program Counter points first instruction procedure. procedure, instruction returns original program flow. pops stack replaces original value into Program Counter. Flags
Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. Unaffected.
Attributes
Mnemonic CALL CALL Destination @RR1 Opcode (Hex) Operand DA[15:8] Operand DA[7:0] Operand
Escaped Mode Addressing Using Escaped Mode Addressing, address mode specifies Working Register. destination address prefixed (1110B), Working Register inferred. example, Working Register (CH) desired destination operand, destination operand opcode. access Registers with addresses EFH, either Working Group Pointer, RP[7:4], indirect addressing.
UM012811-0904
Instruction Description
Examples
contents Program Counter 1A47H contents Stack Pointer 3002H, statement: CALL 3521H Object Code: causes Stack Pointer decremented 3000H, 1A4AH (the address following CALL instruction) stored Program Memory locations 3001H 3000H, Program Counter loaded with 3521H. Program Counter points address first statement called procedure executed. flags unaffected.
contents Program Counter 1A47H contents Stack Pointer 3724H, contents Register 34H, contents Register Pair 3521H, statement: CALL @A4H Object Code: causes Stack Pointer decrement 3722H, stores 1A4AH (the address following CALL instruction) Program Memory locations 3723H 3722H, loads Program Counter with 3521H. Program Counter points address first statement called procedure executed. flags unaffected.
UM012811-0904
Instruction Description
Complement Carry Flag
Operation Description Carry flag complemented. Flags
Complemented. Unaffected. Unaffected. Unaffected. Unaffected. Unaffected.
Attributes
Mnemonic Destination, Source Opcode (Hex) Operand Operand Operand
Example Carry flag contains statement: Object Code: sets Carry flag
UM012811-0904
Instruction Description
Clear
Operation Description destination operand cleared 00H. Flags
Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. Unaffected.
Attributes
Mnemonic Destination Opcode (Hex) Operand Operand Operand
Escaped Mode Addressing Using Escaped Mode Addressing, address modes specify Working Register. destination address prefixed (1110B), Working Register inferred. example, Working Register (CH) desired destination operand, destination operand opcode. access Registers with addresses EFH, either Working Group Pointer, RP[7:4], indirect addressing. Examples
Using Escaped Mode Addressing, Working Register contains AFH, statement: Object Code: leaves value Working Register
UM012811-0904
Instruction Description
Register contains value 23H, Register contains value FCH, statement: @A5H Object Code: leaves value Register 23H.
UM012811-0904
Instruction Description
Complement
Operation ~dst Description contents destination operand complemented (one's complement). bits changed bits changed Flags
Unaffected. result zero; reset otherwise. result set; reset otherwise. Reset Unaffected. Unaffected.
Attributes
Mnemonic Destination Opcode (Hex) Operand Operand Operand
Escaped Mode Addressing Using Escaped Mode Addressing, address modes specify Working Register. destination address prefixed (1110B), Working Register inferred. example, Working Register (CH) desired destination operand, destination operand opcode. access Registers with addresses EFH, either Working Group Pointer, RP[7:4], indirect addressing. Examples
Register contains (00100100B), statement: Object Code: leaves value (11011011B) Register 08H, sets flag clears flags.
UM012811-0904
Instruction Description
Register contains value 24H, Register contains value (11111111B), statement: @08H Object Code: leaves value (00000000B) Register 24H, sets flag clears flags.
UM012811-0904
Instruction Description
Compare dst,
Operation Description source operand compared (subtracted from) destination operand flags according results operation. contents both source destination operands unaffected. Flags
borrow required reset otherwise. result zero; reset otherwise. result set; reset otherwise. arithmetic overflow occurs; reset otherwise. Unaffected. Unaffected.
Attributes
Mnemonic Destination, Source @R1, Opcode (Hex) Operand {r1, {r1, Operand Operand
Escaped Mode Addressing Using Escaped Mode Addressing, address modes specify Working Register. high nibble source destination address (1110B), Working Register inferred. example, Working Register (CH) desired destination operand, destination operand opcode. access Registers with addresses EFH, either Working Group Pointer, RP[7:4], indirect addressing.
UM012811-0904
Instruction Description
Examples
Working Register contains value Working Register contains value 20H, statement: Object Code: sets flags, clears flags.
Working Register contains value 16H, Working Register contains value 20H, Register contains 11H, statement: R15, @R10 Object Code: clears flags.
Register contains value Register contains value 1BH, statement: 34H,12H Object Code: clears flags.
Register contains value 82H, Working Register contains value 10H, Register contains value 01H, statement: 4BH, Object Code: sets flag, clears flags.
Register contains value 2AH, statement: 6CH, #2AH Object Code: sets flag, clears flags.
Register contains value FCH, Register contains value 8FH, statement: @D4H, #FFH Object Code: sets flag, clears flags.
UM012811-0904
Instruction Description
Compare with Carry dst,
Operation Description source operand with compared (subtracted from) destination operand. contents both operands unaffected. multi-precision operation, repeating this instruction enables multi-byte compares. Zero flag only initial state Zero flag result compare Flags
borrow required reset otherwise. result zero initial Zero flag reset otherwise. result negative; reset otherwise. arithmetic overflow occurs; reset otherwise. Unaffected. Unaffected.
Attributes
Mnemonic Destination, Source @R1, Opcode (Hex) Operand {r1, {r1, Operand Operand
Escaped Mode Addressing Using Escaped Mode Addressing, address modes specify Working Register. high nibble source destination address (1110B), Working Register inferred. example, Working Register (CH) desired destination operand, destination operand opcode. access Registers with addresses EFH, either Working Group Pointer, RP[7:4], indirect addressing.S
UM012811-0904
Instruction Description
Examples
Working Register contains value 16H, Working Register contains value Carry flag statement: Object Code: sets flags, clears flags.
Working Register contains value 16H, Working Register contains value 20H, Register contains value Carry flag statement: R15, @R10 Object Code: clears flags.
Register contains value Register contains value 1BH, Carry Flag statement: 34H,12H Object Code: clears flags.
Register contains value 82H, Working Register contains value 10H, Register contains value 81H, Carry flag Zero flag statement: 4BH, Object Code: sets flag, clears flags.
Register contains value 2AH, Carry flag Zero flag statement: 6CH, #2AH Object Code: clears flags.
Register contains value FCH, Register contains value 8FH, Carry Flag statement: @D4H, #FFH Object Code: sets flag, clears flags.
UM012811-0904
Instruction Description
CPCX
Compare with Carry using Extended Addressing CPCX dst,
Operation Description source operand with compared (subtracted from) destination operand appropriate flags accordingly. contents both operands unaffected. multi-precision operation, repeating this instruction enables multi-byte compares. Only initial state Zero flag result compare Zero flag set. Flags
borrow required reset otherwise. result zero initial Zero flag reset otherwise. result negative; reset otherwise. arithmetic overflow occurs; reset otherwise. Unaffected. Unaffected.
Attributes
Mnemonic Destination, Source CPCX CPCX ER1, ER1, Opcode (Hex) Operand ER2[11:4] Operand {0H, ER1[11:8]} Operand ER1[7:0] {ER2[3:0], ER1[11:8]} ER1[7:0]
Escaped Mode Addressing Using Escaped Mode Addressing, address mode source destination specify Working Register with 4-bit addressing. high byte source destination address (11101110B), Working Register inferred. example, operand EE3H selects Working Register full 12bit address given {RP[3:0], RP[7:4], 3H}. access Registers Page (addresses E00H EFFH), Page Pointer, RP[3:0], Working Group Pointer, RP[7:4], desired Working Group.
UM012811-0904
Instruction Description
Examples
Register AB3H contains value 16H, Register 911H contains value Carry flag statement: CPCX %AB3, %911 Object Code: sets flags, clears flags.
Register 26CH contains value 2AH, Carry flag Zero flag statement: CPCX 26CH, #2AH Object Code: sets flag clears flags.
UM012811-0904
Instruction Description
Compare using Extended Addressing dst,
Operation Description source operand compared (subtracted from) destination operand appropriate flags accordingly. contents both operands unaffected. Flags
borrow required reset otherwise. result zero; reset otherwise. result negative; reset otherwise. arithmetic overflow occurs; reset otherwise. Unaffected. Unaffected.
Attributes
Mnemonic Destination, Source ER1, ER1, Opcode (Hex) Operand ER2[11:4] Operand {0H, ER1[11:8]} Operand ER1[7:0] {ER2[3:0], ER1[11:8]} ER1[7:0]
Escaped Mode Addressing Using Escaped Mode Addressing, address mode source destination specify Working Register with 4-bit addressing. high byte source destination address (11101110B), Working Register inferred. example, operand EE3H selects Working Register full 12bit address given {RP[3:0], RP[7:4], 3H}. access Registers Page (addresses E00H EFFH), Page Pointer, RP[3:0], Working Group Pointer, RP[7:4], desired Working Group.
UM012811-0904
Instruction Description
Examples
Register AB3H contains Register 911H contains 20H, statement: %AB3, %911 Object Code: sets flags, clears flags.
Register 26CH contains 2AH, statement: 26CH, #2AH Object Code: sets flag clears flags.
UM012811-0904
Instruction Description
Decimal Adjust
Operation DA(dst) Description destination operand adjusted form 4-bit digits following binary addition subtraction operation encoded bytes. addition (ADD ADC) subtraction (SUB SBC), Table indicates operation performed. destination operand result valid addition subtraction digits, operation undefined.
Table Operation Instruction Carry Instruction Before Bits Value (HEX) Flag Before Bits Value (HEX) Number Added Byte Carry After
ADD\ADC
SUB\SBC
UM012811-0904
Instruction Description
Flags
there carry from reset otherwise. result zero; reset otherwise. result set; reset otherwise. Undefined. Unaffected. Unaffected.
Attributes
Mnemonic Destination Opcode (Hex) Operand Operand Operand
Escaped Mode Addressing Using Escaped Mode Addressing, address modes specify Working Register. destination address prefixed (1110B), Working Register inferred. example, Working Register (CH) desired destination operand, destination operand opcode. access Registers with addresses EFH, either Working Group Pointer, RP[7:4], indirect addressing. Example
addition performed using value result should incorrect, however, when binary representations added destination location using standard binary arithmetic.
0001 0101 0010 0111 0011 1100
result addition stored Register 5FH, statement: Object Code: adjusts this result obtain correct representation.
0011 1100 0000 0110 0100 0010
Register contains value clears flags. undefined.
UM012811-0904
Instruction Description
Decrement
Operation Description contents destination operand decremented one. Flags
Unaffected. result zero; reset otherwise. result set; reset otherwise. arithmetic overflow occurs; reset otherwise. Unaffected. Unaffected.
Attributes
Mnemonic Destination Opcode (Hex) Operand Operand Operand
Escaped Mode Addressing Using Escaped Mode Addressing, address modes specify Working Register. destination address prefixed (1110B), Working Register inferred. example, Working Register (CH) desired destination operand, destination operand opcode. access Registers with addresses EFH, either Working Group Pointer, RP[7:4], indirect addressing. Examples
Working Register contains 2AH, statement: Object Code: leaves value Working Register clears flags.
Register contains CBH, Register contains 01H, statement:
UM012811-0904
Instruction Description
@B3H Object Code: leaves value Register CBH, sets flag clears flags.
UM012811-0904
Instruction Description
DECW
Decrement Word DECW
Operation Description 16-bit value indicated destination operand decremented one. Only even addresses used register pair. indirect addressing, indirect address value, effective address only even address. Flags
Unaffected. result zero; reset otherwise. result set; reset otherwise. arithmetic overflow occurs; reset otherwise. Unaffected. Unaffected.
Attributes
Mnemonic DECW DECW Destination Opcode (Hex) Operand Operand Operand
Escaped Mode Addressing Using Escaped Mode Addressing, address modes specify Working Register Pair specify Working Register. high nibble source destination address (1110B), Working Register Pair) inferred. example, Working Register Pair (with base address desired destination operand, destination operand opcode. access Register Pairs with addresses EFH, either Working Group Pointer, RP[7:4], indirect addressing.
UM012811-0904
Instruction Description
Examples
Register Pair contain value 0AF2H, statement: DECW Object Code: leaves value 0AF1H Register Pair clears flags.
Working Register contains Register Pair contain value FAF3H, statement: DECW Object Code: leaves value FAF2H Register Pair 31H, sets flag clears the. flags.
UM012811-0904
Instruction Description
Disable Interrupts
Operation Disable Interrupts: IRQCTL[7] Description Interrupt Control Register reset This disables Interrupt Controller. Flags
Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. Unaffected.
Attributes
Mnemonic Destination, Source Opcode (Hex) Operand Operand Operand
Example IRQCTL (Interrupt Control register FCFH) contains (10000000B), interrupts globally enabled. Upon execution command, statement: Object Code: IRQCTL (Interrupt Control register FCFH) contains (00000000B) globally disables interrupts.
UM012811-0904
Instruction Description
DJNZ
Decrement Jump Non-Zero DJNZ dst,
Operation where jump offset, calculated assembler from Program Counter (PC) value Destination Address (DA). Description Working Register that used counter decremented. contents Working Register zero after being decremented, then relative address added Program Counter control passes statement whose address Program Counter. range relative address +127 -128. original value Program Counter address instruction byte following DJNZ statement. When specified Working Register counter reaches zero, control falls through statement following DJNZ instruction. Flags
Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. Unaffected.
UM012811-0904
Instruction Description
Attributes
Mnemonic DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ Destination, Address Opcode (Hex) r2,RA r10, r11, r12, r13, r14, r15, Operand Operand Operand
Example DJNZ typically controls "loop" instructions. this example, bytes moved from buffer area Register File another. steps involved are: Load counter with (12H). Load source pointer. Load destination pointer. loop perform moves. loop with DJNZ.
UM012811-0904
Instruction Description
assembly listing required this routine follows:
#12H #36H #24H @R2, djnz loop ;Load counter with (18d) ;Load source pointer ;Load destination pointer ;Load byte from source ;Write byte destination ;Decrement source pointer ;Decrement destination pointer ;Decrement loop until count
LOOP:
UM012811-0904
Instruction Description
Enable Interrupts
Operation Enable Interrupts: IRQCTL[7] Description Interrupt Control Register This value enables Interrupt Controller. Flags
Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. Unaffected.
Attributes
Mnemonic Destination, Source Opcode (Hex) Operand Operand Operand
Example IRQCTL (Interrupt Control register FCFH) contains value (00000000B), interrupts globally disabled. Upon execution command, statement: Object Code: IRQCTL (Interrupt Control register FCFH) contains value (10000000B) globally enable interrupts.
UM012811-0904
Instruction Description
HALT
Halt Mode HALT
Operation Halt Mode Description HALT instruction places into HALT mode. Refer device-specific Product Specification information HALT mode operation. Flags
Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. Unaffected.
Attributes
Mnemonic HALT Destination, Source Opcode (Hex) Operand Operand Operand
Example statement: HALT Object Code: places HALT mode.
UM012811-0904
Instruction Description
Increment
Operation Description contents destination operand incremented one. Flags
Unaffected. result zero; reset otherwise. result set; reset otherwise. arithmetic overflow occurs; reset otherwise. Unaffected. Unaffected.
UM012811-0904
Instruction Description
Attributes
Mnemonic Destination Opcode (Hex) Operand Operand Operand
Escaped Mode Addressing Using Escaped Mode Addressing, address modes specify Working Register. destination address prefixed (1110B), Working Register inferred. example, Working Register (CH) desired destination operand, destination operand opcode. access Registers with addresses EFH, either Working Group Pointer, RP[7:4], indirect addressing.
UM012811-0904
Instruction Description
Examples
Working Register contains value 2AH, statement: Object Code: leaves value Working Register clears flags.
Register contains value CBH, statement: Object Code: leaves value Register CBH, sets flag clears flags.
Register contains Register contains FFH, statement: @B3H Object Code: leaves value Register CBH, sets flag clears flags.
UM012811-0904
Instruction Description
INCW
Increment Word INCW
Operation Description 16-bit value indicated destination operand incremented one. Only even addresses used register pair. indirect addressing, indirect address value, effective address only even address. Flags
Unaffected. result zero; reset otherwise. result set; reset otherwise. arithmetic overflow occurs; reset otherwise. Unaffected. Unaffected.
Attributes
Mnemonic INCW INCW Destination Opcode (Hex) Operand Operand Operand
Escaped Mode Addressing Using Escaped Mode Addressing, address modes specify Working Register Pair specify Working Register. high nibble source destination address (1110B), Working Register Pair) inferred. example, Working Register Pair (with base address desired destination operand, destination operand opcode. access Register Pairs with addresses EFH, either Working Group Pointer, RP[7:4], indirect addressing.
UM012811-0904
Instruction Description
Examples
Register Pair contain value 0AF2H, statement: INCW Object Code: leaves value 0AF3H Register Pair clears flags.
Working Register contains 30H, Register Pair contain value FAF3H, statement: INCW Object Code: leaves value FAF4H Register Pair 31H, sets flag clears flag.
UM012811-0904
Instruction Description
IRET
Interrupt Return IRET
Operation FLAGS IRQCTL[7] Description This instruction issued interrupt service routine. Execution IRET restores Flags Register Program Counter. Interrupt Controller enabled setting Interrupt Control Register Flags
Restored original setting before interrupt occurred. Restored original setting before interrupt occurred. Restored original setting before interrupt occurred. Restored original setting before interrupt occurred. Restored original setting before interrupt occurred. Restored original setting before interrupt occurred.
Attributes
Mnemonic IRET Destination, Source Opcode (Hex) Operand Operand Operand
Example Stack Pointer High register, FFEH, contains value EFH, Stack Pointer register FFFH contains value 45H, Register contains value 00H, Register contains 6FH, Register contains E4H, statement: IRET Object Code: restores Flags Register with value 00H, restores with value 6FE4H, re-enables interrupts, sets Stack Pointer value 48H. Stack Pointer High register remains unchanged with value EFH. next instruction executed 6FE4H.
UM012811-0904
Instruction Description
Jump
Operation Description unconditional jump replaces contents Program Counter with contents destination. Program control then passes instruction addressed Program Counter. Flags
Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. Unaffected.
Attributes
Mnemonic Destination @RR1 Opcode (Hex) Operand DA[15:8] Operand DA[7:0] Operand
Escaped Mode Addressing Using Escaped Mode Addressing, address mode specify Working Register Pair. high nibble source destination address (1110B), Working Register Pair inferred. example, Working Register Pair (with base address desired destination operand, destination operand opcode. access Register Pairs with addresses EFH, either Working Group Pointer, RP[7:4], indirect addressing. Example
Working Register Pair contains value 3F45H, statement: @RR2 Object Code:
UM012811-0904
Instruction Description
replaces contents with value 3F45H transfers program control that location.
UM012811-0904
Instruction Description
Jump Conditionally
Operation (condition code) true (1){ Description conditional jump transfers program control destination address condition specified true. Otherwise, instruction following instruction executed. SeeSection Condition Codes <Plain>on page more information. Flags
Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. Unaffected.
UM012811-0904
Instruction Description
Attributes
Mnemonic Condition Code, Destination Address Opcode (Hex) ULE, UGT, NOV, Operand DA[15:18] DA[15:8] DA[15:8] DA[15:8] DA[15:8] DA[15:8] DA[15:8] DA[15:8] DA[15:8] DA[15:8] DA[15:8] DA[15:8] DA[15:8] DA[15:8] DA[15:8] DA[15:8] Operand DA[7:0] DA[7:0] DA[7:0] DA[7:0] DA[7:0] DA[7:0] DA[7:0] DA[7:0] DA[7:0] DA[7:0] DA[7:0] DA[7:0] DA[7:0] DA[7:0] DA[7:0] DA[7:0] Operand
Example
Carry flag set, statement:
1520H Object Code:
replaces contents Program Counter with value 1520H transfers program control that location. Carry flag set, control would have passed through statement following instruction.
UM012811-0904
Instruction Description
Jump Relative
Operation where jump offset, calculated assembler from Program Counter (PC) value Destination Address (DA). Description relative address offset added Program Counter control passes instruction located address specified Program Counter. range relative address +127 -128 original value Program Counter taken address first instruction byte following instruction. Flags
Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. Unaffected.
Attributes
Mnemonic Condition Code, Address Opcode (Hex) Operand Operand Operand
UM012811-0904
Instruction Description
Jump Relative Conditionally
Operation (condition code) true (1){ where jump offset, calculated assembler from Program Counter (PC) value Destination Address (DA). Description condition specified "cc" true, relative address offset added Program Counter control passes instruction located address specified Program Counter. SeeSection Condition Codes <Plain>on page control code information. Otherwise, instruction following instruction executed. range relative address +127 -128 original value Program Counter taken address first instruction byte following instruction. Flags
Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. Unaffected.
UM012811-0904
Instruction Description
Attributes
Mnemonic Condition Code, Address ULE, UGT, NOV, Opcode (Hex) Operand Operand Operand
UM012811-0904
Instruction Description
Load dst,
Operation Description contents source operand loaded into destination operand. contents source operand unaffected. Flags
Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. Unaffected.
UM012811-0904
Instruction Description
Attributes
Mnemonic Destination, Source @R1, @r1, @R1, X(r2) X(r1), r10, r011 r12, r13, r14, r15, Opcode (Hex) Operand {r1, {r1, {r1, {r2, Operand Operand
Escaped Mode Addressing Using Escaped Mode Addressing, address modes specify Working Register. high nibble source destination address (1110B), Working Register inferred. example, Working Register (CH) desired destination operand, destination operand opcode. access Registers with addresses EFH, either Working Group Pointer, RP[7:4], indirect addressing.
UM012811-0904
Instruction Description
Examples
statement: R15, #34H Object Code: loads value into Working Register R15.
Register contains value FCH, statement: R14, Object Code: loads value into Working Register R14. contents Register affected.
Working Register contains value 45H, statement: 34H, Object Code: loads value into Register 34H. contents Working Register affected.
Working Register contains value 34H, Register contains value FFH, statement: R13, @R12 Object Code: loads value into Working Register R13. contents Working Register Register affected.
Working Register contains value 45H, Working Register contains value statement: @R13, Object Code: loads value into Register 45H. contents Working Register Working Register affected.
Register contains value CFH, statement: 34H, Object Code: loads value into Register 34H. contents Register affected.
Register contains value Register contains value FFH, statement: 34H, @45H Object Code:
UM012811-0904
Instruction Description
loads value into Register 34H. contents Register Register affected.
statement: 34H, #A4H Object Code: loads value into Register 34H.
Working Register contains value 7FH, statement: @R14, #FCH Object Code: loads value into Register 7FH. contents Working Register affected.
Register contains value Register contains value FFH, statement: @34H, Object Code: loads value into Register CFH. contents Register Register affected.
Working Register contains value Register (24H 2CH) contains value 4FH, statement: R10, 24H(R0) Object Code: loads Working Register with value 4FH. contents Working Register Register affected.
Working Register contains value Working Register contains statement: F0H(R0), Object Code: loads value into Register (F0H FBH). contents Working Registers unaffected load.
UM012811-0904
Instruction Description
Load Constant to/from Program Memory dst,
Operation Description This instruction loads byte constant from Program Memory into Working Register vice versa. address Program Memory location specified Working Register Pair. contents source operand unaffected. Flags
Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. Unaffected.
Attributes
Mnemonic Destination, Source @rr2 @r1, @rr2 @rr1, Opcode (Hex) Operand {r1, rr2} {r1, rr2} {r2, rr1} Operand Operand
Examples
Working Register Pair contain value 30A2H Program Memory location 30A2H contains value 22H, statement: @RR6 Object Code: loads value into Working Register value Program Memory location 30A2H unchanged load. Working Register contains value 22H, Working Register Pair contains value 10A2H, statement: @RR6, Object Code:
UM012811-0904
Instruction Description
loads value into Program Memory location 10A2H. value Working Register unchanged load.
UM012811-0904
Instruction Description
LDCI
Load Constant to/from Program Memory Auto-Increment Addresses LDCI dst,
Operation rr+1 Description This instruction performs block transfers data between Program Memory Register File. address Program Memory location specified Working Register Pair address Register File location specified Working Register. contents source location loaded into destination location. Both addresses Working Registers then incremented automatically. contents source operand unaffected. Flags
Unaffected. Unaffected. Unaffected. Unaffected. Unaffected. Unaffected.
Attributes
Mnemonic LDCI LDCI Destination, Source @r1, @rr2 @rr1, Opcode (Hex) Operand {r1, rr2} {r2, rr1} Operand Operand
UM012811-0904
Other recent searches
TC55VD836FF-133 - TC55VD836FF-133 TC55VD836FF-133 Datasheet
Si3050 - Si3050 Si3050 Datasheet
NJU26040-09B - NJU26040-09B NJU26040-09B Datasheet
NJU26040-09A - NJU26040-09A NJU26040-09A Datasheet
MC68HC08AB16A - MC68HC08AB16A MC68HC08AB16A Datasheet
ICS87974I - ICS87974I ICS87974I Datasheet
DTM60119 - DTM60119 DTM60119 Datasheet
CLS0571M-L152 - CLS0571M-L152 CLS0571M-L152 Datasheet
AP70L02GS - AP70L02GS AP70L02GS Datasheet
2SK2905-01R - 2SK2905-01R 2SK2905-01R Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
