DESCRIPTION ST8012 120-output segment/common driver suitable driv

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DESCRIPTION ST8012 120-output segment/common driver suitable driv

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Sitronix
DESCRIPTION
ST8012 120-output segment/common driver suitable driving small/medium scale matrix panels, used electronic dictionary ST8012 good segment driver common driver common/segment driver, create power consuming, high-resolution LCD. ST8012 have eight modes selected common segment numbers select pin. ST8012 also have analog DC/DC converter used.
ST8012
Matrix Output Common/Segment driver
Functions have initial value, user default value setting programmable set. select segment mode then except booster circuit will opened others circuit (follower regulator circuit) will automatic closed. When don't used serial interface, select default modes serial interface pins please Table5. Package: 154-pin COB. (Segment mode) Shift clock frequency (MAX.): +5.0 (MAX.): +3.0 (MAX.): +2.5 Adopts data system 4-bit parallel serial input modes selectable with mode (P/S) Automatic transfer function enable signal Automatic counting function which, chip selection mode, causes internal clock stopped automatically counting 887256 bits input data Line latch circuits reset when XDISPOFF active (Common mode) Shift clock frequency: (MAX.) Built-in X-bit shift register Available single mode Y1->YX Single mode YX->Y1 Single mode PS:X=3248648096112120 above shift directions pin-selectable Shift register circuits reset when XDISPOFF active
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FEATURES
Number drive outputs: Supply voltage drive: +16V Supply voltage logic system: +2.5 +5.5 power consumption output impedance Display duty selectable select SEL2,SEL1,SEL0 DUTY 1/32 1/48 1/64 1/80 1/96 1/112 1/120 BIAS Segment mode 1/10 1/11 1/11
Low-power liquid crystal display power supply circuit equipped internally. Booster circuit (with Boost ratio 2X/3X/4X/5X/6X) Abundant command functions bias set, electronic volume, voltage regulation internal resistor ratio booster frequency.
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Sitronix DESCRIPTION
SYMBOL COMSEG0-COMSEG119 V0~V4 EIO2, EIO1 DI0-DI3 XDISPOFF XRST DESCRIPTION drive output Power supply drive Display data shift direction selection Power supply logic system (+2.5 +5.5 Input/output chip selection segment mode input output function com/seg mode common mode Display data input segment mode Clock input taking display data segment mode Control input output non-select level Latch pulse input display data segment mode/ Shift clock input shift register common mode AC-converting signal input drive waveform System Reset .When level active. XRST PULSE timing value 200us value 0.5s This parallel data input/serial data input switch terminal. P/S="H": Parallel data input. P/S="L": Serial data input. CAP1P Ground DC/DC voltage converter. Connect capacitor between this terminal CAP2- terminal. DC/DC voltage converter. Connect capacitor between this terminal CAP1- terminal. DC/DC voltage converter. Connect capacitor between this terminal CAP2- terminal. DC/DC voltage converter. Connect capacitor between this terminal CAP2- terminal. DC/DC voltage converter. Connect capacitor between this terminal CAP1- terminal. DC/DC voltage converter. Connect capacitor between this terminal CAP2- terminal. DC/DC voltage converter. Connect capacitor between this terminal CAP1- terminal. DC/DC voltage converter. Connect capacitor between this terminal VSS. This command mode select pin. When XCS="L" then write command LCD. Figure1
ST8012
CAP1+
CAP2-
CAP2+
CAP3+
CAP4+
CAP5+
VOUT
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Don't toggle SCLK from level while signal HIGHT
ST8012
command data. Figure1 serial clock input. Figure1 These Duty selection. SEL2,SEL1,SEL0 DUTY -1/32 1/48 1/64 1/80 1/96 1/112 1/120 BIAS Segment mode 1/10 1/11 1/11
SCLK
SEL2~SEL0
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Sitronix BLOCK DIAGRAM
COMSEG COMSEG COM/SEG COM/SEG
ST8012
Voltage fallower circuit XRST Vout CAP1CAP1+ CAP2CAP2+ CAP3CAP4+ CAP5+ SCLK Voltage Regulator circuit Voltage booster circuit
Power Supply Circuit
COM/SEGMENT DRIVER
LEVEL SHIFTER
/DISPOFF COM/SEG DATA LATCH Command decorder
EIO1 EIO2
Control
SEGMENT DATA LATCH
SEL2~SEL0
SHIFT Control
SHIFT_CONTROL
DI0~DI3
DATA Control
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Sitronix INPUT/OUTPUT CIRCUITS
ST8012
Interna
Input Circuit
Input Circuit
Internal Circuit Control Signal
(0V)
(0V)
Output Signal Application Pins Control Signal (0V)
Input/Output Circuit
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Sitronix FUNCTIONAL DESCRIPTION
Functions
FUNCTION Logic system power supply pin, connected +2.5 +5.5 Ground pin, connected (Segment mode) SYMBOL
ST8012
This multi-level power supply liquid crystal drive. voltage Supply applied determined liquid crystal cell, changed through resistive voltage divided through changing impedance using amp. Voltage levels determined based VSS, must maintain relative magnitudes shown below.
When power supply turns internal power supply circuits produce V1to V4voltages shown below. voltage settings selected using bias command. 1/120 Duty 1/112 Duty
1/11*V0, 1/9*V0 2/11*V0, 2/9*V0 9/11*V0, 7/9*V0 10/11*V0,8/9*V0
1/96Duty
1/80Duty
1/64Duty
1/48 Duty
1/30 Duty
1/11*V0 ,1/9*V0 2/11*V0,1/9*V0 9/11*V0, 7/9*V0 10/11*V0,8/9*V0
1/10*V0, 1/8*V0 1/9*V0, 1/7*V0 1/9*V0, 1/7*V0 1/7*V0, 1/5*V0 1/6*V0, 1/5*V0 2/10*V0, 2/8*V0 2/9*V0, 2/7*V0 2/9*V0, 2/7*V0 2/7*V0, 2/5*V0 2/6*V0, 2/5*V0 8/10*V0, 6/8*V0 7/9*V0, 5/7*V0 7/9*V0, 5/7*V0 5/7*V0, 3/5*V0 4/6*V0, 3/5*V0 9/10*V0, 7/8*V0 8/9*V0, 6/7*V0 8/9*V0, 6/7*V0 6/7*V0, 4/5*V0 5/6*V0, 4/5*V0
Input pins display data 4-bit parallel input mode, input data into pins, DI3-DI0. DI3-DI0 serial input mode, input data into pin,DI0. Connect DI3-DI1 Refer "RELATIONSHIP BETWEEN DISPLAY DATA DRIVE OUTPUT PINS" Functional Operations. Clock input taking display data Data read falling edge clock pulse. System Reset .When level active. XRST used hardware reset, this must pull height. XRST PULSE timing value 200us value 0.5s Latch pulse input display data Data latched falling edge clock pulse. Input selecting reading direction display data When level "L", data read sequentially from COMSEG119 COMSEG0. When level "H", data read sequentially from COMSEG0 COMSEG119. Refer "RELATIONSHIP BETWEEN DISPLAY DATA DRIVE OUTPUT PINS" Functional Operations. Control input output non-select level XDISPOFF input signal level-shifted from logic voltage level drive voltage level, controls drive circuit.
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ST8012
When level "L", drive output pins (COMSEG0-COMSEG119) level Vss. When "L", contents line latch reset, display data read data latch regardless condition XDISPOFF. When XDISPOFF function canceled, driver outputs non-select level V3), then outputs contents data latch next falling edge that time, XDISPOFF removal time does correspond what shown characteristics, cannot output reading data correctly. Table truth-values shown "TRUTH TABLE" Functional Operations. signal input drive waveform input signal level-shifted from logic voltage level drive voltage level, controls drive circuit.
Normally inputs frame inversion signal. drive output pins' output voltage levels using line latch output signal signal. Table truth-values shown "TRUTH TABLE" Functional Operations. Interface Mode selection
When then parallel data input mode. When serial data input mode, Input/output pins chip selection. segment mode: When input level "L", ElO1 output, EIO2 input(connect Vss). When input level "H", ElO1 input(connect Vss), EIO2 output. During output, while after bits data have been read, cycle (from falling edge failing edge XCK), after which returns "H". During input, chip selected while after signal input. chip non-selected after bits data have been read.
ElO1, EIO2
COMSEG0 -COMSEG119 CAP1CAP1+ CAP2CAP2+ CAP3+ CAP4+ CAP5+ VOUT SCLK
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drive output pins Corresponding directly each data latch, level (V0, ,V3,Vss) selected output. Table truth values shown "TRUTH TABLE" Functional Operations. DC/DC voltage converter. Connect capacitor between this terminal CAP2- terminal. DC/DC voltage converter. Connect capacitor between this terminal CAP1- terminal. DC/DC voltage converter. Connect capacitor between this terminal CAP2- terminal. DC/DC voltage converter. Connect capacitor between this terminal CAP2- terminal. DC/DC voltage converter. Connect capacitor between this terminal CAP1- terminal. DC/DC voltage converter. Connect capacitor between this terminal CAP2- terminal. DC/DC voltage converter. Connect capacitor between this terminal CAP1- terminal. DC/DC voltage converter. Connect capacitor between this terminal VSS. This command mode select pin. When XCS="L" then write command LCD, when used command mode then must fixed Figure1 command data. Figure1 serial clock input. Figure1
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(Common mode) SYMBOL FUNCTION Logic system power supply pin, connected +2.5 +5.5 Ground pin, connected
ST8012
This multi-level power supply liquid crystal drive. voltage Supply applied determined liquid crystal cell, changed through resistive voltage divided through changing impedance using amp. Voltage levels determined based VDD, must maintain relative magnitudes shown below. When power supply turns internal power supply circuits produce voltages shown below. voltage settings selected using bias command.
1/120 Duty 1/112 Duty
1/11*V0, 1/9*V0 2/11*V0, 2/9*V0 9/11*V0, 7/9*V0 10/11*V0,8/9*V0
1/96Duty
1/80Duty
1/64Duty
1/48 Duty
1/30 Duty
1/11*V0 ,1/9*V0 2/11*V0,1/9*V0 9/11*V0, 7/9*V0 10/11*V0,8/9*V0
1/10*V0, 1/8*V0 1/9*V0, 1/7*V0 1/9*V0, 1/7*V0 1/7*V0, 1/5*V0 1/6*V0, 1/5*V0 2/10*V0, 2/8*V0 2/9*V0, 2/7*V0 2/9*V0, 2/7*V0 2/7*V0, 2/5*V0 2/6*V0, 2/5*V0 8/10*V0, 6/8*V0 7/9*V0, 5/7*V0 7/9*V0, 5/7*V0 5/7*V0, 3/5*V0 4/6*V0, 3/5*V0 9/10*V0, 7/8*V0 8/9*V0, 6/7*V0 8/9*V0, 6/7*V0 6/7*V0, 4/5*V0 5/6*V0, 4/5*V0
Shift clock pulse input bi-directional shift register Data shifted falling edge clock pulse. System Reset .When level active.
used hardware reset, this must pull height. XRST PULSE timing value 200us value 0.5s Input selecting shift direction bi-directional shift register Data shifted from COMSEG119 COMSEG0 when level "L", data shifted from COMSEG0 COMSEG119 when level "H".
Refer "RELATIONSHIP BETWEEN DISPLAY DATA DRIVE OUTPUT PINS" Functional Operations.
Control input output non-select level input signal level-shifted from logic voltage level drive voltage level, controls drive circuit. When level "L", drive output pins (COMSEG0-COMSEGx) level Vss. XDISPOFF When "L", contents shift register reset reading data. When /DISPOFF function canceled, driver outputs non-select level V4), shift data read next falling edge that time, /DISPOFF removal time does correspond what shown characteristics, shift data read correctly. Table truth-values shown "TRUTH TABLE" Functional Operations. signal input drive waveform input signal level-shifted from logic voltage level drive voltage level, controls drive circuit.
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Normally inputs frame inversion signal.
ST8012
drive output pins' output voltage levels using shift register output signal signal. Table truth-values shown "TRUTH TABLE" Functional Operations.
DI3-DI0
used Connect DI3-DI0 VSS, floating. used pulled down common mode, connect drive output pins
COMSEG0 -COMSEG119
Corresponding directly each shift register, level VSS) selected output. Table truth-values shown "TRUTH TABLE" Functional Operations.
Shift data Input/output pins shift register EIO1 output when level "L", EIO1 input when level When L/R=H, EIO1 used input pin, will connect FLM. When L/R=L, EIO1 used output pin, won't connect FLM. ElO1, EIO2 EIO2 input when level "L", EIO1 output when level When L/R=H, EIO2 used output pin, won't connect FLM, When L/R=L, EIO2 used input pin, will connect Refer "RELATIONSHIP BETWEEN DISPLAY DATA DRIVE OUTPUT PINS" Functional Operations. CAP1CAP1+ CAP2CAP2+ CAP3+ CAP4+ CAP5+ VOUT SCLK DC/DC voltage converter. Connect capacitor between this terminal CAP2- terminal. DC/DC voltage converter. Connect capacitor between this terminal CAP1- terminal. DC/DC voltage converter. Connect capacitor between this terminal CAP2- terminal. DC/DC voltage converter. Connect capacitor between this terminal CAP2- terminal. DC/DC voltage converter. Connect capacitor between this terminal CAP1- terminal. DC/DC voltage converter. Connect capacitor between this terminal CAP2- terminal. DC/DC voltage converter. Connect capacitor between this terminal CAP1- terminal. DC/DC voltage converter. Connect capacitor between this terminal VSS. This command mode select pin. When XCS="L" then write command LCD, when used command mode then must fixed Figure1 command data. Figure1 serial clock input. Figure1
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(common /segment mode)
Input/output pins chip selection common/segment mode: When input level "L", ElO1 output, EIO2 input.
ST8012
ElO1 segment chip enable output, default segment enabled internally non-selected after 8,24,40,56,72 bits data have been read. Depend select mode. ElO2 :common shift data input, sift data output ElO1, EIO2 When input level "H", ElO1 input, EIO2 output. ElO1 :common shift data, shift data output ElO2 segment chip enable output, default segment enabled internally non-selected after 8,24,40,56,72 bits data have been read. Depend select mode. During output, while after bits data have been read, cycle (from falling edge failing edge XCK), after which returns "H". During input, chip selected while after signal input. chip non-selected after bits data have been read.
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Functional Operations TRUTH TABLE
(Segment Mode) LATCH DATA /DISPOFF
ST8012
DRIVE OUTPUT VOLTAGE LEVEL (COMSEG0-COMSEG119)
(Common Mode)
LATCH DATA
/DISPOFF
DRIVE OUTPUT VOLTAGE LEVEL (COMSEG0-COMSEG119)
NOTES: (+2.5 +5.5 Don't care "Don't care" should fixed "L", avoiding floating. There kinds power supply (logic level voltage drive voltage) driver. Supply regular voltage that assigned specification each power pin.
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ST8012
RELATIONSHIP BETWEEN DISPLAY DATA DRIVE OUTPUT PINS
(Segment Mode) 4-bit Parallel Input Mode EIO1 EIO2 DATA INPUT CLOCK CLOCK Output Input Input Output COMSEG0 COMSEG1 COMSEG2 COMSEG3 COMSEG4 COMSEG5 NUMBER CLOCKS CLOCK CLOCK CLOCK CLOCK
COMSEG8 COMSEG108 COMSEG112 COMSEG116 COMSEG9 COMSEG109 COMSEG113 COMSEG117
COMSEG6 COMSEG10 COMSEG110 COMSEG114 COMSEG118 COMSEG7 COMSEG11 COMSEG111 COMSEG115 COMSEG119 COMSEG3 COMSEG2 COMSEG1 COMSEG0
COMSEG119 COMSEG115 COMSEG111 COMSEG11 COMSEG7 COMSEG118 COMSEG114 COMSEG110 COMSEG10 COMSEG6 COMSEG117 COMSEG113 COMSEG109 COMSEG9 COMSEG116 COMSEG112 COMSEG108 COMSEG8 COMSEG5 COMSEG4
Serial Input Mode EIO1 EIO2 DATA NUMBER CLOCKS CLOCK CLOCK CLOCK
INPUT CLOCK CLOCK CLOCK COMSEG0 COMSEG1
COMSEG2 COMSEG117 COMSEG118 COMSEG119 COMSEG1 COMSEG0
Output Input
COMSEG119 COMSEG118 COMSEG117 COMSEG2
Input Output
(Common Mode) DATA TRANSFER DIRECTION COMSEG119 COMSEG0 COMSEG0 COMSEG119 EIO1 Output Input EIO2 Input Output
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MODE(SEGMENT/ COMMON MODE) When (SEL2,SEL1,SEL0)=(0,0,1) SELECT COM/88 SEGMENT MODE THEN SEGMENT SIDE MODE 4-bit Parallel Input Mode EIO1 EIO2 DATA INPUT CLOCK CLOCK Seg_end Com_FLM Output Input Com_FLM Seg_end Input Output Serial Input Mode EIO1 EIO2 DATA INPUT CLOCK Seg_end Com_FLM Output Input Com_FLM Seg_end Input Output COMMON SIDE MODE NOTES: (+2.5 +5.5 Don't care "Don't care" should fixed "L", avoiding floating. DATA TRANSFER DIRECTION COMSEG119 COMSEG88 COMSEG0 COMSEG31 EIO1 Seg_end output Input EIO2 Input Seg_end output COMSEG0 CLOCK COMSEG1 NUMBER CLOCKS CLOCK CLOCK COMSEG0 COMSEG1 COMSEG2 COMSEG3 COMSEG4 COMSEG5 NUMBER CLOCKS CLOCK CLOCK
ST8012
CLOCK
CLOCK
COMSEG8 COMSEG76 COMSEG80 COMSEG84 COMSEG9 COMSEG77 COMSEG81 COMSEG85
COMSEG6 COMSEG10 COMSEG78 COMSEG82 COMSEG86 COMSEG7 COMSEG11 COMSEG79 COMSEG83 COMSEG87
COMSEG119 COMSEG115 COMSEG110 COMSEG43 COMSEG39 COMSEG35 COMSEG118 COMSEG114 COMSEG109 COMSEG42 COMSEG38 COMSEG34 COMSEG117 COMSEG113 COMSEG108 COMSEG41 COMSEG37 COMSEG33 COMSEG116 COMSEG112 COMSEG107 COMSEG40 COMSEG36 COMSEG32
CLOCK
CLOCK
COMSEG2 COMSEG85 COMSEG86 COMSEG87
COMSEG119 COMSEG118 COMSEG117 COMSEG34 COMSEG33 COMSEG32
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Connection examples plural segment drivers(120 segment)
When
data Data flow Last data
ST8012
COMSEG119
EIO2
COMSEG0
EIO1
COMSEG119
EIO2
COMSEG0 COMSEG119
EIO1 EIO2
COMSEG0
EIO1
DI3-DI0
DI3-DI0
DI3-DI0
DI3-DI0
When
DI3-DI0 EIO1 EIO2 DI3-DI0 EIO1 EIO2 DI3-DI0 EIO1 EIO2 DI3-DI0
COMSEG0
data
COMSEG119
Data flow
COMSEG0 COMSEG0 COMSEG119
Last data
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ST8012
Timing chart 4-device cascade connection segment drivers
DATA
LAST DATA
device
device
device
device
(device (device
(device
(device 4-bit parallel input mode serial input mode
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Connection examples signal common drivers (120 common)
First
ST8012
COMSEG119
COMSEG0
EIO2 XDISPOFF
EIO1
XDISPOFF
XDISPOFF
XDISPOFF
EIO1
EIO2
COMSEG0
First
COMSEG119
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Connection examples plural common/segment(mix mode) drivers mode 1/32,1/48,1/64,1/80,1/96,1/112 duty mode
ST8012
DI3-DI0 EIO2 EIO1 EIO2 EIO1 DI3-DI0 DI3-DI0
Y119 YX+1
Data flow
Y119
PS:Y==>COMSEG
L/R="H"
DI3-DI0 EIO1 EIO2 DI3-DI0 EIO1 EIO2 DI3-DI0
YX+1 Y119
Data flow
Y119
PS:Y==>COMSEG
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Connection examples &120 (for 1/120 duty)
ST8012
DI3-DI0 EIO2 EIO1 EIO2 EIO1 DI3-DI0 DI3-DI0
Y119 YX+1
Y119
PS:Y==>COMSEG
Data flow
DI3-DI0 EIO1 EIO2 DI3-DI0 EIO1 EIO2 DI3-DI0
YX+1 Y119
Y119
PS:Y==>COMSEG
Data flow
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PRECAUTIONS
Precautions when connecting disconnecting power supply This high-voltage driver, high current that flow voltage supplied drive power supply while logic system power supply floating permanently damage details follows, When connecting power supply, connect drive power after connecting logic system power. Furthermore, when disconnecting power, disconnect logic system power after disconnecting drive power when connecting logic power supply, logic
ST8012
condition this inside insecure. Therefore connect drive power supply after resetting logic condition this inside /DISPOFF function. After that, cancel /DISPOFF function after drive power supply become stable. Furthermore, when disconnecting power, drive output pins level /DISPOFF function. Then disconnect logic system power after disconnecting drive power. When connecting power supply, follow recommended sequence shown here
XDISPOFF
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Sitronix DESCRIPTION FUNCTIONS
ST8012
Interface Selecting Interface Type
With ST8012 chips, data transfers done through 4-bit parallel data through serial data input (SI). Through selecting terminal polarity possible select either parallel data input serial data input shown Table
Table
Parallel Input Serial Input
D3~D1
D3~D1
Command Serial Interface
With ST8012 chips, command data transfers done through serial data input. it's timing show Figure1.
Figure1
Write command timing diagram
SCLK
:when don't command must height level.
Power Supply Circuits (use serial interface)
power supply circuits low-power consumption power supply circuits that generate voltage levels required drivers. They Booster circuits, voltage regulator circuits, voltage follower circuits. They only enabled master operation, when mode common mode common/segment mode. power supply circuits turn Booster circuits, voltage regulator circuits, voltage follower circuits independently through Power Control command. Consequently, possible make external power supply internal power supply function somewhat parallel. Table shows Power Control Command 3-bit data control function, Table shows reference combinations.
Table3
Function
Booster circuit control
Status "111" "000"
Control Details Each Power Control Command
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Table4
Settings Only internal power supply used Only voltage regulator circuit voltage follower circuit used Only internal power supply used Only voltage regulator circuit voltage follower circuit used mode mode Com/Seg mode External voltage input
ST8012
Voltage Voltage booster regulator
Voltage follower
Step-up voltage
Used
VOUT,
Open
Used
VOUT,
Open
Command interface unused mode (use default value)
When command interface unused. CS,SCLK signal fixed following mode
Table5
SCLK
Booster
Regulator
Follower
Default register used (All Off)
DEFAULT BIAS,CONTRAST CONTROL,Ra/Rb ratio Boost Frequency used when above mode selected. NOTE SCLK signals level. default power control register will used, power control booster, regulator follower will always off. PROGRAM NOTE: toggle sclk from level while signal HIGHT. Entry Standby mode: Entry standby must closed circuit(BOOSTER) /XDISPOFF also level.
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Step-up Voltage Circuits
Using step-up voltage circuits equipped within ST8012 chips possible product step-up: Connect capacitor between CAP1+ CAP1-, between CAP2+ CAP2-, between CAP1+ CAP3-, between CAP2+ CAP4-,between CAP1+ CAP5-, between VOUT, produce step-up: Connect capacitor between CAP1+ CAP1-, between CAP2+ CAP2-, between CAP1+ CAP3-, between CAP2+ CAP4-,and between step-up: Connect capacitor between CAP1+ CAP1-, between CAP2+ CAP2-, between CAP1+ CAP3-, between VOUT, produce step-up: Connect capacitor between CAP1+ CAP1-, between CAP2+ CAP2- between VOUT,and short between CAP3- VOUT produce voltage level negative direction VOUT step-up: Connect capacitor between CAP1+ CAP1-, between VOUT, leave CAP2+ open, short between CAP2-, CAP3- VOUT produce voltage negative direction VOUT terminal that twice voltage between VSS.
ST8012
step-up voltage levels.
voltage level negative direction VOUT terminal that times voltage level between VSS.
VOUT, produce voltage level negative direction VOUT terminal that times voltage level between VSS.
voltage level negative direction VOUT terminal that times voltage level between VSS.
terminal that times voltage difference between VSS. step-up voltage relationships shown Figure2.
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VOUT CAP3+ CAP1C1 CAP1+ CAP2+ CAP2CAP4+ CAP5+ step-up voltage circuit VOUT=4xVDD=12V VDD=3V VSS=0V step-up voltage relationships CAP2CAP4+ CAP5+ step-up voltage circuit VOUT=3xVDD=9V VDD=3V VSS=0V step-up voltage relationships OPEN CAP2CAP4+ CAP5+ step-up voltage circuit VOUT=2xVDD=6V VDD=3V VSS=0V ST8012 VOUT CAP3+ ST8012 CAP1C1 CAP1+ CAP2+ VOUT CAP3+
ST80
ST8012
CAP1C1 CAP1+ CAP2+
step-up voltage relationships
VOUT CAP3+ CAP1C1 CAP1+ CAP2+ CAP2C1 CAP4+ Vout CAP5+ ST8012
VOUT CAP3+ ST8012 CAP1C1 CAP1+ CAP2+ CAP2CAP4+ CAP5+ step-up voltage circuit VOUT=6xVDD=15V VDD=2.5V VSS=0V step-up voltage relationships
step-up voltage circuit VOUT=5xVDD=15V VDD=3V VSS=0V step-up voltage relationships
Figure2
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voltage range must that VOUT terminal voltage does exceed absolute maximum rated value
2003
Sitronix
Voltage Regulator Circuit
step-up voltage generated VOUT outputs driver voltage through voltage regulator circuit. Because ST78012 chips have internal high-accuracy fixed voltage power supply with 64-level electronic volume function internal
ST80
resistors voltage regulator, systems constructed without having include high-accur voltage regulator circuit components.(VREG ther gradients approximate -0.05%/°C)
When Voltage Regulator Internal Resistors Used
Through voltage regulator internal resistors electronic volume function liquid crystal power supply voltage controlled commands alone (without adding external
resistors), making possible adjust liquid crystal display brightness. voltage calculated using equation over range wher VOUT|.
Figure
Internal
Internal
(constant voltage supply+electronic volume)
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VREG IC-internal fixed voltage supply, voltage 25°C shown Table
ST8012
Table6
Part ST8012
Equipment Type
Internal Power Supply
Thermal Gradient
-0.05 %/°C
VREG
2.1V
level possible levels electronic volume function depending data 6-bit electronicvolume register. Table shows value depending electronic volume register settings. Rb/Ra voltage regulator internal resistor ratio, different levels through voltage regulator internal resistor ratio command. Rb/Ra ratio assumes values shown Table depending 3-bit data settings voltage regulator internal resistor ratio register.
Table7
voltage regulator internal resistance ratio register value Rb/Ra) ratio (Reference value)
Table8
Register ST8012 -0.05 %/°C 5.22 5.48 5.76 6.07 6.42 6.81 7.25
UNIT Ta=25 booster off, regulator, follower out=16V, Vdd=3V
Electronic volume Resistor ratio
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Voltage Generator Circuit
voltage produced resistive voltage divider within produced voltage levels required liquid crystal
ST8012
driving. Moreover, when voltage follower changes impedance, provides liquid crystal drive circuit.
Reference Circuit Examples
Figure shows reference circuit examples. 1.When used step-up circuit, voltage regulating circuit circuit. (Example with setup-up) 2.When voltage regulator circuit circuit alone used
Figure
VOUT CAP3+ CAP1CAP1+ CAP2CAP2+ ST8012 CAP4+ CAP5+ Vout
Externa power supply
VOUT CAP3+ CAP1CAP1+ CAP2CAP2+ ST8012 CAP4+ CAP5+
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3.When built-in power circuit used drive liquid crystal panel heavily loaded with recommended connect external resistor stabilize potentials which
ST8012
output from built-in voltage follower. Examples shared reference settings When vary between
Item
value
units
ST8012
determined size being driven
Reference value R4:100K
recommended optimum resistance value wveform
taking liquid crystal display drive
Because terminal input impedance high, short leads shielded lines. determined size being driven. Select value that will stabilize liquid crystal drive voltage. Example Process which Determine Settings: Turn voltage regulator circuit voltage follower circuit supply voltage VOUT from outside. Determine displaying pattern with heavy load (such horizontal stripes) selecting that stabilizes liquid crystal drive voltages V4). Note that capacitors must have same capacitance value. Next turn power supplies determine
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Sitronix
COMMANDS
ST8012 identify data signals combination XCS, SDI, SCLK signals. <Example Commands> Bias This command selects voltage bias ratio required liquid crystal display. select Frame direction select normal else select reverse. Select Status
1/120duty 1/112duty 1/96duty 1/80duty 1/64duty
ST8012
1/48duty
1/32duty
1/11 bias 1/11 bias 1/10 bias bias bias bias
bias bias bias bias
bias bias bias bias
bias bias bias bias
bias bias bias bias
1/11 bias 1/11 bias 1/10 bias bias bias bias
Power Controller This command sets power supply circuit functions. function explanation "The Power Supply Circuit," details
Selected Mode
Booster circuit: Booster circuit:
Voltage Regulator Internal Resistor Ratio This command sets voltage regulator internal resistor ratio. details, function explanation "The Voltage Regulator circuit table
Rb/Ra Ratio
Small
Large
Electronic Volume This command makes possible adjust brightness liquid crystal display controlling drive voltage through output from voltage regulator circuits internal liquid crystal power supply. Electronic Volume Register using this command bits data electronic volume register, liquid crystal drive voltage assumes voltage levels. When this command input, electronic volume mode released after
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electronic volume register been set.
ST8012
|VSS|
Small
Large
Booster Frequency using this command three bits data booster frequency, liquid crystal drive Booster Frequency assumes frequencies. When this command input, booster frequency register been set.
Booster Frequency Small
Large
default value ST8012
When select common mode common/segment mode BiasContrast controlRa/Rb Ratio Booster Frequency have default value, user don't used programmable setting status used default value. DUTY -1/32 1/48 1/64 1/80 1/96 1/112 1/120 BIAS Segment mode 1/10 1/11 1/11 Contrast control Ra/Rb Ratio Booster Frequency
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Sitronix TABLE ST8012 COMMAND
ST8012
Command
bias
Command Code
Function
D0Sets drive voltage bias ratio.0: bias, bias (ST8012)
Power control voltage regulator internal resistor ratio Electronic volume mode Electronic volume register Electronic volume value
Power control Resistor ratio
select frame direction.0:normal,1:reverse Select internal power supply operating mode
Select internal resistor ratio(Rb/Ra) mode
output voltage electronic volume register
Booster Frequency
Booster Frequency booster frequency
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Sitronix BSOLUTE MAXIMUM RATINGS
PARAMETER Supply voltage SYMBOL Supply voltage Input voltage Storage temperature TSTG APPLICABLE PINS D14-DI0, XCK, L/R, EIO1, EIO2,XDISPOFF, RATING UNIT
ST8012
NOTE
-0.3~+5.5
VDD+10~ VDD-0.3 VDD+10~ VDD-0.3 -0.3~V5S+10 -0.3~V5S+10
-0.3 VDD+0.3
+125
NOTES: maximum applicable voltage with respect
RECOMMENDED OPERATING Conditions
PARAMETER Supply voltage Supply voltage Operating temperature SYMBOL TOPR APPLICABLE PINS MIN. +2.5 +6.0 TYP. MAX. +5.5 +16.0 UNIT NOTE
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Sitronix ELECTRICAL CHARACTERISTICS
Characteristics
(Segment Mode) (VSS +2.5 +3.6 +15.0 TOPR +85°C)
ST8012
PARAMETER
Input "Low" voltage Input "High" voltage Output "Low" voltage Output "High" voltage Input leakage current Output resistance Standby current Supply current (Non-selection) Supply current (Selection) Supply current
SYMBOL CONDITIONS
ILIL ILIH ISTB IDD1 IDD2 +0.4 -0.4 |VON| =0.5V
APPLICABLE PINS
MIN. TYP. MAX. UNIT NOTE
0.2VDD +0.4 VDD-0.4
DI3-DI0, XCK, EIO1, EIO2,XDISPOFF 0.8VDD EIO1, EIO2 DI3-DI0, XCK, LIR, EIO1, EIO2, XDISPOFF Y1-Y120
NOTES: +3.0 +12.0 +3.0 +12.0 fXCK MHz, no-load, VDD. input data turned over data taking clock (4-bit parallel input mode). +3.0 +12.0 fXCK MHz, no-load, VSS. input data turned over data taking clock (4-bit parallel input mode). +3.0 +12.0 fXCK 8MHz, 19.2 kHz, no-load. input data turned over data taking clock (4-bit parallel input mode). (Common Mode) (VSS +2.5 +3.6 +6.0 +15.0 TOPR PARAMETER Input "Low" voltage Input "High" voltage Output "Low" voltage Output "High" voltage Input leakage current ILIH Input pull-down current Output resistance |VON| =0.5V SYMBOL ILIL CONDITIONS APPLICABL PINS MIN. TYP. MAX. UNIT NOTE 0.2VDD DI4-DI0, XCK, P/S, DIX, EIO1, 0.8VDD EIO2, XDISPOFF +0.4 EIO1, EIO2 VDD-0.4 DI4-DI0, XCK, P/S, DIX, EIO1, -10.0 EIO2, XDISPOFF DI4-DI0, L/R, +10.0 P/S, DIX, XDISPOFF XCK, EIO1, EIO2 COMSEG0COMSEG119
+0.4 -0.4
Standby current ISPD Supply current Supply current NOTES: +3.0 +12.0 +3.0 +12.0 =19.2 kHz, 1/240 duty operation, no-load.
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Characteristics
(Segment Mode
ST8012
(VSS +2.5 +3.6 +15.0 TOPR 10+85 TYP. MAX. UNIT NOTE
PARAMETER SYMBOL CONDITIONS Shift clock period tWCK tR,tF 11ns Shift clock pulse width tWCKH Shift clock pulse width tWCKL Data setup time Data hold time Latch pulse pulse width tWLPH Shift clock rise latch pulse rise time Shift clock fall latch pulse fall time Latch pulse rise shift clock rise time Latch pulse fall shift clock fall time Enable setup time Input signal rise time Input signal fall time DISPOFF removal time DISPOFF pulse width tWDL Output delay time Output delay time tPD1, Output delay time NOTES: Takes cascade connection into consideration. (tWCK tWCKH tWCKL)/2 maximum case high speed operation. (Segment Mode
(VSS +5.0±0.5 +15.0 TOPR MIN. TYP. MAX. UNIT NOTE
PARAMETER SYMBOL CONDITIONS Shift clock period tWCK tR,tF 10ns Shift clock pulse width tWCKH Shift clock pulse width tWCKL Data setup time Data hold time Latch pulse pulse width tWLPH Shift clock rise latch pulse rise time Shift clock fall latch pulse fall time Latch pulse rise shift clock rise time Latch pulse fall shift clock fall time Enable setup time Input signal rise time Input signal fall time DISPOFF removal time DISPOFF pulse width tWDL Output delay time Output delay time tPD1, Output delay time NOTES: Takes cascade connection into consideration. (tWCK tWCKH tWCKL)/2 maximum case high speed operation.
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(Segment Mode (VSS +3.0 +3.6 +15.0 TOPR 10+85 CONDITIONS tR,tF 10ns MIN. TYP. MAX. PARAMETER SYMBOL Shift clock period tWCK Shift clock pulse width tWCKH Shift clock pulse width tWCKL Data setup time Data hold time Latch pulse pulse width tWLPH Shift clock rise latch pulse rise time Shift clock fall latch pulse fall time Latch pulse rise shift clock rise time Latch pulse fall shift clock fall time Enable setup time Input signal rise time Input signal fall time DISPOFF removal time DISPOFF pulse width tWDL Output delay time Output delay time tPD1, Output delay time NOTES: Takes cascade connection into consideration. (tWCK tWCKH tWCKL)/2 maximum case high speed operation. (Common Mode) (VSS +2.5 +5.5 +15.0 TOPR 10+85
ST8012
UNIT NOTE
PARAMETER
Shift clock period Shift clock pulse width Data setup time Data hold time Input signal rise time Input signal fall time DISPOFF removal time DISPOFF pulse width Output delay time Output delay time Output delay time
SYMBOL
tWLP tWLPH tWDL tPD1,tPD2 tPD3
CONDITIONS
20ns VDD=5± 0.5V VDD=2.5~4.5V
UNIT
CL=10pF CL=10pF CL=10pF
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Timing Chart Segment Mode
tWLPH
ST8012
tWCKH tWCKL
tWCK
LAST DATA
DATA
tWDL
XDISPOFF
4-bit parallel input mode serial input mode
tPD1 tPD2 XDISPOFF tPD3 Y120
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(Common Mode) (VSS +2.5 +3.6 +6.0 +15.0 TOPR +85° SYMBOL tWLP tWLPH tWDL tPD1, CONDITIONS tR,tF 20ns +5.0± 0.5V +2.5+ 4.5V MIN. TYP. MAX. PARAMETER Shift clock period Shift clock pulse width Data setup time Data hold time Input signal rise time Input signal fall time DISPOFF removal time DISPOFF pulse width Output delay time Output delay time Output delay time
ST8012
UNIT
Timing Chart Common Mode
tWLP
tWLPH
EIO2
EIO1
tWDL
XDISPOFF
tPD1 tPD2 XDISPOFF tPD3 Y120
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Sitronix
serial interface timing
tCCSS (CS2="1") tSCYC tSLW SCLK tSHW tSDS tSDH tCSH
ST8012
Item
Signal
Symbol
Condition
Serial Clock Period pulse width pulse width Data setup time Data hold time CS-SCL time CS-SCL time
SCLK
tSCYC tSHW tSLW tSDS tSDH tCSS tCSH
Rating Min. Max. Rating Min. Max. Rating Min. Max.
Units
Item
Signal
Symbol
Condition
Units
Serial Clock Period pulse width pulse width Data setup time Data hold time CS-SCL time CS-SCL time
Item
SCLK
tSCYC tSHW tSLW tSDS tSDH tCSS tCSH
Symbol Condition
Signal
Units
Serial Clock Period pulse width pulse width Data setup time Data hold time CS-SCL time CS-SCL time
SCLK
tSCYC tSHW tSLW tSDS tSDH tCSS tCSH
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Sitronix APPLICATION CIRCUIT
8051 serial transfer mode example
SCLK MOVBIT SID,D.7 SETB SCLK SCLK MOVBIT SID,D.6 SETB SCLK SCLK MOVBIT SID,D.5 SETB SCLK SCLK MOVBIT SID,D.4 SETB SCLK SCLK MOVBIT SID,D.3 SETB SCLK SCLK MOVBIT SID,D.2 SETB SCLK SCLK MOVBIT SID,D.1 SETB SCLK SCLK MOVBIT SID,D.0 SETB SCLK SCLK SETB ;SID=D.0 READ DATA FROM ;SID=D.1 READ DATA FROM ;SID=D.2 READ DATA FROM ;SID=D.3 READ DATA FROM ;SID=D.4 READ DATA FROM ;SID=D.5 READ DATA FROM ;SID=D.6 READ DATA FROM ;SID=D.7 READ DATA FROM
ST8012
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Application Data Writing segment mode
ST8012
When ST8012 segment mode driver must write data part display, when segments used Example: second segment have segments ,but only segments then must write data that need right ,then still write data fill part segments used .Otherwise there will having errors, when don't write data fill part display segments. summary ST8012 segment mode must write number segments data fill segments.(EX ST8012 show 64X132, then must write 80X160 data fill segments, three ST8012 show 120X200 must write 120X240 data fill segments.)
segments must write data.
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Application1 Circuit Module VLCD
Duty Vlcd
ST8012
1/32 1/48 1/64 1/80 1/96 1/112 1/120
9,10 10,11 10,11 11,12 11,12
Note value panel's resistor
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Application2 Circuit Module 1/120 duty, commons segments
DI3~DI0 XDISPOFF
ST8012
DI3~DI0
COMSEG0~ COMSEG119
Vout
XDISPOFF
PANEL
ST8012
COMSEG0~ COMSEG119
EIO1 EIO2
R=100~3.3K
DI3~DI0 SEL2 SEL1 SEL0 XDISPOFF
Vout
ST8012
1/80 duty, commons segments
DI3~DI0 SEL2 SEL1 SEL0 XDISPOFF EIO1
R=100~3.3K
DI3~DI0
COMSEG0~ COMSEG119
XDISPOFF
PANEL
EIO2
Vout
COMSEG0~ COMSEG119
ST8012
DI3~DI0 SEL2 SEL1 SEL0 XDISPOFF
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EIO1
EIO2
ST8012
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Sitronix DIAGRAM
Chip size5,840(µm) 2,820(µm) size80 Origin Chip center (0,0) Pitch110 Chip Thickness19 (19X25.4µm=482.6µm)
ST8012
COMSEG111
COMSEG119 VOUT CAP3P CAP1N CAP1P CAP2P CAP2N CAP4P CAP5P XRST EIO1 EIO2 XDISPOFF SCLK SEL2 SEL1 SEL0 COMSEG0
COMSEG9
COMSEG110
COMSEG10
ST8012
COMSEG32
COMSEG87
Substrate Connect Vss.
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COMSEG33
COMSEG86
Sitronix
Unitum Pin.No Page name COMSEG110 COMSEG111 COMSEG112 COMSEG113 COMSEG114 COMSEG115 COMSEG116 COMSEG117 COMSEG118 COMSEG119 VOUT CAP3P CAP1N CAP1P CAP2P CAP2N CAP4P CAP5P XRST EIO1 EIO2 XDISPOFF SCLK SEL2 SEL1 SEL0 COMSEG0 COMSEG1
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ST8012
2810 2650 2510 2380 2260 2150 2050 1950 1850 1750 1650 1550 1450 1350 1250 1150 1050 -150 -250 -350 -450 -550 -650 -750 -850 -950 -1050 -1150 -1250 -1350 -1450 -1550 -1650 -1750 -1850 Pin.No Page name 1300 COMSEG33 1300 COMSEG34 1300 COMSEG35 1300 COMSEG36 1300 COMSEG37 1300 COMSEG38 1300 COMSEG39 1300 COMSEG40 1300 COMSEG41 1300 COMSEG42 1300 COMSEG43 1300 COMSEG44 1300 COMSEG45 1300 COMSEG46 1300 COMSEG47 1300 COMSEG48 1300 COMSEG49 1300 COMSEG50 1300 COMSEG51 1300 COMSEG52 1300 COMSEG53 1300 COMSEG54 1300 COMSEG55 1300 COMSEG56 1300 COMSEG57 1300 COMSEG58 1300 COMSEG59 1300 COMSEG60 1300 COMSEG61 1300 COMSEG62 1300 COMSEG63 1300 COMSEG64 1300 COMSEG65 1300 COMSEG66 1300 COMSEG67 1300 COMSEG68 1300 COMSEG69 1300 COMSEG70 1300 COMSEG71 1300 COMSEG72 1300 COMSEG73 1300 COMSEG74 1300 COMSEG75 1300 COMSEG76 1300 COMSEG77 1300 COMSEG78
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-2810 -2650 -2510 -2380 -2260 -2150 -2050 -1950 -1850 -1750 -1650 -1550 -1450 -1350 -1250 -1150 -1050 -950 -850 -750 -650 -550 -450 -350 -250 -150 1050 1150 1250 1350 1450 1550 1650 1750 1850
-1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300
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COMSEG2 COMSEG3 COMSEG4 COMSEG5 COMSEG6 COMSEG7 COMSEG8 COMSEG9 COMSEG10 COMSEG11 COMSEG12 COMSEG13 COMSEG14 COMSEG15 COMSEG16 COMSEG17 COMSEG18 COMSEG19 COMSEG20 COMSEG21 COMSEG22 COMSEG23 COMSEG24 COMSEG25 COMSEG26 COMSEG27 COMSEG28 COMSEG29 COMSEG30 COMSEG31 COMSEG32 -1950 -2050 -2150 -2260 -2380 -2510 -2650 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 1300 1300 1300 1300 1300 1300 1300 1300 1160 1030 -100 -200 -300 -400 -500 -600 -700 -800 -910 -1030 -1160 COMSEG79 COMSEG80 COMSEG81 COMSEG82 COMSEG83 COMSEG84 COMSEG85 COMSEG86 COMSEG87 COMSEG88 COMSEG89 COMSEG90 COMSEG91 COMSEG92 COMSEG93 COMSEG94 COMSEG95 COMSEG96 COMSEG97 COMSEG98 COMSEG99 COMSEG100 COMSEG101 COMSEG102 COMSEG103 COMSEG104 COMSEG105 COMSEG106 COMSEG107 COMSEG108 COMSEG109
ST8012
1950 2050 2150 2260 2380 2510 2650 2810 2810 2810 2810 2810 2810 2810 2810 2810 2810 2810 2810 2810 2810 2810 2810 2810 2810 2810 2810 2810 2810 2810 2810 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1300 -1160 -1030 -910 -800 -700 -600 -500 -400 -300 -200 -100 1030 1160
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ST8012
NOTE 2001.12/19 Modify booster capacity 2002 Modify serial command interface-timing block (p16) 2002 1/14 Modify Register command code 2002 1/17 Modify Reset Register command defined 2002 1/23 Modify description defined command interface unused mode (p17) 2002 2/22 Modify Booster circuit diagram (p19) 2002 2/22 Modify Mode table(p10)add serial interface timing(p33p34)add data(p37) 2002 2/22 Modify (p34) 2002/3/20 Modify serial interface, when serial interface data.and direction. 2002/4/3 Modify location (P39) 2002/06/04 Modify XREST ACTIVE (p2) 2002/06/010 Modify Chip Size (P37) 2002/06/21 Modify common segment mode description (P6~P8) 2002/07/01 Modify booster circuit (P20) 2002/07/09 Command interface unused mode (use default value)(P18) 2002/10/14 Delete software reset package regulator liner line delete some application. 2002/11/22 Modify booster frequency V1.1A 2003/03/31 Modify booster turns command (p28) 2003/04/04 used math. 2003/4/17 Modify Application circuit 2003/6/17 Application circuit V1.3 2003/11/12 Pitch value V1.4
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DESCRIPTION ST8012 120-output segment/common driver suitable driv

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