matrix possible power operation support: 5.5V Wide range driver power

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matrix possible power operation support: 5.5V Wide range driver power

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Sitronix
matrix possible power operation support: 5.5V Wide range driver power 7.0V Support high speed serial interface Correspond high speed interface (when 9-bit display characters max.) 19840-bit character generator total character fonts(5 dot) 8-bit character generator character fonts dot)
ST7070
Matrix Controller/Driver
16-common 80-segment liquid crystal display driver Programmable duty cycles line dots with cursor 1/16 lines dots cursor Wide range instruction functions: Display clear, cursor home, display on/off, cursor on/off, cursor shift, display shift Automatic reset circuit that initializes controller/driver after power Internal oscillator with external resistors power consumption
Description
ST7070 dot-matrix liquid crystal display controller driver displays alphanumeric, Japanese kana characters, symbols. configured drive dot-matrix liquid crystal display under control 8-bit microprocessor. With high speed serial interface(3-line 4-line SPI), external control ST7070 directly. Since functions such display RAM, character generator, liquid crystal driver, required driving dot-matrix liquid crystal display internally provided chip, minimal system interfaced with this controller/driver. ST7070 function partial compatibility with HD44780, KS0066 SED1278 that allows user easily replace with ST7070. ST7070 character generator extended generate character fonts total different character fonts. power supply (2.7V 5.5V) ST7070 suitable portable battery-driven product requiring power dissipation. ST7070 driver consists common signal drivers segment signal drivers which extend display size cascading segment driver ST7921. maximum display size either characters 1-line display characters 2-line display. single ST7070 display 16-character line 16-character lines.
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ST7070
ST7070 Serial Specification Revision History Version 0.1- Preliminary Date 2002/9/23 Preliminary version Description
0.1- Preliminary 2002/11/21 3-line interface 0.2- Preliminary 2002/12/20 0.3- Preliminary 2003/01/21 0.4- Preliminary substrate change substrate. location modify. Modify "Supply Voltage Drive" Description Configuration
2003/2/18 Application circuit 2003/07/24 Modify interface Initializing flow Instruction 2003/08/28 Change font Table (0B) 2003/09/09 Characteristics Note 2003/11/10 Modify interface Initializing flow Instruction serial interface Initializing flow
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ST7070 Block Diagram
OSC1 OSC2 Timing generator
XRESET
Reset circuit Instruction register(IR)
Instruction decoder
Display data (DDRAM) 80x9 bits
16-bit shift register
Common signal driver
COM1 COM16
interface Address counter 80-bit shift register 80-bit latch circuit Segment signal driver
SEG1 SEG80
Input/ output buffer
Data register (DR) drive voltage selector
Busy flag
Character generator (CGRAM) bytes
Character generator (CGROM) 19840 bits
Cursor blink controller
Parallel/serial converter attribute circuit
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ST7070 Arrangement
Mark
Substrate must connect "Vss".
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ST7070 Configuration
Function DB[7] XRESET DB[6] DB[5] DB[4] DB[3] DB[2] DB[1] DB[0] COM[9] COM[10] COM[11] COM[12] COM[13] COM[14] COM[15] COM[16] SEG[41] SEG[42] SEG[43] SEG[44] SEG[45] SEG[46] SEG[47] SEG[48] SEG[49] SEG[50] SEG[51] -2585 -2585 -2585 -2585 -2585 -2585 -2585 -2585 -2585 -2585 -2585 -2585 -2585 -2585 -2445 -2315 -2195 -2085 -1975 -1865 -1755 -1645 -1535 -1425 -1315 -1208 -1102 -997 -892 -787 -682 -577 -105 -210 -320 -430 -540 -660 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 Function SEG[52] SEG[53] SEG[54] SEG[55] SEG[56] SEG[57] SEG[58] SEG[59] SEG[60] SEG[61] SEG[62] SEG[63] SEG[64] SEG[65] SEG[66] SEG[67] SEG[68] SEG[69] SEG[70] SEG[71] SEG[72] SEG[73] SEG[74] SEG[75] SEG[76] SEG[77] SEG[78] SEG[79] SEG[80] -472 -367 -262 -157 1102 1207 1315 1425 1535 1645 1755 1865 1975 2085 2195 2315 2445 2585 2585 2585 2585 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -660 -540 -430
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ST7070
Function OSC2 OSC1 SEG[40] SEG[39] SEG[38] SEG[37] SEG[36] SEG[35] SEG[34] SEG[33] SEG[32] SEG[31] SEG[30] SEG[29] SEG[28] SEG[27] SEG[26] SEG[25] SEG[24] SEG[23] SEG[22] SEG[21] SEG[20] SEG[19] SEG[18] 2585 2585 2585 2585 2585 2585 2585 2585 2585 2585 2585 2445 2315 2195 2085 1975 1865 1755 1645 1535 1425 1315 1207 1102 -320 -210 -105 Function SEG[17] SEG[16] SEG[15] SEG[14] SEG[13] SEG[12] SEG[11] SEG[10] SEG[9] SEG[8] SEG[7] SEG[6] SEG[5] SEG[4] SEG[3] SEG[2] SEG[1] COM[1] COM[2] COM[3] COM[4] COM[5] COM[6] COM[7] COM[8] -157 -262 -367 -472 -577 -682 -787 -892 -997 -1102 -1208 -1315 -1425 -1535 -1645 -1755 -1865 -1975 -2085 -2195 -2315 -2445 -2585
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ST7070 Function
Name Number Interfaced with
Function
Select registers. Instruction register (for write) Busy flag: address counter (for read) Data register (for write read) When serial interface select pull floating. Select read write. Write Read When serial interface select ,R/W pull low, floating. Starts data read/write. When serial interface select pull height floating. Hardware reset pin, active Parallel /Serial selection. PSB: Parallel Serial. Four high order bi-directional tristate data pins. Used data transfer receive between ST7070. used busy flag. Serial: DB7:data input serial mode(SI) DB6:serial clock input serial mode(SCL) DB5:chip select serial mode(/CS) When serial interface select pull height floating. 4bits mode These pins used during 4-bit operation. Four order bi-directional tristate data pins. Used data transfer receive between ST7070. These pins used during 4-bit operation serial interface must pull height floating. Clock latch serial data sent Extension driver Clock shift serial data Switch signal converting liquid crystal drive waveform Character pattern data corresponding each segment signal Common signals that used changed non-selection waveform. COM9 COM16 non-selection waveforms duty factor COM12 COM16 non-selection waveforms 1/11 duty factor. Segment signals Power supply drive (Max) 2.7V 5.5V, GND: When crystal oscillation performed, resistor must connected externally. When input external clock, must input OSC1.
XRESET
Extension driver Extension driver Extension driver Extension driver
COM1 COM16 SEG1 SEG80 OSC1, OSC2
Power supply Power supply Oscillation resistor clock
Note: must maintained clock options:
R=91K(Vcc=5V) R=75K(Vcc=3V)
OSC1
OSC2 Clock input
OSC1
OSC2
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ST7070 Function Description
System Interface This chip kinds interface type with 4-bit 8-bit bus. 4-bit 8-bit selected instruction register. During read write operation, 8-bit registers used. data register (DR), other instruction register(IR). data register(DR) used temporary data storage place being written into read from DDRAM/CGRAM, target selected address setting instruction. Each internal operation, reading from writing into RAM, done automatically. speak, after reads data, data next DDRAM/CGRAM address transferred into automatically. Also after writes data data transferred into DDRAM/CGRAM automatically. Instruction register(IR) used only store instruction code transferred from MPU. cannot read instruction data. select register, input 4-bit/8-bit mode.
Operation
Instruction Write operation (MPU writes Instruction code into Read Busy Flag(DB7) address counter (DB6 DB0) Data Write operation (MPU writes data into Data Read operation (MPU reads data from
Table Various kinds operations according bits. Busy Flag (BF) When "High", indicates that internal operation being processed. during this time next instruction cannot accepted. read, when High (Read Instruction Operation), through port. Before executing next instruction, sure that High.
Address Counter (AC) Address Counter(AC) stores DDRAM/CGRAM address, transferred from After writing into (reading from) DDRAM/CGRAM, automatically increased (decreased) When "Low" "High", read through ports.
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ST7070
Display Data (DDRAM) Display data (DDRAM) stores display data represented 9-bit character codes. extended capacity bits, characters. area display data (DDRAM) that used display used general data RAM. Figure relationships between DDRAM addresses positions liquid crystal display. DDRAM address (ADD address counter (AC) hexadecimal. 1-line display (Figure When there fewer than display characters, display begins head position. example, using only ST7070, characters displayed. Figure When display shift operation performed, DDRAM address shifts. Figure
High Order bits
Order bits
Example: DDRAM Address
Figure DDRAM Address
Display Position (Digit) DDRAM Address
Figure 1-Line Display
Display Position DDRAM Address
Shift Left
Shift Right
Figure 1-Line 8-Character Display Example
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ST7070
2-line display (Figure
Display Position
DDRAM Address (hexadecimal)
Figure 2-Line Display Case When number display characters less than lines, lines displayed from head. Note that first line address second line start address consecutive. example, when just ST7070 used, characters lines displayed. Figure When display shift operation performed, DDRAM address shifts. Figure
Display
Position DDRAM Address
Shift Left
Shift Right
Figure 2-Line 16-Character Display Example
Case 16-character 2-line display, Figure When display shift operation performed, DDRAM address shifts. Figure
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ST7070
Character Generator (CGROM) character generator generates character patterns from 9-bit character codes. generate character patterns. User-defined character patterns also available mask-programmed ROM. Character Generator (CGRAM) character generator RAM, user rewrite character patterns program. dots, eight character patterns written. Write into DDRAM character codes addresses shown left column Table show character patterns stored CGRAM. Table relationship between CGRAM addresses data display patterns. Areas that used display used general data RAM. Timing Generation Circuit timing generation circuit generates timing signals operation internal circuits such DDRAM, CGROM CGRAM. read timing display internal operation timing access generated separately avoid interfering with each other. Therefore, when writing data DDRAM, example, there will undesirable interference, such flickering, areas other than display area. Driver Circuit Driver circuit common segment signals driving. Data from CGRAM/CGROM transferred segment latch serially, then stored shift latch. When each common selected common register, segment data also output through segment driver from segment latch. case 1-line display mode, COM1 COM8 have duty, 2-line mode, COM1 COM16 have 1/16 duty ratio. Cursor Control Circuit generate cursor cursor control circuit. cursor blink appears digit display data address address counter.
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ST7070
Table Correspondence between Character Codes Character Patterns (Page (b8=0)
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ST7070
Table Correspondence between Character Codes Character Patterns (Page (b8=1)
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ST7070
Character Code (DDRAM Data)
CGRAM Address
Character Patterns (CGRAM Data)
Table Relationship between CGRAM Addresses, Character Codes (DDRAM) Character patterns (CGRAM Data) Notes: Character code bits correspond CGRAM address bits bits: types). CGRAM address bits designate character pattern line position. line cursor position display formed logical with cursor. Maintain line data, corresponding cursor display position, cursor display. line data bits will light line regardless cursor presence. Character pattern positions correspond CGRAM data bits (bit being left). shown Table CGRAM character patterns selected when character code bits However, since character code effect, display example above selected either character code 08H. CGRAM data corresponds display selection non-selection. "-": Indicates effect.
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ST7070 Instructions
There four categories instructions that: Designate ST7070 functions, such display format, data length, etc. internal addresses Perform data transfer with internal Others Instruction Table:
Instruction Code Instruction Clear Display Return Home Display ON/OFF Cursor Display Shift Function Read Busy flag address Write data Read data from Entry Mode CGRAM address DDRAM address
Sets cursor move direction specifies display shift. These operations performed during data write read. CGRAM address address counter DDRAM address address counter
Description
Description Time
(270KHz)
Write "20H" DDRAM. DDRAM address "00H" from DDRAM address "00H" from return cursor original position shifted. contents DDRAM changed. D=1:entire display C=1:cursor font table page selection cursor moving display shift control bit, direction, without changing DDRAM data. interface data bits number line
1.52
1.52
Whether during internal operation known reading contents address counter also read. Write data into internal (DDRAM/CGRAM) Read data from internal (DDRAM/CGRAM)
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ST7070
Used internal resister only provide bias mode Rb[1:0]=00 External Resister Rb[1:0]=01~11 Internal Resistor C1com1~8 com8~1 C2com9~16 com16~9 S1seg1~40 seg40~1 S2seg41~80 seg80~41
Bias resistor select
COMSEG direction select display data length
specify number data bytes(3SPI mode)
Note: sure ST7070 busy state before sending instruction from ST7070. instruction sent without checking busy flag, time between first instruction next instruction will take much longer than instruction time itself. Refer Instruction Table list each instruction execution time.
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ST7070 Instruction Description
EXT=0 Clear Display
Code
Clear display data writing "20H" (space code) DDRAM address, DDRAM address "00H" into (address counter). Return cursor original status, namely, bring cursor left edge first line display. Make entry mode increment (I/D "1"). Return Home
Code
Return Home cursor return home instruction. DDRAM address "00H" into address counter. Return cursor original site return display original status, shifted. Contents DDRAM does change.
Display ON/OFF
Code
Control display/cursor/blink ON/OFF register. Display ON/OFF control When "High", entire display turned When "Low", display turned off, display data remained DDRAM. Cursor ON/OFF control When "High", cursor turned When "Low", cursor disappeared current display, register remains data.
Alternating display Every frames Cursor
Font table selection When "Low", select page font table.(set DDRAM data bit-8=0) When "High", select page font table(set DDRAM data bit-8=1)
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ST7070
Cursor Display Shift
Code
Without writing reading display data, shift right/left cursor position display. This instruction used correct search display data. During 2-line mode display, cursor moves line after 40th digit line. Note that display shift performed simultaneously line. When displayed data shifted repeatedly, each line shifted individually. When display shift performed, contents address counter changed.
Function
Description
Shift cursor left Shift cursor right Shift display left. Cursor follows display shift
Value
AC=AC-1 AC=AC+1 AC=AC
Shift display right. Cursor follows display shift AC=AC
Code
Interface data length control When "High", means 8-bit mode with MPU. When "Low", means 4-bit mode with MPU. speak, signal select 8-bit 4-bit mode. When 4-bit mode, needs transfer 4-bit data times. Display line number control When "Low", means 1-line display mode. When "High", 2-line display mode set. Select basic extended instruction When EXT="L" commands `Entry Mode Set' `Set CGRAM address' `Set DDRAM address' performed when EXT="H" commands `Bias resistor select' `COMSEG direction select' `Set display data length' performed. Other command executed both cases. When EXT="L" disable extension instruction When EXT="H" enable extension instruction
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ST7070
Read Busy Flag Address
Code
When "High", indicates that internal operation being processed.So during this time next instruction cannot accepted. address Counter (AC) stores DDRAM/CGRAM addresses, transferred from After writing into (reading from) DDRAM/CGRAM, automatically increased (decreased) Write Data CGRAM DDRAM
Code
Write binary 8-bit data DDRAM/CGRAM. selection from DDRAM, CGRAM, previous address instruction DDRAM address set, CGRAM address set. instruction also determine direction RAM. DDRAM data bit-8 come from "P"(Display on/off instruction) register setting After write operation, address automatically increased/decreased according entry mode.
Read Data from CGRAM DDRAM
Code
Read binary 8-bit data from DDRAM/CGRAM. selection previous address instruction. address instruction performed before this instruction, data that read first invalid, because direction determined. read data several times without address instruction before read operation, correct data from second, first data would incorrect, because there time margin transfer data. case DDRAM read operation, cursor shift instruction plays same role DDRAM address instruction also transfer data output data register. After read operation address counter automatically increased/decreased according entry mode. After CGRAM read operation, display shift executed correctly. case write operation, after this increased/decreased like read operation. this time, indicates next address position, read only previous data read instruction.
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ST7070
EXT=0 Entry Mode
Code
moving direction cursor display. Increment decrement DDRAM address (cursor blink) When "High", cursor moves right DDRAM address increased When "Low", cursor moves left DDRAM address decreased CGRAM operates same DDRAM, when read from write CGRAM. Shift entire display When DDRAM read (CGRAM read/write) operation "Low", shift entire display performed. "High" DDRAM write operation, shift entire display performed according value (I/D shift left, shift right).
Description
Shift display left Shift display right
CGRAM Address
Code
CGRAM address This instruction makes CGRAM data available from MPU. DDRAM Address
Code
DDRAM address This instruction makes DDRAM data available from MPU. When 1-line display mode DDRAM address from "00H" "4FH". 2-line display mode DDRAM address line from "00H" "27H", DDRAM address line from "40H" "67H".
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ST7070
EXT=1 Bias resistor select
Code
internal bias resistor value.
Description
External bias resistor select. Build-in resistor select (R=2.2K). Build-in resistor select (R=6.8K).
Build-in resistor select (R=9.0K).
COMSEG direction select
Code
output ST7070 have bi-direction control register. OUTPUT output COM1 COM1 COM8 Common Address Common Address COM8 COM8 COM1
output OUTPUT output SEG1 SEG1 SEG40 Segment Address Segment Address SEG40 SEG40 SEG1 COM9 COM9 COM16 Common Address Common Address COM16 COM16 COM9
output SEG41 SEG41 SEG80 Segment Address Segment Address SEG80 SEG80 SEG41
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ST7070
display data length
Code
Data length
Only 3line-SPI interface will register number display data(Max=4F). write data DDRAM send Data Direction Command 3-pin Data latched rising edge SCLK DDRAM column address pointer will increased automatically.
SCLK initial EXT=1 No.of Data Data0 Command
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ST7070 Reset Function
Initializing Internal Reset Circuit internal reset circuit automatically initializes ST7070 when power turned hardware reset low. following instructions executed during initialization. busy flag (BF) kept busy state until initialization ends busy state lasts after rises Display clear Function set: 8-bit interface data 2-line display EXT=0;disable extension instruction. Display on/off control: Display Cursor Page font table(DDRAM data b8=0) Entry mode set: Increment shift Bias resistor select: Rb1=0;Rb2=0 select external bias resistor. COMSEG direction select: C1=0;C2=0;S1=0;S2=0 reverse. Note: electrical characteristics conditions listed under table Power Supply Conditions Using Internal Reset Circuit met, internal reset circuit will operate normally will fail initialize ST7070. such case, initialization must performed explain following figure.
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ST7070 Initializing Instruction
8-bit Interface (fosc=270KHz)
POWER
Wait time >40mS After >4.5V
Function
cannot checked before this instruction.
Wait time >37uS
Function
cannot checked before this instruction.
Wait time >37uS
Display ON/OFF control
Wait time >37uS
Display clear
Wait time >1.52mS
Entry mode
Initialization
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ST7070
Initial Program Code Example 8051 MPU(8 Interface): ;-INITIAL_START: CALL DELAY40mS CALL CALL CALL CALL CALL CALL CALL CALL A,#38H ;FUNCTION WRINS_NOCHK bit,N=1,5*7dot DELAY37uS A,#38H ;FUNCTION WRINS_NOCHK bit,N=1,5*7dot DELAY37uS A,#0FH WRINS_CHK DELAY37uS A,#01H WRINS_CHK DELAY1.52mS ;DISPLAY
;CLEAR DISPLAY
A,#06H ;ENTRY MODE CALL WRINS_CHK ;CURSOR MOVES RIGHT CALL DELAY37uS ;-MAIN_START: XXXX XXXX XXXX XXXX ;-WRINS_CHK: CALL CHK_BUSY WRINS_NOCHK: ;EX:Port ;EX:Port SETB ;EX:Port P1,A ;EX:Port 1=Data P1,#FFH ;For Check Busy Flag ;-CHK_BUSY: ;Check Busy Flag SETB SETB P1.7,$
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ST7070
4-bit Interface (fosc=270KHz)
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ST7070
Initial Program Code Example 8051 MPU(4 Interface):
;-INITIAL_START: CALL DELAY40mS CALL CALL CALL CALL A,#38H WRINS_ONCE DELAY2mS A,#38H WRINS_ONCE DELAY37uS ;FUNCTION bit,N=1,5*7dot
;FUNCTION bit,N=1,5*7dot
CALL CALL CALL CALL CALL CALL CALL CALL CALL CALL
A,#38H WRINS_ONCE DELAY37uS
;FUNCTION bit,N=1,5*7dot
A,#28H ;FUNCTION WRINS_NOCHK bit,N=1,5*7dot DELAY37uS A,#28H ;FUNCTION WRINS_NOCHK bit,N=1,5*7dot DELAY37uS A,#0FH WRINS_CHK DELAY37uS A,#01H WRINS_CHK DELAY1.52mS ;DISPLAY
;CLEAR DISPLAY
A,#06H ;ENTRY MODE CALL WRINS_CHK CALL DELAY37uS ;-MAIN_START: XXXX XXXX XXXX XXXX
;-WRINS_CHK: CALL CHK_BUSY WRINS_NOCHK: PUSH A,#F0H ;EX:Port ;EX:Port SETB ;EX:Port P1,A ;EX:Port1=Data SWAP WRINS_ONCE: A,#F0H SETB P1,A P1,#FFH ;For Check Flag ;-CHK_BUSY: ;Check Busy Flag PUSH P1,#FFH SETB SETB A,P1 P1,#FFH SETB SETB A.7,$1
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ST7070
Serial Interface (fosc=270KHz)
POWER
Wait time >40mS After >4.5V
Function
cannot checked before this instruction.
Wait time >37uS
Display ON/OFF control
Wait time >37uS
Display clear
Wait time >1.52mS
Entry mode
Initialization
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ST7070 Interfacing
ST7070 send data either 4-bit operations 8-bit operation serial operation, thus allowing interfacing with 8-bit serial MPU.
4-bit interface data, only four lines (DB4 DB7) used transfer. lines disabled. data transfer between ST7070 completed after 4-bit data been transferred twice. order data transfer, four high order bits (for 8-bit operation, DB7) transferred before four order bits (for 8-bit operation, DB3). busy flag must checked (one instruction) after 4-bit data been transferred twice. more 4-bit operations then transfer busy flag address counter data.
Example busy flag check timing sequence
Internal operation
Functioning
Busy flag check
Busy Busy flag check
Instruction write
Instruction write
Intel 8051 interface
COM1 COM16 P1.0 P1.3
P3.0 P3.1 P3.2 Intel 8051 Serial
SEG1 SEG80
ST7070
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ST7070
8-bit interface data, eight lines (DB0 DB7) used.
Example busy flag check timing sequence
Internal operation
Functioning
Data Instruction write
Busy Busy flag check
Busy Busy flag check
Busy Busy flag check
Data Instruction write
Intel 8051 interface
COM1 COM16 P1.0 P1.7
P3.0 P3.1 P3.2 Intel 8051 Serial
SEG1 SEG80
ST7070
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ST7070
serial interface data, lines (DB5 DB7) used. 4-Pin
Example timing sequence
Intel 8051 interface(Serial)
COM1 COM16 P1.5to P1.7
P3.0
SEG1 SEG80
Intel 8051 Serial
ST7070
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ST7070
serial interface data, lines (DB5 DB7) used. 3-Pin
Example timing sequence
command number data
display data length
data
Intel 8051 interface(Serial)
COM1 COM16 P1.5to P1.7
SEG1 SEG80 Intel 8051 Serial ST7070
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ST7070 Supply Voltage Drive
There different voltages that supply ST7070's obtain drive waveform. could register command (Ra1,Ra0) Internal External Bias Resister. relations bias, duty factor supply voltages shown below. External Bias Resistor could bias bias, Internal Bias Resistor only could bias.
External Resistor Supply Voltage Bias Resistor Select
Duty Factor 1/8,1/16 Bias Ra1=0,Ra0=0 VLCD 3/4VLCD 1/2VLCD 1/2VLCD 1/4VLCD Ra1=0,Ra0=0 VLCD 4/5VLCD 3/5VLCD 2/5VLCD 1/5VLCD
bias (1/8 duty cycle) bias (1/16 duty cycle) VLCD
VLCD
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ST7070
Internal Resistor Supply Voltage Bias Resistor Select Internal Resistor Ra1=0,Ra0=1 R=2.2K VLCD 4/5VLCD 3/5VLCD 2/5VLCD 1/5VLCD Duty Factor 1/16 Bias Ra1=1,Ra0=0 R=6.8K VLCD 4/5VLCD 3/5VLCD 2/5VLCD 1/5VLCD Ra1=1,Ra0=1 R=9.0K VLCD 4/5VLCD 3/5VLCD 2/5VLCD 1/5VLCD
Ra1=0,Ra0=1 bias R=2.2K (1/8,1/16 duty cycle) Ra1=1,Ra0=1 bias R=9.0K (1/8,1/16 duty cycle)
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Ra1=1,Ra0=0 VLCD bias R=6.8K (1/8,1/16 duty cycle) VLCD
VLCD
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ST7070 Timing Characteristics
Writing data from ST7070
VIH1 VIL1
tDSW
DB0-DB7
Valid data
Reading data from ST7070
VIH1 VIL1
tDDR Valid data
DB0-DB7
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ST7070
Interface Timing with External Driver
VOH2 tCWH tCWH VOL2
tCST tCWL
Internal Power Supply Reset
2.7V/4.5V
0.2V
0.2V
0.2V
trcc 0.1mStrcc80mS
tOFF tOFF1mS
Notes: tOFF compensates power oscillation period caused momentary power supply oscillations. Specified 4.5V operation,and 2.7V operation. 4.5V reached during operation,teh internal reset circuit will operate normally.
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ST7070 Characteristics
6800 interface 2.7V Symbol Characteristics
fOSC Frequency
Test Condition
Internal Clock Operation External Clock Operation
Min. Typ. Max.
Unit
External Frequency Duty Cycle
TR,TF
Rise/Fall Time
Write Mode (Writing data from ST7070) TR,TF TDSW Enable Cycle Time
Enable Pulse Width Enable Rise/Fall Time Address Setup Time Pins: RS,RW,E Address Hold Time Data Setup Time Data Hold Time Pins: RS,RW,E Pins: Pins:
Read Mode (Reading Data from ST7070 MPU) TR,TF TDDR Enable Cycle Time 1200
Enable Pulse Width Enable Rise/Fall Time Address Setup Time Pins: RS,RW,E Address Hold Time Data Setup Time Data Hold Time Pins: RS,RW,E Pins: Pins:
Interface Mode with Driver(ST7921) TCWH TCWL TCST Clock Pulse with High Pins: CL1, Clock Pulse with Pins: CL1, Clock Setup Time Data Setup Time Data Hold Time Delay Time Pins: CL1, Pin: Pin: Pin: 2000
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ST7070 Characteristics
6800 interface Symbol Characteristics
fOSC Frequency
Test Condition
Internal Clock Operation External Clock Operation
Min. Typ. Max.
Unit
External Frequency Duty Cycle
TR,TF
Rise/Fall Time
Write Mode (Writing data from ST7070) TR,TF TDSW Enable Cycle Time
Enable Pulse Width Enable Rise/Fall Time Address Setup Time Pins: RS,RW,E Address Hold Time Data Setup Time Data Hold Time Pins: RS,RW,E Pins: Pins:
Read Mode (Reading Data from ST7070 MPU) TR,TF TDDR Enable Cycle Time 1200
Enable Pulse Width Enable Rise/Fall Time Address Setup Time Pins: RS,RW,E Address Hold Time Data Setup Time Data Hold Time Pins: RS,RW,E Pins: Pins:
Interface Mode with Driver(ST7921) TCWH TCWL TCST Clock Pulse with High Pins: CL1, Clock Pulse with Pins: CL1, Clock Setup Time Data Setup Time Data Hold Time Delay Time Pins: CL1, Pin: Pin: Pin: 2000
V0.8
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ST7070 Characteristics
Serial interface 2.7V Symbol Characteristics
fOSC Frequency
Test Condition
Internal Clock Operation External Clock Operation
Min. Typ. Max.
Unit
External Frequency Duty Cycle
TR,TF
Rise/Fall Time
Write Mode (Writing data from ST7070) TR,TF TDSW Enable Cycle Time 2000
Enable Pulse Width Enable Rise/Fall Time Address Setup Time Pins: RS,E Address Hold Time Data Setup Time Data Hold Time Pins: RS,,E Pins: Pins:
Interface Mode with Driver(ST7921) TCWH TCWL TCST Clock Pulse with High Pins: CL1, Clock Pulse with Pins: CL1, Clock Setup Time Data Setup Time Data Hold Time Delay Time Pins: CL1, Pin: Pin: Pin: 2000
V0.8
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ST7070 Characteristics
Serial Interface Symbol Characteristics
fOSC Frequency
Test Condition
Internal Clock Operation External Clock Operation
Min. Typ. Max.
Unit
External Frequency Duty Cycle
TR,TF
Rise/Fall Time
Write Mode (Writing data from ST7070) TR,TF TDSW Enable Cycle Time
Enable Pulse Width Enable Rise/Fall Time Address Setup Time Pins: RS,E Address Hold Time Data Setup Time Data Hold Time Pins: RS,E Pins: Pins:
Interface Mode with Driver(ST7921) TCWH TCWL TCST Clock Pulse with High Pins: CL1, Clock Pulse with Pins: CL1, Clock Setup Time Data Setup Time Data Hold Time Delay Time Pins: CL1, Pin: Pin: Pin: 2000
V0.8
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ST7070 Absolute Maximum Ratings
Characteristics
Power Supply Voltage Driver Voltage Input Voltage Operating Temperature Storage Temperature
Symbol
VLCD TSTO
Value
-0.3 +5.5 Vss+7.0 Vss-0.3 -0.3 VCC+0.3
Characteristics
Symbol Characteristics Test Condition
VLCD Operating Voltage Voltage Power Supply Current Input High Voltage (Except OSC1) Input Voltage (Except OSC1) Input High Voltage (OSC1) Input Voltage (OSC1) Output High Voltage (DB0 DB7) Output Voltage (DB0 DB7) Output High Voltage (Except DB7) Output Voltage (Except DB7) Common Resistance Segment Resistance Input Leakage Current Pull Current fOSC 270KHz VCC=3.0V
Min. Typ. Max.
0.25
Unit
VIH1
0.7Vcc
VIL1
VIH2
0.7Vcc
VIL2
0.75
0.2Vcc
VOH1
-0.1mA
VOL1
0.1mA
0.2Vcc
VOH2
-0.04mA
0.8VCC
VOL2 RCOM RSEG ILEAK IPUP
0.04mA VLCD 0.05mA VLCD 0.05mA
0.2VCC
NOTE External bias resistor select doesn't include follower current.
V0.8
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ST7070 Characteristics
Symbol Characteristics
VLCD Operating Voltage Voltage Power Supply Current Input High Voltage (Except OSC1) Input Voltage (Except OSC1) Input High Voltage (OSC1) Input Voltage (OSC1) Output High Voltage (DB0 DB7) Output Voltage (DB0 DB7) Output High Voltage (Except DB7) Output Voltage (Except DB7) Common Resistance Segment Resistance Input Leakage Current Pull Current
Test Condition
fOSC 270KHz VCC=5.0V
Min. Typ. Max.
Unit
VIH1
VIL1
-0.3
VIH2
VCC-1
VIL2
VOH1
-0.1mA
VOL1
0.1mA
VOH2
-0.04mA
0.9VCC
VOL2 RCOM RSEG ILEAK IPUP
0.04mA VLCD 0.05mA VLCD 0.05mA
0.1VCC
NOTE External bias resistor select doesn't include follower current.
V0.8
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ST7070 Frame Frequency
Assume oscillation frequency 270KHZ, clock cycle time 3.7us, 1/16 duty; bias,1 frame 3.7us 11840us=11.8ms(84.7Hz)
clocks
COM1
COM2
COM16
SEGx
SEGx frame
V0.8
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ST7070
Assume oscillation frequency 270KHZ, clock cycle time 3.7us, duty; bias,1 frame 3.7us 11840us=11.8ms (84.7Hz)
clocks
COM1
COM2
COM8
SEGx
SEGx frame
V0.8
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ST7070 Configuration
PMOS PMOS PMOS
NMOS
NMOS NMOS
PSB=1==>E(Floating) PSB=0==>E(Pull
PSB=1==>R/W(With Pull PSB=0==>R/W(With Pull down)
PMOS
PMOS
NMOS PSB=1==>RS(With Pull PSB=0==>RS(Floating)
PMOS
Output PAD:CL1,CL2,M,D
NMOS
V0.8
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ST7070
PMOS
PMOS
Enable PMOS
NMOS
Data NMOS PAD:DB4-DB0 PSB=1==> Pull PSB=0==>Pull
PMOS
PMOS
Enable PMOS
NMOS
Data NMOS PAD:DB7-DB5 PSB=1==> Pull PSB=0==>Floating
V0.8
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ST7070 ST7070 Connection
dots, characters line (1/4 bias, duty)
ST7070
COM1 COM8 SEG1 SEG80 Panel: Characters line
dots, characters line (1/5 bias, 1/16 duty)
COM1 COM8 COM9 COM16 SEG1 SEG80 Panel: Characters line
V0.8
ST7070
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ST7070
dots, characters line (1/5 bias, 1/16 duty)
COM1 COM8 SEG1 SEG80 COM9 COM16
ST7070
Panel: Characters line
V0.8
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Matrix Panel
(Line) Characters dots/character
1-16 SHL1 SHL2
1-80
1~96
1~24
ST7921
SHL1 SHL2
ST7921
ST7070
RS/RW/E/DB0-DB7
Application Circuit
Vcc(+5V)
Resistor
Resistor
Resistor
Resistor
Resistor
ST7070
VR=10K~30Kohm
V0.8
Note:Resistor=2.2K~10K
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ST7070 INTERFACE
ST7070 Series connected 6800 Series MPUs. Moreover, using serial interface possible operate ST7070 series chips with fewer signal lines. display area enlarged using multiple ST7070 Series chips When this done chip select signal used select individual access. 6800 bits Series MPUs
VLCD
/RES
/RES
ST7070
When external bias resistor must connect
6800 bits Series MPUs
VLCD
/RES
/RES
ST7070
When external bias resistor must connect
V0.8
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ST7070
Using Serial Interface-For
D7(SI) D6(SCL) D7(SI) D6(SCL) D5(CS) /RES /RES
VLCD
D5(CS)
ST7070
When external bias resistor must connect
Using Serial Interface-For
D7(SI) D6(SCL) D7(SI) D6(SCL) D5(CS) /RES /RES
VLCD
D5(CS)
ST7070
When external bias resistor must connect
V0.8
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matrix possible power operation support: 5.5V Wide range driver power

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