PRELIMINARY Notice: This final specification. Some parameters subject

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ST2204
PRELIMINARY Notice: This final specification. Some parameters subject change.
Integrated Microcontroller with 512K Bytes
FEATURES
Totally static 8-bit ROM: 512K 8-bit RAM: 8-bit Stack: 128-level deep Operation voltage: 2.4V 3.6V Operation frequency: 3.0Mhz@2.4V(Min.) 4.0Mhz@2.7V(Min.) Voltage Detector (LVD) Voltage Reset (LVR) Memory interface ROM, RAM, Flash Memory configuration Three kinds bank program, data interrupts 12-bit bank register supports bytes programmable chip-selects with modes Maximum single device bytes General-Purpose (GPIO) ports multiplexed CMOS bidirectional programmable I/Os Hardware de-bounce option Port-A programmable pull-up input pins programmable pull-up/down open-drain/CMOS Port-C Programmable Watchdog Timer (WDT) Timer/Counter 8-bit timer, 16-bit event counter 8-bit Base timer with coexistent interrupt time settings Three clocking outputs Clock sources including Timer0/1, baud rate generator prioritized interrupts with dedicated exception vectors External interrupt (edge triggered) TIMER0 interrupt TIMER1 interrupt BASE timer interrupt PORTA interrupt (transition triggered) reload interrupt buffer interrupt interrupt (x2) UART interrupts (x2) Dual clock sources with warm-up timer frequency crystal oscillator (OSCX) 32768 oscillator High frequency crystal/resonator oscillator (Bonding option)
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Direct Memory Access (DMA) Block-to-Block transfer Block Single port Controller (LCDC) Software programmable screen size 320X240 Support 4-bit data Share system memory with display memory Large display area with small internal buffer possible free more internal temporary access Unique internal memory sharing with loss time Diverse functions including virtual screen, panning, scrolling, contrast control alternating signal generator Gray level support: Hardware levels/Software levels Universal Asynchronous Receiver/Transmitter (UART) Full-duplex operation Baud rate generator with digital Standard baud rates 115.2 kbps Direct glueless support IrDA physical layer protocol sets I/Os (TX,RX) independent devices Serial Peripheral Interface (SPI) Master slave modes serial signals including enable data-ready stage buffer transmitter receiver continuous data exchange Programmable data length from 7-bit 16-bit Programmable Sound Generator (PSG) channels with three playing modes Tone/noise generator 16-level volume control 8-bit speech/voice dedicated outputs directly driving large current Three power down modes WAI0 mode WAI1 mode mode
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ST2204
GENERAL DESCRIPTION
ST2204 8-bit integrated microcontroller designed with CMOS silicon gate technology. true static core, power down modes dual oscillators design makes ST2204 suitable power saving long battery life designs. ST2204 integrates various logic support functions on-chip which needed system designers. This also important lower system complexity, small board size and, course, shorter time market less cost. ST2204 features capacity memory access maximum bytes which needed products with large data bases, also function fast memory transfer. chip selects equipped direct connection external ROM, SRAM, Flash memory other devices. Maximum single device bytes possible. ST2204 I/Os grouped into ports, Port-A Port-E Port-L. Each programmed input output. There options: pull-up/down inputs Port-C only pull-up inputs other ports. case output, there open-drain/CMOS options outputs PortC only CMOS other ports. Port-A/B designed keyboard scan with de-bounce transition triggered interrupt Port-A, while Port-C/D/E/L shared with other system functions. properties pins still programmable when they assigned another function. This enlarges flexibility usage function signals. ability driving large panels, 320x240, hardware/software gray-level support rich display information diversity contents well. This done with need external display because internal
VCC/GND TEST1/2 ICE2/3 /ICE1 RESET OSCI OSCXI OSCXO A[22:0] D[7:0] PVCC/PGND PSGO/PSGOB MMD/CS0 1/PD4 /A23 /PD5 TCO0/PE0 TCO1/PE1 BCO/PE2 PE7~2 Port-D
memory sharing design. variable buffer design also make large panel size with little internal possible. User free major internal computing temporary access while keeping display content. ST2204 equips serial communication ports UART perform different communications, ex.: RS-232 IrDA, with system components other products such Notebook, popular PDA. Three clocking outputs produce synthesized signals high frequency carrier remote control. This helps products become more useful daily life. built-in channel PSG/one channel production tone, melody, voice, speech. dedicated pins with large driving capacity drive buzzer/speaker directly minimum cost. ST2204 Voltage Detector (LVD) power management. status internal external power detected reported management software. Power bouncing during power major problem when designing reliable system. ST2204 equips Voltage Reset function keep whole system reset status when power low. After power backs normal, system recover original states keeps working correctly. With these integrated functions inside, ST2204 single chip microcontroller right solution PDA, translator, databank other consumer products.
Voltage Detector Voltage Reset Power Reset Clock Generator Clock Generator OSCX 8-bit External Memory 512K bytes SRAM bytes De-bounce Logic Transition Detector
Port-A
PA7~0
Port-B 8-bit Static Base Timer 8-bit Port-C
PB7~0 INTX/PC0 SCK/PC1 MISO/PC2 MOSI/PC3 /PC4 DATA_READY /PC5 TXD0/PC6 RXD0/PC7 TXD1/PD6 RXD1/PD7 LD[3:0]/PL3~0 CP/PL4 AC/PL5 LOAD1/PL6 FLM/PL7 POFF BLANK LOAD2
Bank Control Logic
Interrupt Controller
Baud Rate Generator
Port-C
Port-C UART with IrDA Mode Port-D Chip Select Logic Clocking Output Timer 8-bit Port-L Controller
Port-E Port-E
FIGURE ST2204 Block Diagram
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ST2204
SIGNAL DESCRIPTIONS
TABLE Signal Function Groups Function Group Power Ground Designation PVCC PGND Description VCC: Power supply system PVCC: Power supply PSGO PSGOB GND: System power ground PGND: Power ground PSGO PSGOB RESET Active system reset signal input /ICE1: voltage reset signal output, connect this RESET make Voltage Reset function work. System control 50,80 1,81 RESET
/ICE1,
ICE1: ICE1 function when mode TEST1/2, ICE2/3: Leave them open when normal operation MMD/CS0: Memory modes selection Normal mode: Enable internal ROM. MMD/ connects GND. Emulation mode: Disable internal ROM. MMD/ connects chip-select external ROM. resistor should added between this pin. After reset cycles, MMD/ changes output, outputs signal XMD: High frequency oscillator (OSC) mode selection input Low: Crystal mode. crystal resonator should connected between OSCI High: Resistor oscillator mode. resistor should connected between OSCI OSCXI, OSCXO: Connect 32768Hz crystal between these pins when using frequency oscillator
ICE2/3, TEST1/2, MMD/
XMD, Clock 19~22 XIO,OSCI OSCXO,OSCXI,
2~4, External memory signals 85~93, 95~105 75~79, 82~84 PSG/PWM Keyboard scan signal (return line) GPIO Chip selects UART 24~25, 27,29~33 34~41 64~69 43~47
A[22:0] D[7:0] PSGO, PSGOB PA7~0 PB7~0
/PD4~0, /A23/PD5
External memory control signals External memory address
External memory data outputs. Connect buzzer speaker port port port chip-select outputs UART signals I/Os signals I/Os
RXD0/PC7,TXD0/PC6, RXD1/PD7,TXD1/PD6
DATA_READY /PC5 /PC4 MOSI/PC3
MISO/PC2 SCK/PC1
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10/20/03 TABLE Signal Function Groups (continued) Function Group External clock/signal interrupt Clocking output GPIO control signals 56~58 59~63 5~14, Designation INTX/PC0 BCO/PE2 TCO1/PE1 TCO0/PE0 PE7~3 FLM/PL7, LOAD1/PL6, AC/PL5 CP/PL4, LD[3:0]/PL3~0, POFF BLANK ,LOAD2 Description External interrupt inputs
ST2204
Clocking outputs port control signals
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ST2204
DIAGRAM
LVR\ICE1 MMD\CS0 ICE2
ST2204
PGND PSGO
LOAD2 TEST2
PSGOB PVCC
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ST2204
DEVICE INFORMATION
size: 90um 90um Substrate: Chip size: 3120um 3490um Symbol ICE2 PGND PSGO PSGOB PVCC Symbol
Symbol TEST1 BLANK POFF RESET OSCI OSCXO OSCXI
\ICE1
1445 1320 1195 1085 -125 -235 -345 -455 -565 -675 -785 -895 -1005 -1130 -1255 -1485 -1485 -1485 -1485 -1485 -1485 -1485 -1485 -1485 -1485
1669.3 1669.3 1669.3 1669.3 1669.3 1669.3 1669.3 1669.3 1669.3 1669.3 1669.3 1669.3 1669.3 1669.3 1669.3 1669.3 1669.3 1669.3 1669.3 1669.3 1669.3 1669.3 1669.3 1669.3 1669.3 1674.8 1549.8 1424.8 1289.8 1179.8 1069.8 959.8 849.8 739.8 629.8
-1485 -1485 -1485 -1485 -1485 -1485 -1485 -1485 -1485 -1485 -1485 -1485 -1485 -1485 -1485 -1485 -1485 -1485 -1485 -1485 -1243.4 -1118.4 -993.4 -883.4 -773.4 -663.4 -553.4 -443.4 -333.4 -223.4 -113.4 -3.4 106.6 216.6 326.6
519.8 409.8 299.8 189.8 79.8 -30.3 -140.3 -250.3 -360.3 -470.3 -580.3 -690.3 -800.3 -910.3 -1020.3 -1130.3 -1294.3 -1419.3 -1544.3 -1669.3 -1669.3 -1669.3 -1669.3 -1669.3 -1669.3 -1669.3 -1669.3 -1669.3 -1669.3 -1669.3 -1669.3 -1669.3 -1669.3 -1669.3 -1669.3
ICE3 TEST2 LOAD2
436.6 546.6 656.6 766.6 876.6 986.6 1096.6 1206.6 1331.6 1456.6 1485 1485 1485 1485 1485 1485 1485 1485 1485 1485 1485 1485 1485 1485 1485 1485 1485 1485 1485 1485 1485 1485 1485 1485 1485 1485
-1669.3 -1669.3 -1669.3 -1669.3 -1669.3 -1669.3 -1669.3 -1669.3 -1669.3 -1669.3 -1453.3 -1328.3 -1203.3 -1093.3 -983.3 -873.3 -763.3 -653.3 -543.3 -433.3 -323.3 -213.3 -103.3 116.8 226.8 336.8 446.8 556.8 666.8 776.8 886.8 996.8 1106.8 1231.8 1356.8
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ST2204
INTERRUPT CONTROLLER
ST2204 supports hardware internal/external interrupts well software interrupt Brk. There exception vectors these interrupts another reset. interrupts controlled interrupt disable flag (bit2 status register initiate equals "0". Hardware interrupts further controlled interrupt enable register IENA. Setting bits IENA enables respective interrupts. interrupt controller owns priority arbitrator. When more than interrupts happen same time, with lower priority number will executed first. Refer TABLE priorities interrupts. Once interrupt event enabled then happens, wakes either wait mode), associated interrupt request register (IREQ) will set. flag cleared, related vector will fetched then interrupt service routine (ISR) will executed. Interrupt request flag cleared methods. write IREQ, other initiate related interrupt service routine. Hardware will automatically clear Interrupt request flag. interrupt vectors listed TABLE 6-1.
TABLE Interrupt Vectors Name RESET INTX Signal Source Internal External External Internal Internal/External Internal/External External Internal Internal External External External External Vector Address $7FFF,$7FFE $7FFD,$7FFC $7FFB,$7FFA $7FF9,$7FF8 $7FF7,$7FF6 $7FF5,$7FF4 $7FF3,$7FF2 $7FF1,$7FF0 $7FEF,$7FEE $7FED,$7FEC $7FEB,$7FEA $7FE9,$7FE8 $7FE7,$7FE6 $7FE5,$7FE4 $7FE3,$7FE2 Priority Reset vector Reserved edge interrupt Reload data interrupt Timer0 interrupt Timer1 interrupt Port-A transition interrupt Base Timer interrupt Frame interrupt Reserved transmit buffer empty interrupt receive buffer ready interrupt UART receiver interrupt UART transmitter interrupt Description Software operation vector
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ST2204
GPIO
ST2204 consists general-purpose (GPIO) which divided into ports: Port-A/B/C/D/E Port-L. Each single programmed input output. This controlled port direction control registers PCx. Setting makes respective output, clearing this input. There options: pull-up/down inputs Port-C only pull-up inputs other ports. case output, there open-drain/CMOS options outputs PortC only CMOS other ports. Refer TABLE 7-1. TABLE Types GPIO Ports Types Port-A/B/D/E/L Port-C Pull-up/Pure Pull-up/Pull-down/Pure Input CMOS Open-drain/CMOS Output
Mode
case input function, port data registers reflect values associated pins. Besides read instruction data signals input, writing register selects types pins, pull-up pull-down. Setting bits port data register select pull-up type. Clearing bits only select pull-down type pins Port-C. There pull-down resistors Port-A/B/D/E Port-L, thereby pull-down resistors will enabled clearing bits Pull-up resistors Port-A/B/D/E/L also controlled PULL (bit7 port miscellaneous register PMCR), disable, while enable them. pull-up/pull-down resistors Port-C further controlled bits port type select registers PSC. They work same with PULL PMCR only single pin, disable, while enable.
PULL-UP PORT CONTROL REGISTER PORT DATA REGISTER DATA INPUT RD_INPUT PULL-UP PMOS
Input Mode
case output function, Write port data registers makes pins output desired value. This value also read back read instruction. Besides Port-C, output pins CMOS type. Port-C have options output types: open-drain CMOS, controlled port type select registers PSC. Clearing bits registers that disable PMOS output stage left only NMOS, while setting bits CMOS. Port-A designed keyboard scan with de-bounce transition triggered interrupt, while Port-C/D/E multiplexed with other system functions, controlled PFC, PFD, PMCR[2:0]. Port-L shared with specific signals LCDC. Turning LCDC setting LPWR (LCTR[7]) reserves Port-L GPIO. Selecting respective pins GPIO signals system function will affect original settings directions types. This entends flexibility usage function signals. Note: properties pins still programmable must ascertained before they assigned system functions, especially direction pins.
Output Mode
FIGURE Configuration Port-A/B/D/E/L
FIGURE Configuration Port-C
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ST2204
CHIP-SELECT LOGIC (CSL)
ST2204 builds chip-select signal embedded 512K bytes mask chip-select signals multiplexed with PD5~0 Port-D which used select external devices address data bus. There options first 512K bytes memory which controlled pin. ground select normal mode enable internal first 512K bytes memory. Connect chip-select external device select emulation mode disable internal ROM. After reset cycles, changes output outputs chip-select signal Refer FIGURE connections different modes. bits CSM[1:0] port miscellaneous register (PMCR) select four modes which define memory size each external chip-select. CSM0 equals "1", chip-select signal changes address signal make single device bytes possible. address range higher number follows range previous lower number. Note: Write port direction control register PCD, then port function-select register activate designated chip-select signal.
Normal Mode
Emulation Mode FIGURE Connections MMD/
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ST2204
TIMER/EVENT COUNTER
ST2204 three timers, Base timer, Timer Timer prescalers PRES PREW. There clock sources, SYSCK INTX, PRES clock source, CLK32, PREW. Refer FIGURE
FIGURE Structure Prescalers
PRES
prescaler PRES 8-bits counter shown FIGURE 9-1. Which provides four clock sources base timer timer1, controlled register PRS. instruction read toward will bring content PRES Instruction write toward will reset, enable select clock sources PRES. When user external interrupt input PRES event counter, combining PRES Timer1 will 16bit-event counter.
PREW
prescaler PREW 8-bits counter shown FIGURE 9-1. PREW provides four clocks source base timer timer1. stops counting only OSCX stops hardware reset occurs.
Base Timer
base timer supports interrupt, which occurs five different rates. Applications base base timer interrupt chose appropriate interrupt rate from five time bases their specific needs. These real-time applications include digitizer sampling, keyboard debouncing, communication polling. Block diagram base timer shown FIGURE 9-2.
Control Register CLK32 2048 Counter Counter Counter Counter Counter
Base Timer Interrupt
FIGURE Base Timer Block Diagram
9.1.1 Base Timer Operations
base timer consists five sub-counters produce five predefined rates. connections between overflow signals these sub-counters base timer interrupt controlled respective fields base timer enable register (BTEN). enabled overflow signals ORed generate base timer interrupt request. Related bits base timer status register (BTSR) will show which rates interrupts should
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serviced. Write BTCLR (bit BTSR) clear this register. Note: Make sure BTSR cleared after interrupt serviced, that request next time
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ST2204
10.1 Function Description
built-in dual channel Programmable Sound Generator (PSG) controlled register file directly. flexibility makes useful applications such music synthesis, sound effects generation, audible alarms tone signaling. order generate sound effects while allowing processor perform other tasks, continue produce sound after
initial commands have been given CPU. structure shown FIGURE 10-2 clock source shown FIGURE 10-1. ST2204 three playing type. channel0(C0) channel1(C1) square type tone sound playing. Second square tone sound noise sound. third sound playing type playing.
SYSCK/ SYSCK/ SYSCK/ SYSC SYSC
FIGURE 10-1 Clock Source Control
Preload Data Before First Count DACE C1TEN DACE PSGC[2] C1NEN PSGC[3] Channel Tone Enable Output LOAD Channel Noise Enable Output C1Tone MUX2 OUTPUT C1out
C1Noise
MIXER Output C1out Vol_CH1 VOL[1~0] From Generator DACE
MUX2 OUTPUT Port MUX2 OUTPUT PSG1 PSG0
FIGURE 10-2 Block Diagram
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built-in analog sampling data voice signals. There interrupt signal from whenever data update needed same signal will decide sampling rate voice. mode, frequency oscillator can't less
11.1 Sample Rate Control
PSG1L PSG1H control sample rate. PSG1[11~6] controls repeat times (usually set=111100 four times reload) PSG1[5~0] usually `1'. input clock source controlled PCK[2~0]. block diagram shown following:
DAC[7~0] DMD[0] DMD[1] Sample Rate Generator PSG1[11~0] PSGCK DACE PSG1[11~0] CK_IN Enable Output
Generator DAC[7~0]
DMD[0] DMD[1]
Reload_DAC
Enable Reload_DAC
FIGURE 11-1 Diagram
SYSC SYSC SYSC SYSC SYSC
FIGURE 11-2 Clock Source Control
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ST2204
CONTROLLER (LCDC)
controller (LCDC) provides display data specific signals external drivers drive panels. LCDC fetches display data directly from internal system memory through unique memory bus. special designed internal shares almost none resources make both fast display data process high speed operation possible. Both black-and-white 4-gray-level supported selected GL[0] control register LCTR. ST2204 builds bytes SRAM, maximum panel size 320x240 240x160 4-gray-level mode. LCDC also supports software gray-level levels displaying pictures photos. ST2204 supports 4-bit data compatibility most popular drivers. output signals shared with Port-L., controlled power control LPWR (LCTL[7]) data selection LMOD (LCK[4]). case 1-bit mode, PL3~1 Port-L still used general purpose. Note: signals will disconnected Port-L will output values assigned after clearing LPWR. Various functions also supported rich display information, including virtual screen, panning, scrolling, contrast control alternating signal generator. Control registers used LCDC listed below.
12.1 Specific Signals
following signals generated LCDC connect ST2204 panel. them dedicated output pins, while rest eight pins multiplexed with Port-L. (LCK[4]). case 1-bit mode, LMOD should cleared LCDC uses only transfer data. LD3~1 still programmed normal inputs outputs. output pixel data inverted through programming. Setting (LCTR) will reverse output data data bus.
(PL7)
frame marker signal indicates start display frame. becomes active after last line pulse frame remains active until next line pulse, which point de-asserts remains inactive until next frame.
POFF (Power control)
power control signal used turn on/off external DC-DC converter, which generates high voltage driving liquid crystal. POFF outputs when clearing LPWR (LCTR), outputs setting this bit, which also default value.
LOAD1 (PL6)
line pulse signal used latch line shifted data segment drivers' outputs also used shift line enable signal common driver. driver outputs then control liquid crystal form desired frame panel.
BLANK (Contrast control)
blank signal used control contrast display setting contrast level LPWM[5:0] with "00000" (default) represents maximum level "11111" minimum. BLANK signal achieves this function outputting signal according settings contrast. Besides contrast control, BLANK signal plays another role turning display off. This controlled register BLNK (LCTR). Setting BLNK will make BLANK signal output blank display regardless contrast control. Setting BLNK will enable contrast control course BLANK signal. LPWMTR[5:0] zeros, BLANK signal will stay high level with modulation.
(PL5)
alternate signal toggles polarity liquid crystal panel. This signal programmed toggle period lines frame. shift clock pulse signal clock output which output data panel synchronized. Data segment drivers shifted into internal line buffer each falling edge
(PL4)
LD3~0 (PL3~0)
data lines transfer pixel data panel that displayed. kinds data busses, 1and 4-bit, supported controlled LMOD
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ST2204
pixel panel. TABLE 12-2 shows mapping display data LCD. When clear control GL[0] (LCTR[2]) enable mode, every display buffer represents pixel screen. case setting GL[0] enable 4-gray-level mode, there will bits present each pixel screen. When 4-gray-level mode, there kinds light gray,1/2 1/3, selected GL[1] (LCTR[3]). Refer TABLE 12-2 relationship data bits displayed pixel.
12.2 Mapping Display Data
screen width height panel programmable through software. Although maximum screen size 1024x512, actual supported resolution limited display buffer size, which also internal size, bytes. Instead screen size specified control registers, larger frame also displayed Virtual Page Width setting. FIGURE 12-1 illustrates relationship between portion large graphic displayed screen actual area that seen. Each bits display memory correspond
FIGURE 12-1 Screen Format
Bit7 Pixel [0,0]
Bit6 Pixel [1,0]
TABLE 12-1 Mapping Memory Data Screen 1-bit-per-pixel mode Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit7 Pixel Pixel Pixel Pixel Pixel Pixel Pixel [2,0] [3,0] [4,0] [5,0] [6,0] [7,0] 8,0] 2-bit-per-pixel mode Bit3 Bit2 Bit1 Bit0 Pixel Pixel [2,0] [3,0]
Bit6 Pixel [9,0]
Bit7 Pixel [0,0]
Bit6
Bit5 Pixel [1,0]
Bit4
Bit7 Pixel [4,0]
Bit6
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10/20/03 TABLE 12-2 Mapping Memory Data Screen Pixel Display Mode Data Pixel White Dark White 1/2(1/3) gray 4-Gray-Level gray Dark normal white panel
ST2204
12.3 Interface Timing
controller continuously pumps pixel data into panel data bus. timed LOAD, signals. kinds data width, 1and 4-bit, supported most monochrome panels. Refer FIGURE 12-2 both 4-bit interface timing.
FIGURE 12-2 Interface Timing 1-/4-Bit Data
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ST2204
SERIAL PERIPHERAL INTERFACE
ST2204 contains serial peripheral interface (SPI) module interface with external devices, such Flash memory, analog-to-digital converter, other peripherals, including another ST2204. consists master- slave-configurable interface that connections both master slave devices allowable. Five signals multiplexed with Port-C used SPI. With equipped DATA_READY (slave-select) control signals transmit/receive buffers, faster data exchange with fewer software interrupts easy made. Data length widely supported from 7-bit 16-bit satisfy various applications. clock generator provided synchronous communication clock SCK, which sourced from OSCK. FIGURE 13-1 illustrates block diagram SPI.
DATA_READY Interface Interface Control 16-bit Receive Buffer 16-bit Transmit Buffer SPICK
Clock Generator
OSCK
MISO 16-bit Shift Register
(MSB First)
MOSI
FIGURE 13-1 Block Diagram
13.1 Operations
contains 16-bit shift register 16-bit buffers transmission receiving respectively. Data with variable length from 7-bit 16-bit exchanged with external devices through data lines. Data length controlled count register BC[3:0] (bit3~0 clock control register SCKR). current exchange will over while exchanged number reaches count setting. synchronous communication clock used synchronize devices transfer data shift register. Data clocked with programmable data rate, which assigned SCK[2:0] (bit6~4 clock control register SCKR). block controlled SPIEN (SCTR[7]). Setting SPIEN will enable function clock divider. Then internal states will reset initial values. After that, write data SDATAL will initiate exchange. While exchanging, busy flag will reported (bit status register SSR). slave select signal (multiplexed with PC4) used identify individual selection slave device. Slave devices that selected interfere with activities. master device, used indicate multiple-master contention which reported mode fault MDERR (bit3 status register SSR).
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UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER
ST2204 integrates universal asynchronous receiver/transmitter (UART), which used communicate with external serial devices. Serial data transmitted received standard rates using internal baud rate generator (BGR), which controlled control register BCTR. FIGURE 14-1 shows block diagram UART.
Interface
TXD1 RXD1
Transmitter Receiver Baud Rate Generator
Serial Interface
IrDA Interface
TXD0 RXD0
FIGURE 14-1 UART Block Diagram
14.2 UART Operations
UART modes operation, IrDA, which represent data different ways serial communication protocols, RS-232 IrDA.
14.2.1 mode
non-return zero (NRZ) mode primarily associated with RS-232. Each character transmitted frame delimited start beginning stop end. Data bits transmitted least significant (LSB) first, each occupies period time equal full bit. parity used, parity transmitted after most significant bit. Data settings including data length, stop number parity controlled fields UCTR. FIGURE 14-2 illustrates character mode.
14.2.2 IrDA mode
IrDA mode uses character frames mode does, but, instead driving ones zeros full bit-time period, zeros transmitted three-sixteenth less) bit-time pulses (which selected PW[1:0] (IRCTR[2:1]), ones remain low. polarity transmitted pulses expected receive pulses inverted that direct connection made external IrDA transceiver modules that active pulses. This controlled RXINV TXINV (IRCTR[7:6]). IrDA mode enabled control IREN (IRCTR[0]). FIGURE 14-3 illustrates character IrDA mode.
Parity
Start
Parity
Start
Stop
FIGURE 14-2 ASCII with Parity
FIGURE 14-3 IrDA ASCII with Parity
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ST2204
DIRECT MEMORY ACCESS (DMA)
speed memory access this system, sequential direct memory access (DMA) controller designed-in. perform memory transfer function more efficient than does. While working, data register (DRR) will disable memory bank register (DMR) access ROM. After complete, bank control still return DRR. With help make across bank boundary smoothly, only valid DMS. automatic increases when across bank boundary.
LCD_CTL
SRAM
FIGURE 15-1 System Block Diagram
CLOCKING OUTPUTS
Three clocking outputs PE0, supported ST2204. These signals very useful outputs high frequency, such base signal carrier remote control. Timer0, Timer1 overflow signals clock sources PE1, while BGRCK PE2.
Clocking Outputs:
Overflow states Timers will connected toggle data PE[0:1] when setting function selection bits TCO0/TCO1 (PMCR[0:1]). Meanwhile PE0/PE1 output clocked data half frequency Timers. After resetting TCO0/TCO1, toggle operation ceases. Then PE0/PE1 return original logic level PE[0:1].
Clocking Output:
BGRCK will output through when setting function selection (PMCR[2]). cleared, returns original logic level PE[2].
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POWER DOWN MODES
ST2204 three power down modes: WAI-0, WAI-1 STP. instruction will enable either WAI-0 WAI-1, which controlled WAIT (SYS[2]). instruction will enable mode same manner. WAI-0 WAI-1 modes waked interrupt. However, mode only waked hardware reset.
17.1 WAI-0 Mode:
WAIT cleared, instruction makes enter WAI-0 mode. mean time, oscillator, interrupts, timer/counter, still working. other hand related instruction execution stop. registers, RAM, pins will retain same states those before entered power down mode. WAI-0 mode #$00 <SYS mode waked reset interrupt request even user sets interrupt disable flag that case will waked entering interrupt service routine. interrupt disable flag cleared (I='0'), corresponding interrupt vector will fetched service routine will executed. sample program shown below:
17.2 WAI-1 Mode:
WAIT set, instruction makes enter WAI-1 mode. this mode, stops, PSG, timer/counter keep running their clock sources from OSCX. #$04 <SYS mode wake-up procedure same WAI-0. difference that warm-up cycles occur when waking from WAI-1. Sample program shown following:
17.3 Mode:
instruction will force enter stop mode. this mode, stops, PSG, timer/counter won't stop clock source from OSCX. power-down mode, only waked hardware reset, warm-up cycles occur same time.
FIGURE 17-1 Status Under Power Down Modes SYSCK source OSC: Mode WAI-0 WAI-1 Timer0,1 Stop Stop SYSCK Stop Stop Stop Stop Stop Stop OSCX Retain Retain Retain Base Timer REG. Wake-up condition Reset, interrupt Reset, interrupt Reset
SYSCK source OSCX: Mode WAI-0 WAI-1 Timer0,1 Stop Stop SYSCK Stop Stop OSCX Retain Retain Retain Base Timer REG.
Wrong Frame
Wake-up condition Reset, interrupt Reset, interrupt Reset
Stop Stop
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ST2204
WATCHDOG TIMER
watchdog timer (WDT) added check that program running sequencing properly. When application software running, responsible keeping 8-second watchdog timer from timing out. watchdog timer times out, indication that software longer being executed intended sequence. this time watchdog timer generates reset signal system.
18.1 Operations
enabled setting enable flag WDTEN (MISC[3]). time settings, seconds, selectable with selection WDTPS (MISC[2]).WDT clocked clock from base timer therefore 0.5-second resolution. recommended that watchdog timer periodically cleared software once enabled. Otherwise, software reset will generated when timer reached binary value Note:The reset writing value MISC register. After system reset, WDTEN cleared. Then returns idle.
VOLTAGE DETECTOR
ST2204 built-in voltage detector power management. voltage signals selected control LVDS (MISC[4]). First power applied ST2204 typical detection level 2.6V. Second signal applied input VIN, typical detection level 1.25V. When LVDEN (SYS[0]) set, enabled detection result will outputted same after Using read instruction twice this result: first read will enable initial stableness control. Second read equal represents 'low voltage'. Once enabled, keeps consuming power. important write LVDEN disable detector after detection completed. FIGURE 19-1 shows application circuit detecting battery voltage 2.5V. Note that current external resistors setting open. Also capacitor minimize noise narrow voltage detection range.
FIGURE 19-1 Application detection voltage FIGURE 19-1 Detection Voltage 1.25 Equation22-1
Rv1=Rv2=100k Then detection voltage 2.5V
VOLTAGE RESET (LVR)
Power bouncing during power major problem when designing reliable system. ST2204 equips Voltage Reset function keep whole system reset status when power stable. Once voltage status detected, active pulse will output from /ICE1. Connect this output RESET perform this protection. After power backs normal, /ICE1 will output high system recover original states keeps working correctly. connection between /ICE1 RESET fixed internally code option. This code option selects only internal connection without turning on/off circuit output /ICE1. circuit always works consumes very current.
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ST2204
APPLICATION CIRCUITS
Note: Connect capacitor 100pF OSCI stabilize oscillation frequency. This capacitor must close OSCI case Voltage Reset code option selected, Voltage Reset function still work connecting /ICE1 RESET Remove this connection when this code option selected. OSCX still work remove increase 47pF.
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ST2204
REVISIONS
REVISION DESCRIPTION
Modify name TABLE 3-1. configuration diagram Port-C FIGURE 7-2. Modify clock selection FIGURE 10-1. Modify clock source selection FIGURE 11-2. Modify name section Modify application circuit, notes page diagram device information Change ICE1 name /ICE1 more description about section section "LOW VOLTAGE RESET" Modify Page Change internal size from bytes. First release 2003/03/13 2003/01/13 2002/10/11
PAGE
DATE
2003/10/13
2003/06/17
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PRELIMINARY Notice: This final specification. Some parameters subject

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