197A807 Other Read/Write Cycle Times (-55 125°C) Number 5962R9689

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197A807 Other Read/Write Cycle Times (-55 125°C) Number 5962R9689

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Radiation Hardened Programmable Read Only Memory (PROM)
197A807
Other Read/Write Cycle Times (-55 125°C) Number 5962R96891 Asynchronous Operation CMOS Compatible Single ±10% Power Supply Operating Power Packaging Options 28-Lead Flat Pack (0.500" 0.720")
Radiation Fabricated with Bulk CMOS Process Total Dose Hardness through 2x105 rad(Si) Neutron Hardness through 1x1012 N/cm2 Immune Latches) Latchup Free
General Description radiation hardened PROM pinout, function package compatible with commercial 28C256 series EEPROMs, such SEEQ 28C256 Atmel AT28C256. PROM fabricated with SYSTEMS' QML-qualified radiation hardened technology, designed systems operating radiation environments. radiation hardened Oxide-Nitride-Oxide (ONO) anti-fuse technology features micron, transistors data path, micron, high voltage PFETs programming path circuitry. PROM operates over full military temperature range, requires single ±10% power supply, available with either CMOS compatible I/O. Power consumption typically mW/MHz operation less than mW/MHz power disabled mode. PROM operation fully asynchronous, with associated typical access time nanoseconds. Synchronous operation also possible using clock. SYSTEMS' enhanced bulk CMOS technology radiation hardened through advanced proprietary design, layout, process hardening techniques.
SYSTEMS 9300 Wellington Road Manassas, Virginia 20110-4122
Functional Diagram
Decoders
Memory Array
VPP*
Column Decoders Section Select
Column Muxing Sense Amps
Control Logic
Buffers
*PROM Programming Voltage
Signal Definitions
0-14
Address input pins that select particular eight-bit word within memory array. Bi-directional data pins that serve data outputs during read operation data inputs during write operation. Negative output enable, when high level, holds data output drivers high impedance state. programming mode, with high low, data driver state "Data-In" enable programming.
Chip enable, when level with level, allows normal operation. When high level, forces data output drivers high impedance state.
Truth Table
Mode Read Tristate Standby Standby Program Inputs(1),(2) High High High 0.5V Data-Out High-Z High-Z High-Z Data-In Power Active Active Standby1 Standby2 Programming
Notes: don't care inputs VIH. High: inputs. CMOS inputs. Low: inputs. CMOS inputs. Minimum drawn when standby mode implemented with (standby1 power).
Absolute Maximum Ratings
Applied Conditions(1) Storage Temperature Range (Ambient) Operating Temperature Range (TCASE) Positive Supply Voltage Input Voltage(2) Output Voltage(2) Power Dissipation(3) Lead Temperature (Soldering sec) Electrostatic Discharge Sensitivity(4)
Notes:
Minimum -65°C -55°C -0.5 -0.5 -0.5
Maximum +150°C +125°C +7.0 VDD+ VDD+ +250°C
(Class
Stresses above absolute maximum rating cause permanent damage device. Extended operation maximum levels degrade performance affect reliability. voltages with reference module ground leads. Maximum applied voltage shall exceed +7.0 Guaranteed design; tested. Class defined MIL-STD-883, Method 3015.
Recommended Operating Conditions
Symbol Parameters(1) Supply Voltage Programming Voltage Supply Voltage Reference Case Temperature Input Logic "Low" CMOS Input Logic "Low" Input Logic "High" CMOS Input Logic "High"
Notes:
Minimum +4.5 +3.5 +2.2
Maximum +5.5 +125 +1.5 +0.8
Units Volt Volt Volt Celsius Volt Volt
voltages referenced GND. during non-programming mode.
Power Sequencing
Power shall applied device only following sequences prevent damage excessive currents: Power-Up Sequence: GND, VDD, Inputs Power-Down Sequence: Inputs, VDD,
Electrical Characteristics
Group Subgroups Device Type Limits Minimum Maximum
Test Supply Current (Cycling Selected) Supply Current (Standby) High Level Output Voltage Level Output Voltage High Level Input Voltage Inputs Level Input Voltage Inputs High Level Input Voltage CMOS Inputs Level Input Voltage CMOS Inputs Input Leakage Output Leakage Cout
Symbol
Test Conditions(1) FMAX 1/tAVAV(min) CMOS Input Output Load FMAX 1/tAVAV(min) IOH= -200 IOL=
Units
IDD1
IDD2 IILK IOLK
xxxT xxxT xxxC xxxC
VOUT
Note: Tcase +125°C; unless otherwise specified. Test conditions measurements: delineation this table input device type (TTL CMOS). xxxT represents device with inputs; xxxC represents device with CMOS inputs. Measured during initial device characterization.
Input Levels Input Rise Fall Time Input Output Timing Reference Levels (Except Tristate Parameters) Input Output Timing Reference Levels Tristate Parameters Programmed Array `1's `0's Output Load Read Cycle
ns/Volt
Output Load Circuit
2.8V
Output Load Circuit Diagram Read Cycle Timing
Read Cycle Timing Characteristics
Limits Minimum Maximum
Test Read Cycle Time Address Access Time
Symbol tAVAV tAVQV tELQV
Device Type X4XX X6XX X4XX X6XX X4XX X6XX X4XX X6XX
Units
Chip Enable Access Time
Output Enable Access Time Chip Enable Output Active Output Enable Output Active Output Hold After Address Change Chip Enable Output Disable Output Enable Output Disable
Note:
tGLQV tELQX tGLQX tAXQX tEHQZ tGHQZ
Test Conditions: -55°C Tcase +125°C; unless otherwise specified.
Read Cycle Timing Diagram
tAVAV
Address
Valid Address tAVQV tELQV tAXQX
tELQX tGLQV
tEHQZ
tGLQX
Data
tGHQZ
Valid Data High Impedance
Dynamic Electrical Characteristics
Read Cycle PROM asynchronous operation, allowing read cycle controlled address chip enable (CE) (refer Read Cycle Timing diagram). perform valid read operation, both chip enable (CE) output enable (OE) must low. output drivers controlled independently signal. Consecutive read cycles executed with held continuously low, with held continuously low, toggling addresses. address-activated read cycle, must valid prior coincident with activating address edge transition(s). amount toggling skew between address edge transitions permissible; however, data outputs will become valid tAVQV time following latest occurring address edge transition. minimum address activated read cycle time tAVAV. When PROM operated minimum addressactivated read cycle time, data outputs will remain valid PROM until tAXQX time following next sequential address transition. control read cycle with addresses must valid prior coincident with enabling edge transition. Address edge transitions occur later than specified setup times however, valid data access time will delayed. address edge transition that occurs during time when will initiate read access, data outputs will become valid until tAVQV time following address edge transition. Data outputs will enter high impedance state tEHQZ time following disabling edge transition. control read cycle with addresses must valid prior coincident with enabling edge transition. Address edge transitions occur later than specified setup times however, valid data access time will delayed. address edge transition that occurs during time when high will initiate read access, data outputs will become valid until tAVQV time following address edge transition. Data outputs will enter high impedance state tGHQZ time following disabling edge transition.
Radiation Characteristics
Total Ionizing Radiation Dose PROM will meet stated functional electrical specifications over entire operating temperature range after total ionizing radiation dose 2x105 rad(Si). electrical timing performance parameters will remain within specifications after rebound 125°C extrapolated years operation. Total dose hardness assured wafer level testing process monitor transistors PROM product using X-ray Co60 radiation sources. Transistor gate threshold shift correlations have been made between X-rays applied dose rate 1x105 rad(Si)/min 25°C gamma rays (Cobalt source) ensure that wafer level X-ray testing consistent with standard military radiation test environments. Neutron Radiation PROM will meet functional timing specification after total neutron fluence 1x1012 applied under recommended operating storage conditions. This assumes equivalent neutron energy MeV. Single Event Effects PROM demonstrated data upset when exposed LETs MeV/mg/cm2. Given that design uses anti-fuse data storage programmability, Single Event Device Rupture (SEDR) testing also performed. SEDR detected effective MeV/mg/cm2. Latchup PROM will latch above radiation exposure conditions when applied under recommended operating conditions.
Radiation Hardness Ratings (1),(2),
Symbol SEDR
Characteristics Total Dose Single Event Latchup Single Event Dielectric Rupture (anti-fuse) Neutron Fluence Single Event Upset
Conditions
Minimum 200K
Maximum
Units rad(Si)
-55°C Tcase 125°C -55°C Tcase 125°C -55°C Tcase 125°C
Immune
Fails/Device-Day Upsets/Fuse-Day N/cm
Upsets/Bit-Day
Notes: Measured room temperature unless otherwise stated. Verification test approved test plan. Device electrical characteristics guaranteed post irradiation levels 25°C, MIL-STD-883, Test Method 1019.5, Condition There storage elements this device. Tested with ions having perpendicular incidence MeV/mg/cm2, worst case particle environment, geosynchronous orbit, 0.025" aluminum shielding.
Tester Timing Characteristics
Configuration
CMOS Configuration
Input Levels*
VDD-
Output Sense Levels
VDD- High
High
VDD- High
High
High
High
*Input rise fall times
Radiation Hardness Assurance
SYSTEMS provides superior quality level radiation hardness assurance products. excellent product quality sustained qualified operation which requires process control with statistical process control, radiation hardness assurance procedures rigid computer controlled manufacturing operation monitoring tracking system. SYSTEMS technology built with resistance radiation effects. product designed exhibit fails/bit-day worst case geosynchronous orbit under worst case operating conditions. Total dose hardness assured irradiating test structures every total dose exposure with Cobalt testing performed quarterly lots assure product meeting radiation hardness requirements.
Reliability
SYSTEMS' reliability starts with overall product assurance system that utilizes quality system involving employees including operators, process engineers product assurance personnel. extensive wafer acceptance methodology, using in-line electrical data well physical data, assures product quality prior assembly. continuous reliability monitoring program evaluates every wafer level, utilizing test structures well product testing. Test structures placed every wafer, allowing correlation checks within-wafer, wafer-to-wafer, from lot-to-lot. Reliability attributes CMOS process characterized testing both irradiated non-irradiated test structures. evaluations allow design model process changes incorporated specific failure mechanisms, i.e., carriers, electromigration, time dependent dielectric breakdown. These enhancements operation create more reliable product. process reliability further enhanced accelerated dynamic life tests both irradiated non-irradiated test structures. Screening testing procedures from customer followed qualify product. final periodic verification quality reliability product validated (Technology Conformance Inspection).
Screening Levels
SYSTEMS screen levels meet full compliant space applications. limited performance evaluation situations, SYSTEMS offers engineering screen level.
Standard Screening Procedure
Level
Flow
Comments
Wafer Acceptance Serialization Destructive Bond Pull Internal Visual Temperature Cycle Constant Acceleration PIND Radiography Electrical Test Blank Array Dynamic Burn-In Electrical Test Test Dynamic Burn-In Final Electrical Fine Gross Leak External Visual
Sample
Sample
Alternate Method Used Traceability MIL-STD-883, 2010
Meets Group Fallout MIL-STD-883, 2009
Fuse Stress Methodology
There main areas fuse-related failure concerns programmable devices. first area concern unprogrammed fuses becoming mistakenly programmed over time. second concern programmed fuses becoming unprogrammed. With anti-fuse technology, been shown that programmed anti-fuse actually becomes more reliable over time that repeated flow current strengthens programmed electrical connection that anti-fuse lifetime greater than other forms standard CMOS electromigration failure mechanisms. addition normal burn-in cycles, electrical stress methodology been implemented that allows screening wafer test unprogrammed anti-fuse infant mortality failures weaker anti-fuses that could diminish programming yield. This accomplished applying higher than normal voltage across unprogrammed anti-fuses. Specifically, there levels high voltage (9V) stresses applied unprogrammed anti-fuses wafer test prior burnin, third cycle unprogrammed fuse stress applied during final programmer personalization. Parts that fail these tests rejected. After personalization, PROM operated will experience subsequent stressing, does require additional postprogrammed electrical temperature stressing. Because antifuse infant mortality failures detected effectively screened, PROM high level reliability standard CMOS processed products. Additional justification performing post-programming burn-in will provided request.
Burn-In Methodology
There methods burn-in defined: Blank Array Wordline burn-in Test "Raster" Bitline burn-in. Blank Array Wordline burn-in designed exercise array cells sequence which will activate latent defects array area. This sequence also creates alternate biasing adjacent lines detect defects wiring levels chip. Test "Raster' Bitline burn-in designed exercise device through series logic level shifts which simulate active mode operation device, i.e., exercises decode, sense amps, datapath, peripheral circuitry. This mode used detect defects device level chip. Through these burn-in modes, chip subjected equivalent level burn-in. pins specified burn-in lists driven through individual series resistors (1.6K 10%). Burn-in voltages defined using following notation: Voltage Levels +5.5V (-0% /+10%) tied this level. Vin(0): +0.4 level programmed signals. Vin(1): +5.5 (-0% /+10%) High level programmed signals. Pins: module pins shall tied ground.
Blank Array Wordline Burn-In Listing
Input Input Signal F/16 DQ0-7 Signal F/16 F/32 F/64 F/128 F/256 F/512 F/1024 Note:
Test "Raster" Burn-In Listing
Input Input Signal F/16 F/32 High High High DQ0-7 Signal High High High F/64 F/128 F/256 F/512
square wave, MHz.
Burn-In Circuit
(±10%) 1.6K (±10%)
PROM
Device Programming
PROM programming accomplished using UnisiteUniversal Programmer made Data corporation. Unisite tool programming device technologies packaging. Data family universal programs corresponding software releases updates available direct from Data Corporation (800) 3-DATAIO,
Technical Support). adapter #1007 must also purchased from Data interface PROM flatpack Data Programmer Unit. PROM device number programming algorithm information contained internal silicon signature which read programmer transparent user.
Minimum System Requirements Device Programming Hardware Unisite Adapter #1007 Host Definition Data Programmer Adapter Card SYSTEMS PROM Host Minicomputer, i.e., Sun, Apollo Workstation DOS-Based Personal Computer i.e., Compatible Stand-Alone Terminal, i.e., 200, Qume VT-101, Wyse WY-30/40/70 Family Terminals Function Program PROMs Interface with Unisite Programmer Control Programmer Remote Storage Data Files
Terminal
Programming
Programming Hints
PROM array built with "1's" anti-fuse technology implemented program "0's." unused locations should remain unprogrammed "1's" save programming time allow additional program locations.
Post Programming Hints
Data Programmer uses slow timings both program verify programming PROM devices. After programming, recommended that users test devices speed over application temperature range ensure that programmed devices meet application requirements.
Packaging
PROM offered custom 28-lead package constructed multilayer ceramic (AI2O3) feature internal power ground planes. also features non-conductive ceramic lead frame. purpose allow electrical testing device, while preserving lead integrity during shipping handling, point lead forming insertion. Optional capacitors mounted package maximize supply noise decoupling increase board packing density. These capacitors attach directly internal package power ground planes. This design minimizes resistance inductance bond wire package, both which critical transient radiation environment. pins must connected either VDD, active driver prevent charge build radiation environment. connect.)
28-Lead Flat Pack Pinout
View
28-Lead Flat Pack
(Width)
A=.017 .002 B=.050 .003 C=.035 .014 D=.400 .020 E=.175 .010
F=.760 .008 G=.500 .008 H=1.650 J=.650 K=.109
(USA) Date Code
Notes:
(Pitch)
Part mark device specification. "QML" required device specification. Dimensions inches. Lead width: .008 .002.
Lead height: .006 .002. Unless otherwise specified, tolerances .005".
Index
Index Marks
Ordering Information
PROM Memory Device Number 197A807-WXYZ
Package Type Flatpack
Speed Designation
Screen Designation
Input Type
1=QML CMOS 3=Engineering 4=QML 5=QML 7=Customer Specific
SYSTEMS reserves right make changes products herein improve reliability, function design. SYSTEMS does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others.
SYSTEMS 9001, AS9000, 14001, Level Company 9300 Wellington Road, Manassas, 20110-4122 866-530-8104 0040_32K_8_PROM.ppt
Cleared Public Domain Release ©2001 SYSTEMS, Rights Reserved
SYSTEMS 9300 Wellington Road Manassas, Virginia 20110-4122

197A807 Other Read/Write Cycle Times (-55 125°C) Number 5962R9689

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