EM83040B matrix driver, which fabricated power CMOS technology. This c
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EM83040B DRIVER CONTROLLER
EM83040B matrix driver, which fabricated power CMOS technology. This chip includes 80-bits shift register, bits data latch bits level driver. inside mapping signal. converts data parallel data output waveform LCD.
Supply power: 2.5~5.5V drive voltage: to13V Internal RAM: 2.5k bits controlled eight signals including four bits data bus. Duty: 1/32, 1/48, 1/64, 1/80 Build DC/DC converter: double, triple, quad five times. Modularized function: connect another 83040B extent matrix converter enabled other 83040B share with this.
(10) Chip form (EM83040BH), package (14mm 20mm EM83040BAQ), package (EM83040BBQ)
(11) Bias: COMMON), COMMON), COMMON) fixed internal circuit.
(12) Internal clock about KHz.
Application
Data Bank Education computer
Internal regulator output DC/DC converter controlled control register.
EM83040B DRIVER CONTROLLER
assignment
EM83040BBQ
MAIN
RAMEN RAMADS RAMW RAMR RAMD3 RAMD2 RAMD1 RAMD0 LOAD VOUT VSS4 VSS3 VSS2+ VSS2V1 VREG
EM83040B DRIVER CONTROLLER
EM83040BAQ
MAIN RAMEN RAMADS RAMW RAMR RAMD3 RAMD2 RAMD1 RAMD0 LOAD VOUT VSS4 VSS3 VSS2+ VSS2V1 VREG
EM83040B DRIVER CONTROLLER
Block diagram
O1~O80
MAIN
CONTROL CIRCUIT CIRCUIT
DRIVER
COMMEN CIRCUIT
SEGMENT CIRCUIT
BITS LATCH TIMING CONTROL CIRCUIT BITS SHIFT REGISTER VOUT VSS4 VSS3 VSS2+ VSS2VREG
RESISTANCE RATIO
LOAD
RAMEN RANADS RAMW RAMR RAMD3 RAMD2 RAMD1 RAMD0
MAPPING
CONVERTER M1,M0
REG(5~0)
REGULATOR
IR(2~0)
Buffer1 Buffer2 Buffer3 Buffer4 Buffer5
:::::
BIAS
EM83040B DRIVER CONTROLLER
description
name VOUT VSS4 VSS3 VSS2+ VSS2VREG MAIN Power Power Power Power Power Power Power Power Function System power supply Ground Voltage converter input/output Connect this through capacitor EN=1,VOUT=VDD Step-up capacitor Step-up capacitor Step-up capacitor Step-up capacitor Output voltage regulator terminal. Provides voltage between through resistive voltage divider. Master slave control signal. MAIN=1, master unit MAIN=0, slave unit This control whole chip power. This chip will work when this connected ground. whole chip will disable when connect voltage. EN=0 MAIN=1 chip will generate VSS2+, VSS2- VSS3, VSS4, VOUT, LOAD signal internal clock. EN=1, standby mode Mode select Mode select read write control signal. read write. read write. data select signal Data, 0=>Address write signal, write read signal, read data address load signal between COMMON signal another. MAIN=1, master unit will output LOAD signal. MAIN=0, slave will accept signal from master unit. Coupling capacitor Coupling capacitor Reference voltage input, highest lowest waveform output
RAMEN RAMADS RAMW RAMR RAMD3~RAMD0 LOAD V1~V5 O1~O80
EM83040B DRIVER CONTROLLER
Function description
User MAIN choose master unit slave unit. MAIN Unit MASTER SLAVE Function Generate these signals: Load, VSS2+, VSS2-, VSS3, VSS4, VOUT Internal clock Accept these Master unit signals Load, VOUT, internal clock
User choose four modes. followed MASTER Mode1 Mode2 Mode3 Mode4 SLAVE Mode1 Mode2 Mode3 Mode4 MAIN MAIN Segment O(16:1)=S(16:1) O(32:1)=S(32:1) O(48:1)=S(48:1) Segment O(80:1)=S(80:1) O(80:1)=S(80:1) O(80:1)=S(80:1) O(80:1)=S(80:1) Common O(80:17)=C(64:1) O(80:1)=C(80:1) O(80:33)=C(48:1) O(80:49)=C(32:1) Common BIAS BIAS
S=Segment, C=Common
(M1, Master must same Slave unit
control Write mode
RAMEN RAMADS RAMD(3:0) RAMW RAMR A3=address(11:8) A2=address(7:4) A1=address(3:0) ADDRESS DATA enable disable
EM83040B DRIVER CONTROLLER written read with control signal. RAMEN select which read write. RAMADS select whether RAMD(3:0) data address RAM. address mode, RAMADS user should sent address three times, from address (11:8) address (3:0). Then will into data mode when RAMADS high. data mode, user sent more nibble data which address increased internal counter. Once RAMEN high, read write.
Read mode
RAMEN RAMADS RAMD(3:0) RAMW RAMR A3=address(11:8) A2=address(7:4) A1=address(3:0) ADDRESS DATA enable disable
same write mode, user sent address three times. read data from which address increased internal counter. Note!! sure make RAMR pulse (Tdv +data) width (Tdd) high width least.
mapping address from address 2562 User fill RAM, driver will generate "light" waveform. Otherwise, will generate "dark" waveform. area mapped segment segment from address address user refer fig.5 Table idea mapping. other general data storage mapping display. address 2560, 2561 2562 control registers. Table mapping area Common Segment Master/slave Master Slave Master Slave Master Slave Master Slave Display area 1,2,3 1,2,3,4 1,2,5,6 1,2,3,4,5,6,7 1,5,8 1,2,3,4,5,6,7,8,9 mapping 1,2,3,4,5,6,7,8,9,10 Area general
EM83040B DRIVER CONTROLLER
Address 2560,2561, 2562Control register
Address2560,2561,2562 control register address2559 address2547. address2528 COM80
Area
EMPTY AREA
Area
COM64
address2047 address2035 .address2019. address2016
Area Area Area Area
Area
COM48
address1535 address1523 .address1511. address1504
Area Area
Area
COM32
address1023 address1011 .address1003. address0992
Area
COM2 COM1
address0063 address0051 address0032 address0031 address0019 address0000 s80s79s78s77
waveform
frame
com0
com1
com2
dark
light
EM83040B DRIVER CONTROLLER
Control register Address 2560 2561 2562 don't care Default status Address 2560,2561 2562, respectively: 0010, 0000, 0000 Address 2562 bit3~2(PS1, PS0) selected: settings Only internal power supply used Only regulator circuit circuit used Only circuit used Only external power supply used Step-up circuit regulator External circuit circuit voltage input VOUT Bit3 REG3 Bit2 REG2 Bit1 REG1 REG5 Bit0 REG0 REG4
Address 2562 bit1~0 2561 bit3~0 (Reg5~Reg0) selected value
REG5~REG0 000000 000001 011111 100000 111110 111111
1.212 1.572 1.584 1.944 1.956
step 0.012V
VOUT
VREG
EM83040B DRIVER CONTROLLER Address 2560 bit3 (IRS) internal resistor selected IRS=0: internal regulator resistor used. IRS=1: internal regulator resistor used. (External resistor used) Address 2560 bit0~2(IR2, IR1, IR0) selected voltage regulator internal resistance ratio IR2~IR0 Resistor ratio (1+Rb/Ra)
voltage calculated using equation over range where VDD<V1VOUT
(REG5~0)=(000000)
(Equation
Example: Default: IRS=0 (internal regulator resistor used), (IR2, IR1, IR0)=(0,
4.656~4.944 When IRS=0 (internal regulator resistor used), (IR2, IR1, IR0)=(0, (REG5~0)=(100000) 6.91~7.34
EM83040B
(IR2~IR0)
(Reg5~Reg0)
FIG. output voltage determined function voltage regulator ratio register (1+Rb/Ra), electric volume resister (REG5~REG0).
EM83040B DRIVER CONTROLLER step-up voltage circuit Case double step-up, triple step-up Case quad step-up VOUT output voltage bias voltage supported from VREG. Double step-up, Triple step-up, Quad step-up five times step-up C1=0.47 1.0f, C2=1.0 4.7uf
VOUT VSS4 VSS3
VOUT VSS4 VSS3
VOUT VSS4
VOUT
VSS4
VSS3
VSS3
EM83040B
EM83040B
VSS2+ VSS2VREG
EM83040B
VSS2+ VSS2VREG
VSS2+ VSS2VREG
EM83040B
VSS2+ VSS2VREG
VOUT=2*VDD
VOUT=3*VDD
VOUT=4*VDD
VOUT=5*VDD
Reference circuit examples following FIG.
Only internal power supply used, control register (PS1, PS0, IRS)=(1,1,0) Only internal power supply used, control register (PS1, PS0, IRS)=(1,1,1) When internal regulator resistor used (external resistor used), V1=VREG*(1+Rb'/Ra') Only regulator circuit circuit used, control register (PS1, PS0, IRS)=(1,0,0) Only regulator circuit circuit used, control register (PS1, PS0, IRS)=(1,0,1), When internal regulator resistor used (external resistor used), V1=VREG*(1+Rb'/Ra') Only circuit used, control register (PS1, PS0)=(0,1) Only external power supply used, control register (PS1, PS0)=(0,0)
EM83040B DRIVER CONTROLLER
VOUT MAIN VSS4 VSS3
VOUT MAIN VSS4 VSS3
VOUT MAIN VSS4 VSS3
EXTERNAL POWER SUPPLY
EM83040B
EM83040B
EM83040B
VSS2+
VSS2+
VSS2+ VSS2VREG
VSS2VREG
VSS2VREG
EXTERNAL POWER SUPPLY
VOUT MAIN VSS4 VSS3
VOUT MAIN VSS4 VSS3
VOUT MAIN VSS4 VSS3
EM83040B
EM83040B
VSS2+ VSS2VREG
VSS2+ VSS2VREG
EM83040B
VSS2+ VSS2VREG
EXTERNAL POWER SUPPLY
EXTERNAL POWER SUPPLY
8.Absolute rating
RATING SUPPLY VOLTAGE INPUT VOLTAGE OPERATING TEMPERATURE RANGE SYMBOL VALUE -0.5 +0.5 UNIT
EM83040B DRIVER CONTROLLER
9.DC characteristic
(Ta=0°C 70°C, VDD=3V±5%, VSS=0V) Symbol Input voltage Output current Standby current Parameter Condition With double step-up With triple step-up With quad step-up With five times step-up VDD=3V EN=1 EN=0. MAIN (MASTER), converter enable, Five times step-up (M1, M0)=(1,1) V1=11V 250KHz clock, load EN=0. MAIN (SLAVE), converter disable, Five times step-up (M1, M0)=(1,1) 250KHz clock, load -100 Unit
Operating current
Ibuf Vreg Ireg R_bias
Current buffer Voltage variation regulator Regulator current BIAS resistor
V-0.1 1800
2000
V+0.1 2200
EM83040B DRIVER CONTROLLER
10.AC Characteristic
(Ta=0°C 70°C, VDD=3V, VSS=0V) Symbol Tframe Tload Parameter clock variable Frame period Load period Enable time Write pulse Data hold time Data data time Data valid time 1/64 1500 Unit
timing
FRAME LOAD
C0C1
Tload
Tframe
POSITIVE FRAME
NEGATIVE FRAME
control timing
EM83040B DRIVER CONTROLLER
RAMEN RAMADS RAMD(3:0) RAMW RAMR A3=address(11:8) A2=address(7:4) A1=address(3:0) ADDRESS
enable
disable
DATA
write mode
RAMEN RAMADS RAMD(3:0) RAMW RAMR
enable
disable
ADDRESS
DATA
A3=address (11:8) A2=address(7:0) A1=address(3:0) first nibble D2=second nibble D3=third nibble data
read mode
EM83040B DRIVER CONTROLLER
Application circuit
MAIN RAMEN O80.O1 LOAD VOUT VSS4 VSS3 VSS2+ VSS2VREG
RAMADS RAMW RAMR RAMD(3:0)
S128
S127 MAIN RAMEN O80.O1 LOAD VOUT VSS4 VSS3 VSS2+ VSS2VREG LOAD VOUT MAIN RAMEN O80.O1 LOAD VOUT VSS4 VSS3 VSS2+ VSS2VREG CONNECT MASTER CHIP LOAD VOUT
RAMADS RAMW RAMR RAMD(3:0)
MASTER
32*128
RAMADS RAMW RAMR RAMD(3:0)
SLAVE
EM83040B DRIVER CONTROLLER
S112
48*112
S111 MAIN RAMEN O80.O1 LOAD VOUT VSS4 VSS3 VSS2+ VSS2VREG LOAD VOUT MAIN RAMEN O80.O1 LOAD VOUT VSS4 VSS3 VSS2+ VSS2VREG CONNECT MASTER CHIP LOAD VOUT
RAMADS RAMW RAMR RAMD(3:0)
RAMADS RAMW RAMR RAMD(3:0)
MASTER
64*96
SLAVE
O80.O1
MAIN RAMEN
LOAD VOUT VSS4 VSS3 VSS2+ VSS2VREG LOAD VOUT MAIN RAMEN
O80.O1
LOAD VOUT VSS4 VSS3 VSS2+ VSS2VREG CONNECT MASTER CHIP LOAD VOUT
RAMADS RAMW RAMR RAMD(3:0)
RAMADS RAMW RAMR RAMD(3:0)
MASTER
SLAVE
EM83040B DRIVER CONTROLLER
C80*S160
80*160
MAIN RAMEN O80.O1 LOAD VOUT VSS4 VSS3 VSS2+ VSS2VREG LOAD VOUT MAIN RAMEN O80.O1 LOAD VOUT VSS4 VSS3 VSS2+ VSS2VREG CONNECT MASTER CHIP LOAD VOUT
RAMADS RAMW RAMR RAMD(3:0)
RAMADS RAMW RAMR RAMD(3:0)
MASTER
SLAVE1
S159 O80.O1 LOAD VOUT VSS4 VSS3 VSS2+ VSS2VREG CONNECT MASTER CHIP LOAD VOUT
MAIN RAMEN
RAMADS RAMW RAMR RAMD(3:0)
SLAVE2
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