dynamic range Digital demodulators Active low-pass filters Dual wideba
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Diversity IF-to-Baseband GSM/EDGE Narrow-Band Receiver AD6650
dynamic range Digital demodulators Active low-pass filters Dual wideband Programmable decimation channel filters phase-locked loop circuitry Serial data output ports Intermediate frequencies noise figure input -9.5 input CMOS core Microprocessor interface JTAG boundary scan
AD6650 diversity (IF-to-baseband) receiver GSM/EDGE. This narrow-band receiver consists integrated DVGA, IF-to-baseband demodulators, low-pass filtering, dual wideband ADC. chip accommodate input from MHz. This receiver architecture designed such that only external surface acoustic wave (SAW) filter main diversity required entire receive signal path meet GSM/EDGE blocking requirements. Digital decimation filtering circuitry provided on-chip remove unwanted signals noise outside channel interest. Programmable coefficient filters allow antialiasing, matched filtering, static equalization functions combined single cost-effective filter. output channel filters provided user serial output data streams.
APPLICATIONS
GSM/EDGE single carrier, diversity receivers Micro cell pico cell systems Wireless local loop Smart antenna systems Software radios In-building wireless telephony
FUNCTIONAL BLOCK DIAGRAM
TWEAK GAIN RELIN CTRL
AD6650 GSM/ EDGE RECEIVER
FILTER
IFIN SCLK CPOUT LFIN VLDO PLL/ SDFS SERIAL PORT SDO0 SDO1 12-BIT COARSE ORDER ORDER PROG. (RCF) FINE BIST
IFIN RELIN CTRL TWEAK GAIN JTAG FILTER 12-BIT COARSE ORDER ORDER PROG. (RCF) FINE BIST
TCLK
TRST
MODE [1:0]
SYNC
AGND
DGND
RESET
MICRO
Figure
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. rights reserved.
BYPASS
DTACK
AVDD
DVDD
[2:0]
[7:0]
03683-001
DIVIDER
MICRO
AD6650 TABLE CONTENTS
Features Applications. Product Description. Functional Block Diagram Revision History Specifications. Explanation Test Levels Specifications. Digital Specifications Electrical Characteristics. General Timing Characteristics Microprocessor Port Timing Characteristics Timing Diagrams. Absolute Maximum Ratings. Thermal Characteristics Caution. Configuration Function Descriptions. Terminology Equivalent Circuits Typical Performance Characteristics Theory Operation Analog Front Digital Back End. Correction Fourth-Order Cascaded Integrator Comb Filter (CIC4) Infinite Impulse Response (IIR) Filter. Coefficient Filter Composite Filter Fine Correction Peak Detector Correction Ranging. User-Configurable Built-In Self Test (BIST) Synthesis. LDO. Loop/Relinearization Serial Output Data Port. Applications Information Required Settings Start-up Sequence Correction.27 Clocking AD6650 Driving Analog Inputs External Reference Power Supplies Digital Outputs Grounding Layout Information. Chip Synchronization Microport Control. External Memory Access Control Register (ACR) Channel Address Register (CAR) Special Function Registers Data Address Registers Write Sequencing Read Sequencing Read/Write Chaining Programming Modes JTAG Boundary Scan. Register Register Details Outline Dimensions Ordering Guide
REVISION HISTORY
3/06-Revision Initial Version
Rev. Page
AD6650 SPECIFICATIONS
EXPLANATION TEST LEVELS
100% production tested. 100% production tested 25°C; sample tested specified temperatures. Sample tested only. Parameter guaranteed design analysis. Parameter typical value only. 100% production tested 25°C; sample tested temperature extreme. 100% production tested +85°C.
CLOAD outputs, unless otherwise specified. timing specifications valid over range 3.15 3.45 VDDIO range 3.15 3.45
SPECIFICATIONS
AVDD DVDD MSPS (driven differentially), duty cycle, unless otherwise noted. minimum specifications guaranteed from -25°C +85°C. minimum specifications degrade slightly from -25°C -40°C. Table
Parameter OVERALL FUNCTION Frequency Range GAIN CONTROL Gain Step Size Gain Step Accuracy Range BASEBAND FILTERS Bandwidth Alias Rejection 25.9 PHASE NOISE Offset Offset Offset Offset Offset Offset Offset Offset 1600 Offset 3000 Offset GAIN ERROR Coarse Correction Noise Figure Input IP21 Input IP31 Image Rejection Full-Scale Input Power Input Impedance Temp Full 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C Test Level 3.36 0.094 ±0.047 -103 -112 -119 -125 -130 -133 -138 -143 -0.7 -9.5 189.6 j33.6 3.64 Unit dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
Full Full Full
Rev. Page
AD6650
Parameter Coarse Correction Noise Figure1 Input IP21 Input IP31 Image Rejection Full-Scale Input Power Input Impedance Coarse Correction Noise Figure1 Input IP21 Input IP31 Image Rejection Full-Scale Input Power Input Impedance Coarse Correction Noise Figure1 Input IP21 Input IP31 Image Rejection Full-Scale Input Power Input Impedance
Temp
Test Level
-11.5 -46.5 169.3 j59.2 -46.5 159.3 j66.9 137.1 j72.7
Unit
Full Full Full
Full Full Full
Full Full Full
This measurement applies maximum gain dB).
DIGITAL SPECIFICATIONS
AVDD, DVDD MSPS, unless otherwise noted. Table
Parameter DVDD AVDD TAMBIENT
Temp Full Full
Test Level
3.15 3.15
3.45 3.45
Unit
AD6650 guaranteed fully functional from -40°C +85°C. minimum specifications guaranteed from -25°C +85°C, degrade slightly from -25°C -40°C.
Rev. Page
AD6650
ELECTRICAL CHARACTERISTICS
Table
Parameter (Conditions) LOGIC INPUTS Logic Compatibility Digital Logic Logic Voltage Logic Voltage Logic Current Logic Current Input Capacitance CLOCK INPUTS Differential Input Voltage Common-Mode Input Voltage Differential Input Resistance Differential Input Capacitance LOGIC OUTPUTS Logic Compatibility Logic Voltage (IOH 0.25 Logic Voltage (IOL 0.25 SUPPLY CURRENT (GSM Example) IVDD IAVDD POWER DISSIPATION (GSM/EDGE Example)
Temp Full Full Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C Full Full Full
Test Level
CMOS
Unit
DVDD/2 CMOS/TTL
Full Full Full
specifications tested driving differentially.
GENERAL TIMING CHARACTERISTICS
Table
Parameter (Conditions) TIMING REQUIREMENTS tCLK Period tCLKL Width tCLKH Width High RESET TIMING REQUIREMENTS tSSF RESET Width PIN_SYNC TIMING REQUIREMENTS SYNC Setup Time SYNC Hold Time SERIAL PORT TIMING REQUIREMENTS: SWITCHING CHARACTERISTICS tDSCLK1 SCLK Delay (Divide-by-1) tDSCLKH SCLK Delay (For Other Divisor) tDSCLKL SCLK Delay (Divide-by-2 Even Number) tDSCLKLL SCLK Delay (Divide-by-3 Number) tDSDFS SCLK SDFS Delay tDSDO SCLK Delay tDSD1 SCLK Delay tDSDR SCLK Delay
Temp Full Full Full Full Full Full Full Full Full Full Full Full Full Full
Test Level
19.2
Unit
tCLK tCLK 12.5
Minimum specification based MSPS clock rate internal divide-by-2 must used with MSPS clock rate); maximum specification based MSPS clock rate. This device optimized operate clock rate MSPS MSPS. timing parameters SCLK, SDFS, SDO0, SDO1, apply both channels
Rev. Page
AD6650
MICROPROCESSOR PORT TIMING CHARACTERISTICS
timing specifications valid over range 3.15 3.45 VDDIO range 3.15 3.45 Table Microprocessor Port, Mode (MODE Asynchronous Operation
Parameter WRITE TIMING tHWR (RW) (DTACK) Hold Time tSAM Address/Data (RW) Setup Time1 tHAM Address/Data (DTACK) Hold Time1 tDRDY (RW) (DTACK) Delay tACC (RW) (DTACK) High Delay1 READ TIMING tSAM Address (DS) Setup Time1 tHAM Address Data Hold Time1 Data Tri-state Delay1 (DTACK) Data Delay1 tDRDY2 (DS) (DTACK) Delay tACC (DS) (DTACK) High Delay1
Temp Full Full Full Full Full Full Full Full Full Full Full
Test Level
tCLK
Unit
15.0 tCLK
tCLK 15.0 tCLK
Timing guaranteed design. Specification pertains control signals such that minimum specification valid after last control signal reached valid logic level.
Table Microprocessor Port, Mode (MODE
Parameter WRITE TIMING tHDS (RD) DTACK (RDY) Hold Time tHRW (WR) DTACK (RDY) Hold Time tSAM Address/Data (WR) Setup Time tHAM Address/Data (WR) Hold Time1 tDDTACK (RD) DTACK (RDY) Delay tACC (WR) DTACK (RDY) Delay1 READ TIMING tHDS (RD) DTACK (RDY) Hold Time tSAM Address (RD) Setup Time1 tHAM Address Data Hold Time1 Data Three-State Delay DTACK (RDY) Data Delay1 tDDTACK (RD) DTACK (RDY) Delay2 tACC (RD) DTACK (RDY) Delay1
Temp Full Full Full Full Full Full Full Full Full Full Full Full Full
Test Level
15.0 15.0
Unit
tCLK 15.0 tCLK tCLK tCLK
Timing guaranteed design. DTACK open-drain device must pulled with resistor.
Rev. Page
AD6650
TIMING DIAGRAMS
RESET
tSSF
Figure Reset Timing Requirements
tDSCLKH
SCLK
03683-003
Figure SCLK Switching Characteristics (Divide-by-1)
tDSCLKH
SCLK
tDSCLKL
03683-004
Figure SCLK Switching Characteristics (Divide-by-2 Even Integer)
tDSCLKH
SCLK
tDSCLKLL
03683-005
Figure SCLK Switching Characteristics (Divide-by-3 Integer)
SCLK
tDSDR
03683-006
Figure SCLK, Switching Characteristics
SCLK
tDSDFS
SDFS
03683-007
Figure SCLK, SDFS Switching Characteristics
SCLK
tDSD0/ tDSD1
SDOx
03683-008
Figure SCLK, SDO0/SDO1 Switching Characteristics
Rev. Page
03683-002
AD6650
SYNC
03683-009
Figure Sync Timing Inputs
(DS)
tHWR
(R/W)
tSAM
A[2:0] VALID ADDRESS
tHAM
tSAM
D[7:0] VALID DATA
tHAM
tDRDY
(DTACK)
tACC
NOTES tACC ACCESS TIME DEPENDS ADDRESS ACCESSED. ACCESS TIME MEASURED FROM RDY. tACC REQUIRES MAXIMUM NINE PERIODS.
03683-010
Figure Microport Write Timing Requirements
(DS)
(RW)
tSAM
A[2:0] VALID ADDRESS
D[7:0]
tHAM
VALID DATA
tDRDY
(DTACK)
tACC
NOTES tACC ACCESS TIME DEPENDS ADDRESS ACCESSED. ACCESS TIME MEASURED FROM RDY. tACC REQUIRES MAXIMUM PERIODS.
03683-011
Figure Microport Read Timing Requirements
Rev. Page
AD6650
tHDS
(RD)
tHRW
(WR)
tSAM
A[2:0]
tHAM
VALID ADDRESS
tSAM
D[7:0] VALID DATA
tHAM
tDDTACK
DTACK (RDY)
tACC
NOTES tACC ACCESS TIME DEPENDS ADDRESS ACCESSED. ACCESS TIME MEASURED FROM DTACK. tACC REQUIRES MAXIMUM NINE PERIODS.
03683-012
Figure Microport Write Timing Requirements
tHDS
(RD)
(WR)
A[2:0] VALID ADDRESS
D[7:0]
VALID DATA
tHAM
tDDTACK
DTACK (RDY)
tACC
NOTES tACC ACCESS TIME DEPENDS ADDRESS ACCESSED. ACCESS TIME MEASURED FROM DTACK. tACC REQUIRES MAXIMUM PERIODS.
Figure Microport Read Timing Requirements
Rev. Page
03683-013
AD6650 ABSOLUTE MAXIMUM RATINGS
Table
Parameter Supply Voltage Input Voltage Output Voltage Swing Load Capacitance Junction Temperature Under Bias Storage Temperature Range Lead Temperature sec) Rating -0.3 +3.6 -0.3 +3.6 -0.3 VDDIO +125°C -65°C +150°C +280°C
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
THERMAL CHARACTERISTICS
121-lead chip scale package ball grid array: 22.8°C/W, airflow, measurements made horizontal position 4-layer board. 20.2°C/W, LFPM airflow, measurements made horizontal position 4-layer board. 20.7°C/W, airflow, soldered 8-layer board with layers dedicated ground planes.
CAUTION
(electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although this product features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
Rev. Page
AD6650 CONFIGURATION FUNCTION DESCRIPTIONS
Table Configuration
DGND SDFS SDO1 (RD) (WR) DGND SCLK SDO0 DTACK (RDY) DVDD DVDD DVDD DVDD DVDD DVDD DVDD MODE2 TRST TCLK DVDD DGND DGND DGND DGND DGND DVDD MODE1 MODE0 RESET SYNC DVDD DGND DGND DGND DGND DGND DVDD CHIP_ID1 CHIP_ID0 DVDD DGND DGND DGND DGND DGND DVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD REFGND VREF AGND AGND AGND AGND AGND AGND AGND AGND REFT REFB AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND VLDO CPOUT AGND AGND
Table Function Descriptions
Mnemonic POWER SUPPLY DVDD AVDD DGND AGND DIGITAL INPUTS RESET SYNC CHIP_ID [1:0] SERIAL DATA PORT SCLK SDFS SDO[1:0] MICROPORTCONTROL [7:0] [2:0] (RD) DTACK (RDY) (WR) MODE [2:0] JTAG TRST TCLK Type I/O/T I/O/T Description Digital Supply. Analog Supply. Digital Ground. Analog Ground. Active Reset Pin. Synchronizes Digital Filters. Chip Serial Clock. Serial Data Frame Sync. Serial Data Outputs. Output Data Ready Indicator. Microport Data. Microport Address Bits. Chip Select. Active Data Strobe (Active Read). Active Data Acknowledge (Microport Status Bit). Read Write (Active Write). Selects Control Port Mode. Test Reset Pin. Test Clock Input. Test Mode Select Input. Test Data Output. Test Data input. Pins
Rev. Page
AD6650
Mnemonic ANALOG INPUTS INPUTS CPOUT VLDO REFT REFB VREF REFGND CLOCK INPUTS Type Description Main Analog Input. Complement AIN. Differential analog input. Diversity Analog Input. Complement BIN. Differential analog input. Charge-Pump Output. Loop Filter. Compensation Internal Low-Dropout Regulator. Bypass ground with chip capacitor. Internal Voltage Reference. Bypass ground with capacitors. Figure recommended connection. Internal Voltage Reference. Bypass ground with capacitors. Figure recommended connection. Internal Voltage Reference. Bypass ground with capacitors. Figure recommended connection. Ground Reference. Figure recommended connection. Encode Input. Conversion initiated rising edge. Complement Encode. Connect. Pins
Rev. Page
AD6650 TERMINOLOGY
Analog Bandwidth analog input frequency which spectral power fundamental frequency determined analysis) reduced Noise Figure (NF) degradation performance input signal after passes through component system. AD6650's noise figure determined equation Image AD6650 incorporates quadrature demodulator that mixes frequency baseband frequency. phase amplitude imbalance this quadrature demodulator observed complex image fundamental frequency. term image arises from mirror-like symmetry signal image frequencies about beating-oscillator frequency this case, this dc). Differential Analog Input Resistance, Differential Analog Input Capacitance, Differential Analog Input Impedance real complex impedances measured each analog input port. resistance measured statically, capacitance differential input impedances measured with network analyzer. Differential Analog Input Voltage Range peak-to-peak differential voltage that must applied converter generate full-scale response. Peak differential voltage computed observing voltage single subtracting voltage from other pin, which 180° phase. peak-to-peak differential voltage computed rotating phases inputs 180° taking peak measurement again. Then difference computed between both peak measurements. Full-Scale Input Power Expressed dBm. computed using following equation:
0.001
0.001
where: Boltzman constant 1.38 10-23. temperature Kelvin. channel bandwidth hertz (200 typical). V2rms full-scale input voltage. input impedance. SNRFS computed signal-to-noise ratio referred full scale with small input signal AD6650 maximum gain.
Input Second-Order Intercept (IIP2) figure merit used determine component's system's susceptibility intermodulation distortion (IMD) from second-order nonlinearities. unmodulated carriers specified frequency relationship injected into nonlinear system exhibiting second-order nonlinearities producing components IIP2 graphically represents extrapolated intersection carrier's input power with second-order component when plotted decibels. Input Third-Order Intercept (IIP3) figure merit used determine component's system's susceptibility intermodulation distortion (IMD) from third-order nonlinearities. unmodulated carriers specified frequency relationship injected into nonlinear system exhibiting third-order nonlinearities producing components IIP3 graphically represents extrapolated intersection carrier's input power with third-order component when plotted decibels.
PowerFullscale
Fullscalerms Input 0.001
where ZInput input impedance.
Noise noise, including both thermal quantization noise, range within computed
Vnoise 0.001
FSdBm SNRdBc SignaldBFS
where: input impedance. FSdBm full scale device frequency question. SNRdBc value particular input level. SignaldBFS signal level within reported decibels below full scale.
Rev. Page
AD6650 EQUIVALENT CIRCUITS
CLAMP
03683-014
1.3V
Figure Analog Input
AVDD 2.5k
03683-015
2.5k
Figure Clock Input
Rev. Page
AD6650 TYPICAL PERFORMANCE CHARACTERISTICS
-44.00
44.00
-45.00
42.00 +25°C 40.00
IMAGE (dBc) IIP2 (dBm)
-46.00 -47.00 -48.00 -49.00 -50.00 -51.00 +25°C
-25°C
+85°C
38.00 36.00 34.00 32.00 30.00
-25°C
+85°C
03683-017
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure Input Frequency
Figure Image Frequency
-6.00 -7.00 -8.00
-44.00 -45.00 -46.00
-25°C
-9.00
IMAGE (dBc)
IIP3 (dBm)
-10.00 -11.00 -12.00 -13.00 -14.00 -15.00 FREQUENCY (MHz) -25°C +25°C
-47.00 +25°C -48.00 -49.00
+85°C
03683-018
+85°C
03683-020
-50.00 -51.00
FREQUENCY (MHz)
Figure Input Frequency
Figure Gain Error Frequency
Rev. Page
03683-019
AD6650 THEORY OPERATION
ANALOG FRONT
AD6650 mixed-signal front-end (MxFETM) component intended direct sampling radios requiring high dynamic range. optimized demanding performance requirements EDGE. AD6650 five signal processing stages: digital VGA, demodulators, seventh-order low-pass filters, dual ADCs, digital filtering. Programming control accomplished microprocessor interface. that total AD6650 response unchanged. 19-bit output block then decimated filtered using CIC4 filter, filter, programmable coefficient filter (RCF). Either 16-bit 24-bit data output through serial port. With gain, 12-bit performance, approximately processing gain, AD6650 capable delivering approximately dynamic range bits performance. this reason, recommended that 24-bit serial output used that dynamic range lost. block diagram digital signal path shown Figure
DITHER GEN. RELIN CTRL FILTER
DVGA
gain-ranging digital used extend dynamic range minimize signal clipping input. maximum gain with nominal step size 0.094 amplifier serves input stage AD6650 nominal input impedance maximum input.
Figure Channel Digital Signal Path
Demodulators
Frequency translation accomplished with demodulators. Real data entering this stage separated into in-phase quadrature components. This stage translates input signal from intermediate frequency (IF) baseband frequency.
CORRECTION
offset analog path AD6650 comes from three sources: analog baseband filters, ADCs, leakage mixers. offsets analog filters ADCs dominate that leakage. offsets data both Channels different because they different analog paths. Each path corrected independently. typical uncorrected offset between relative full scale (dBFS) ADC. When range considered along with this offset, effectively slid down gain setting that approximately dBFS dBFS smaller when AD6650 maximum gain.
-100 -110 -120 -130 -140 -150 -160 -170 -180
Low-Pass Filters
each signal path seventh-order low-pass active filter with bandwidth automatic resistance-capacitance calibration ±4%. This filter typically offers greater than alias rejection 25.9 MHz.
Dual ADCs
AD6650 ADCs. Each implemented with AD9238 core preceded dual track-and-holds that multiplex signals MSPS each. full-scale input power into dBm.
OFFSET
DIGITAL BACK
12-bit data goes through coarse correction block, which performs one-time calibration offsets paths. output this block drives automatic gain control (AGC) loop block, which adjusts digitally controlled analog path. adjusts amplitude incoming signal interest programmable level prevents from clipping. gain subtracted relinearization block that externally AD6650 appears have constant gain. example, must increase gain from decrease signal power, relinearization word changes from gain
0.024
0.049
0.074
0.099
-0.126
-0.101
-0.076
-0.051
-0.026
FREQUENCY (MHz)
Figure Uncorrected Offset
Rev. Page
-0.001
0.124
03683-022
03683-021
COARSE
ORDER
ORDER
PROG. (RCF)
FINE
BIST
SPORT
AD6650
Coarse Correction
coarse correction block simple integrate-and-dump that integrates data 16,384 cycles clock rate (typically MSPS) then updates estimate This estimate then subtracted from signal path. signal clipped after subtraction avoid numerical wrap around with large signals. dBFS dBFS uncorrected offset sufficient demodulate large signals, does leave margin signal-to-dc desired. essential consider offset signal point where AD6650 begins range. This important because once signal blocker range loop, signal that appears output AD6650 modulated change gain loop. gain decreases, signal output remains same power level digital relinearization, signal output gained relinearization process. this reason, coarse correction used provide additional correction before relinearizing data provide additional margin. This block gains another (sometimes rejection that provides additional margin. coarse correction provided reasons:
value that subtracted Equation comes from amount scaling needed compensate minimum decimation frequency response CIC4 filter given Equations gain pass-band droop CIC4 calculated using these equations. gain and/or droop CIC4 filter acceptable, they compensated programmable filter stage.
MCIC Gain
Gain
output rate this stage given Equation
SAMP
CIC4 Rejection
Table shows amount bandwidth percentage input sample rate (ADC sample rate) that protected with various decimation rates alias rejection specifications. maximum input rate into CIC4 MHz. Table shows half-bandwidth characteristics CIC4.
Table CIC4 Alias Rejection Table
Rate 2.494 2.224 2.006 1.827 1.676 1.549 1.439 1.344 1.261 1.187 1.122 1.063 1.010 0.962 0.919 0.879 0.842 0.809 0.778 0.749 0.722 0.697 0.674 0.653 0.632 1.921 1.713 1.546 1.408 1.292 1.194 1.110 1.037 0.972 0.916 0.865 0.820 0.779 0.742 0.709 0.678 0.650 0.624 0.600 0.578 0.557 0.538 0.520 0.503 0.488 1.473 1.315 1.187 1.081 0.992 0.917 0.852 0.796 0.747 0.703 0.665 0.630 0.599 0.570 0.544 0.521 0.499 0.479 0.461 0.444 0.428 0.413 0.400 0.387 0.375 1.128 1.007 0.909 0.828 0.760 0.703 0.653 0.610 0.572 0.539 0.509 0.483 0.459 0.437 0.417 0.399 0.383 0.367 0.353 0.340 0.328 0.317 0.306 0.297 0.287 0.860 0.768 0.693 0.632 0.580 0.536 0.499 0.466 0.437 0.411 0.389 0.369 0.350 0.334 0.319 0.305 0.292 0.281 0.270 0.260 0.251 0.242 0.234 0.226 0.219 -100 0.651 0.581 0.525 0.478 0.439 0.406 0.378 0.353 0.331 0.312 0.295 0.279 0.265 0.253 0.241 0.231 0.221 0.212 0.204 0.197 0.190 0.183 0.177 0.171 0.166
provide additional margin carrier-to-dc term large input signals. provide more range fine correction upper threshold decreasing total input power block small input signals. (This described more detail Fine Correction section.)
FOURTH-ORDER CASCADED INTEGRATOR COMB FILTER (CIC4)
CIC4 processing stage implements fixed-coefficient decimating filter. reduces sample rate signal allows subsequent filtering stages implemented more efficiently. input CIC4 driven 19-bit relinearized data maximum input rate clock rate). CIC4 decimation ratio, MCIC4, programmed from (all integer values). CIC4 scale factor, SCIC4, programmable unsigned integer between serves control attenuation data into CIC4 stage increments such that CIC4 does overflow. Because this scale factor steps, CIC4 filter gain between -6.02 when properly scaled. best dynamic range, SCIC4 should smallest value possible (lowest attenuation) without creating overflow condition. ceil
Gain
SCIC
Rev. Page
AD6650
Table enables calculation upper bound decimation ratio (MCIC4), given desired filter characteristics input sample rate. Figure shows phase response filter over range ±100 after time delay during which ~13.449 input samples filter have been removed. input rate same 2.16 from above GSM/EDGE configuration. Examining plot shows that filter exactly phase linear. (Linear phase would flat after time delay been removed). seen, however, that phase response over band interest essentially perfect. From -100 +100 kHz, phase distortion ~0.056° rms. This phase response several orders magnitude below analog analog filter phase distortions.
0.001
INFINITE IMPULSE RESPONSE (IIR) FILTER
filter AD6650 seventh-order low-pass filter with infinite impulse response. This filter cannot bypassed always performs decimation seen from Z-transform, filter gain -6.02 accommodate signal peaking within structure. designed free limit cycles unconditionally stable. filter described Z-transform coefficients shown following equation:
IIR(
PHASE RESPONSE (Degrees)
10-4
10-4
PHASE RESPONSE
where: 0.046227 0.278961 0.76021 1.208472 0.12895 0.254698 1.026276 Figure shows magnitude response filter typical GSM/EDGE case where ADCs sampling filter decimating generate 2.16 symbol rate) input rate IIR.
RESPONSE
10-4
10-4
03683-024
-0.001 -100
CHANNEL (kHz)
Figure Phase Response
COEFFICIENT FILTER
final signal processing stage sum-of-products decimating filter with programmable coefficients (see Figure 24). data memories I-RAM Q-RAM store Ntaps taps) most recent complex samples from filter with 23-bit resolution. coefficient memory, CMEM, stores coefficients with 20-bit resolution. every MHz) cycle, calculated using same coefficients. output consists 16-bit 24-bit data.
I-RAM
C-RAM
COARSE SCALE
-100 -110 -120
03683-023
Q-RAM
WORD
Figure Block Diagram
Decimation Register
Each channel decimate data rate factor decimation register 3-bit register. decimation stored Address 0x18 form MRCF input rate fSAMPIIR.
1000
-800
-600
-400
-1200
-1000
FREQUENCY (MHz)
Figure Frequency Response
-200
1200
Rev. Page
03683-025
AD6650
Decimation Phase Register
AD6650 uses value stored this register preload counter. Therefore, instead starting from counter loaded with this value, thus creating time offset output data. This data stored Address 0x19 3-bit number. Time delays achieved even units input rate, which typically symbol time GSM.
coefficient offset register used purposes. main purpose allow multiple filters loaded into memory selected simply changing offset. other contribute symbol timing adjustment. desired filter length padded with ends, starting point adjusted form slight delays time filter computed with reference high speed clock. This allows vernier adjustment symbol timing. Coarse adjustments made with decimation phase. output rate this filter (fSAMPR) determined output rate stage MRCF.
SAMPR SAMPIIR
Filter Length
maximum number taps this filter calculate, Ntaps, given Equation value Ntaps written channel register within AD6650 Address 0x1B.
taps SAMPIIR
where: fCLK external frequency oscillator. MRCF filter decimation rate. fSAMPHR input rate RCF. coefficients located Addresses 0x40 0x6F interpreted 20-bit twos complement numbers. When writing coefficient RAM, lower addresses multiplied relatively older data from IIR, higher coefficient addresses multiplied relatively newer data from IIR. coefficients need symmetric, coefficient length, Ntaps, even odd. coefficients symmetric, both sides impulse response must written into coefficient RAM. stores data from into RAM. assigned data, assigned data. When triggered calculate filter output, starts multiplying oldest value data first coefficient, which pointed coefficient offset register (Address 0x1A). This value accumulated with products newer data-words multiplied subsequent locations coefficient until coefficient address RCFOFF Ntaps reached.
Table Three-Tap Filter
Coefficient Address (Ntaps Impulse Response h(0) h(1) h(2) Data N(0) oldest N(1) N(2) newest
(10)
where: fSAMPIIR input rate RCF. MRCF filter decimation rate.
Output Scale Factor Control Register
Address 0x1C used configure scale factor filter. This 2-bit register used scale output data increments. possible output scales range from AD6650 uses recirculating multiply accumulator (MAC) compute filter. This accumulator three bits growth, allowing output accumulator times large input signal. achieve best filter performance, coefficients should large possible without overflowing accumulator. gain filter merely coefficients; therefore, normal steady state signals, coefficients must less than coefficients slightly less, very rare transient events overflow accumulator. prevent this, absolute values coefficients should less than then impossible filter overflow. filter 4-position output accumulator. This chooses which bits propagated output adjusts rounding appropriately. This viewed gain block that varied steps controlled 2-bit scale register. resulting gain (RCFgain) then represented following equation:
RCFgain Coef RCFScale (11)
where RCFScale value scale register.
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AD6650
COMPOSITE FILTER
total gain digital filters calculated with Equation must less than equal dB). Typically, coefficient gain scaled compensate gain IIR, scale factor
exists because high-pass filter very bandwidth, only track very slow changes (over hours, days, weeks) offsets device. other hand, higher bandwidth, able estimate properly presence large baseband signal. Given assumption that signal interest uniformly distributed across frequency, processing gain equation used provide starting point system optimization. Enough processing gain must guaranteed estimate valid minimum signal case. This typically depends baseband signal processing particular system. GSM/EDGE, which distributed over about single sideband (SSB), this implies that bandwidth must between SSB. every that signal power increases, more processing gain required; therefore, bandwidth needs decrease factor more.
Gain
SCIC
Coef RCFScale
(12)
where: Gain gain digital filters. MCIC4 CIC4 decimation ratio. SCIC4 CIC4 scale factor. RCFScale value scale register. individual responses CIC4 filters, along with composite response filters, shown Figure
CIC4 RESPONSE AD6650 DIGITAL COMPOSITE RESPONSE FILTER RESPONSE
(13)
-100 -110 -120 -1.98 -1.46 -0.94 -0.43 0.61 FREQUENCY (MHz) 1.13 1.65
03683-026
where: channel filter bandwidth. fHPF bandwidth. case GSM, simple well suited this problem because signal power vary more from time slot time slot total dynamic range more. large time slot would excite impulse response HPF, possibly resulting peak occurring later when small time-slot present. provide more optimal correction, AD6650 adaptively adjusts bandwidth based signal power. signal level decreases, bandwidth increases. Conversely, signal level increases, bandwidth decreases. AD6650 implements this high-pass filter form accumulator that integrates number samples output produces estimate after samples accumulated. estimated then removed from signal path simple subtraction. subtraction clamped avoid overflow problems. bandwidth varied changing integration time (equivalent SYNC filter decimation integrator). integration time varied based output peak detector circuit according process described Peak Detector Correction Ranging section.
2.17
Figure Composite Digital Response with Rate
FINE CORRECTION
fine correction block AD6650 lies between serial output port. While coarse correction block front channel included provide onetime correction startup rare intervals when commanded user, fine correction block intended continuously track changes offsets analog front end. achieve this efficiently under varying signal conditions, this estimation process adaptive.
Adaptive Correction Filter
typical applications where offsets corrected, high-pass filter (HPF) used remove some small percentage input signal power. This approach straightforward works well when input signal relatively constant power when bandwidth extremely small range) content does vary. general, more input signal power vary, narrower bandwidth high-pass filter must avoid frequency transients filter that larger than smallest expected signals. fundamental trade-off
PEAK DETECTOR CORRECTION RANGING
peak detector AD6650 always looks maximum signal power present data path. paths treated totally independently correction circuitry because analog paths guaranteed match. first sample that arrives rectified preloaded into peak detector. control counter minimum period
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AD6650
control register setting. every input sample, peak detector determines sample larger than currently held sample, peak detector updated. contents peak detector then examined. they below lower threshold, control counter counts down when reaches updates estimate, resets accumulator, reloads peak detector with newest input sample magnitude. peak detector value above upper threshold correction, estimate currently being calculated discarded. When signal drops below upper threshold, calculation estimate begins. current estimate held, last known content continues removed. paths AD6650 each treated independently correction circuitry because analog paths guaranteed match, separate estimates need kept each. Separate peak detectors, estimate accumulators, estimate subtractors, control counters implemented each these paths. digital word from peak detector indicates that desired signal between lower threshold upper threshold, fine correction circuit normal mode operation. this mode, control counter starts with minimum period reloaded with minimum period every time peak detector output words increment This errs side caution ensures that correction integrates long enough obtain valid estimate. smaller integrations preferred, minimum period decreased lower threshold raised.
integration period given Equations factor exponent shows that peak signal power increases, integration time increased factor This decreases bandwidth estimation filter, thus providing additional processing gain estimation term. When desired signal power equals upper threshold,
Period Ceil Upper Threshold Lower Threshold 6.02
(14)
Peak Detector
peak detector always stores input sample with largest magnitude. absolute value every input sample compared what currently peak detector's holding register. only exception when control counter reaches this point, offset estimate updated peak detector current input magnitude. output each peak detectors then encoded into digital word that represents signal power steps relative full scale (FS).
When desired signal power less than upper threshold,
Period Ceil Desired Signal Power Lower Threshold 6.02
(15)
where Min_Period, Upper_Threshold, Lower_Threshold register-programmable values. calculate time required fine correction converge following equation: Fine Converge TSYM (16)
Accumulator
accumulator accumulates 24-bit samples input from filter until control counter reaches this time, estimate holding register updated, accumulator directly loaded with input sample begin work next estimate.
where: TSYM output symbol rate AD6650. Fine_DC_Converge expressed minutes, application with oversampling, 3.69 10-6.
Control Counter
This counter controls update correction block based peak detector value input control registers. following three conditions possible. digital word from peak detector indicates that desired signal below lower threshold, counter merely cycles through minimum period.
SMALL SIGNAL LARGE SIGNAL
FREQUENCY
Figure Adaptive Bandwidth Filter
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digital word from peak detector indicates that desired signal above upper threshold, control counter held minimum period value does count down; therefore, update made. When signal returns below upper threshold, this counter resumes counting.
AD6650
USER-CONFIGURABLE BUILT-IN SELF TEST (BIST)
AD6650 includes BIST assess digital functionality. This feature verifies integrity main digital signal paths AD6650. Each BIST register independent, meaning that each channel tested independently same time. BIST thorough test selected AD6650 digital signal path. With this test mode, possible internal pseudorandom generator produce known test data. signature register follows fine correction block. This register read back compared known good signature. known good signature matches register value, channel fully operational. error detected, each internal block bypassed another test debug fault. paths tested independently. following steps perform this test: Reset AD6650. Program desired AD6650 channel parameters desired application (these parameters include decimation rates, scalars, coefficients). Also ensure that start holdoff counter nonzero value. Register 0xA, (PN_EN). Register 0x21, (fine BIST). Start and/or channels with microprocessor write (Soft_SYNC) pulse SYNC (Pin_SYNC). Wait least Read four BIST registers compare values known good device. This ensures that AD6650 programmed correctly that each channel functioning correctly. internal reference voltage. After band select, normal action resumes. nominal value MHz/V, where sensitivity. Immediately following programmable half-rate divider that settings divide-by-2, -2.5, -3.5, divide-by-8. This function divides frequency down four times frequency effectively extends tuning range VCO. half-rate divider thought single lower frequency with frequency range 1040 MHz. Autocalibration selects both operating band oscillator amplitude ensure peak operating performance across entire frequency range. half-rate divide setting also selected part calibration. Autocalibration performed whenever Register (the test mode latch) written; therefore, other registers should first, Register should written last. This true whenever programming portion synthesizer because need recalibrate itself, depending changes made registers.
integer-N type consists programmable reference divider (R-divider), prescalar feedback divider (N-divider), phase-frequency detector (PFD), charge pump. output charge pump drives external loop filter, which turn drives input VCO.
Divider
14-bit R-divider divides down input clock frequency produce reference frequency phase-frequency detector. Although division ratios from 16,383 allowed, maximum update rate MHz. selected update rate subsequent charge pump determines spurious performance synthesizer; therefore, reference frequency should optimal placement spurs.
SYNTHESIS
AD6650 fully integrated quadrature synthesizer consisting voltage-controlled oscillator (VCO) phaselocked loop (PLL). Together these blocks generate quadrature signals demodulators. Figure shows block diagram synthesis block. Besides usual VCO, there also programmable half-rate divider (Div-X fixed divide-by-4 quadrature divider that produces final signals).
Prescalar Feedback Dividers
dual modulus prescalar (P/P feedback dividers bits bits, respectively) combine provide wide ranging N-divider feedback loop. feedback division Including final quadrature divider (divide-by-4), frequency given (17)
generates on-chip signal range GHz. only external component required bypass capacitor low-dropout (LDO) voltage regulator used power tank core. uses overlapping bands achieve wide tuning range while maintaining excellent phase noise spurious performance. During band selection, which takes cycles, VTUNE disconnected from output loop filter connected
where: local oscillator frequency. fCLK external frequency oscillator. 13-bit divider 8191). 5-bit swallow divider 31). input reference divider 16,384).
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AD6650
fCLK/4R term combines effects reference divider final quadrature divider, determines frequency spacing synthesizer. typical application, fCLK result update rate, which sets frequency spacing desired kHz. However, this also places spurs offsets multiples, which might degrade interferer/blocker performance.
CHARGE PUMP
R-DIVIDER
CLR1
PROGRAMMABLE DELAY
fCLK
R-DIV 14-BIT
fREF
CHARGE PUMP
EXTERNAL LOOP FILTER DIV-X DIV-4
ADP2 ADP1
IOUT QOUT
N-DIVIDER
CLR2
DOWN
CPGND
N-Counter B-DIV 13-BIT A-DIV 5-BIT
PRESCALER /P+1
R-DIVIDER
N-DIVIDER
03683-028
Figure Circuit
OUTPUT
Figure Simplified Schematic Timing (Locked)
Charge Pump
phase-frequency detector (PFD) takes inputs from R-divider N-divider produces output proportional phase frequency difference between them. includes programmable delay element, which controls width antibacklash pulse. This pulse ensures that there dead zone transfer function minimizes reference spurs.
AD6650 includes on-chip low-dropout (LDO) voltage regulator that supplies other sections PLL. 0.22 bypass capacitor required VLDO output ensure stability. This employs same technology used anyCAP® line regulators from Analog Devices, Inc., making insensitive type capacitor used. Driving external load from VLDO output supported.
Loop Filter
final element synthesizer external loop filter, which generally first- second-order low-pass filter. filter like shown Figure recommended provide good balance stability, spurs, phase noise. This particular filter optimized update rate MHz.
LOOP/RELINEARIZATION
consists three gain control loops: slow loop, fast attack (FA) loop, fast decay (FD) loop.
POWER DETECTOR DECIMATION FILTERS RE-LINEARIZTION FORMATTER
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UPPER THRESHOLD
AD6650
1.0µF
56000pF
3900pF
VLDO
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Figure Loop Filter Circuit
STATE MACHINE
FAST LOOP DETECTORS
SLOW LOOP, SIGNAL LEVEL SIGNAL PLUS BLOCKER LEVEL
Figure Loop Block Diagram
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AD6650
Slow Loop
slow loop main loop associated with loop gain parameter. This parameter controls rate change gain should always less than determine loop gain, Equation should used. AGCLoopGain Mantissa Exponent (18)
Fast Decay (FD) Loop
loop fast loop that increases gain when signal falls below threshold during deep channel fade ramp down. fast loop accomplishes this task comparing peak signal-plus-blocker level output (which includes signal blockers that pass through filter) with programmable level (SPB_level) that determines when this loop activated. SBP_level default value dBFS. When wideband signal below level, loop activated. This loop overrides slow loop programmable step size (default 0.094 programmable peak detect period (defaults four samples 1.08 MHz).
UPPER THRESHOLD1 (OVER LOAD PROTECTION) ~-1dBFS OPERATIONAL RANGE -6dBFS REQUESTED LEVEL2
where: KMantissa loop gain mantissa. Values range from KExponent loop gain exponent. Values range from loop gain value increases, speed response loop increases; loop gain value decreases, does speed response loop. slow loop attempts maintain signal entering given level, referred requested level. This level specified dBFS between dBFS dBFS 0.094 steps) converter resolution. default value -6.02 dBFS. slow loop peak detection function, period which user. This period should symbol period greater prevent loop from gaining envelope EDGE signal. This detection period works because peak detector's operation based dB(max(|I|, |Q|)); therefore, samples reflected back into quadrant plane. sampling frequency, symbol period clock cycles; therefore, obtain peak detector period that symbol period, peak detector period should minimum samples. following equation also used: Peak Samples SAMP (19)
-46dBFS LOWER THRESHOLD3 (DEEP FADE PROTECTION)
ADJUSTABLE LEVEL, WITH PROGRAMMABLE STEP SIZE ADJUSTABLE PERIOD. ADJUSTABLE LEVEL, LOOP GAIN (<1), HYSTERESIS, INTEGRATION PERIOD. 3ADJUSTABLE LEVEL, ADJUSTABLE STEP SIZE.
Figure Thresholds
SERIAL OUTPUT DATA PORT
AD6650 configurable serial output ports (SDO0 SDO1). Both ports must identically configured programmed using same control register. ports share common SFDS, SCLK, connection external ASIC DSP; therefore, outputs cannot programmed independently.
where: fSYM 270.833 (GSM symbol rate). fSAMP MHz.
Serial Output Data Format
AD6650 utilizes twos complement data format with selectable serial data-word length bits. data shifted device MSB-first format.
Fast Attack (FA) Loop
loop utilizes analog threshold detector that prevents overdrive analog signal path. situation that could potentially overdrive ADC, loop takes over from slow loop decreases gain front end. step size used loop programmable between 1.504 0.094 steps. loop also counter, which programmable between When initialized count loop decreases gain count clock cycles when threshold crossed.
Serial Data Frame Sync
serial data frame sync (SDFS) signals start serial data frame. channel data becomes available output AD6650's filters, this data transferred into serial data buffer. internal serial controller initiates SDFS next rising edge serial clock. AD6650, there three modes which frame sync generated, which described SDFS Modes section.
Configuring Serial Ports
Both serial output ports must function master serial ports. serial master provides SCLK SDFS outputs. Serial Ports must programmed masters setting serial control register high.
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AD6650
Serial Port Data Rate
SCLK frequency defined Equation SCLK SDIV (19)
SCLK SDFS MINIMUM WIDTH SCLK
tDSO
SDFS
where: fCLK frequency master clock AD6650 channel. SDIV serial division word channel. SDIV Serial Port programmed Internal Control Register 0x21. Valid SDIV values between corresponding divide ratios between
FIRST DATA AVAILABLE FIRST RISING SCLK AFTER SDFS GOES HIGH
Figure Timing Serial Output Port
SCLK
SCLK output AD6650. outputs switched rising edge SCLK. SDFS sampled falling edge SCLK. This allows AD6650 recognize SDFS time initiate frame next SCLK rising edge. maximum speed this port MHz.
Serial Output Frame Timing
SDFS signal transitions high signal start data frame. next rising edge SCLK, port drives first serial data pin. falling edge SCLK subsequent rising edge then used sample data until required number bits received (determined serial output port word length). ability count bits, identify when complete frame received.
serial data output. Serial output data shifted rising edge SCLK. next SCLK rising edge after SDFS, data from channel shifted. every subsequent SCLK edge, piece data shifted until last data shifted out. last data shifted data from channel. three-stated when serial port outside time-slot. This allows AD6650 share SDIN with other AD6650s other devices.
Serial Port Timing Specifications
Figure Figure indicate timing required AD6650 serial port.
tSCLK tSCLKH
SCLK
SDFS
SDFS serial data frame sync signal. SDFS configured output. SDFS sampled falling edge SCLK. When sampled high, chip functions serial master. this mode, AD6650 responsible generating serial control data. Four modes that operation Channel Address 0x21,
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tSCLKL
Figure SCLK Timing Requirements
tDSCLKH tSCLKH
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Serial Word Length
SCLK
tSCLKL
Figure SCLK Switching Characteristics (Divide-by-1)
tDSDO
SCLK
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Address 0x21 determines length serial word this each word bits wide bits bits this serial words bits wide.
Figure Serial Output Data Switching Characteristics
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IMSB
IMSB1
AD6650
SDFS Modes
mentioned Serial Data Frame Sync section, there three modes operation. Setting Address 0x21 high indicates that Input Channel data output SDO0 Input Channel data output SDO1. this condition, there three modes operation. (There technically four modes, Mode Mode same). Mode Mode (Address 0x21, 6-5:00; 7:1): SDFS valid complete clock cycle prior data shift. This single pulse valid Output Channels SDO0 SDO1. next clock cycle, AD6650 begins shifting digitally processed data stream. Depending precision serial configuration, either bits bits data shifted out, followed bits bits data. Mode (Address 0x21 Bits 6-5:10; 7:1): Because both SDO0 SDO1 used, SDFS pulses high clock cycle prior data also pulses high clock cycle prior data each corresponding input channel. this mode, there SFDS pulses each output channel. Mode (Address 0x21 Bits 6-5:11; 7:1): SDFS high while valid bits being shifted. SDO0, SDFS remains high bits bits data, followed bits bits data corresponding Input Channel SDO1, SDFS remains high bits bits data, followed bits bits data corresponding Input Channel SDFS goes high complete clock cycle before first shifted AD6650.
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AD6650 APPLICATIONS INFORMATION
REQUIRED SETTINGS START-UP SEQUENCE CORRECTION
startup, fine correction block take several minutes converge good estimate, especially large signal present input. improve this convergence without run-time trade-offs, two-step start-up process. first step configure fine correction block with parameters shown Table freeze that fine correction responds after coarse correction updated. same time, minimum period small value, such This guarantees quicker convergence because minimum period smaller, resulting smaller integration period. Also, setting registers described Table subsequently programming AD6650 ensures that mixer powered down during power-on calibration avoid signals with large content from interfering with estimation component from analog path. After ~500 freeze (Address 0x0B, written low. correction then converges begins removing offset. desired, minimum period then larger value. mixer disabled during power-up using AutoCal control register recommended, approximately suppression achieved, user must guarantee that significant content present frequency that will translated enhanced performance desired from coarse correction, switch other device used shut input AD6650 until correction been completed.
Overall Correction Performance
With recommended settings, correction performance approximately -120 dBFS better small signals. Once signal large enough trip loop, component also rises; however, this component been shown always below signal interest. Therefore, carrier-todc ratio degrades small signals. additional details correction registers, associated descriptions Register section.
CLOCKING AD6650
AD6650 encode signal must high quality, phase noise source prevent degradation performance. AD6650 clocked with single-ended signal, must ac-coupled ground. optimum performance, AD6650 must clocked differentially. encode signal should ac-coupled into pins transformer capacitors. These pins biased internally require additional bias. Figure shows preferred method clocking AD6650. clock source (low jitter) converted from single-ended differential using transformer. back-to-back Schottky diodes across secondary transformer limit clock excursions into AD6650 approximately differential. This helps prevent large voltage swings clock from feeding through other portions AD6650 limits noise presented encode inputs.
CLOCK SOURCE T1-4T
0.1µF
AD6650
0.01µF
HSMS2812 DIODES
Figure Crystal Clock Oscillator-Differential Encode
Table Correction Register Recommendations
Description AutoCal Control Register AutoCal Control Register AutoCal Control Register AutoCal Control Register Upper Threshold Lower Threshold Minimum Period Freeze Channel Address 0x22 0x22 0x22 0x22 0x0B 0x0B 0x0B 0x0B Value Enabled Power down DACs startup Enabled Sync ADCs Enabled
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AD6650
Another option ac-couple differential ECL/PECL signal encode input pins shown Figure device that offers excellent jitter performance MC100EL16 device from same family) from Motorola.
0.1µF ECL/ PECL 0.1µF
03683-034
EXTERNAL REFERENCE
reference should connected shown Figure achieve results specified this data sheet.
AIN/BIN AIN/BIN REFT 0.1µF CHANNEL CHANNEL CORE REFB 0.1µF VREF 0.1µF 10µF RINT SELECT LOGIC 0.5V 0.1µF 10µF
AD6650
Figure Differential Encode
VREF
DRIVING ANALOG INPUTS
with most high speed, high dynamic range devices, analog input AD6650 differential. Differential inputs allow much improvement performance on-chip because signals processed through attenuation gain stages. Most improvement result differential analog stages that have high rejection even-order harmonics. Differential inputs also beneficial level. First, differential inputs have high common-mode rejection stray signals, such ground power noise, good rejection common-mode signals, such local oscillator feedthrough. AD6650 analog input voltage range offset from ground resistor network input properly biases followers maximum linearity range. Therefore, analog source driving AD6650 should ac-coupled input pins. input resistance AD6650 input voltage range differential. This equates full-scale input power. recommended method driving analog input AD6650 balun.
J101 C101 47000pF T101 T102 C103 47000pF R101 68.9 AIN/BIN
03683-035
REFGND
Figure Reference Connection
POWER SUPPLIES
Care should taken when selecting power source. Linear supplies strongly recommended. Switching supplies tend have radiated components that received AD6650. Each power supply pins should decoupled closely package possible using chip capacitors. AD6650 separate digital analog power supply pins. analog supplies denoted AVDD, digital supply pins denoted DVDD. Although analog digital supplies tied together, best performance achieved when supplies separate because fast digital output swings couple switching current back into analog supplies. Note that AVDD DVDD must held within
C102 47000pF AIN/BIN
DIGITAL OUTPUTS
recommended that digital outputs drive series resistor (for example, minimize capacitive loading, number gates each output should limited. series resistors should placed close AD6650 possible limit amount current that flow into output stage. These switching currents confined between ground DVDD pin. Also note that excessive capacitive loading increases output timing invalidate timing specifications.
Figure Balun-Coupled Analog Input Circuit
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RINT
AD6650
GROUNDING
optimum performance, highly recommended split ground between analog digital grounds. AGND should connected analog ground board, DGND should connected digital ground board. minimize potential noise coupling, highly recommended place multiple ground return traces vias such that digital output currents flow back toward analog front end, instead routed quickly away from AD6650. This accomplished simply placing substantial ground connections directly back supply point between analog front digital outputs. Judicious ceramic chip capacitors between power supply ground planes also helps suppress digital noise. layout should incorporate enough bulk capacitance supply peak current requirements during switching periods.
Start with Soft_SYNC
AD6650 includes ability synchronize channels chips under microprocessor control. start holdoff counter (Address 0x14), conjunction with SYNC (External Memory Address allows this synchronization. start holdoff counter delays start synchronization channel(s) value (number AD6650 CLKs). following method synchronize start channel microprocessor control: appropriate channels sleep mode. hard reset AD6650 (RESET taken low) puts both channels into sleep mode. Enable Channel and/or Channel (External Memory Address Write start holdoff counter(s) (Address 0x14) appropriate value (greater than less than 65,535). Program other registers AD6650 that already set. Write Soft_SYNC high (External Memory Address When Soft_SYNC goes high, start holdoff counter begins count down using AD6650 signal after divider. When start holdoff counter reaches count selected channel(s) activated.
LAYOUT INFORMATION
multilayer board should utilized achieve optimal results. highly recommended high quality ceramic chip capacitors decouple each supply ground directly device. arrangement AD6650 facilitates ease implementation high frequency, high resolution design practices. digital outputs opposite side package from analog inputs isolation purposes. Care should taken when routing digital output traces. prevent coupling through digital outputs into analog portion AD6650, minimal capacitive loading should placed these outputs. layout encode circuit equally critical. noise received this circuitry results corruption digitization process lower overall performance. encode clock must isolated from digital outputs analog inputs.
Start with SYNC
AD6650 SYNC that used provide synchronization between AD6650s external hardware resolution sample cycle. This accomplished providing 1-CLK-cycle-wide pulse SYNC when edge-sensitive register (External Memory Address which useful when FPGA other external hardware operating rate AD6650. Synchronization also accomplished setting edge-sensitive high that SYNC input rising edge sensitive, which useful when external hardware operating clock that much slower than AD6650 asynchronous
CHIP SYNCHRONIZATION
AD6650 designed allow synchronization multiple AD6650s within system. AD6650 synchronized with either microprocessor write (Soft_SYNC) pulse SYNC (Pin_SYNC). first sync event starts device, subsequent sync events resynchronize filters AD6650. using start holdoff counter, possible align phase AD6650 other devices. synchronize AD6650 with external hardware, Start with SYNC section.
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AD6650 MICROPORT CONTROL
AD6650 8-bit microprocessor port. microport interface multimode interface that allows flexibility when dealing with host processor. There modes operation: Intel nonmultiplexed mode (INM) Motorola nonmultiplexed mode (MNM). mode selected based host processor which mode best suited that processor. microport 8-bit data [7:0]), 3-bit address [2:0]), three control lines (CS, WR), status (DTACK RDY). functionality control signals status line change slightly depending selected mode. Refer timing diagrams Figure through Figure descriptions Programming Modes, Intel Nonmultiplexed Mode (INM), Motorola Nonmultiplexed Mode (MNM) sections details operation each mode.
ACCESS CONTROL REGISTER (ACR)
register auto-increment bit. this register, described Channel Address Register (CAR) section, increments value after every access channel. This allows blocks address space, such coefficient memory, initialized more efficiently. register unused must written low. register instruction bits that allow multiple AD6650s receive same write access. instruction bits allow single multiple four) AD6650 chip(s) configured simultaneously. There seven possible instructions, which defined Table where represents disregarded values digital decoding. multiple AD6650 chips using same line, readback valid because potential contention. Therefore, device readback capability desired, lines should separated individual control. facilitate device debug verification, separate lines each AD6650 recommended. register address bits that decode which channel accessed. Because channels AD6650 cannot programmed independently, these bits should
EXTERNAL MEMORY
external memory used gain access channel address space. 8-bit data address buses used eight registers shown Table These registers collectively referred external interface registers because they control access channel address space global chip functions. each register described Table
Table External Memory
Addr. (Hex) Name Access Control Register (ACR) Definition auto-increment reserved (write low) 5-2: instruction [3:0] 1-0: [9:8] 7-0: [7:0] sync enable correction sync enable sync enable 3-1: reserved issue Soft_SYNC first sync only enable edgesensitivity 3-1: reserved enable Pin_SYNC 7-4: reserved status Channel enable Channel status Channel enable Channel 7-4: reserved 3-0: [19:16] 15-8: [15:8] 7-0: [7:0]
CHANNEL ADDRESS REGISTER (CAR)
register represents 8-bit internal address each channel. auto-increment this value incremented after every access register, which turn accesses location pointed this address.
Channel Address Register (CAR) Special Function Register (SF2)
SPECIAL FUNCTION REGISTERS
AD6650 three special function registers, SF0, SF1, SF2, that control synchronizing enabling channels. controls channel enabling, controls Pin_SYNC, controls Soft_SYNC. SF0, allow Channel Channel respectively, exit sleep mode method selected SF1. read-only bits indicate whether Channel Channel respectively, active. indicates that channel active, indicates that active. Bits through unused. SF1, both channels wait pulse appear SYNC before exiting sleep mode; otherwise, channels assume soft start desired wait start holdoff counter issue sync. When set, both channels ignore subsequent attempts resync once they have exited sleep mode.
Special Function Register (SF1)
Special Function Register (SF0)
Data Register (DR2) Data Register (DR1) Data Register (DR0)
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AD6650
Table Microport Instructions
Instruction 0xxx 1000 1001 1100 1101 1110 1111
READ/WRITE CHAINING
microport AD6650 allows multiple accesses while held tied permanently microport shared with additional devices). user access multiple locations pulsing line changing contents external 3-bit address bus. Access external registers listed Table accomplished modes using MODE inputs. access modes mode mode. These modes controlled MODE input (MODE INM, MODE MNM). control access type each mode.
Comment chips obtain access. chips with Chip_ID [1:0] obtain access.1 chips with Chip_ID [1:0] obtain access.1 chips with Chip_ID [1:0] obtain access.1 chips with Chip_ID [1:0] obtain access.1 chips with Chip_ID [1:0] obtain access.1 chips with Chip_ID [1:0] obtain access.1
[9:8] bits control which channel decoded access.
SF2, prompts startup block start holdoff counter from value programmed start holdoff counter control register issue sync when this task complete. Bits used enable syncs individual blocks channels.
PROGRAMMING MODES
AD6650 programmed using several different modes. These modes include microport modes, mode mode. programming mode selected setting MODE pins. Table identifies MODE pins select desired programming mode.
Table Programming Modes
MODE [2:0] Comment Microport Intel nonmultiplexed mode Microport Motorola nonmultiplexed mode Reserved Reserved Reserved Reserved Reserved Reserved
DATA ADDRESS REGISTERS
External Addresses [2:0] form Data Registers DR2, DR1, DR0, respectively. internal data-words have widths that less than equal bits. Access triggers internal access AD6650 based address indicated CAR. Therefore, during writes internal registers, must written last. this point, data transferred internal memory location indicated [9:0]. Reads performed reverse sequence. Once address set, must first data register read initiate internal access. only bits wide. Data written upper bits this register ignored. Likewise, reading from this register produces only LSBs.
WRITE SEQUENCING
Writing internal location achieved first writing upper bits address into (these bits should low). Bits select chips access indicated above. then written with lower eight bits internal address does matter written before ACR, long both written before internal access). must written first because write Data Register triggers internal access. must always last register written initiate internal write.
Intel Nonmultiplexed Mode (INM)
Setting mode word bits places AD6650 mode. access controlled user with (DS), (RW) inputs. (DTACK) signal produced microport communicate user that access been completed. (DTACK) goes start access released when internal cycle complete. Figure Figure mode read write timing.
Motorola Nonmultiplexed Mode (MNM)
Setting mode word bits places AD6650 mode. access type controlled user with (RD), (WR) inputs. DTACK (RDY) signal generated microport signal user that access been completed. DTACK (RDY) goes when internal access complete returns high after (RD) deasserted. Figure Figure mode read write timing.
READ SEQUENCING
Reading from microport accomplished same manner. internal address same write. read from activates internal read; therefore, must read first initiate internal read followed reads from DR2.
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AD6650
JTAG BOUNDARY SCAN
AD6650 supports subset IEEE Standard 1149.1 specification. details standard, IEEE Standard Test Access Port Boundary-Scan Architecture, IEEE-1149 publication. AD6650 five pins associated with JTAG interface. These pins, listed Table used access on-chip test access port. input JTAG pins pull-ups except TCLK, which pull-down.
Table Boundary Scan Test Pins
Mnemonic TRST TCLK Description Test access port reset Test clock Test access port mode select Test data input Test data output
Bypass (2'b11)
bypass instruction allows remain normal functional mode selects 1-bit bypass register between TDO. During this instruction, serial data transferred from without affecting operation
Sample/Preload (2'b01)
sample/preload instruction allows remain normal functional mode selects boundary-scan register connected between TDO. boundary-scan register accessed scan operation take sample functional data entering leaving Also, test data preloaded into boundary-scan register before extest instruction.
Extest (2'b00)
extest instruction places into external boundarytest mode selects which boundary-scan register connected between TDO. During this operation, boundary-scan register accessed drive test data off-chip boundary outputs receive test data off-chip from boundary inputs.
AD6650 supports three codes, listed Table These instructions mode JTAG interface.
Table Boundary Scan Codes
Instruction Bypass Sample/Preload Extest Code
BSDL file this device available. Contact Analog Devices sales representative more information.
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AD6650 REGISTER
Table Memory
Reg. (Hex) Name Clock Divider Control Register Register Register Register Clamp Control Tweak Gain Width Comment Power-up value 1'b1. Control Register Control Register Control Register Control Register Various control signals. Provides ±1.6 additional gain steps. Additional Information Code Table Table Table Table Power-up value 6'b100011 Code Code Must written 8'b00000000 Must written 8'b00000000 Must written 8'b00010001 Power-up value 2'b00 Power-up value 4'b0000 Code
Result Bypass Divide-by-2
Clamp Disable Clamp Disable Reserved Reserved Reserved Reserved Coarse Correction
Disables clamps output Channel Disables clamps output Channel Reserved. Reserved. Reserved. Must written Coarse correction control registers.
Gain (dB) +1.6 +1.4 +1.2 +0.2 -0.2 -1.2 -1.4 Result Enable clamp Disable clamp Enable clamp Disable clamp
PN_EN
Calibrate coarse correction Channel Coarse correction occurs automatically start-up AutoCal control register high. Calibrate coarse correction Channel Coarse correction occurs automatically start-up AutoCal control register high. Enables sequence generator test digital block.
Result Disabled Recalibrate
Disabled Recalibrate
Coarse Enable
Enables coarse DCC. This register must held high during start- sequence coarse correction occur.
Rev. Page
Code
Disabled Enable sequence generator Result Disabled enabled
AD6650
Reg. (Hex) Name Correction Control Upper Threshold Width Comment Fine control registers. Additional Information Power-up value 20'b00000000000000000000 Code Code
Fine upper threshold. estimation made signal above upper threshold.
Lower Threshold
Fine lower threshold. maximum range lower limit dBFS 138.46 dBFS.
Level (dBFS) dBFS -0.75 dBFS -1.5 dBFS -94.5 dBFS -95.25 dBFS dBFS -6.02 dBFS -12.04 dBFS -132.44 dBFS -138.46 dBFS Integration Time 2^30 2^31 sample period Result Update estimate Keep estimate Disabled Enabled Disabled Enabled Result Disabled Enable forced gain mode Disabled Enable fast decay loop Result Disabled Enable fast attack loop
Minimum Period
Fine integration period.
Bypass
Fine bypass.
Code
Interpolate
Fine interpolator reduces discontinuity between current estimate estimate. Fine freeze used hold current estimate.
Code
Freeze Control Force Gain
FD_Enable
Force gain specific value. This control line overrides slow loop, fast decay loop, fast attack loop when enabled. Fast decay loop enable.
Code
FA_Enable
Fast attack loop enable.
Reserved
Reserved.
Rev. Page
AD6650
Reg. (Hex) Name Control Gain Width Comment gain (dB) (0.094) gain word. This drives directly when force gain Additional Information Code Code Code Code Code
Gain (dB) 0.094 0.188 35.9 36.002 Hysteresis (dB) ±.094 ±.188 ±23.876 ±23.97 Requested Level (dBm) +3.906 +3.812 -19.8 -19.97 Loop Gain Mantissa
Control Hysteresis
hysteresis requested level. Upper hysteresis threshold requested level hysteresis. Lower hysteresis threshold requested level hysteresis. gain word does change peak measurement falls between upper lower hysteresis threshold.
Requested Level
requested level slow loop. full-scale input into AD6650 dBm.
Control Loop Gain Exponent
Loop gain (mantissa/256) Loop gain exponent (slow loop).
Reserved Loop Gain Mantissa
Reserved. Loop gain mantissa (slow loop).
Rev. Page
AD6650
Reg. (Hex) Name Control Width Comment Fast attack fast decay loop parameters. Fast decay step size. Additional Information
FD_Step
FA_Thresh
Fast attack threshold measured antialiasing filters.
FA_Count
Fast attack count. fast attack loop steps gain down FA_Step FA_Count number clock cycles.
3-0: FA_Step
Fast attack step size.
Code Code Code Code
Step size (dB) 0.094 0.188 0.564 0.658 Threshold -6.02 dBFS -3.1 dBFS -0.915 dBFS dBFS Count Step size (dB) 0.094 0.188 1.316 1.41 Samples clock cycles)
Control
Slow loop peak detector period. Code Must written 8'b00000000 Must written 7'b0000000 Code
Peak Detector Period
Signal plus blocker peak detector period slow loop; MHz; fSYM 270833; peak period (fSAMP/fSYM).
Reserved Reserved Control
Reserved. Reserved. Fast decay signal plus blocker threshold.
Threshold
Threshold dBFS -0.094 dBFS -0.188 dBFS -47.94 dBFS -48.034 dBFS
Rev. Page
AD6650
Reg. (Hex) Name Start Holdoff Counter Width Comment power-up sequence initiated with Soft_SYNC, then start holdoff counter counts down chip power-up sequence starts. invalid value. Additional Information Code 65,534 65,535 Code Code
CIC4 Decimation MCIC4
Should greater because have maximum rates MHz/12.
CIC4 Scale
Controls attenuation data into CIC4 stage increments. This register range which supports decimations from according Equation
Count 65,534 65,535 Decimation Scale Factor
Scale
Control
Sync mask.
Decimation Register
Decimation
MRCF
Decimation Phase
Phase from MRCF
PRCF
Coefficient Offset CORCF
Range taps.
Code Code Code Code
Results Disabled Enabled Decimation Phase Offset
Rev. Page
AD6650
Reg. (Hex) Name Taps Width Comment Additional Information Code Code
NTaps
Scale
gain adjust prevent coefficients from clipping MAC. 16-bit data available, I/DATA_I. 16-bit data available, Q/DATA_Q. 16-bit data available, I/DATA_I. 16-bit data available, Q/DATA_Q. Power-up value 9'bxxxxx0xxx make serial slave. Data available through BIST registers when high. Port data serial output select.
Taps Scale Factor
BIST BIST BIST BIST Serial Control Fine Data BIST Data Serial Ouput Select
Code
I_SDFS Control
Serial port control functions.
SOWL SDIV [2:0]
Serial output word length. Serial master. Serial divider.
Results SDO0 data SDO1 data pulse pulses pulses High SDO0 valid 16-bit words 24-bit words Serial slave Serial master Divide-by-1 Divide-by-8
AutoCal Control Reserved Reserved Power-Down Disable Enable
calibration sequence control registers. Power-up value 4'b0000. Reserved. Reserved. Power down DACs during powerup sequence calibrate offset. Autocalibration enable.
Must written Must written Code
Results Power down DACs DACs Disabled Enabled
Reserved Coefficient Memory Reserved
Common coefficients Channels
Rev. Page
AD6650
REGISTER DETAILS
Table Register Control Latch
Address DB21 Register RSVD Definitions Reserved Comment Must written 0000 0111 1100 0100 0000 (MSB LSB).
Table Register Counter Latch
Address DB21 DB14 DB13 Register RSVD Definitions Reserved 14-bit reference counter, Comment Must written 0001 0100 (DB21 DB14).
Table Register Counter Latch
Address DB21 DB19 DB18 Register RSVD RSVD A5-A1 Definitions Reserved 13-bit counter Reserved 5-bit counter Comment Must written 000. programs 13-bit counter. Must written programs 5-bit counter. divide range (00000) (11111).
Table Register Reserved
Address DB21 Register RSVD Definitions Reserved Comment Must written 0001 1000 0000 0000 0000 (MSB LSB).
0x00: Clock Divider Control
clock divider control sets internal clock rate AD6650. this clock rate MSPS, internal divide-by-2 bypassed. faster clock rate desired, clock divider control should high. setting this high, internal divide-by-2 used.
0x04: Control Register [21:0]
This register reserved must written 0001 1000 0000 0000 0000 (MSB LSB).
0x05: Clamp Control [5:0]
This register either enables disables clamps output mixers. These clamps should enabled.
0x01: Control Register [21:0]
This register reserved must written 0000 0111 1100 0100 0000 (MSB LSB).
0x06: Reserved [8:0]
This register reserved must written 00000000.
0x02: Control Register [21:0]
DB13 DB0: These bits used R-counter PLL. DB21 DB14: These bits reserved must written 0001 0100.
0x07: Reserved [8:0]
This register reserved must written 00000000.
0x08: Reserved [8:0]
This register reserved must written 00010001.
0x09: Reserved [1:0]
This register reserved should written low.
0x03: Control Register [21:0]
DB0: This 5-bit register used value counter PLL. DB5: This reserved must written DB18 DB6: This 13-bit register used value B-counter PLL. DB21 DB19: These bits reserved must written 000.
Rev. Page
AD6650
0x0A: Coarse Correction Control Register [3:0]
Address coarse correction control register. used enable coarse correction with initiate calibrations Channel and/or Channel this register used initiate coarse calibrations when device running used conjunction with external switch desired. used activate internal pseudorandom noise generator, which useful looking digital filter response performing built-in self-test.
Table Coarse Correction Control Functions
Bits Description Calibrate Calibrate PN_EN CDCC enable
guideline, upper threshold should between dBFS dBFS. below dBFS, uncorrected offset from analog front coarse correction increase effective minimum period because peak detectors fine correction block ranges content well signal interest. lower threshold determines where minimum integration period used. When peak input fine correction block lower than this level, accumulators average 2Min_period samples output rate samples/symbol). When peak signal increases above this, integration periods increase factor every that signal power increases. should noted that content left after coarse correction seen fine correction peak detector causes integration period change. example lower threshold dBFS content dBFS, signal least larger; therefore, integration period least (418/6) minimum period. lower threshold near upper threshold provide constant integration period 2Min_period desired. This interval equal 2Min_period. minimum period determines integration period when peak signal power into fine correction block less than lower threshold. This used combination with lower threshold make sure there enough integration estimate small signals. Min_period period integration signal with power less than equal -96.32 dBFS 4096 samples. each 6.02 dBFS increase signal power, integration period quadruples. Min_period register programmed from valid value this register. This bypass that effectively shuts down fine correction block. When this correction performed. This enables interpolator that smooth updated estimate transition fixed interpolation 256. This linear interpolator that allows correction block gradually shift between estimate estimate avoid transients there been significant shift. disabled, shift correction values happens instantaneously, causing discontinuity signal; however, interpolator enabled, this shift occurs over samples, preventing large discontinuities. interpolator should enabled Min_period less than period samples). interpolator recommended this time, this should
0xB: Fine Correction Filter [19:0]
fine correction block used provide good correction small signals that under range loop. Address four parameters.
Table Fine Correction Filter Functions
Bits Description Upper threshold Lower threshold Minimum period Bypass Interpolator enable Freeze
upper threshold disables fine correction algorithm large input signals that could potentially contain significant content from modulated data. This should below range loop, which equal requested level should also above uncorrected level that fine guaranteed range. upper threshold should enough that content estimated while loop ranging because changing gain distorts estimate. Setting upper threshold lower also decreases effects from content signal such offset from modulated data with high correlations mobiles with feedthrough. equally important upper threshold low. upper threshold that desired signal consistently higher than this threshold, estimate, which necessary compensate power supply temperature drifts, will occur. Therefore, thorough understanding signal statistics application required.
Rev. Page
AD6650
When this freezes estimate correction resets peak detector smallest possible signal state (-138 peak signal). This way, estimated once constantly corrected. This useful debugging when estimate performed discrete predefined times. Even though upper threshold register vary between Min_period register vary between only certain combinations valid. This because growth restricted bits. Equation used determine combination values valid. combination invalid; otherwise, combination valid. Upper Threshold) Min_period) (20) These lower eight bits requested level slow loop. Setting code sets requested level dBm, which corresponds full-scale input AD6650. Setting code sets requested level -19.97 dBm.
0x0F: Control [10:0]
This 3-bit register sets loop gain exponent slow loop AD6650 AGC. values range from equation loop gain noted Loop/Relinearization section. These bits reserved should written low. This 6-bit register represents loop gain mantissa slow loop AD6650 AGC. values this register range from equation loop gain noted Loop/Relinearization section.
0x0C: Control [3:0]
force gain control register allows user force gain specific value. This control line overrides slow loop, fast decay loop, fast attack loop when enabled. setting this low, force gain control disabled. setting this high, force gain control enabled. normal operation, this should disabled. setting this high, fast decay loop enabled; setting this low, fast decay loop disabled. recommended that fast decay loop enabled normal operation. description fast decay functionality, please Loop/Relinearization section. setting this high, fast attack loop enabled; setting this low, fast attack loop disabled. recommended that fast decay loop enabled normal operation. description fast attack functionality, please Loop/Relinearization section. This reserved should written low.
0x10: Control [12:0]
This 3-bit register used fast decay step size. gain continues increase until reached fast decay threshold until maximum gain been reached. This 2-bit register sets threshold fast attack loop. When desired signal reaches this threshold, gain reduced FA_Step FA_Count number clock cycles. fast attack loop steps gain down FA_Step FA_Count number clock cycles. FA_Step register determines large step take once fast attack threshold been reached. This value expressed decibels.
0x11: Control [15:0]
This 8-bit register sets signal plus blocker peak detector period slow loop. from samples. Reserved must written 00000000.
0x0D: Control [8:0]
force enabled Control Register (Bit this register controls gain setting VGA. gain controlled 0.094 steps with maximum gain Code corresponds gain minimum gain, whereas Code corresponds gain maximum gain.
0x12: Reserved [6:0]
This register reserved must written 0000000.
0x0E: Control [15:0]
Control register 16-bit register that sets amount hysteresis used loop sets requested level loop. These upper bits hysteresis level 0.094 steps. Code corresponds hysteresis, Code corresponds ±23.97 hysteresis.
0x13: Control [8:0]
This 9-bit register used threshold fast decay signal plus blocker. Values range from dBFS dBFS. peak detector this threshold monitors desired signal blocker peaks output.
Rev. Page
AD6650
0x14: Start Holdoff Counter [15:0]
start holdoff counter loaded with value written this address when sync initiated. initiated either Soft_SYNC Pin_SYNC. counter begins decrementing, when reaches value channel exits sleep mode begins processing data. this register written start occurs immediately when SYNC comes into channel. written SYNC occurs.
0x19: Decimation Phase (PRCF) [2:0]
This register allows MRCF phases filter used adjusted dynamically. Each time filter started, this phase updated. When channel synchronized, retains phase setting selected. This used part timing recovery loop with external processor allow multiple RCFs work together while using single pair. Coefficient Filter section more details.
0x15: CIC4 Decimation Minus (MCIC4 [4:0]
This register used decimation CIC4 filter. value written this register decimation minus one. value this register should greater because have rates MHz/12. Although this 5-bit register, decimation usually limited between Decimations higher than require more scaling than CIC4's capability.
0x1A: Coefficient Offset (CORCF) [5:0]
This register used specify which section 256-word coefficient memory used filter. used select among multiple filters that loaded into memory referenced this pointer. This register shadowed filter pointer updated every time filter started. This allows coefficient offset written even while filter being computed without disturbing operation. next sample that comes will with filter.
0x16: CIC4 Scale [3:0]
CIC4 scale factor used compensate growth CIC4 filter. Fourth-Order Cascaded Integrator Comb Filter (CIC4) section details.
0x1B: Taps Minus (NRCF-1) [5:0]
number taps filter minus written this register.
0x17: Control Register
Address 0x17 control register. When this sync mask disabled. this mode, after SYNC issued AD6650, data path cleared. sync mask enabled, data path cleared contents starts accumulating data first valid clock after Soft_SYNC Pin_SYNC issued.
0x1C: Scale Register [1:0]
This 2-bit register represents output scale factor RCF. This register used scale output data between steps.
0x1D 0x20: BIST Register [23:0]
These four registers allow complete digital functionality data path channels tested system. User-Configurable Built-In Self Test (BIST) section more details.
0x18: Decimation Register Minus (MRCF [2:0]
This register used decimation stage. value written decimation minus one. This 3-bit register that allows decimations
Rev. Page
AD6650
0x21: Serial Control Register [8:0]
This register controls serial port AD6650 determines output format. Fine data BIST. this enabled (set high), Channel data output Serial Data Output (SDO1). Choose serial data frame sync (SDFS) mode. Please Serial Data Frame Sync section full description each mode. following bits select corresponding mode.
Table Serial Port Control Functions
Bits Description High SDO0 valid pulses pulses pulse
0x22: Autocalibration Register [3:0]
Address 0x22 autocalibration register controls automatic coarse autocalibration start-up. Reserved-this should Reserved-this should Determines whether power down mixer coarse calibration. This should allow state machine power down mixer. known that there input into part, this improve correction performance, which allows more flexibility setting lower threshold. Enables autocalibration. This should calibration automatically. Then AD6650 waits approximately 20.63 after Soft_SYNC Pin_SYNC enables part then runs coarse calibration. This allows some warm-up time analog path thermally stabilize.
setting this low, output data stream 16-bit 16-bit data-words both channels. setting this high, output data stream 24-bit 24-bit data words both channels. fully realize dynamic range AD6650, recommended that 24-bit mode used. setting this high, AD6650 becomes serial master. recommended that this enabled (set high). This 3-bit register controls divider serial clock (SCLK) output AD6650. possible divide SCLK allowing flexible interface FPGA.
0x23 0x3F: Reserved
These registers must written.
0x40 0x6F: Coefficient Memory
This memory utilized store forty-eight 20-bit coefficients shared Channels
0x70 0xFF: Reserved
These registers must written.
Rev. Page
AD6650 OUTLINE DIMENSIONS
12.20 12.00 11.80 CORNER INDEX AREA
BALL INDICATOR VIEW
10.00
1.00 BOTTOM VIEW *1.85 1.71 1.40 0.50 0.30 0.70 0.60 0.50 BALL DIAMETER SEATING PLANE 0.20 COPLANARITY DETAIL
DETAILA
*1.31 1.21 1.11
*COMPLIANT WITH JEDEC STANDARDS MO-192-AED-1 WITH EXCEPTION PACKAGE HEIGHT PACKAGE THICHNESS.
Figure 121-Lead Chip Scale Package Ball Grid Array [CSP_BGA] (BC-121) Dimensions shown millimeters
ORDERING GUIDE
Model AD6650BBC AD6650BBCZ AD6650/PCB
Temperature Range -25°C +85°C -25°C +85°C
Package Description 121-Lead Chip Scale Package Ball Grid Array [CSP_BGA] 121-Lead Chip Scale Package Ball Grid Array [CSP_BGA] Evaluation Board with AD6650 Software
Package Option BC-121 BC-121
AD6650 guaranteed fully functional from -40°C +85°C. minimum specifications guaranteed from -25°C +85°C, degrade slightly from -25°C -40°C. Pb-free part.
©2006 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners. D03683-0-3/06(0)
Rev. Page
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