MC74ACT564 high-speed, power octal flip-flop with buffered common Cloc

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MC74ACT564 high-speed, power octal flip-flop with buffered common Cloc

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MC74ACT564 Octal D-Type Flip-Flop with 3-State Outputs
MC74ACT564 high-speed, power octal flip-flop with buffered common Clock (CP) buffered common Output Enable (OE). information presented inputs stored flip-flops LOW-to-HIGH Clock (CP) transition. MC74ACT564 device functionally indentical MC74ACT574, with inverted outputs.
Inputs Outputs Opposite Sides Package Allowing
Easy Interface with Microprocessors
Useful Input Output Port Microprocessor Functionally Indentical MC74ACT574 with Inverted
Outputs
MC74ACT564 AWLYYWW PDIP-20 SUFFIX CASE
3-State Outputs Bus-Oriented Applications Outputs Source/Sink Compatible Inputs These devices available Pb-free package(s). Specifications herein
apply both standard Pb-free devices. Please website www.onsemi.com specific Pb-free orderable part numbers, contact your local Semiconductor sales office representative.
SO-20 SUFFIX CASE 751D
ACT564 AWLYYWW
TSSOP-20 SUFFIX CASE 948E
ALYW
Location
Assembly Wafer Year Work Week
ORDERING INFORMATION
Device MC74ACT564N MC74ACT564DW MC74ACT564DWR2 MC74ACT564DT Package PDIP-20 SOIC-20 Shipping Units/Rail Units/Rail
SOIC-20 1000 Tape Reel TSSOP-20 Units/Rail
MC74ACT564DTR2 TSSOP-20 2500 Tape Reel
Semiconductor Components Industries, LLC, 2006
March, 2006 Rev.
Publication Order Number: MC74ACT564/D
MC74ACT564
ASSIGNMENT
D0-D7 O0-O7 FUNCTION Data Inputs Clock Pulse Input 3-State Output Enable Input 3-State Outputs
Figure Pinout: 20-Lead Packages Conductors (Top View)
Figure Logic Symbol
Please note that this diagram provided only understanding logic operations should used estimate propagation delays.
Figure Logic Diagram FUNCTION TABLE
Inputs Internal Outputs Hold Hold Load Load Data Available Data Available Change Data Change Data Function
HIGH Voltage Level Voltage Level Immaterial High Impedance LOW-to-HIGH Transition Change
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MC74ACT564
FUNCTIONAL DESCRIPTION MC74ACT564 consists eight edge-triggered flip-flops with individual D-type inputs 3-state complementary outputs. buffered clock buffered Output Enable common flip-flops. eight flip-flops will store state their individual inputs that meet setup
MAXIMUM RATINGS (Note
Symbol IGND TSTG Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Sink/Source Current Supply Current Output Ground Current Output Storage Temperature Range Lead temperature, from Case Seconds Junction temperature under Bias Thermal resistance PDIP SOIC TSSOP PDIP SOIC TSSOP (Note Parameter Value *0.5 )7.0 *0.5 )0.5 *0.5 )0.5 )150 )150 Level Oxygen Index: Human Body Model (Note Machine Model (Note Charged Device Model (Note Above Below 85_C (Note UL-94-VO (0.125 2000 1000 $100 Unit _C/W
hold times requirements LOW-to-HIGH Clock (CP) transition. With Output Enable (OE) LOW, contents eight flip-flops available outputs. When HIGH, outputs high impedance state. Operation input does affect state flip-flops.
Power Dissipation Still 85_C
VESD
Moisture Sensitivity Flammability Rating Withstand Voltage
ILatch-Up
Latch-Up Performance
Absolute maximum continuous ratings those values beyond which damage device occur. Extended exposure these conditions conditions beyond those indicated adversely affect device reliability. Functional operation under absolute maximum-rated conditions implied. absolute maximum rating must observed. Tested EIA/JESD22-A114-A. Tested EIA/JESD22-A115-A. Tested JESD22-C101-A. Tested EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol Vin, Vout Parameter Input Voltage (Referenced GND) Input Voltage, Output Voltage (Referenced GND) Operating Temperature, Package Types Input Rise Fall Time (Note Junction Temperature (PDIP) Output Current High Output Current Unit ns/V
Unused Inputs left open. inputs must tied high voltage level logic voltage level. from refer individual Data Sheets devices that differ from typical input rise fall times.
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MC74ACT564
CHARACTERISTICS
+255C Symbol Parameter Minimum High Level Input Voltage Maximum Level Output Voltage DICCT Maximum Input Leakage Current Additional Max. ICC/Input Maximum 3-State Current ±0.5 0.001 0.001 4.49 5.49 3.86 4.86 0.36 0.36 ±0.1 -405C +855C Unit Conditions VOUT VOUT IOUT *VIN IOUT *VIN VCC, (OE) VIL, VCC, VCC, VOLD 1.65 VOHD 3.85
Guaranteed Limits 3.76 4.76 0.44 0.44 ±1.0 ±5.0
Maximum Level Input Voltage
Minimum High Level Output Voltage
IOLD IOHD
Minimum Dynamic Output Current Maximum Quiescent Supply Current
*All outputs loaded; thresholds input associated with output under test. Maximum test duration output loaded time.
CHARACTERISTICS (For Figures Waveforms, Figures
Symbol Parameter VCC* fmax tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum Clock Frequency Propagation Delay Propagation Delay Output Enable Time Output Enable Time Output Disable Time Output Disable Time 10.5 10.5 +25°C -40°C +85°C 11.5 10.5 11.5 Unit
*Voltage Range ±0.5
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MC74ACT564
OPERATING REQUIREMENTS
Symbol Parameter Setup Time, HIGH Hold Time, HIGH Pulse Width HIGH VCC* +25°C -40°C +85°C Guaranteed Minimum Unit
*Voltage Range ±0.3 *Voltage Range ±0.5
CAPACITANCE
Symbol Input Capacitance Power Dissipation Capacitance Parameter Value Unit Test Conditions
SWITCHING WAVEFORMS
1/fmax tPLH tPHL
Figure
Figure
VALID DATA
Figure
INPUT
OUTPUT DEVICE UNDER TEST
SCOPE TEST POINT
*Includes probe capacitance
Figure Test Circuit
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MC74ACT564
PACKAGE DIMENSIONS
SUFFIX PLASTIC PACKAGE CASE 738-03 ISSUE
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: INCH. DIMENSION CENTER LEAD WHEN FORMED PARALLEL. DIMENSION DOES INCLUDE MOLD FLASH. INCHES 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 0.050 0.070 0.100 0.008 0.015 0.110 0.140 0.300 0.020 0.040 MILLIMETERS 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 1.27 1.77 2.54 0.21 0.38 2.80 3.55 7.62 0.51 1.01
SEATING PLANE
0.25 (0.010)
0.25 (0.010)
SUFFIX PLASTIC SOIC PACKAGE CASE 751D-04 ISSUE
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSIONS INCLUDE MOLD PROTRUSION. MAXIMUM MOLD PROTRUSION 0.150 (0.006) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.13 (0.005) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. MILLIMETERS 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 0.25 0.32 0.10 0.25 10.05 10.55 0.25 0.75 INCHES 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 0.010 0.012 0.004 0.009 0.395 0.415 0.010 0.029
0.010 (0.25)
0.010 (0.25)
SEATING PLANE
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MC74ACT564
PACKAGE DIMENSIONS
TSSOP-20 SUFFIX PLASTIC TSSOP PACKAGE CASE 948E-02 ISSUE
0.15 (0.006)
0.10 (0.004)
IDENT
0.15 (0.006)
0.100 (0.004) SEATING
PLANE
DETAIL
Semiconductor registered trademarks Semiconductor Components Industries, (SCILLC). SCILLC reserves right make changes without further notice products herein. SCILLC makes warranty, representation guarantee regarding suitability products particular purpose, does SCILLC assume liability arising application product circuit, specifically disclaims liability, including without limitation special, consequential incidental damages. "Typical" parameters which provided SCILLC data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. SCILLC does convey license under patent rights rights others. SCILLC products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure SCILLC product could create situation where personal injury death occur. Should Buyer purchase SCILLC products such unintended unauthorized application, Buyer shall indemnify hold SCILLC officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that SCILLC negligent regarding design manufacture part. SCILLC Equal Opportunity/Affirmative Action Employer. This literature subject applicable copyright laws resale manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center Semiconductor P.O. 61312, Phoenix, Arizona 85082-1312 Phone: 480-829-7710 800-344-3860 Toll Free USA/Canada Fax: 480-829-7709 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com American Technical Support: 800-282-9855 Toll Free USA/Canada Japan: Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder additional information, please contact your local Sales Representative.
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SECTION 0.25 (0.010) DETAIL
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSION DOES INCLUDE MOLD FLASH, PROTRUSIONS GATE BURRS. MOLD FLASH GATE BURRS SHALL EXCEED 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE INTERLEAD FLASH PROTRUSION. INTERLEAD FLASH PROTRUSION SHALL EXCEED 0.25 (0.010) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.08 (0.003) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. TERMINAL NUMBERS SHOWN REFERENCE ONLY. DIMENSION DETERMINED DATUM PLANE -W-. MILLIMETERS 6.40 6.60 4.30 4.50 1.20 0.05 0.15 0.50 0.75 0.65 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 INCHES 0.252 0.260 0.169 0.177 0.047 0.002 0.006 0.020 0.030 0.026 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252
MC74ACT564/D

MC74ACT564 high-speed, power octal flip-flop with buffered common Cloc

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