µPD78217A,78218A 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTI

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µPD78217A,78218A 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTI

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INTEGRATED CIRCUIT
µPD78217A,78218A
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
PD78217A 78218A members 78K/II series microcontrollers featuring high-speed highperformance CPU. µPD78217A 78218A based µPD78213 78214, feature increased memory capacity added functions, such timer/counter macro servicing. Functions described detail following User's Manuals, which should read when carrying design work. µPD78218A Subseries User's Manual: Hardware (IEU-1313) 78K/II Series User's Manual: Instruction (IEU-1311)
FEATURES
Upper compatibility with µPD78214 subseries (pin-compatible) High-speed instruction execution MHz): (µPD78218A), µPD78217A) On-chip high-performance interrupt controller On-chip converter: bits channels Number pins: (µPD78218A), PD78217A)
Real-time output ports: bits channel bits channels Serial interface: channels Timer/counter: bits channel bits channels
APPLICATION FIELDS
Printers, typewriters, equipment such plain paper copiers (PPCs) faxes, electronic music instruments, inverters, cameras, etc.
ORDERING INFORMATION
Part Number Package 64-pin 64-pin 64-pin 64-pin plastic plastic plastic plastic shrink (750 mil) shrink (750 mil) On-Chip None None On-Chip 1024 1024 1024 1024
µPD78217ACW µPD78217AGC-AB8
Remark
code suffix.
information this document subject change without notice. Document IC-2748E IC-8131E) Date Published April 1995 Printed Japan mark shows revised points.
1991 1992
µPD78217A, 78218A
78K/II Product Development
On-Chip Converters Additional Output Function Improved Macro Service Timer/Counter Comparator Deletion
µPD78234 Subseries
µPD78244 Subseries
On-Chip Converter Additional Output Function Improved Macro Service Timer/Counter Additional EEPROM Improved Macro Service Timer/Counter
µPD78224 Subseries
On-Chip Converter Improved Timer/Counter Baud Rate Generator Function Comparator Deletion
µPD78214 Subseries
µPD78218A Subseries
Expanded On-Chip Memory Capacity Improved Macro Service Timer/Counter
µPD78218A(A) µPD78P218A µPD78218A µPD78217A
µPD78217A, 78218A
FUNCTION LIST
Item Basic instructions (mnemonic) Minimum instruction execution time Instruction
µPD78217A
µPD78218A
12-MHz)
16-bit operation Multiply divide bits bits, bits bits) manipulate adjust, etc. None 1024 bytes Program memory: Kbytes, data memory: Mbytes ROM-less version bits banks (memory mapping) 16-bit timer/counter Timer register Capture register Compare register Timer register Capture/compare register Compare register Timer register Capture register Compare register Timer register Compare register Pulse output capability Toggle output, PWM/PPG One-shot pulse output Pulse output capability (Real-time outputs, bits level Kbytes
On-chip memory capacity Address space pins Input Output Input/Output Total
Note
Additional function pins
Pins with pull-up resistor direct drive outputs Transistor direct drive outputs
ROM-less mode setting General registers Timer/counter
8-bit timer/counter
8-bit timer/counter
Pulse output capability Toggle output PWM/PPG
8-bit timer/counter
Real-time output port
Output port linked 8-bit timer/counter bits channels UART channel (on-chip dedicated baud rate generator) (3-wire serial I/O, SBI) channel 8-bit resolution channels sources (external internal instruction 2-level priority order (programmable) servicing modes (vectored interrupt, macro service) 64-pin plastic shrink (750 mil) 64-pin plastic
Serial interface converter Interrupt
Package
Note Additional function pins included pins.
µPD78217A, 78218A
CONFIGURATION (TOP VIEW)
64-pin plastic shrink
P67/REFRQ/AN7 P66/WAIT/AN6 P65/WR P64/RD P63/A19 P62/A18 P61/A17 P60/A16 RESET P57/A15 P56/A14 P55/A13 P54/A12 P53/A11
P37/TO3 P36/TO2 P35/TO1 P34/TO0 P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P33/SO/SB0 P32/SCK P31/T P30/R P27/SI P26/INTP5 P25/INTP4/ASCK P24/INTP3 P23/INTP2/CI P22/INTP1 P21/INTP0 P20/NMI ASTB P40/AD0 P41/AD1
µPD78217ACW µPD78218ACW-
P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2
µPD78217A, 78218A
64-pin plastic
P67/REFRQ/AN7 P66/WAIT/AN6
P64/RD P63/A19 P62/A18 P61/A17 P60/A16 RESET P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9
P70/AN0
P37/TO3
P36/TO2
P35/TO1
P34/TO0
P65/WR
P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P33/SO/SB0 P32/SCK P31/T P30/R P27/SI P26/INTP5 P25/INTP4/ASCK
µPD78217AGC-AB8 µPD78218AGC- -AB8
P20/NMI
P21/INTP0
P22/INTP1
P23/INTP2/CI
P24/INTP3
P41/AD1
P40/AD0
P50/A8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
ASTB
µPD78217A, 78218A
IDENTIFICATION
Port Port Port Port Port Port Port WAIT ASTB REFRQ RESET AVREF AVSS Read Strobe Write Strobe Wait Address Strobe Refresh Request Reset Crystal External Access Analog Input Reference Voltage
ASCK INTP0 INTP5
Timer Output Clock Input Receive Data Transmit Data Serial Clock Asynchronous Serial Clock Serial Serial Input Serial Output Non-maskable Interrupt Interrupt From Peripherals Address/Data
Analog Ground Power Supply Ground
Address
µPD78217A, 78218A
EXAMPLE SYSTEM CONFIGURATION (INVERTER AIR-CONDITIONER IN-DOOR UNIT)
Quick Heater Varistor Outdoor Unit
µPD78218A
Remote Control Receive
INTP0 P55,P56 Relay Driver
Wind Direction Setting
Wired Remote Control
P00-P03 P60-P63 Driver Driver
Up-Down Wind Direction
Room Temperature Special Sensor Humidity Heat Exchanger Temperature
P04-P07
Driver
Right/ Left Wind Direction
P50-P54
Driver
Indoor Motor
Serial Communication Display Buzzer Control P40-P47 P35,P36 RESET RESET
Stepping Motors
Right/ Left Wind Direction
µPD78217A, 78218A
INTERNAL BLOCK DIAGRAM
ADDRESS
A16-A19 (Expansion) A8-A15 AD0-AD7
INTP0-INTP5 ASCK SO/SB0 INTP3 PROGRAMMABLE INTERRUPT CONTROLLER
CONTROL
UART BAUD RATE GENERATOR CLOCKED SERIAL INTERFACE TEMPORARY REGISTERS
ADDRESS/DATA
WAIT REFRQ ASTB
TIMER/COUNTER BITS) TIMER/COUNTER CHANNEL-1 BITS) TIMER/COUNTER CHANNEL-2 BITS) TIMER/COUNTER CHANNEL-3 BITS)
DATA
INTP0 INTP1 INTP2
MICRO MICRO- SEQUENCER
BOOLEAN PROCESSOR
SYSTEM CONTROL
(256 Bytes) MACRO SERVICE CHANNEL DATA
RESET
P00-P03 P04-P07 AN0-AN7 AVREF AVSS INTP5
REAL-TIME OUTPUT PORT BITS
CONVERTER
PORT
-P07
-P27
-P37
-P47
Note
-P57
Note
Note
-P63 -P67
-P75
Caution Note
Inernal ROM/RAM capacity varies depending product.
case µPD78217A, P47, P57, cannot used ports.
µPD78217A, 78218A
CONTENTS DIFFERENCES BETWEEN µPD78218A µPD78214 SUBSERIES FUNCTIONS
PORTS NON-PORT PINS CIRCUITS UNUSED CONNECTION
INTERNAL BLOCK FUNCTIONS
MEMORY SPACE PORTS REAL-TIME OUTPUT PORT TIMER/COUNTER UNIT CONVERTER SERIAL INTERFACE 3.6.1 Asynchronous Serial Interface 3.6.2 Clock Synchronous Serial Interface
INTERNAL/EXTERNAL CONTROL FUNCTION
INTERRUPTS 4.1.1 Interrupt Sources 4.1.2 Vectored Interrupt 4.1.3 Macro Service 4.1.4 Macro Service Application Examples LOCAL INTERFACE 4.2.1 Memory Expansion 4.2.2 Programmable Wait 4.2.3 Pseudo-Static Refresh Function STANDBY RESET
INSTRUCTION ELECTRICAL SPECIFICATIONS PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS
APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS
Series Name Part Number Minimum instruction execution time 12-MHz) PUSH instruction execution time (number clocks) Power voltage range On-chip memory pins 16-bit timer/counter one-shot pulse output Macro service counter width Macro service type MPD, increments Macro service execution time Restrictions when data transferred from macro service type memory converter Input voltage restrictions AVREF voltage restrictions Stabilization time oscillation STOP mode release Package
DIFFERENCES BETWEEN µPD78218A µPD78214 SUBSERIES
µPD78218A Subseries µPD78217A
µPD78214 Subseries µPD78P218A µPD78212
µPD78218A
µPD78213
µPD78214
µPD78P214
When stack area internal dual port Other than above VDD=+5V±10% ROM-less Kbytes (mask ROM) 1024 bytes Available 8/16 bits select capability (except type 16-bit increment
When stack area internal dual port Other than above VDD=+5V±10% Kbytes (mask ROM) bytes available Only bits Only low-order bits increment (high-order bits unchanged) ROM-less Kbytes (mask ROM) bytes
VDD=+5V±0.3V Kbytes (PROM)
Kbytes (PROM)
Macro service depends mode. Compare with user's manual products. Generated when transfer source buffer (memory) address 0FED0H 0FEDFH. Generated when transfer data DFH.
Only pins involved conversion
Pins involved conversion pins selected register bits ANI0 ANI2 only: AVREF voltage
µPD78217A, 78218A
Dedicated counter bits active pulse width dedicated counter bits 64-pin plastic shrink (750 mil) 64-pin plastic 64-pin ceramic shrink (CERDIP, with window, mil): µPD78P218A only
active pulse width dedicated counter bits
64-pin plastic shrink (750 mil) 64-pin plastic QUIP: Except µPD78212 68-pin plastic QFJ: Except µPD78212 64-pin plastic 74-pin plastic 64-pin ceramic shrink (CERDIP, with window, mil): µPD78P214 only
µPD78217A, 78218A
FUNCTIONS
PORTS
Name
Alternate Function Port (P0):
Function
Output
Established real-time output port bits Direct drive transistors capability
Note
Input
INTP0 INTP1 INTP2/CI INTP3 INTP4/ASCK INTP5
Port (P2): cannot used general-purpose port. (Non-maskable interrupt) However, input level confirmed interrupt routine. connection on-chip pull-up resistor specified 6-bit unit software.
Input/ output
SO/SB0
Port (P3): input/output specifiable bit-wise. Input mode pins specifiable on-chip pull-up resistor connection batch software.
Input/ output
Port (P4): input/output specifiable 8-bit batch. connection on-chip pull-up resistor specifiable 8-bit batch software. direct drive capability.
Note
Input/ output
Port (P5): input/output specifiable bit-wise. Input mode pins specifiable on-chip pull-up resistor connection batch software. direct drive capability.
Note Note
Output Input/ output
WAIT/AN6 REFRQ/AN7
Port (P6): enables specify input/output bit-wise. connection on-chip pull-up resistor input mode pins specified batch software.
Input
Port (P7)
Note
case µPD78217A, these cannot used ports.
µPD78217A, 78218A
NON-PORT PINS
Alternate Function /INTP2 P25/INTP4 P33/SO P33/SB0 P23/CI P25/ASCK Input/output Output Output Output Output Input Output Output Input Input P67/AN7
Note Note
Name ASCK INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 WAIT ASTB REFRQ RESET
Output Input Input Output Input Input/output Input Output Input/output Input
Function Timer output Count clock input 8-bit timer/counter Serial data input (UART) Serial data output (UART) Baud rate clock input (UART) Serial data input/output (SBI) Serial data input (3-wire serial I/O) Serial data output (3-wire serial I/O) Serial clock input/output (SBI, 3-wire serial I/O) External interrupt request
Time multiplexing address/data (external memory connection) Upper address (external memory connection) Upper address when extending address (external memory connection) Read strobe into external memory Write strobe into external memory Wait insertion Address latch timing output (during external memory access) Refresh pulse output into external pseudo-static memory Chip reset Crystal connection system clock oscillation (external clock input enabled)
Note Note
P66/AN6
Input
ROM-less operating specification (external access same space internal ROM). Used high µPD78218A used µPD78217A.
AN6, AVREF AVSS
Input
P66/WAIT, P67/REFRQ
Analog voltage input converter
Reference voltage apply converter converter Positive power supply
Note
case µPD78217A, these cannot used ports.
µPD78217A, 78218A
CIRCUITS UNUSED CONNECTION input/output circuit type each recommended connection unused pins shown Table 2-1. input/output circuit configuration each type, Fig. 2-1. Table Input/Output Circuit Type Each
Name P20/NMI P21/INTP0 P22/INTP1 P23/INTP2/CI P24/INTP3 P25/INTP4/ASCK P26/INTP5 P27/SI P30/RXD P31/TXD P32/SCK P33/SB0/SO P34/TO0 P37/TO3 P40/AD0 P47/AD7 P50/A8 P57/A15 P60/A16 P63/A19 P64/RD P65/WR P66/WAIT/AN6 P67/REFRQ/AN7 P70/AN0 P75/AN5 ASTB RESET AVREF AVSS
Input/Output Circuit Type
Output Input Leave open.
Unused Connection
Connected
Connected
Input/output
Input Output
Connected VDD. Leave open.
10-A
Output Input/output
Leave open. Input Output Connected VDD. Leave open. Connected VDD. Leave open.
Note
Input Output
Input Output Input
Connected Leave open.
Connected Connected
Note
Note
voltage outside range AVSS AVREF should applied, this damage PD78217A/78218A. input/output mode undefined input/output dual-function pins, connect these pins resistor several (Especially reset input exceeds low-level input voltage power-on case input/ output switching software.)
Caution
Remark
type numbers standardized series, therefore they always consecutive numbers each product (some circuits incorporated).
µPD78217A, 78218A
Fig. Input/Output Circuits
Type Type
pullup enable
Schmitt-Triggered Input with Hysteresis Characteristic Type Schmitt-Triggered Input with Hysteresis Characteristic Type data output disable input enable data output disable Type pullup enable
Push-pull output which enables output high-impedance (both P-ch N-ch off). Type pullup enable data output disable
Type
Comparator Vref (Threshold Voltage)
input enable
Type 10-A
Type
pullup enable data open drain output disable
pullup enable data
output disable Comparator
Vref (Threshold Voltage) input enable
µPD78217A, 78218A
INTERNAL BLOCK FUNCTIONS
MEMORY SPACE memory space Mbytes accessed. Fig. shows that memory space. program memory mapping differs depending status. µPD78217A program memory mapped onto external memory (64256 bytes: 00000H 0FAFFH). This area also used data memory. data memory mapped onto internal (1024 bytes: 0FB00H 0FEFFH). 1-Mbyte expansion mode, external memory (960 Kbytes: 10000H FFFFFH) mapped expanded data memory. µPD78218A program memory mapped onto internal Kbytes: 00000H 07FFFH) external memory (31488 bytes: 08000H 0FAFFH). external memory accessed external memory expansion mode. area mapped onto external memory also used data memory. data memory mapped onto internal (1024 bytes: 0FB00H 0FEFFH). 1-Mbyte expansion mode, external memory (960 Kbytes: 10000H FFFFFH) mapped expanded data memory.
µPD78217A, 78218A
Fig. Memory
(ROM-Less Mode) Note3
FFFFFH
Extended Address
Data Memory
External Memory Note1 (960 Kbytes)
Note1
10000H
0FFFFH 0FFDFH 0FFD0H 0FF00H
0FEFFH Special Function Register (SFR)
Note2
General Register bytes) Macro Service Control Word bytes) Data Area (1024 bytes)
(256 bytes)
0FEE0H 0FEDFH
0FEC2H
Memory Space Mbytes)
0FEFFH
Data Memory
Internal (1024 bytes) 0FB00H 0FB00H 07FFFH
Normal Address Kbytes)
0FAFFH
Program Memory/ Data Memory
01000H 00FFFH CALLF Entry Area Kbytes) 08000H 07FFFH 00800H 007FFH 00080H 0007FH 00040H 0003FH 00000H Program Area (1920 bytes) CALLT Table Area bytes) Vector Table Area bytes) 00FFFH
Program Memory/ Data Memory
Internal Kbytes)
00000H
Notes Accessed 1-Mbyte expansion mode. Shaded areas denote internal memory. Accessed external memory expansion mode. µPD78217A applies only when
Program Memory Data Memory
External Memory Note2 (31488 bytes)
Program Area Kbytes)
External Memory (64256 bytes)
µPD78217A, 78218A
PORTS
µPD78217A/78218A ports shown Fig. which allow various kinds control. functions each port shown Table 3-1. ports on-chip pull-up resistor specified software input. Fig. Port Configuration
P00-P07
Port
P20-P27
Port
Port
P40-P47
Port
Note
Port
Note
P60-63
Port
Note
P70-P75
Port
Note
case µPD78217A, P47, P57, P64, cannot used ports.
µPD78217A, 78218A
Table Port Function
Name Port
Name
Function Output high-impedance specifiable 8-bit batch. also operate bits real-time output (P00 P03, P07). Transistor direct drive capability.
Designation Software Pull-Up -----
Port Port
Input port Input output specifiable bit-wise.
6-bit batch (P22 P27) Input mode pins specifiable batch
Port
Note
Input output specifiable 8-bit batch. direct drive capability.
8-bit batch
Port
Note
Input output specifiable bit-wise. direct drive capability.
Input mode pins specifiable batch ----- Input mode pins specifiable batch
Port
Note
Output port Input output specifiable bit-wise.
Port
Input port
-----
Note
case µPD78217A, P47, P57, P64, cannot used ports.
µPD78217A, 78218A
REAL-TIME OUTPUT PORT
real-time output port outputs data stored buffer synchronization with timer match interrupts external interrupts. jitterless pulse output obtained means this. Therefore, most suitable applications which output pattern interval time. (Stepping motor open loop control, etc.) Port buffer register core elements configuration, shown Fig. 3-3. Fig. Real-Time Output Port Block Diagram
Internal
Real-Time Output Port Control Register
Buffer Register
INTP0 (From Outside) INTC10 (From Timer) INTC11 (From Timer) Output Trigger Control Circuit
Output Latch (P0)
µPD78217A, 78218A
TIMER/COUNTER UNIT
µPD78217A/78218A 16-bit timer/counter unit channel 8-bit timer/counter units channels. Table Type Function Timer/Counter
Unit Type Function Interval timer Type External event counter One-shot timer Timer output Toggle output PWM/PPG output Function One-shot pulse output Real-time output Pulse amplitude measurement Number interrupt requests Clock source serial interface
16-Bit Timer/ Counter
8-Bit Timer/ Counter
8-Bit Timer/ Counter
8-Bit Timer/ Counter
Since interrupt requests supported total, also function timer channels. Remark one-shot pulse output function activates pulse output level software, inactivates hardware (interrupt request signal). This function different from one-shot timer function 8-bit timer/counter
µPD78217A, 78218A
Fig. Timer/Counter Unit Block Diagram 16-bit timer/counter unit
Software Trigger fCLK/8 Timer Register
Compare Register CR00
Pulse Output Control
Match
Compare Register CR01
Match
INTP3
Edge Detection
INTC00 Capture Register CR02 INTP3 INTC01
8-bit timer/counter unit
fCLK/16 Prescaler Timer Register
Compare Register CR10
Match
INTC10 Real-Time Output Port
INTP0
Edge Detection
Capture/Compare Register CR11
Match
INTC11
INTP0
8-bit timer/counter unit
fCLK/16 Prescaler
Timer Register
Pulse Output Control
INTP2/CI
Edge Detection
Event Input INTP2
Compare Register CR20
Match
Compare Register CR21
Match
INTP1
Edge Detection
Capture Register CR22
INTC20 INTC21
INTP1
8-bit timer/counter unit
fCLK/8 Prescaler Timer Register Clear UART
Compare Register CR30
Match INTP4/ INTC30
INTP4/ ASCK
Edge Detection
OVF: Overflow Flag
µPD78217A, 78218A
CONVERTER
µPD78217A/78218A incorporate analog/digital (A/D) converter with 8-channel multiplexed analog input (AN0 AN7). conversion method used successive approximation. After conversion results generated, they held 8-bit conversion result register (ADCR), which allow high-speed high-precision conversion (conversion time: Approx. 12-MHz operation). following modes available starting conversion: Hardware start Starts conversion trigger input (INTP5) Software start Starts conversion converter mode register (ADM) setting
following modes operation after starting available: Scan mode Multiple analog input selected sequentially conversion data obtained from pins.
Select mode analog input fixed continuous conversion value obtained.
above modes conversion operation stopped ADM. conversion result transferred ADCR, interrupt request INTAD generated, (except software start select mode). Therefore, conversion value transferred memory continuously using macro service (See section 4.1.3 "Macro Service"). Table INTAD Generation Mode
Scan Mode Hardware start Software start
Select Mode
µPD78217A, 78218A
Fig. Converter Block Diagram
Successive Approximation Register (SAR) Edge Detector Conversion Trigger Controller
Series Resistor String
Input Selector
Sample Hold Circuit
INTP5
INTAD
Selector
Selector Interrupt Request
Voltage Comparator
INTP5 Trigger Enable
Conversion Result Register (ADCR)
Converter Mode Register (ADM)
Internal
µPD78217A, 78218A
SERIAL INTERFACE
µPD78217A/78218A independent serial interfaces. Asynchronous serial interface (UART) Clock synchronous serial interface (CSI) 3-wire serial Serial interface (SBI) Therefore, communication with external devices local communication inside system performed simultaneously (See Fig. 3-6). Fig. Serial Interface Example
UART
µPD78218A (Master)
PD4711A
[UART] RS-232-C Driver [SBI] Port
PD75402A (Slave)
PD75328 (Slave)
UART 3-wire serial
µPD78218A (Master)
PD4711A
[UART] RS-232-C Driver Port [3-Wire Serial I/O]
Note
PD78C11A (Slave)
Port
INTPm Port
PD78C14 (Slave)
INTPn Port
Note
Port
Note Handshake Line
µPD78217A, 78218A
3.6.1
Asynchronous Serial Interface
µPD78217A/78218A incorporates UART (Universal Asynchronous Receiver Transmitter) asynchronous serial interface. UART used send/receive byte data following start bit. UART incorporates dedicated baud rate generator which generate wide range desired baud rates also determine baud rates scaling ASCK input clocks 8-bit timer/counter output (TM3 output), allowing transmission/reception with variety baud rates. UART dedicated baud rate generator used, MIDI standard baud rate (31.25 kbps) also obtained. Fig. Asynchronous Serial Interface (UART) Block Diagram
Internal
Receive Buffer
Receive Shift Register
Transmit Shift Register
Receive Control Parity Check
INTSR INTSER
Transmit Control Parity Addition
INTST
1/16
1/16
UART Dedicated Baud Rate Generator fCLK 1/N1
Selector
1/N2
ASCK
Selector
Output
fCLK: Internal system clock frequency (System Clock Frequency/2)
Selector
µPD78217A, 78218A
3.6.2
Clock Synchronous Serial Interface
master device starts transmission activating serial clock transfers one-byte data synchronization with this clock. Fig. Clock Synchronous Serial Interface Block Diagram
Internal
Clear Selector Shift Register Output Latch
SO/SB0
N-ch Open-drain output also possible (SB0: SBI) Release Command/ Acknowledge Detector
Busy/ Acknowledge Generator
Serial Clock Counter
Interrupt Generator
INTCSI
Output/2 Selector Serial Clock Controller fCLK/8 fCLK/32
fCLK: Internal System Clock Frequency (System Clock Frequency/2) 3-wire serial This interface communicating with devices incorporating conventional clock synchronous serial interface. Basically, communication performed with three lines, serial clock line (SCK) serial data lines (SI, SO). When connecting multiple devices, handshake line necessary. Communication with multiple devices performed with serial clock line (SCK) serial line (SB0). This NEC's standard serial interface. master device selects slave device communicated with outputting "address" from pin. Therefore, "commands" "data" perform transfer receive between master slave.
µPD78217A, 78218A
INTERNAL/EXTERNAL CONTROL FUNCTION
INTERRUPTS interrupt request servicing methods selected, shown following table. Table Interrupt Request Servicing
Service Mode Vectored interrupt
Servicing Subject Software
Service Branches service routine, executes (any process contents) Data transfer, etc., between memory (fixed process contents)
Contents With save return
Macro service
Firmware
Hold
µPD78217A, 78218A
4.1.1
Interrupt Sources
There types interrupt sources instruction execution, shown Table 4-2. priority interrupt servicing levels (high priority levels). Therefore, levels nest control when interrupt progress when interrupt requests occur simultaneously (see Fig. 4-1, Fig. 4-2) separated. Nesting will always take place macro service won't hold). default priority priority level (fixed) service interrupt requests which occur same level simultaneously (see Fig. 4-2). Table Interrupt Sources
Type Software Nonmaskable Maskable
Default Priority
Source Name Instruction execution input edge detection Trigger
Internal/ External ----- External
Macro Service
(highest)
INTP0 INTP1 INTP2 INTP3 INTC00 INTC01 INTC10 INTC11 INTC21 INTP4 INTC30
input edge detection (TM1 capture trigger) input edge detection (TM2 capture trigger) input edge detection (TM2 event counter input) input edge detection (TM0 capture trigger) CR00 match signal generation CR01 match signal generation CR10 match signal generation CR11 match signal generation CR21 match signal generation input edge detection CR30 match signal generation input edge detection converter conversion termination (transfer ADCR) CR20 match signal generation receive error generation receive termination transmit termination transfer termination External Internal External Internal Internal
INTP5 INTAD
(lowest)
INTC20 INTSER INTSR INTST INTCSI
16-bit timer 8-bit timer Asynchronous serial interface Clock synchronous serial interface
µPD78217A, 78218A
Fig. Servicing Example when Interrupt Request Occurrence Issued while Interrupt Serviced
Main Routine [Nesting Servicing Servicing Macro Service Request Vectored Interrupt Request (Low-Priority Level) Servicing Vectored Interrupt Request (High-Priority Level) Servicing Macro Service Request [Nesting [Nesting
Servicing Servicing Macro Service Request Vectored Interrupt Request (High-Priority Level) Macro Service Request
Vectored Interrupt Request (Low-Priority Servicing Level: Pending) Servicing
Fig. Servicing Example Simultaneous Interrupt Requests
Main Routine [Nesting Servicing [Nesting
Vectored Interrupt Request (Low-Priority Level) Macro Service Request (High-Priority Level) Macro Service Request (Low-Priority Level) Vectored Interrupt Request (High-Priority Level) Default Priority:
Servicing
Servicing
Servicing
µPD78217A, 78218A
4.1.2 Vectored Interrupt memory contents vector table address, which corresponds interrupt source, branched into service routine destination address. executes interrupt servicing, following operations occur. When branch When return Saving status (PC, contents) stack. Returning status (PC, contents) from stack.
RETI instruction executes returning main routine from service routine. Table Vector Table Address
Interrupt Source INTP0 INTP1 INTP2 INTP3 INTC00 INTC01 INTC10 INTC11
Vector Table Address 003EH 0002H 0006H 0008H 000AH 000CH 0014H 0016H 0018H 001AH
Interrupt Source INTC21 INTP4 INTC30 INTP5 INTAD INTC20 INTSER INTSR INTST INTCSI
Vector Table Address 001CH 000EH
0010H
0012H 0020H 0022H 0024H 0026H
4.1.3 Macro Service This function transfer data between memory special function registers (SFR) without going through CPU. macro service controller accesses memory SFR, transfers data directly without fetching High-speed data transfer enabled because data saved, restored fetched. Fig. Macro Service
Read Memory Write
Macro Service Controller
Write Read
Internal
µPD78217A, 78218A
4.1.4
Macro Service Application Examples
Transmit operation serial interface
Transmit Data Storage Buffer (Memory) Data Data
Data Data
Internal
Transmit Shift Register (SFR)
Transmission Control
INTST
Whenever macro service request INTST generated, next transmit data transferred from memory. When data (last byte) transferred (the transmit data storage buffer becomes empty), vectored interrupt request INTST generated. Receive operation serial interface
Receive Data Storage Buffer (Memory) Data Data
Data Data
Internal
Receive Buffer
(SFR)
Receive Shift Register
Receive Control
INTSR
Whenever macro service request INTSR generated, receive data transferred memory from RXB. When data (last byte) transferred memory (the receive data storage buffer becomes empty), vectored interrupt request INTSR generated.
µPD78217A, 78218A
Real-time output port INTC10 INTC11 become output triggers real-time output port. macro service them, next output pattern interval simultaneously. Therefore, INTC10 INTC11 control system stepping motor independently. Also, they applied control motor, etc.
Output Pattern Profile (Memory) Pn-1
Output Timing Profile (Memory) Tn-1
Internal
Internal
(SFR)
Match
CR10
(SFR)
INTC10 Output Latch P00-P03
Whenever macro service request INTC10 generated, pattern timing transferred CR10, respectively. When contents match with contents CR10, next INTC10 generated contents sent output latch. (last byte) sent CR10, vectored interrupt request INTC10 generated. same operation available INTC11 (differences: CR10 CR11, P0H, P00-P03 P04-P07).
µPD78217A, 78218A
LOCAL INTERFACE
µPD78217A/78218A connected external memory (memory mapped I/O), supports 1M-byte memory space (see Fig.3-1). Fig. Local Interface Example
µPD78218A
A16-A19 Decoder
REFRQ Pseudo SRAM PROM PD27C256A
Kanji-Character Generator PD24C1000
AD0-AD7
Data
ASTB
Latch
A8-A15
Address
Gate Array Expansion Centronics I/F, etc.
4.2.1
Memory Expansion
following modes have been prepared memory expansion function. External memory expansion mode Expands program memory data memory 31488 bytes (64256 bytes µPD78217A) externally. However, this area used unconditionally under ROM-less mode 1-Mbyte expansion mode Expands data memory Kbytes become 1-Mbyte memory space.
4.2.2
Programmable Wait
wait independently inserted memory mapped both normal address (00000H 0FFFFH) expanded address (10000H FFFFFH). Therefore, efficiency entire system decreased. 4.2.3 Pseudo-Static Refresh Function
refresh operations follows. Pulse refresh Outputs refresh pulse REFRQ synchronization with cycle. Power-down self refresh Outputs low-level REFRQ standby mode holds contents pseudo-static RAM.
µPD78217A, 78218A
STANDBY
This function reduce power consumption chip. following modes available. HALT mode Stops operation clock CPU. average power consumption reduced switching from normal mode HALT mode vice-versa. STOP mode Stops oscillator. This stops operation chip enables minute power consumption consisting only leakage current. These modes programmable. macro service started from HALT mode. Fig. Standby Status Flow
Program Operation
HALT
STOP (Standby)
RESET Input Input Vectored Interrupt Request Note
rans
Interrupt Request Interrupt Disable
HALT (Standby)
Traation rmin
Macro Service
Vectored Interrupt Request
Note
Notes case vectored interrupt request low-priority level (status disable interrupt low-priority sequence under HALT setting). case vectored interrupt request high-priority level case status enable interrupt low-priority sequence under HALT setting. case macro service high-priority level (status disable interrupt low-priority sequence under HALT setting). case macro service high-priority level case status enable interrupt low-priority sequence under HALT setting.
µPD78217A, 78218A
RESET
When level input RESET pin, internal hardware initialized (reset state). When RESET input changes from level high level, following data program counter (PC). Lower bits Upper bits Contents 0000H address Contents 0001H address
contents destination address program starts executed from address. Therefore, start from address reset start. Please program contents each register required. noise eliminator been incorporated RESET input circuit prevent error from noise. This noise eliminator sampling circuit based analog delay. Fig. Reset Acknowledge
Delay
Delay
Delay
Initialization
Instruction Execution Reset Start Address
RESET (Input)
Internal Reset Signal
Reset Start
Reset
RESET signal active reset operation power-on until oscillation stabilization time (approx. elapses. Fig. Reset Operation Power-On
Oscillation Stabilization Time
Delay
Initialization
Instruction Execution Reset Start Address
RESET (Input)
Internal Reset Signal
Reset
µPD78217A, 78218A
INSTRUCTION
8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, Table Instructions Classified 8-Bit Addressing Mode
Operand #byte Operand
Note1
saddr saddr' Note1 Note1 Note1 Note1 &mem !addr16 &!addr16
None
Note2
ROLC RORC
Note1
MULU DIVUW DBNZ
saddr Note1 Note1 Note1
DBNZ PUSH
mem1 &mem1 !addr16 &!addr16 STBC
ROR4 ROL4 PUSH
Notes
ADDC, SUB, SUBC, AND, same ADD. There operand, operand operand address.
µPD78217A, 78218A
16-bit instructions MOVW, ADDW, SUBW, CMPW, INCW, DECW, SHRW, SHLW, PUSH, Table Instructions Classified 16-Bit Addressing Mode
Operand #word Operand ADDW SUBW CMPW
saddrp ADDW SUBW CMPW MOVW ADDW SUBW CMPW MOVW ADDW SUBW CMPW sfrp mem1 &mem1 None
MOVW
MOVW
MOVW
MOVW
MOVW
SHLW SHRW
INCW DECW PUSH
saddrp sfrp mem1 &mem1
MOVW MOVW
MOVW MOVW MOVW
MOVW
MOVW
INCW DECW
µPD78217A, 78218A
manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BTCLR Table Instructions Classified Manipulation Instruction Addressing Mode
Operand Operand MOV1 AND1 XOR1 AND1 MOV1 AND1 XOR1 AND1 A.bit /A.bit X.bit /X.bit
saddr. MOV1 AND1 XOR1
/saddr. sfr.bit MOV1 AND1 XOR1 MOV1 AND1 XOR1 /sfr.bit PSW.bit
/PSW.
None
Note
AND1
AND1
AND1
SET1 CLR1 NOT1 SET1 CLR1 NOT1 BTCLR SET1 CLR1 NOT1 BTCLR SET1 CLR1 NOT1 BTCLR SET1 CLR1 NOT1 BTCLR SET1 CLR1 NOT1 BTCLR
A.bit
MOV1
X.bit
MOV1
saddr.bit
MOV1
sfr.bit
MOV1
PSW.bit
MOV1
Note There operand, operand operand address.
µPD78217A, 78218A
Call/branch instructions CALL, CALLF, CALLT, BTCLR, DBNZ, BNC, BNL, BNZ, Table Instructions Classified Call/Branch Instruction Addressing Mode
Operands Instruction Address Basic instructions Compound instructions
$addr16 BCNote BTCLR DBNZ
!addr16 CALL
CALL
!addr11 CALLF
[addr5] CALLT
Note
BNC, BNL, same
Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, NOP,
µPD78217A, 78218A
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
TEST CONDITIONS
RATING -0.5 +7.0 -0.5 +0.5 -0.5 +0.5 -0.5 +0.5
UNIT
Supply voltage
AVREF AVSS
Input voltage Output voltage Output current,
output pins Note
-0.5 AVREF +0.5 -0.5 +0.5 +150
Output current, high
output pins Tstg
Operating ambient temperature Storage temperature
Note
P70/AN0 P75/AN5, P66/WAIT/AN6, P67/REFRQ/AN7 pins used converter input pins. However, absolute maximum ratings should also satisfied.
Caution
Product quality suffer absolute maximum rating exceeded even single parameter even momentarily. That absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions which ensure that absolute maximum ratings exceeded.
OPERATING CONDITIONS
CLOCK FREQUENCY
OPERATING AMBIENT TEMPERATURE (TA)
SUPPLY VOLTAGE (VDD
CAPACITANCE
PARAMETER Input capacitance Output capacitance capacitance
SYMBOL
TEST CONDITIONS unmeasured pins returned
MIN.
TYP.
MAX.
UNIT
µPD78217A, 78218A
OSCILLATOR CHARACTERISTICS (TA=
RESONATOR RECOMMENDED CIRCUIT
PARAMETER
MIN.
MAX.
UNIT
Ceramic resonator crystal resonator
Oscillator frequency (fXX)
External clock HCMOS Inverter
input frequency (fX)
input rising/falling time (tXR input high/low level width (tWXH tWXL)
Caution
When using clock oscillator, wiring area enclosed with dotted line should carried follows avoid adverse effect from wiring capacitance. Wiring should short possible. Wiring should cross other signal lines. Wiring should placed close varying high current. potential oscillator capacitor ground should same VSS. ground ground pattern which high current flows. fetch signal from oscillator.
µPD78217A, 78218A
RECOMMENDED OSCILLATOR CONSTANTS CERAMIC RESONATOR
MANUFACTURER
FREQUENCY [MHz]
PART NUMBER
RECOMMENDED CONSTANTS [pF] [pF]
CSA12.0MTZ Murata Mfg. CST12.0MTW EFOGC1205C4 Matsushita Electronics Parts
Note
Capacitor on-chip type Capacitor on-chip type
EFOEC1205C4 EFOEN1205C4 FCR12.0M2S
FCR12.0MC
Capacitor on-chip type
Note
Production discontinued.
µPD78217A, 78218A
CHARACTERISTICS
PARAMETER Input voltage,
SYMBOL VIH1
TEST CONDITIONS
MIN.
TYP.
MAX. AVREF 0.45
UNIT
Pins except Note Note Note Note
Note3
Input voltage, high
VIH2 VIH3 VOL1
Output voltage, VOL2 VOH1 Output voltage, high VOH2 VOH3 input current, input current, high Input leakage current Output leakage current AVREF current AIREF IDD1 supply current IDD2 Data retention voltage VDDDR HALT mode STOP mode STOP mode Pull-up resistor VDDDR VDDDR VDD-1.0 VDD-0.5
Note4
-1.0 -100 -5.0 VIH3 Operating mode Operating mode
-100
Data retention current
IDDDR
Notes P70/AN0 P75/AN5, P66/WAIT/AN6, P67/REFRQ/AN7 pins used converter input pins. RESET, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK, P26/ INTP5, P27/SI, P32/SCK, P33/SO/SB0, pins P40/AD0 P47/AD7, P50/A8 P57/A15 pins pins
µPD78217A, 78218A
CHARACTERISTICS READ/WRITE OPERATION (1/2)
PARAMETER input clock cycle time Address setup time ASTB) Address hold time (from ASTB)
Note
SYMBOL tCYX tSAST tHSTA tHRA tHWA tDAR tFAR tDAID tDSTID tDRID tDSTR tHRID tDRA tDRST tWRL tWSTH tDAW tDSTOD tDWOD tDSTW1
TEST CONDITIONS
MIN.
MAX.
UNIT
Address hold time (from Address hold time (from delay time from address Address float time (from Data input time from address Data input time from ASTB Data input time from delay time from ASTB Data hold time (from Address active time from ASTB delay time from low-level width ASTB high-level width delay time from address Data output time from ASTB Data output time from delay time from ASTB
waits waits waits waits
Refreshing disabled Refreshing enabled waits Refreshing enabled Refreshing disabled waits Refreshing enabled waits
tDSTW2 Data setup time Data setup time Data hold time (from
Note
tSODWR tSODWF tHWOD tDWST tWWL1
ASTB delay time from
low-level width tWWL2 WAIT input time from address WAIT input time from ASTB tDAWT tDSTWT
Note
hold time includes time hold under load conditions
Remarks values above table based "fXX pF". parameter with SYMBOL column, refer "tCYX DEPENDENT TIMING DEFINITION" well.
µPD78217A, 78218A
READ/WRITE OPERATION (2/2)
PARAMETER WAIT hold time from ASTB WAIT delay time from ASTB WAIT input time from WAIT hold time from WAIT delay time from Data input time from WAIT delay time from WAIT delay time from WAIT WAIT input time from refresh disabled) WAIT hold time Refresh disabled from WAIT delay Refresh enabled Refresh disabled
SYMBOL tHSTWT tDSTWTH tDRWTL tHRWT tDRWTH tDWTID tDWTW tDWTR tDWWTL tHWWT1 tHWWT2 tDWWTH1 tDWWTH2 tDRRFQ tDWRFQ tWRFQL tDRFQST
TEST CONDITIONS external waits external waits
MIN.
MAX.
UNIT
external waits external waits
external waits external waits external waits external waits
time from Refresh enabled REFRQ delay time from REFRQ delay time from REFRQ low-level width ASTB delay time from REFRQ
Remarks
values above table based "fXX pF". parameter with SYMBOL column, refer "tCYX DEPENDENT TIMING DEFINITION" well.
µPD78217A, 78218A
SERIAL OPERATION
PARAMETER
SYMBOL Input
TEST CONDITIONS External clock Internal divided Output Internal divided Input External clock Internal divided Output Internal divided Input External clock Internal divided Internal divided
MIN.
MAX.
UNIT
Serial clock cycle time
tCYSK
Serial clock low-level width
tWSKL
Serial clock high-level width
tWSKH
Output
setup time SCK) hold time (from SCK)
tSSSK tHSSK tDSBSK1 CMOS push-pull output (3-wire serial mode) Open-drain output (SBI mode), tDSBSK2
SO/SB0 output delay time (from SCK)
mode
tCYX tCYX tCYX tCYX
high hold time (from SCK) setup time SCK) low-level width high-level width
tHSBSK tSSBSK tWSBL tWSBH
Remark
values above table based "fXX pF".
µPD78217A, 78218A
OTHER OPERATIONS
PARAMETER low-level width high-level width INTP0 INTP5 low-level width INTP0 INTP5 high-level width RESET low-level width RESET high-level width SYMBOL tWNIL tWNIH tWITL tWITH tWRSL tWRSH TEST CONDITIONS MIN. MAX. UNIT
tCYX tCYX
EXTERNAL CLOCK TIMING
PARAMETER input low-level width input high-level width input rise time input fall time input clock cycle time SYMBOL tWXL tWXH tCYX TEST CONDITIONS MIN. MAX. UNIT
CONVERTER CHRACTERISTICS AVSS
PARAMETER Resolution AVREF +70°C Overall error
Note1
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
AVREF +70°C AVREF
±1/2
tCYX
Quantization error tCYX (The "0") Conversion time tCONV tCYX (The "1") tCYX (The "0") Sampling time tSAMP tCYX (The "1")
tCYX
tCYX
-0.3 AVREF +0.3 1000
tCYX
Analog input voltage Analog input impedance Reference voltage AVREF current
VIAN
AVREF AIREF Note
Notes
Quantization error included. Represented ratio full-scale value. When register's STOP mode.
µPD78217A, 78218A
tCYX DEPENDENT TIMING DEFINITION (1/2)
PARAMETER input clock cycle time Address setup time ASTB) delay time from address Address float time (from Data input time from address Data input time from ASTB Data input time from delay time from ASTB Address active time from ASTB delay time from low-level width ASTB high-level width delay time from address Data output time from ASTB SYMBOL tCYX tSAST tDAR tFAR tDAID tDSTID tDRID tDSTR tDRA tDRST tWRL tWSTH tDAW tDSTOD tDSTW1 delay time from ASTB tDSTW2 2tCYX (Refreshing enabled) Data setup time Data setup time ASTB delay time from tSODWR tSODWF (Refreshing enabled) tDWST tWWL1 low-level width tWWL2 tCYX tCYX (Refreshing disabled) tCYX (Refreshing enabled) WAIT input time from address WAIT input time from ASTB tDAWT tDSTWT 3tCYX 2tCYX MAX. MAX. MIN.
Note
FORMULA
MIN./MAX. MIN.
Note
UNIT
tCYX 2tCYX tCYX/2 tCYX tCYX tCYX tCYX 2tCYX 2tCYX tCYX tCYX 2tCYX tCYX tCYX (Refreshing disabled)
MIN. MIN. MIN. MAX. MAX. MAX. MIN. MIN. MIN. MIN. MIN. MIN. MAX. MIN.
Note
Note
Note
MIN.
Note
tCYX tCYX
MIN. MIN. MIN. MIN.
Note
Remark Note
indicates number waits. When
µPD78217A, 78218A
tCYX DEPENDENT TIMING DEFINITION (2/2)
PARAMETER WAIT hold time from ASTB WAIT delay time from ASTB WAIT input time from WAIT hold time from WAIT delay time from Data input time from WAIT delay time from WAIT delay time from WAIT WAIT input time from refresh disabled) WAIT hold time Refresh disabled from WAIT delay Refresh enabled Refresh disabled SYMBOL tHSTWT tDSTWTH tDRWTL tHRWT tDRWTH tDWTID tDWTW tDWTR tDWWTL tHWWT1 tHWWT2 tDWWTH1 tDWWTH2 tDRRFQ tDWRFQ tWRFQL tDRFQST FORMULA 2XtCYX X)tCYX tCYX 1)tCYX 1)tCYX tCYX 2tCYX tCYX tCYX 1)tCYX 1)tCYX 1)tCYX 2XtCYX 2tCYX tCYX 2tCYX 4tCYX MIN./MAX. MIN. MAX. MAX. MIN. MAX. MAX. MIN. MIN. MAX. MIN. MIN. MAX. MAX. MIN. MIN. MIN. MIN.
Note Note
UNIT
Note Note
Note Note Note Note
time from Refresh enabled REFRQ delay time from REFRQ delay time from REFRQ low-level width ASTB delay time from REFRQ
Remarks Note
number external waits tCYX (fXX MHz) indicates number waits.
When
µPD78217A, 78218A
DATA RETENTION CHARACTERISTICS (TA=
PARAMETER Data retention voltage Data retention current rise time fall time hold time (from STOP mode setting) STOP release signal input time Oscillation stabilization wait time Low-level input voltage High-level input voltage
SYMBOL VDDDR IDDDR
TEST CONDITIONS STOP mode VDDDR VDDDR
MIN.
TYP.
MAX.
UNIT
tRVD tFVD tHVD
tDREL
Crystal resonator VDDDR VDDDR VDDDR
tWAIT Ceramic resonator Specified
Note
Note
RESET, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK, P26/INTP5, P27/SI, P32/SCK, P33/SO/SB0 pins.
Timing Test Point
DD-1 Test Points 0.45
µPD78217A, 78218A
Timing Waveform Read operation
tCYX
A8-A15 P60-P63 tDAR AD0-AD7 tSAST tHSTA tFAR tDSTID ASTB tWSTH tDSTR tDRID tWRL tDRST tHRID tDRA tDAID tHRA
Write operation
tCYX
A8-A15 P60-P63 tDAW AD0-AD7 tSAST tHSTA tDSTOD ASTB tWSTH tWWL1 tWWL2 tDSTW1 tDSTW2 tDWST tDWOD tSODWF tSODWR tHWOD tHWA
µPD78217A, 78218A
External WAIT Signal Input Timing Read operation
A8-A15 P60-P63
AD0-AD7
tDWTID ASTB tDSTWTH tHSTWT tDRWTH tHRWT tDSTWT tDAWT WAIT tDRWTL tDWTR
Write operation
A8-A15 P60-P63
AD0-AD7 tDWWTH1 tHWWT1 tDSTWTH tHSTWT tDWWTH2 tHWWT2 tDAWT WAIT tDWWTL tDSTWT tDWTW
ASTB
µPD78217A, 78218A
Refresh Timing Waveform Refresh after read
ASTB
tDRRFQ tDRFQST
REFRQ tWRFQL
Refresh after write
ASTB
tDWRFQ tDRFQST
REFRQ tWRFQL
µPD78217A, 78218A
Serial Operation 3-wire serial mode
tWSKL tWSKH
tCYSK tDSBSK1 Output Data tSSSK tHSSK
Input Data
Mode release signal transfer
tHSBSK tWSBL tWSBH tSSBSK
Command signal transfer
tWSKL tWSKH
tHSBSK tSSBSK tCYSK tDSBSK2 tSSSK tHSSK Data
µPD78217A, 78218A
Interrupt Input Timing
tWNIH tWNIL
tWITH
tWITL
INTP0-INTP5
Reset Input Timing
tWRSH
tWRSL
RESET
µPD78217A, 78218A
External Clock Timing
tWXH
tWXL
tCYX
Data Retention Characteristics
STOP Mode Setting
tHVD tFVD
VDDDR tDREL tWAIT tRVD
RESET
(Release Falling Edge)
(Release Rising Edge)
µPD78217A, 78218A
PACKAGE DRAWINGS
PLASTIC SHRINK (750 mil)
NOTE Each lead centerline located within 0.17 (0.007 inch) true position (T.P.) maximum material condition. Item center leads when formed parallel.
ITEM
MILLIMETERS 58.68 MAX. 1.78 MAX. 1.778 (T.P.) 0.50±0.10 MIN. 3.2±0.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 19.05 (T.P.) 17.0 0.25 +0.10 -0.05 0.17 0~15°
INCHES 2.311 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.126±0.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.750 (T.P.) 0.669 0.010 +0.004 -0.003 0.007 0~15° P64C-70-750A,C-1
Remark
versions have same package drawings same materials mass-produced versions.
µPD78217A, 78218A
PLASTIC
detail lead
P64GC-80-AB8-3 ITEM MILLIMETERS 17.6 14.0 14.0 17.6 0.35 0.10 0.15 (T.P.) 0.15+0.10 -0.05 0.10 2.55 2.85 MAX. INCHES 0.693 0.016 0.551+0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.039 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.071 0.008 0.031+0.009 -0.008 0.006+0.004 -0.003 0.004 0.100 0.004 0.004 0.112 MAX.
NOTE Each lead centerline located within 0.15 (0.006 inch) true position (T.P.) maximum material condition.
Remark
versions have same package drawings same materials mass-produced versions.
5°±5°
µPD78217A, 78218A
RECOMMENDED SOLDERING CONDITIONS
µPD78217A/78218A should soldered mounted under conditions recommended table below. detail recommended soldering conditions, refer information document "Semiconductor Device Mounting Technology Manual" (IEI-1207). soldering methods conditions other than those recommended below, contact sales representative. Table Surface Mounting Type Soldering Conditions
64-pin plastic
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: Reflow time: seconds less higher), Maximum number reflow processes: times <Cautions> After first reflow process, cool package down room temperature then start second reflow process. After first reflow process, water remove residual flux. Package peak temperature: Reflow time: seconds less higher), Maximum number reflow processes: times <Cautions> After first reflow process, cool package down room temperature then start second reflow process. After first reflow process, water remove residual flux. temperature: below, Heat time: seconds less (per each side device) VP15-00-2 Symbol IR35-00-2
Partial heating
Caution
Apply only kind soldering method device, except partial heating method.
Table Insertion Type Soldering Conditions
64-pin plastic shrink (750 mil)
Soldering Method Wave soldering (pin only) Partial heating
Soldering Conditions Solder temperature: below, Flow time: seconds less temperature: below, Heat time: seconds less (per pin)
Caution
wave soldering process must applied only pins, make sure that package body does soldered.
µPD78217A, 78218A
APPENDIX DEVELOPMENT TOOLS
following development tools available system development using PD78217A/78218A. Language Processing Software
RA78K/II Notes1, CC78K/II Notes1, CC78K/II-L Notes1,
78K/II series common assembler package 78K/II series common compiler package 78K/II series common compiler library source file
PROM Writing Tools
PG-1500 PA-78P214CW PA-78P214GC PG-1500 controller Notes1, PROM programmer Programmer adapters connected PG-1500
PG-1500 control program
Debugging Tools
IE-78240-R-A IE-78240-R Note4 IE-78200-R-BK IE-78240-R-EM IE-78200-R-EM Note4 EP-78210CW Note4 EP-78240CW-R EP-78210GC Note4 EP-78240GC-R EV-9200GC-64 SD78K/II Notes1, DF78210 Notes1,
µPD78218A subseries common in-circuit emulators
78K/II series common break board
µPD78218A subseries evaluation emulation boards µPD78218A subseries common emulation probes
Socket mounted user system board made 64-pin plastic IE-78240-R-A screen debugger
µPD78218A subseries device file
Fuzzy Inference Development Support System
FE9000 Note1, FE9200 Note5 FT9080 Note1, FT9085 Note2 FI78K/II Notes1, FD78K/II Notes1, Fuzzy knowledge data creation tool Translator Fuzzy inference module Fuzzy inference debugger
µPD78217A, 78218A
Notes PC-9800 series (MS-DOSTM) based PC/AT(PC DOSTM) based HP9000 series 300(HP-UXTM) based, SPARCstation(Sun OSTM) based, EWS-4800 series (EWS-UX/ based longer manufactured available purchase PC/AT WindowsTM) based
Remark
third-party development tools, 78K/II Series Development Tool Selection Guide (EF-231).
µPD78217A, 78218A
APPENDIX RELATED DOCUMENTS
Device Related Documents
Document Name Document (Japanese) IEU-755 IEU-754 IEA-607 IEA-700 IEA-686 IF-304 IEM-5101 IEM-5102 IEM-5532 Document (English) IEU-1313 IEU-1311 IEA-1220 IEA-1282 IEA-1273 IF-1160
µPD78218A Subseries User's Manual: Hardware
78K/II Series User's Manual: Instruction 78K/II Series Application Note Fundamentals Application Floating Point Operation Program 78K/II Series Selection Guide 78K/II Series Instruction Table 78K/II Series Instruction
µPD78218A Series Special Function Register Table
Development Tool Related Documents (User`s Manuals)
Document Name RA78K Series Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor CC78K Series Compiler Operation Language CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller IE-78240-R-A In-Circuit Emulator IE-78240-R In-Circuit Emulator Hardware Software SD78K/II Screen Debugger MS-DOS Based Introduction Reference SD78K/II Screen Debugger Based Introduction Reference 78K/II Series Development Tool Selection Guide EEU-956 EF-231 EEU-1447 Document (Japanese) EEU-809 EEU-815 EEU-817 EEU-656 EEU-655 EEU-777 EEU-651 EEU-704 EEU-796 EEU-705 EEU-706 EEU-841 EEU-813 EEU-1335 EEU-1291 EEU-1395 EEU-1322 EEU-1331 Document (English) EEU-1399 EEU-1404 EEU-1402 EEU-1280 EEU-1284
Caution
contents above related documents subject change without notice. latest documents should used design, etc.
µPD78217A, 78218A
Embedded Software Related Documents (User's Manuals)
Document Name RX78K/II Real-Time Basic Installation Debugger Technical Fuzzy Knowledge Data Creation Tool 78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System 78K/II Series Fuzzy Inference Development Support System 78K/II Series Fuzzy Inference Debugger Translator
Document (Japanese) EEU-910 EEU-884 EEU-895 EEU-885 EEU-829 EEU-862
Document (English)
EEU-1438 EEU-1444
Fuzzy Inference Module
EEU-860
EEU-1440
EEU-917
EEU-1459
Other Related Documents
Document Name QTOP Microcomputer Pamphlet Semiconductor Device Package Manual Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Devices Semiconductor Device Reliability Quality Control System Electrostatic Discharge (ESD) Test Guide Quality Assurance Semiconductor Devices Microcomputer-Related Products Guide Third Party Products Document (Japanese) IB-5040 IEI-635 IEI-616 IEI-620 IEM-5068 MEM-539 MEI-603 MEI-604 MEI-1202 IEI-1213 IEI-1207 IEI-1209 Document (English)
Caution
contents above related documents subject change without notice. latest documents should used design, etc.
µPD78217A, 78218A
[MEMO]
µPD78217A, 78218A
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must Semiconductor adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
µPD78217A, 78218A
export these products from Japan regulated Japanese government. export some these products prohibited without governmental license. export re-export some these products from country other than Japan also prohibited without license from that country. Please call sales representative. License needed: µPD78217ACW, 78217AGC-AB8 customer must judge need license: µPD78218ACW-xxx, 78218AGC-xxx-AB8
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customer must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact Sales Representative advance. Anti-radioactive design implemented this product.
94.11
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µPD78217A,78218A 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTI

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