ADF4110: MHz; ADF4111: GHz; ADF4112: GHz; ADF4113: power supply Separa

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ADF4110: MHz; ADF4111: GHz; ADF4112: GHz; ADF4113: power supply Separa

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Frequency Synthesizers ADF4110/ADF4111/ADF4112/ADF4113
ADF4110: MHz; ADF4111: GHz; ADF4112: GHz; ADF4113: power supply Separate charge pump supply (VP) allows extended tuning voltage systems Programmable dual-modulus prescaler 8/9, 16/17, 32/33, 64/65 Programmable charge pump currents Programmable antibacklash pulse width 3-wire serial interface Analog digital lock detect Hardware software power-down mode
ADF4110 family frequency synthesizers used implement local oscillators upconversion downconversion sections wireless receivers transmitters. They consist noise digital (phase frequency detector), precision charge pump, programmable reference divider, programmable counters, dual-modulus prescaler (P/P (6-bit) (13-bit) counters, conjunction with dual-modulus prescaler (P/P implement divider addition, 14-bit reference counter counter) allows selectable REFIN frequencies input. complete phase-locked loop (PLL) implemented synthesizer used with external loop filter voltage controlled oscillator (VCO). Control on-chip registers simple 3-wire interface. devices operate with power supply ranging from powered down when use.
APPLICATIONS
Base stations wireless radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANS Communications test equipment CATV equipment
AVDD DVDD
FUNCTIONAL BLOCK DIAGRAM
CPGND REFERENCE RSET
REFIN
14-BIT COUNTER COUNTER LATCH
PHASE FREQUENCY DETECTOR
CHARGE PUMP
DATA
24-BIT INPUT REGISTER
FUNCTION LATCH COUNTER LATCH
LOCK DETECT
CURRENT SETTING
CURRENT SETTING
SDOUT
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
FROM FUNCTION LATCH 13-BIT COUNTER LOAD LOAD 6-BIT COUNTER
HIGH AVDD MUXOUT
RFINA RFINB
SDOUT
PRESCALER
AGND DGND
Figure Functional Block Diagram Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 2004 Analog Devices, Inc. rights reserved.
03496-0-001
ADF4110/ADF4111 ADF4112/ADF4113
ADF4110/ADF4111/ADF4112/ADF4113 TABLE CONTENTS
Specifications. Timing Characteristics. Absolute Maximum Ratings. Transistor Count. Caution. Configurations Function Descriptions Typical Performance Characteristics Circuit Description. Reference Input Section. Input Stage. Prescaler (P/P Counters Counter Phase Frequency Detector (PFD) Charge Pump. Muxout Lock Detect. Input Shift Register Function Latch. Initialization Latch Device Programming after Initial Power-Up Resynchronizing Prescaler Output. Applications. Local Oscillator Base Station Transmitter Using Converter Drive RSET Pin. Shutdown Circuit Wideband Direct Conversion Modulator Interfacing Design Guidelines Chip Scale Package Outline Dimensions Ordering Guide.
REVISION HISTORY
3/04-Data sheet changed from Rev. Rev. Updated Format.Universal Changes Specifications Changes Figure Changes Ordering Guide. 3/03-Data sheet changed from Rev. Rev. Edits Specifications Updated OUTLINE DIMENSIONS 1/01-Data sheet changed from Rev. Rev. Changes Specifications Version, Chips, Unit, Test Conditions/Comments Columns. Changes Absolute Maximum Rating. Changes FRINA Function Test Changes Figure Graph Added-TPC Change Polarity Table Change Polarity Table Change Polarity Paragraph Addition Material (PCB Design Guidelines Chip-Scale package) Replacement CP-20 Outline with CP-20 Outline.
Rev. Page
ADF4110/ADF4111/ADF4112/ADF4113 SPECIFICATIONS
AVDD DVDD 10%, 10%; AVDD AGND DGND CPGND RSET referred TMIN TMAX, unless otherwise noted. Operating temperature range follows: Version: -40°C +85°C. Table
Parameter CHARACTERISTICS Input Sensitivity Input Frequency ADF4110 ADF4110 ADF4111 ADF4112 ADF4112 ADF4113 Maximum Allowable Prescaler Output Frequency2 CHARACTERISTICS Input Sensitivity Input Frequency ADF4110 ADF4111 ADF4112 ADF4113 ADF4113 Maximum Allowable Prescaler Output Frequency2 REFIN CHARACTERISTICS REFIN Input Frequency Reference Input Sensitivity REFIN Input Capacitance REFIN Input Current PHASE DETECTOR FREQUENCY4 CHARGE PUMP Sink/Source High Value Value Absolute Accuracy RSET Range 3-State Leakage Current Sink Source Current Matching Temperature LOGIC INPUTS VINH, Input High Voltage VINL, Input Voltage IINH/IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Voltage Version -15/0 80/550 50/550 0.08/1.2 0.2/3.0 0.1/3.0 0.2/3.7 Chips1 -15/0 80/550 50/550 0.08/1.2 0.2/3.0 0.1/3.0 0.2/3.7 Unit min/max min/max min/max min/max min/max min/max min/max lower frequencies, ensure slew rate (SR) V/µs. Input level dBm. lower frequencies, ensure V/µs. lower frequencies, ensure V/µs. Input level dBm. Input level dBm. lower frequencies, ensure V/µs. Test Conditions/Comments Figure input circuit.
-10/0 80/550 0.08/1.4 0.1/3.0 0.2/3.7 0.2/4.0 5/104 0.4/AVDD 3.0/AVDD ±100
-10/0 80/550 0.08/1.4 0.1/3.0 0.2/3.7 0.2/4.0 5/104 0.4/AVDD 3.0/AVDD ±100
min/max min/max min/max min/max min/max min/max min/max min/max min/max MHz, ensure V/µs. AVDD biased AVDD/2. Note AVDD biased AVDD/2. Note lower frequencies, ensure V/µs. lower frequencies, ensure V/µs. lower frequencies, ensure V/µs. lower frequencies, ensure V/µs. Input level
2.7/10 DVDD DVDD DVDD
2.7/10 DVDD DVDD DVDD
Programmable (see Table With RSET With RSET Table VP/2.
Rev. Page
ADF4110/ADF4111/ADF4112/ADF4113
Parameter POWER SUPPLIES AVDD DVDD IDD5 (AIDD DIDD) ADF4110 ADF4111 ADF4112 ADF4113 Power Sleep Mode NOISE CHARACTERISTICS ADF4113 Normalized Phase Noise Floor6 Phase Noise Performance7 ADF4110: Output8 ADF4111: Output9 ADF4112: Output9 ADF4113: Output9 ADF4111: Output10 ADF4112: 1750 Output11 ADF4112: 1750 Output12 ADF4112: 1960 Output13 ADF4113: 1960 Output13 ADF4113: 3100 Output14 Spurious Signals ADF4110: Output9 ADF4111: Output9 ADF4112: Output9 ADF4113: Output9 ADF4111: Output10 ADF4112: 1750 Output11 ADF4112: 1750 Output12 ADF4112: 1960 Output13 ADF4113: 1960 Output13 ADF4113: 3100 Output14 Version 2.7/5.5 AVDD AVDD/6.0 -215 -97/-106 -98/-110 -91/-100 -100/-110 -81/-84 -88/-90 -65/-73 -80/-84 -80/-84 -80/-82 Chips1 2.7/5.5 AVDD AVDD/6.0 -215 -97/-106 -98/-110 -91/-100 -100/-110 -81/-84 -88/-90 -65/-73 -80/-84 -80/-84 -82/-82 Unit min/V min/V dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz output offset frequency offset frequency offset frequency offset frequency offset frequency offset frequency offset frequency offset frequency offset frequency offset frequency kHz/400 frequency kHz/400 frequency kHz/400 frequency kHz/400 frequency kHz/60 frequency kHz/400 frequency kHz/20 frequency kHz/400 frequency kHz/400 frequency MHz/2 frequency AVDD Figure Figure typical typical typical typical 25°C Test Conditions/Comments
chip specifications given typical values. This maximum operating frequency CMOS counters. prescaler value should chosen ensure that input divided down frequency that less than this value. coupling ensures AVDD/2 bias. Figure typical circuit. Guaranteed design. 25°C; AVDD DVDD SYNC RFIN ADF4110 MHz; RFIN ADF4111, ADF4112, ADF4113 MHz. synthesizer phase noise floor estimated measuring in-band phase noise output VCO, TOT, subtracting 20logN (where divider value) 10logFPFD: PNSYNTH PNTOT 10logFPFD 20logN. phase noise measured with EVAL-ADF411xEB1 evaluation board HP8562E spectrum analyzer. spectrum analyzer provides REFIN synthesizer (fREFOUT dBm). SYNC (Table fREFIN MHz; fPFD kHz; offset frequency kHz; MHz; 2700; loop kHz. fREFIN MHz; fPFD kHz; offset frequency kHz; MHz; 4500; loop kHz. fREFIN MHz; fPFD kHz; offset frequency MHz; 27867; loop kHz. fREFIN MHz; fPFD kHz; offset frequency kHz; 1750 MHz; 8750; loop fREFIN MHz; fPFD kHz; offset frequency 1750 MHz; 175000; loop kHz. fREFIN MHz; fPFD kHz; offset frequency kHz; 1960 MHz; 9800; loop kHz. fREFIN MHz; fPFD MHz; offset frequency kHz; 3100 MHz; 3100; loop kHz.
Rev. Page
ADF4110/ADF4111/ADF4112/ADF4113 TIMING CHARACTERISTICS
Guaranteed design production tested. AVDD DVDD 10%, 10%; AVDD AGND DGND CPGND RSET TMIN TMAX, unless otherwise noted. Table
Parameter Limit TMIN TMAX Version) Unit Test Conditions/Comments DATA CLOCK setup time DATA CLOCK hold time CLOCK high duration CLOCK duration CLOCK setup time pulse width
CLOCK
DATA DB20 (MSB) DB19
(CONTROL (LSB) (CONTROL
03496-0-002
Figure Timing Diagram
Rev. Page
ADF4110/ADF4111/ADF4112/ADF4113 ABSOLUTE MAXIMUM RATINGS
25°C, unless otherwise noted Table
Parameter AVDD GND1 AVDD DVDD AVDD Digital Voltage Analog Voltage REFIN, RFINA, RFINB RFINA RFINB Operating Temperature Range Industrial Version) Storage Temperature Range Maximum Junction Temperature TSSOP Thermal Impedance LFCSP Thermal Impedance (Paddle Soldered) LFCSP Thermal Impedance (Paddle Soldered) Lead Temperature, Soldering Vapor Phase sec) Infrared sec) Rating -0.3 -0.3 +0.3 -0.3 -0.3 +5.5 -0.3 -0.3 -0.3 ±320 -40°C +85°C -65°C +150°C 150°C 150.4°C/W 122°C/W 216°C/W
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. This device high performance integrated circuit with rating sensitive. Proper precautions should taken handling assembly.
TRANSISTOR COUNT
6425 (CMOS) (Bipolar).
215°C 220°C
AGND DGND
CAUTION
(electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although this product features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
Rev. Page
ADF4110/ADF4111/ADF4112/ADF4113 CONFIGURATIONS FUNCTION DESCRIPTIONS
DVDD
RSET CPGND AGND RFINB RFINA AVDD REFIN
ADF4110 ADF4111 ADF4112 ADF4113
DVDD MUXOUT
CPGND AGND
MUXOUT DATA
AGND
DATA
ADF4110 ADF4111 ADF4112 ADF4113
VIEW (Not Scale)
DGND
AVDD
AVDD
REFIN
DGND
DGND
03496-0-003
VIEW (Not Scale)
RFINB RFINA
DVDD
RSET
Figure TSSOP Configuration
Figure LFCSP Configuration
Table Function Descriptions
TSSOP LFCSP Mnemonic RSET Function Connecting resistor between this CPGND sets maximum charge pump output current. nominal voltage potential RSET 0.56 relationship between RSET
CPmax
23.5
CPGND AGND RFINB RFINA AVDD
REFIN
DGND
DATA MUXOUT DVDD
with RSET ICPmax Charge Pump Output. When enabled, this provides ±ICP external loop filter, which turn drives external VCO. Charge Pump Ground. This ground return path charge pump. Analog Ground. This ground return path prescaler. Complementary Input Prescaler. This point should decoupled ground plane with small bypass capacitor, typically Figure Input Prescaler. This small-signal input ac-coupled from VCO. Analog Power Supply. This range from Decoupling capacitors analog ground plane should placed close possible this pin. AVDD must same value DVDD. Reference Input. This CMOS input with nominal threshold VDD/2, equivalent input resistance Figure This input driven from CMOS crystal oscillator, ac-coupled. Digital Ground. Chip Enable. logic this powers down device puts charge pump output into three-state mode. Taking high powers device depending status powerdown Serial Clock Input. This serial clock used clock serial data registers. data latched into 24-bit shift register rising edge. This input high impedance CMOS input. Serial Data Input. serial data loaded first with LSBs being control bits. This input high impedance CMOS input. Load Enable, CMOS Input. When goes high, data stored shift registers loaded into four latches; latch selected using control bits. This multiplexer output allows either lock detect, scaled scaled reference frequency accessed externally. Digital Power Supply. This range from Decoupling capacitors digital ground plane should placed close possible this pin. DVDD must same value AVDD. Charge Pump Power Supply. This should greater than equal VDD. systems where used drive with tuning range
Rev. Page
03496-0-004
ADF4110/ADF4111/ADF4112/ADF4113 TYPICAL PERFORMANCE CHARACTERISTICS
FREQ -UNIT FREQ 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 PARAM -TYPE MAGS11 0.89207 0.8886 0.89022 0.96323 0.90566 0.90307 0.89318 0.89806 0.89565 0.88538 0.89699 0.89927 0.87797 0.90765 0.88526 0.81267 0.90357 0.92954 0.92087 0.93788 DATA KEYWORD -FORMAT ANGS11 -2.0571 -4.4427 -6.3212 -2.1393 -12.13 -13.52 -15.746 -18.056 -19.693 -22.246 -24.336 -25.948 -28.457 -29.735 -31.879 -32.681 -31.522 -34.222 -36.961 -39.343 FREQ 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 IMPEDANCE -OHMS ANGS11 -40.134 -43.747 -44.393 -46.937 -49.6 -51.884 -51.21 -53.55 -56.786 -58.781 -60.545 -61.43 -61.241 -64.051 -66.19 -63.775
03496-0-005
OUTPUT POWER (dB)
REFERENCE LEVEL -4.2dBm
MAGS11 0.9512 0.93458 0.94782 0.96875 0.92216 0.93755 0.96178 0.94354 0.95189 0.97647 0.98619 0.95459 0.97945 0.98864 0.97399 0.97216
FREQUENCY 200kHz LOOP BANDWIDTH 20kHz RES. BANDWIDTH 10Hz VIDEO BANDWIDTH 10Hz SWEEP AVERAGES
-92.5dBc/Hz
Figure S-Parameter Data ADF4113 Input GHz)
-2.0kHz
-1.0kHz
900MHz FREQUENCY
1.0kHz
2.0kHz
Figure ADF4113 Phase Noise (900 MHz, 200kHz, kHz) with SYNC Enabled
PHASE NOISE (dBc/Hz)
-100 -110 -120 NOISE 0.52° -40dBc/Hz
INPUT POWER (dBm)
+25°C +85°C
-130
03496-0-006
100k
INPUT FREQUENCY (GHz)
FREQUENCY OFFSET FROM 900MHz CARRIER (Hz)
Figure Input Sensitivity (ADF4113)
Figure ADF4113 Integrated Phase Noise (900 MHz, kHz, kHz, Typical Lock Time:
OUTPUT POWER (dB)
REFERENCE LEVEL -4.2dBm
PHASE NOISE (dBc/Hz)
FREQUENCY 200kHz LOOP BANDWIDTH 20kHz RES. BANDWIDTH 10Hz VIDEO BANDWIDTH 10Hz SWEEP AVERAGES
-100 -110 -120 -130
03496-0-007 03496-0-010
NOISE 0.62° -40dBc/Hz
-91.0dBc/Hz
-100 -2.0kHz -1.0kHz 900MHz FREQUENCY 1.0kHz 2.0kHz
-140
100k
FREQUENCY OFFSET FROM 900MHz CARRIER (Hz)
Figure ADF4113 Phase Noise (900 MHz, kHz, kHz)
Figure ADF4113 Integrated Phase Noise (900 MHz, kHz, kHz, Typical Lock Time:
Rev. Page
03496-0-009
-40°C
-140
03496-0-008
-100
ADF4110/ADF4111/ADF4112/ADF4113
OUTPUT POWER (dB)
REFERENCE LEVEL -4.2dBm
PHASE NOISE (dBc/Hz)
FREQUENCY 200kHz LOOP BANDWIDTH 20kHz RES. BANDWIDTH 1kHz VIDEO BANDWIDTH 1kHz SWEEP 2.5s AVERAGES
-100 -110 -120 -130
03496-0-011 03496-0-014 03496-0-016 03496-0-015
NOISE 1.6° -40dBc/Hz
-90.2dBc/Hz
-100 -400kHz -200kHz 900MHz FREQUENCY 200kHz 400kHz
-140
100k
FREQUENCY OFFSET FROM 1750MHz CARRIER (Hz)
Figure ADF4113 Reference Spurs (900 MHz, kHz, kHz)
Figure ADF4113 Integrated Phase Noise (1750 MHz, kHz, kHz)
OUTPUT POWER (dB)
REFERENCE LEVEL -4.2dBm
OUTPUT POWER (dB)
FREQUENCY 200kHz LOOP BANDWIDTH 35kHz RES. BANDWIDTH 1kHz VIDEO BANDWIDTH 1kHz SWEEP 2.5s AVERAGES
03496-0-012
REFERENCE LEVEL -5.7dBm
FREQUENCY 30kHz LOOP BANDWIDTH 3kHz RES. BANDWIDTH VIDEO BANDWIDTH SWEEP 255s POSITIVE PEEK DETECT MODE
-79.6dBc/Hz
-89.3dBc/Hz
-100 -400kHz -200kHz 900MHz FREQUENCY 200kHz 400kHz
-100 -80kHz -40kHz 1750MHz FREQUENCY 40kHz 80kHz
Figure ADF4113 (900 MHz, kHz, kHz)
Figure ADF4113 Reference Spurs (1750 MHz, kHz, kHz)
OUTPUT POWER (dB)
REFERENCE LEVEL -8.0dBm FREQUENCY 30kHz LOOP BANDWIDTH 3kHz RES. BANDWIDTH 10kHz VIDEO BANDWIDTH 10kHz SWEEP 477ms AVERAGES
OUTPUT POWER (dB)
REFERENCE LEVEL -4.2dBm
FREQUENCY 1MHz LOOP BANDWIDTH 100kHz RES. BANDWIDTH 10Hz VIDEO BANDWIDTH 10Hz SWEEP 1.9s AVERAGES
-86.6dBc/Hz
-75.2dBc/Hz
-400Hz
-200Hz
1750MHz FREQUENCY
200Hz
400Hz
03496-0-013
-100
-100 -2.0kHz -1.0kHz 3100MHz FREQUENCY 1.0kHz 2.0kHz
Figure ADF4113 Phase Noise (1750 MHz, kHz, kHz)
Figure ADF4113 Phase Noise (3100 MHz, MHz, kHz)
Rev. Page
ADF4110/ADF4111/ADF4112/ADF4113
PHASE NOISE (dBc/Hz)
NOISE 1.7° 40dBc/Hz
PHASE NOISE (dBc/Hz)
-100 -110 -120 -130
03496-0-017
FREQUENCY OFFSET FROM 3100MHz CARRIER (Hz)
TEMPERATURE (°C)
Figure ADF4113 Integrated Phase Noise (3100 MHz, MHz, kHz)
OUTPUT POWER (dB)
Figure ADF4113 Phase Noise Temperature (900 MHz, kHz, kHz)
REFERENCE LEVEL -17.2dBm
FIRST REFERENCE SPUR (dBc)
FREQUENCY 1MHz LOOP BANDWIDTH 100kHz RES. BANDWIDTH 1kHz VIDEO BANDWIDTH 1kHz SWEEP AVERAGES
-80.6dBc/Hz
03496-0-018
-2.0MHz
-1.0MHz
3100MHz FREQUENCY
1.0MHz
2.0MHz
TEMPERATURE (°C)
Figure Reference Spurs (3100 MHz, MHz, kHz)
Figure ADF4113 Reference Spurs Temperature (900 MHz, kHz, kHz)
-120
-130
PHASE NOISE (dBc/Hz)
FIRST REFERENCE SPUR (dBc)
-140
-150
-160
-170
03496-0-019
1000
10000
PHASE DETECTOR FREQUENCY (kHz)
TUNING VOLTAGE
Figure ADF4113 Phase Noise (Referred Output) Phase Detector Frequency
Figure ADF4113 Reference Spurs (200 kHz) VTUNE (900 MHz, kHz, kHz)
Rev. Page
03496-0-022
-180
-105
03496-0-021
-100
-100
03496-0-020
-140
-100
ADF4110/ADF4111/ADF4112/ADF4113
PHASE NOISE (dBc/Hz)
DIDD (mA)
03496-0-023
TEMPERATURE (°C)
PRESCALER OUTPUT FREQUENCY (MHz)
Figure ADF4113 Phase Noise Temperature (836 MHz, kHz, kHz)
(mA)
Figure DIDD Prescaler Output Frequency (ADF4110, ADF4111, ADF4112, ADF4113)
FIRST REFERENCE SPUR (dBc)
03496-0-024
TEMPERATURE (°C)
Figure ADF4113 Reference Spurs Temperature (836 MHz, kHz, kHz)
AIDD (mA)
Figure Charge Pump Output Characteristics ADF4110 Family
ADF4113
16/17 PRESCALER VALUE 32/33 64/65 ADF4110 ADF4111
03496-0-025
ADF4112
Figure AIDD Prescaler Value
Rev. Page
03496-0-027
-100
03496-0-026
-100
ADF4110/ADF4111/ADF4112/ADF4113 CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
reference input stage shown Figure normally closed switches. normally open. When power-down initiated, closed opened. This ensures that there loading REFIN power-down.
COUNTERS
CMOS counters combine with dual-modulus prescaler allow wide ranging division ratio feedback counter. counters specified work when prescaler output less. Thus, with input frequency GHz, prescaler value 16/17 valid value not. Pulse Swallow Function counters, conjunction with dual-modulus prescaler, make possible generate output frequencies that spaced only reference frequency divided equation frequency fVCO A]fREFIN/R where: fVCO output frequency external voltage controlled oscillator (VCO) preset modulus dual-modulus prescaler preset divide ratio binary 13-bit counter(3 8191) preset divide ratio binary 6-bit swallow counter fREFIN output frequency external reference frequency oscillator preset divide ratio binary 14-bit programmable reference counter 16383)
POWER-DOWN CONTROL 100k COUNTER BUFFER
03496-0-028
REFIN
Figure Reference Input Stage
INPUT STAGE
input stage shown Figure followed two-stage limiting amplifier generate current mode logic (CML) clock levels needed prescaler.
BIAS GENERATOR RFINA RFINB
1.6V AVDD
COUNTER
14-bit counter allows input reference frequency divided down produce reference clock phase frequency detector (PFD). Division ratios from 16,383 allowed.
AGND
Figure Input Stage
FROM INPUT STAGE
03496-0-029
13-BIT COUNTER
PRESCALER (P/P
Along with counters, dual-modulus prescaler (P/P enables large division ratio, realized dual-modulus prescaler, operating levels, takes clock from input stage divides down manageable frequency CMOS counters. prescaler programmable; software 8/9, 16/17, 32/33, 64/65. based synchronous core.
PRESCALER MODULUS CONTROL
LOAD LOAD 6-BIT COUNTER
Figure Counters
Rev. Page
03496-0-030
ADF4110/ADF4111/ADF4112/ADF4113
PHASE FREQUENCY DETECTOR (PFD) CHARGE PUMP
takes inputs from counter counter produces output proportional phase frequency difference between them. Figure simplified schematic. includes programmable delay element that controls width antibacklash pulse. This pulse ensures that there dead zone transfer function minimizes phase noise reference spurs. bits reference counter latch, ABP2 ABP1, control width pulse. Table Lock Detect MUXOUT programmed types lock detect: digital lock detect analog lock detect. Digital lock detect active high. When counter latch digital lock detect high when phase error three consecutive phase detector (PD) cycles less than With five consecutive cycles less than required lock detect. stays high until phase error greater than detected subsequent cycle. N-channel open-drain analog lock detect should operated with nominal external pull-up resistor. When lock been detected, this output high with narrow lowgoing pulses.
CHARGE PUMP
DIVIDER CLR1
DVDD
PROGRAMMABLE DELAY
ABP1 CLR2 DIVIDER
ABP2
ANALOG LOCK DETECT DIGITAL LOCK DETECT COUNTER OUTPUT COUNTER OUTPUT SDOUT
CONTROL
MUXOUT
DGND
CPGND
Figure MUXOUT Circuit
DIVIDER
INPUT SHIFT REGISTER
ADF4110 family digital section includes 24-bit input shift register, 14-bit counter, 19-bit counter comprised 6-bit counter 13-bit counter. Data clocked into 24-bit shift register each rising edge first. Data transferred from shift register four latches rising edge destination latch determined state control bits (C2, shift register. These LSBs, DB0, shown Figure truth table these bits shown Table Table shows summary latches programmed.
DIVIDER
03496-0-031
OUTPUT
Figure Simplified Schematic Timing Lock)
MUXOUT LOCK DETECT
output multiplexer ADF4110 family allows user access various internal points chip. state MUXOUT controlled function latch. Table shows full truth table. Figure shows MUXOUT section block diagram form.
Table Truth Table
Control Bits Data Latch Counter Counter Function Latch (Including Prescaler) Initialization Latch
Rev. Page
03496-0-032
DOWN
ADF4110/ADF4111/ADF4112/ADF4113
Table ADF4110 Family Latch Summary
REFERENCE COUNTER LATCH
RESERVED LOCK DETECT PRECISION
SYNC
TEST MODE BITS
ANTIBACKLASH WIDTH DB16 DB15 DB14 DB13
14-BIT REFERENCE COUNTER, DB12 DB11 DB10
CONTROL BITS
DB23
DB22 DB21 SYNC
DB20 DB19
DB18 DB17
ABP2 ABP1
DON'T CARE
COUNTER LATCH
GAIN
RESERVED DB23 DB22
13-BIT COUNTER DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
6-BIT COUNTER
CONTROL BITS
DB21 DB20
DON'T CARE
FUNCTION LATCH
FASTLOCK MODE FASTLOCK ENABLE POLARITY
CURRENT SETTING DB20 DB19 CPI6 CPI5 CURRENT SETTING
PRESCALER VALUE DB23
TIMER COUNTER CONTROL
COUNTER RESET
POWERDOWN
POWERDOWN
THREESTATE
MUXOUT CONTROL
CONTROL BITS
DB22 DB21
DB18 DB17 CPI4 CPI3
DB16 DB15 DB14 DB13 DB12 DB11 CPI2 CPI1
DB10
INITIALIZATION LATCH
THREE-STATE FASTLOCK MODE FASTLOCK ENABLE POLARITY COUNTER RESET
POWERDOWN
PRESCALER VALUE DB23 DB22
CURRENT SETTING DB19 DB18 CPI5 CPI4
CURRENT SETTING DB17 DB16 CPI3 CPI2
TIMER COUNTER CONTROL DB13 DB12
POWERDOWN
MUXOUT CONTROL
CONTROL BITS
DB21 DB20 CPI6
DB15 DB14 CPI1
DB11 DB10
03496-0-033
Rev. Page
ADF4110/ADF4111/ADF4112/ADF4113
Table Reference Counter Latch
RESERVED LOCK DETECT PRECISION
SYNC
TEST MODE BITS DB19 DB18
ANTIBACKLASH WIDTH DB17 DB16 ABP2 ABP1 DB15 DB14 DB13 DB12
14-BIT REFERENCE COUNTER DB11 DB10
CONTROL BITS
DB23 DB22
DB21 DB20 SYNC
DON'T CARE ABP2 ABP1 ANTIBACKLASH PULSE WIDTH 3.0ns 1.5ns 6.0ns 3.0ns DIVIDE RATIO 16380 16381 16382 16383
TEST MODE BITS SHOULD NORMAL OPERATION
OPERATION THREE CONSECUTIVE CYCLES PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT SET. FIVE CONSECUTIVE CYCLES PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT SET.
SYNC
OPERATION NORMAL OPERATION OUTPUT PRESCALER RESYNCHRONIZED WITH NONDELAYED VERSION INPUT NORMAL OPERATION OUTPUT PRESCALER RESYNCHRONIZED WITH DELAYED VERSION INPUT
03496-0-034
Rev. Page
ADF4110/ADF4111/ADF4112/ADF4113
Table Counter Latch
GAIN
RESERVED DB23 DB22
13-BIT COUNTER DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
6-BIT COUNTER
CONTROL BITS
DB21 DB20
DON'T CARE COUNTER DIVIDE RATIO
COUNTER DIVIDE RATIO ALLOWED ALLOWED ALLOWED 8188 8189 8190 8191
(FUNCTION LATCH) FASTLOCK ENABLE*
GAIN
OPERATION CHARGE PUMP CURRENT SETTING PERMANENTLY USED. CHARGE PUMP CURRENT SETTING PERMANENTLY USED. CHARGE PUMP CURRENT SETTING USED. CHARGE PUMP CURRENT SWITCHED SETTING TIME SPENT SETTING DEPENDENT UPON WHICH FASTLOCK MODE USED. FUNCTION LATCH DESCRIPTION.
*SEE TABLE
PRESCALER VALUE FUNCTION LATCH, MUST GREATER THAN EQUAL CONTINUOUSLY ADJACENT VALUES FREF), OUTPUT, -P).
Rev. Page
03496-0-035
THESE BITS USED DEVICE DON'T CARE BITS
ADF4110/ADF4111/ADF4112/ADF4113
Table Function Latch
THREE-STATE FASTLOCK FASTLOCK ENABLE POLARITY
CURRENT SETTING DB19 DB18 CPI5 CPI4
CURRENT SETTING
PRESCALER VALUE
TIMER COUNTER CONTROL
MUXOUT CONTROL
CONTROL BITS
DB23
DB22 DB21 DB20
DB17 DB16
CPI3 CPI2
DB15 DB14 CPI1
DB13
DB12 DB11 DB10
CPI6
C2(1)
C1(0)
COUNTER OPERATION
NORMAL COUNTERS HELD RESET
PHASE DETECTOR POLARITY NEGATIVE POSITIVE
CHARGE PUMP OUTPUT NORMAL THREE-STATE
FASTLOCK MODE
FASTLOCK DISABLED FASTLOCK MODE FASTLOCK MODE
TIMEOUT (PFD CYCLES)
CPI6 CPI3 CPI5 CPI2 CPI4 CPI1
DIVIDER OUTPUT ANALOG LOCK DETECT (N-CHANNEL OPEN-DRAIN) SERIAL DATA OUTPUT DGND
OUTPUT
THREE-STATE OUTPUT DIGITAL LOCK DETECT (ACTIVE HIGH) DIVIDER OUTPUT DVDD
(mA)
2.7k 1.09 2.18 3.26 4.35 5.44 6.53 7.62 8.70
4.7k 0.63 1.25 1.88 2.50 3.13 3.75 4.38 5.00
0.29 0.59 0.88 1.76 1.47 1.76 2.06 2.35
FUNCTION LATCH, TIMER COUNTER CONTROL SECTION
MODE ASYNCHRONOUS POWER-DOWN NORMAL OPERATION ASYNCHRONOUS POWER-DOWN SYNCHRONOUS POWER-DOWN
PRESCALER VALUE 16/17 32/33 64/65
03496-0-036
Rev. Page
ADF4110/ADF4111/ADF4112/ADF4113
Table Initialization Latch
THREE-STATE FASTLOCK ENABLE POLARITY FASTLOCK
PRESCALER VALUE
CURRENT SETTING DB20
CPI6
CURRENT SETTING
TIMER COUNTER CONTROL
DB13 DB12
MUXOUT CONTROL
CONTROL BITS
DB23
DB22
DB21
DB19
CPI5
DB18
CPI4
DB17
CPI3
DB16
CPI2
DB15 DB14
CPI1
DB11 DB10
PHASE DETECTOR POLARITY
COUNTER OPERATION NORMAL COUNTERS HELD RESET
NEGATIVE POSITIVE
CHARGE PUMP OUTPUT NORMAL THREE-STATE
FASTLOCK MODE FASTLOCK DISABLED FASTLOCK MODE FASTLOCK MODE
CPI6 CPI3 CPI5 CPI2 CPI4 CPI1
(mA)
TIMEOUT (PFD CYCLES)
OUTPUT THREE-STATE OUTPUT DIGITAL LOCK DETECT (ACTIVE HIGH) DIVIDER OUTPUT DIVIDER OUTPUT ANALOG LOCK DETECT (N-CHANNEL OPEN-DRAIN) SERIAL DATA OUTPUT DGND
2.7k 1.09 2.18 3.27 4.35 5.44 6.53 7.62 8.70
4.7k 0.63 1.25 1.88 2.50 3.13 3.75 4.38 5.00
0.29 0.59 0.88 1.76 1.47 1.76 2.06 2.35
FUNCTION LATCH, TIMER COUNTER CONTROL SECTION
MODE ASYNCHRONOUS POWER-DOWN NORMAL OPERATION ASYNCHRONOUS POWER-DOWN SYNCHRONOUS POWER-DOWN
PRESCALER VALUE 16/17 32/33 64/65
03496-0-037
Rev. Page
ADF4110/ADF4111/ADF4112/ADF4113
FUNCTION LATCH
on-chip function latch programmed with Table shows input data format programming function latch. Counter Reset (F1) counter reset bit. When counter counters reset. normal operation, this should Upon powering must disabled, counter resumes counting "close" alignment with counter. (The maximum error prescaler cycle.) Power-Down (PD1) DB21 (PD2) ADF411x provide programmable power-down modes. They enabled pin. When low, device immediately disabled regardless states PD2, PD1. programmed asynchronous power-down, device powers down immediately after latching into PD1, provided been loaded with programmed synchronous power-down, device power-down gated charge pump prevent unwanted frequency jumps. Once power-down enabled writing into (provided also been loaded PD2), device goes into power-down next charge pump event. When power-down activated (either synchronous asynchronous mode including activated power-down), following events occur: active current paths removed. timeout counters forced their load state conditions. charge pump forced into three-state mode. digital clock detect circuitry reset. RFIN input debiased. reference input buffer circuitry disabled. input register remains active capable loading latching data. Fastlock Mode DB10 function latch fastlock enable bit. When fastlock enabled, this determines which fastlock mode used. fastlock mode fastlock mode selected; fastlock mode fastlock mode selected. Fastlock Mode charge pump current switched contents Current Setting device enters fastlock having written gain counter latch. device exits fastlock having written gain counter latch. Fastlock Mode charge pump current switched contents Current Setting device enters fastlock having written gain counter latch. device exits fastlock under control timer counter. After timeout period determined value through TC1, gain counter latch automatically reset device reverts normal mode instead fastlock. Table timeout periods. Timer Counter Control user option programming charge pump currents. Current Setting meant used when output stable system static state. Current Setting meant used when system dynamic state change (i.e., when output frequency programmed). normal sequence events follows: user initially decides what preferred charge pump currents going example, they choose Current Setting Current Setting same time, they must also decide long they want secondary current stay active before reverting primary current. This controlled timer counter control bits, DB14 through DB11 (TC4 through TC1) function latch. truth table given Table user program output frequency simply programming counter latch with values same time, gain which sets charge pump with value CPI6-CPI4 period determined through TC1. When this time charge pump current reverts value CPI3-CPI1. same time, gain counter latch reset ready next time user wishes change frequency.
MUXOUT Control on-chip multiplexer controlled ADF4110 family. Table shows truth table. Fastlock Enable function latch fastlock enable bit. Fastlock enables only when this
Rev. Page
ADF4110/ADF4111/ADF4112/ADF4113
Note that there enable feature timer counter. enabled when Fastlock Mode chosen setting fastlock mode (DB10) function latch Charge Pump Currents CPI3, CPI2, CPI1 program Current Setting charge pump. CPI6, CPI5, CPI4 program Current Setting charge pump. truth table given Table Prescaler Value function latch prescaler values. prescaler value should chosen that prescaler output frequency always less than equal MHz. Thus, with frequency GHz, prescaler value 16/17 valid value not. Polarity This sets phase detector polarity bit. Table Three-State This controls output pin. With high, output into three-state. With low, output enabled. When initialization latch loaded, following occurs: function latch contents loaded. internal pulse resets timeout counters load state conditions three-states charge pump. Note that prescaler band reference oscillator input buffer unaffected internal reset pulse, allowing close phase alignment when counting resumes. Latching first counter data after initialization word activates same internal reset pulse. Successive loads trigger internal reset pulse unless there another initialization. Apply VDD. Bring device into power-down. This asynchronous power-down that happens immediately. Program function latch (10). Program counter latch (00). Program counter latch (01). Bring high take device power-down. counters resume counting close alignment.
Method
INITIALIZATION LATCH
When initialization latch programmed. This essentially same function latch (programmed when However, when initialization latch programmed, additional internal reset pulse applied counters. This pulse ensures that counter load point when counter data latched, device begins counting close phase alignment. latch programmed synchronous power-down high; high; low), internal pulse also triggers this power-down. prescaler reference oscillator input buffer unaffected internal reset pulse, close phase alignment maintained when counting resumes. When first counter data latched after initialization, internal reset pulse again activated. However, successive counter loads after this will trigger internal reset pulse.
After goes high, duration required prescaler band voltage oscillator input buffer bias reach steady state. used power device down order check channel activity. input register does need reprogrammed each time device disabled enabled long been programmed least once after initially applied. Counter Reset Method Apply VDD. function latch load LSBs). part this, load bit. This enables counter reset. counter load LSBs). counter load LSBs). function latch load LSBs). part this, load bit. This disables counter reset.
DEVICE PROGRAMMING AFTER INITIAL POWER-UP
After initial power-up device, there three ways program device. Initialization Latch Method Apply VDD. Program initialization latch LSBs input word). Make sure programmed Then, load LSBs). Then load LSBs).
This sequence provides same close alignment initialization method. offers direct control over internal reset. Note that counter reset holds counters load point three states charge pump does trigger synchronous power-down. counter reset method requires extra function latch load compared initialization latch method.
Rev. Page
ADF4110/ADF4111/ADF4112/ADF4113
RESYNCHRONIZING PRESCALER OUTPUT
Table (the Reference Counter Latch Map) shows bits, DB22 DB21, which labeled SYNC, respectively. These bits affect operation prescaler. With SYNC prescaler output resynchronized with input. This effect reducing jitter prescaler lead overall improvement synthesizer phase noise performance. Typically, improvement seen ADF4113. lower bandwidth devices show even greater improvement. example, ADF4110 phase noise typically improved when SYNC enabled. With prescaler output resynchronized with delayed version input. SYNC feature used synthesizer, some care must taken. some point, certain temperatures output frequencies), delay through prescaler coincides with active edge input; this causes SYNC feature break down. important aware this when using SYNC feature. Adding delay signal, programming extends operating frequency temperature somewhat. Using SYNC feature also increases value AIDD device. With output, ADF4113 AIDD increases about when SYNC enabled additional enabled. typical performance plots this data sheet, except Figure apply SYNC i.e., resynchronization delay enabled.
Rev. Page
ADF4110/ADF4111/ADF4112/ADF4113 APPLICATIONS
LOCAL OSCILLATOR BASE STATION TRANSMITTER
Figure shows ADF4111/ADF4112/ADF4113 being used with produce base station transmitter. reference input signal applied circuit FREFIN and, this case, terminated typical system would have TCXO driving reference input without termination. order have channel spacing (GSM standard), reference input must divided using on-chip reference divider ADF4111/ ADF4112/ADF4113. charge pump output ADF4111/ADF4112/ADF4113 (Pin drives loop filter. calculating loop filter component values, number items need considered. this example, loop filter designed that overall phase margin system would degrees. Other system specifications MHz/V Loop Bandwidth FREF 4500 Extra Reference Spur Attenuation these specifications needed used come with loop filter component values shown Figure loop filter output drives VCO, which turn back input synthesizer. also drives output terminal. T-circuit configuration provides matching between output, output, RFIN terminal synthesizer. system, important know when system lock. Figure this accomplished using MUXOUT signal from synthesizer. MUXOUT programmed monitor various internal signals synthesizer. these lock-detect signal.
RFOUT
100pF
1000pF FREFIN
1000pF
AVDD DVDD REFIN
100pF
3.3k
5.6k
620pF
VCO190-902T
ADF4111 ADF4112 ADF4113
DATA RFINA
8.2nF LOCK DETECT 100pF
MUXOUT
COMPATIBLE SERIAL
RSET
CPGND
RFINB
AGND
4.7k
DGND
100pF
USED WHEN GENERATOR SOURCE IMPEDANCE 2OPTIONAL MATCHING RESISTOR DEPENDING FREQUENCY.
DECOUPLING CAPACITORS AVDD, DVDD, ADF411x POSITIVE SUPPLY VCO190-902T HAVE BEEN OMITTED FROM DIAGRAM INCREASE CLARITY.
Figure Local Oscillator Base Station
Rev. Page
03496-0-038
ADF4110/ADF4111/ADF4112/ADF4113
RFOUT 100pF
FREFIN
REFIN
LOOP FILTER
INPUT OUTPUT
100pF
ADF4111 ADF4112 ADF4113
DATA
RSET
MUXOUT
LOCK DETECT
100pF RFINA RFINB 100pF
2.7k
AD5320 12-BIT V-OUT
POWER SUPPLY CONNECTIONS DECOUPLING CAPACITORS OMITTED CLARITY.
03496-0-039
COMPATIBLE SERIAL
Figure Driving RSET with Converter
USING CONVERTER DRIVE RSET
converter used drive RSET ADF4110 family, thus increasing level control over charge pump current, ICP. This advantageous wideband applications where sensitivity varies over tuning range. compensate this, varied maintain good phase margin ensure loop stability. Figure
tuning range wide octave. example, cable tuners have total range about MHz. Figure shows application where ADF4113 used control program Micronetics M3500-2235. loop filter designed output 2900 MHz, loop bandwidth kHz, frequency MHz, (2.5 synthesizer multiplied gain factor MHz/V (sensitivity M3500-2235 output 2900 MHz), phase margin 45°C. narrow-band applications, there generally small variation output frequency (generally less than 10%) small variation sensitivity over range (typically 15%). However, wideband applications, both these parameters have much greater variation. Figure example, there -25% +17% variation output from nominal GHz. sensitivity vary from MHz/V 2750 MHz/V 3400 (+33%, -17%). Variations these parameters change loop bandwidth. This turn affect stability lock time. changing programmable ICP, possible compensation these varying loop conditions ensure that loop always operating close optimal conditions.
SHUTDOWN CIRCUIT
attached circuit Figure shows shut down both ADF4110 family accompanying VCO. ADG701 switch goes closed circuit when Logic applied input. cost switch available both SOT-23 MSOP packages.
WIDEBAND
Many wireless applications synthesizers VCOs PLLs narrow band nature. These applications include various wireless standards like GSM, DSC1800, CDMA, WCDMA. each these cases, total tuning range local oscillator less than MHz. However, there also wideband applications which local oscillator could have
Rev. Page
ADF4110/ADF4111/ADF4112/ADF4113
POWER-DOWN CONTROL
ADG701
RFOUT 100pF
FREFIN
AVDD DVDD REFIN RSET 4.7k
LOOP FILTER
100pF
ADF4110 ADF4111 ADF4112 ADF4113
100pF RFINA
CPGND
DGND
AGND
RFINB
100pF
03496-0-040
DECOUPLING CAPACITORS INTERFACE SIGNALS HAVE BEEN OMITTED FROM DIAGRAM INCREASE CLARITY.
Figure Local Oscillator Shutdown Circuit
RFOUT 100pF 100pF
FREFIN
AVDD DVDD 1000pF 1000pF REFIN
RSET
3.3k 2.8nF
4.7k
AD820
V_TUNE
M3500-2235
19nF
130pF
ADF4113
MUXOUT DATA RFINA 100pF LOCK DETECT
SPI-COMPATIBLE SERIAL
CPGND
RFINB
DGND
AGND
100pF
DECOUPLING CAPACITORS AVDD, DVDD, ADF4113 M3500-2250 HAVE BEEN OMITTED FROM DIAGRAM CLARITY.
Figure Wideband Phase-Locked Loop
Rev. Page
03496-0-041
ADF4110/ADF4111/ADF4112/ADF4113
DIRECT CONVERSION MODULATOR
some applications, direct conversion architecture used base station transmitters. Figure shows combination available from implement this solution. circuit diagram shows AD9761 being used with AD8346. dual integrated DACs such AD9761 with specified ±0.02 ±0.004 gain offset matching characteristics ensures minimum error contribution (over temperature) from this portion signal chain. local oscillator (LO) implemented using ADF4113. this case, 3B1-13M0 provides stable reference frequency. system designed channel spacing output center frequency 1960 MHz. target application WCDMA base station transmitter. Typical phase noise performance from this dBc/Hz offset. port AD8346 driven single-ended fashion. LOIN ac-coupled ground with capacitor; LOIP driven through coupling capacitor from source. drive level between required. circuit Figure gives typical level dBm. output designed drive load must accoupled shown Figure inputs driven quadrature signals, resulting output power around dBm.
REFIO MODULATED DIGITAL DATA
IOUTA IOUTB
LOW-PASS FILTER
IBBP IBBN VOUT
100pF RFOUT
AD9761 TxDAC
QOUTA QOUTB LOW-PASS FILTER QBBP QBBN
AD8346
LOIN
LOIP 100pF
4.7k 3B1-13M0 TCXO REFIN RSET
910pF
100pF
3.3k 3.9k 620pF 9.1nF RFINB RFINA 100pF
POWER SUPPLY CONNECTIONS DECOUPLING CAPACITORS OMITTED FROM DIAGRAM INCREASE CLARITY. VCO190-1960T
100pF
SERIAL DIGITAL INTERFACE
ADF4113
100pF
Figure Direct Conversion Transmitter Solution
Rev. Page
03496-0-042
ADF4110/ADF4111/ADF4112/ADF4113
INTERFACING
ADF4110 family simple SPI® compatible serial interface writing device. SCLK, SDATA, control data transfer. When latch enable (LE) goes high, bits that have been clocked into input register each rising edge SCLK transferred appropriate latch. Figure timing diagram Table latch truth table. maximum allowable serial clock rate MHz. This means that maximum update rate possible device kHz, update every This certainly more than adequate systems that have typical lock times hundreds microseconds. ADuC812 Interface Figure shows interface between ADF4110 family ADuC812 MicroConverter®. Since ADuC812 based 8051 core, this interface used with 8051 based microcontroller. MicroConverter master mode with CPHA initiate operation, port driving brought low. Each latch ADF4110 family needs 24-bit word. This accomplished writing three 8-bit bytes from MicroConverter device. When third byte been written, input should brought high complete transfer. When power first applied ADF4110 family, three writes needed (one each counter latch, counter latch, initialization latch) output become active. port lines ADuC812 also used control powerdown input), detect lock (MUXOUT configured lock detect polled port input). When ADuC812 operating mode described above, maximum SCLOCK rate ADuC812 MHz. This means that maximum rate which output frequency changed kHz. ADSP-2181 Interface Figure shows interface between ADF4110 family ADSP-21xx digital signal processor. ADF4110 family needs 24-bit serial word each latch write. easiest accomplish this using ADSP-21xx family auto buffered transmit mode operation with alternate framing. This provides means transmitting entire block serial data before interrupt generated.
SCLK SCLK SDATA
ADSP-21xx
FLAGS
ADF4110 ADF4111 ADF4112 ADF4113
03496-0-044
MUXOUT (LOCK DETECT)
Figure ADSP-21xx ADF4110 Family Interface
word length bits three memory locations each 24-bit word. program each 24-bit latch, store three 8-bit bytes, enable auto buffered mode, then write transmit register DSP. This last operation initiates autobuffer transfer.
DESIGN GUIDELINES CHIP SCALE PACKAGE
lands chip scale package (CP-20) rectangular. printed circuit board these should longer than package land length 0.05 wider than package land width. land should centered pad. This ensures that solder joint size maximized. bottom chip scale package central thermal pad. thermal printed circuit board should least large this exposed pad. printed circuit board, there should clearance least 0.25 between thermal inner edges pattern. This ensures that shorting avoided. Thermal vias used printed circuit board thermal improve thermal performance package. vias used, they should incorporated thermal pitch grid. diameter should between 0.33 barrel should plated with copper plug via. user should connect printed circuit board thermal AGND.
SCLOCK
SCLK SDATA
ADuC812
MOSI
PORTS
ADF4110 ADF4111 ADF4112 ADF4113
03496-0-043
MUXOUT (LOCK DETECT)
Figure ADuC812 ADF4110 Family Interface
Rev. Page
ADF4110/ADF4111/ADF4112/ADF4113 OUTLINE DIMENSIONS
0.60 INDICATOR VIEW 3.75 0.75 0.55 0.35 1.00 0.85 0.80 SEATING PLANE 0.50 0.80 0.65 0.05 0.02 0.20 COPLANARITY 0.08
0.60
BOTTOM VIEW
2.25 2.10 1.95
0.25 0.30 0.23 0.18
COMPLIANT JEDEC STANDARDS MO-220-VGGD-1
Figure 20-Lead Lead Frame Chip Scale Package [LFCSP] (CP-20-1) Dimensions shown millimeters
5.10 5.00 4.90
4.50 4.40 4.30
6.40
1.20 0.20 0.09 0.65 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 0.75 0.60 0.45
0.15 0.05
COMPLIANT JEDEC STANDARDS MO-153AB
Figure 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown millimeters
Rev. Page
ADF4110/ADF4111/ADF4112/ADF4113 ORDERING GUIDE
Model ADF4110BRU ADF4110BRU-REEL ADF4110BRU-REEL7 ADF4110BCP ADF4110BCP -REEL ADF4110BCP-REEL7 ADF4111BRU ADF4111BRU-REEL ADF4111BRU-REEL7 ADF4111BCP ADF4111BCP-REEL ADF4111BCP-REEL7 ADF4112BRU ADF4112BRU-REEL ADF4112BRU-REEL7 ADF4112BRUZ1 ADF4112BRUZ1-REEL ADF4112BRUZ1-REEL7 ADF4112BCP ADF4112BCP-REEL ADF4112BCP-REEL7 ADF4113BRU ADF4113BRU-REEL ADF4113BRU-REEL7 ADF4113BRUZ1 ADF4113BRUZ1-REEL ADF4113BRUZ1-REEL7 ADF4113BCP ADF4113BCP-REEL ADF4113BCP-REEL7 ADF4113BCHIPS EVAL-ADF4112EB1 EVAL-ADF4113EB1 EVAL-ADF4113EB2 EVAL-ADF411XEB1 Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C Package Description Thin Shrink Small Outline Package Thin Shrink Small Outline Package Thin Shrink Small Outline Package Lead Frame Chip Scale Package Lead Frame Chip Scale Package Lead Frame Chip Scale Package Thin Shrink Small Outline Package Thin Shrink Small Outline Package Thin Shrink Small Outline Package Lead Frame Chip Scale Package Lead Frame Chip Scale Package Lead Frame Chip Scale Package Thin Shrink Small Outline Package Thin Shrink Small Outline Package Thin Shrink Small Outline Package Thin Shrink Small Outline Package Thin Shrink Small Outline Package Thin Shrink Small Outline Package Lead Frame Chip Scale Package Lead Frame Chip Scale Package Lead Frame Chip Scale Package Thin Shrink Small Outline Package Thin Shrink Small Outline Package Thin Shrink Small Outline Package Thin Shrink Small Outline Package Thin Shrink Small Outline Package Thin Shrink Small Outline Package Lead Frame Chip Scale Package Lead Frame Chip Scale Package Lead Frame Chip Scale Package Evaluation Board Evaluation Board Evaluation Board Evaluation Board Package Option RU-16 RU-16 RU-16 CP-20 CP-20 CP-20 RU-16 RU-16 RU-16 CP-20 CP-20 CP-20 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 CP-20 CP-20 CP-20 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 CP-20 CP-20 CP-20
Pb-free part.
Purchase licensed components Analog Devices sublicensed Associated Companies conveys license purchaser under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips.
2004 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners. C03496-0-3/04(C)
Rev. Page

ADF4110: MHz; ADF4111: GHz; ADF4112: GHz; ADF4113: power supply Separa

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