ADF4116: ADF4117: ADF4118: power supply Separate allows extended tunin

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ADF4116: ADF4117: ADF4118: power supply Separate allows extended tunin

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Frequency Synthesizers ADF4116/ADF4117/ADF4118
ADF4116: ADF4117: ADF4118: power supply Separate allows extended tuning voltage systems Grade: -40°C +125° Dual modulus prescaler ADF4116: ADF4117/ADF4118: 32/33 3-wire serial interface Digital lock detect Power-down mode Fastlock mode
ADF4116 family frequency synthesizers used implement local oscillators (LO) upconversion downconversion sections wireless receivers transmitters. They consist low-noise digital phase frequency detector (PFD), precision charge pump, programmable reference divider, programmable counters, dual-modulus prescaler (P/P (5-bit) (13-bit) counters, conjunction with dual-modulus prescaler (P/P implement divider addition, 14-bit reference counter counter) allows selectable REFIN frequencies input. complete phase-locked loop (PLL) implemented synthesizer used with external loop filter voltage controlled oscillator (VCO). on-chip registers controlled simple 3-wire interface. devices operate with power supply ranging from powered down when use.
APPLICATIONS
Base stations wireless radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANs Communications test equipment CATV equipment
AVDD DVDD
FUNCTIONAL BLOCK DIAGRAM
CPGND REFERENCE
ADF4116/ADF4117/ADF4118
REFIN 14-BIT COUNTER COUNTER LATCH DATA 21-BIT INPUT REGISTER FUNCTION LATCH COUNTER LATCH LOCK DETECT
PHASE FREQUENCY DETECTOR
CHARGE PUMP
SDOUT FROM FUNCTION LATCH RFINA RFINB
AVDD
HIGH
13-BIT COUNTER LOAD LOAD 5-BIT COUNTER
MUXOUT
SDOUT
PRESCALER
SWITCH
00392-001
AGND DGND
Figure
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 2005 Analog Devices, Inc. rights reserved.
ADF4116/ADF4117/ADF4118 TABLE CONTENTS
Features Applications. Functional Block Diagram Revision History Specifications. Timing Characteristics Absolute Maximum Ratings. Transistor Count. Caution. Configuration Function Descriptions. Typical Performance Characteristics Circuit Description. Reference Input Section. Input Stage. Prescaler (P/P Counters Counter Phase Frequency Detector (PFD) Charge Pump. MUXOUT Lock Detect. Input Shift Register Function Latch. Counter Reset Power-Down MUXOUT Control. Phase Detector Polarity Charge Pump Three-State. Fastlock Enable Fastlock Mode Bit. Timer Counter Control Initialization Latch Device Programming after Initial Power-Up Applications. Local Oscillator Base Station Transmitter. Shutdown Circuit Direct Conversion Modulator Interfacing Outline Dimensions Ordering Guide
REVISION HISTORY
11/05-Rev. Rev. Changes Table Changes Table Changes Table Changes Table Changed 3B1-13M0 FOX801BH-130 Changes Ordering Guide 9/04-Rev. Rev. Changes Specifications Changes Ordering Guide 3/01-Rev. Rev. 4/00-Rev. Initial Version
Rev. Page
ADF4116/ADF4117/ADF4118 SPECIFICATIONS
AVDD DVDD 10%, 10%; AVDD AGND DGND CPGND TMIN TMAX, unless otherwise noted; referred Table
Parameter CHARACTERISTICS Input Sensitivity Input Frequency ADF4116 ADF4116 ADF4117 ADF4118 ADF4118 Maximum Allowable Prescaler Output Frequency REFIN CHARACTERISTICS Reference Input Frequency Reference Input Sensitivity REFIN Input Capacitance REFIN Input Current PHASE DETECTOR FREQUENCY CHARGE PUMP Sink/Source High Value Value Absolute Accuracy Three-State Leakage Current Sink Source Current Matching Temperature LOGIC INPUTS VINH, Input High Voltage VINL, Input Voltage IINH/IINL, Input Current CIN, Input Capacitance Reference Input Current LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Voltage Version -15/0 -10/0 80/550 45/550 0.1/1.2 0.1/3.0 0.2/3.0 5/100 0.4/AVDD 3.0/AVDD ±100 Version -10/0 -10/0 Unit min/max min/max min/max min/max min/max min/max min/max min/max min/max min/max Test Conditions/Comments AVDD AVDD Figure input circuit Input level dBm; lower frequencies, ensure slew rate (SR) Input level Input level AVDD, DVDD AVDD, DVDD MHz, ensure AVDD biased AVDD/2 AVDD biased AVDD/2
0.1/3.0 5/100 0.4/AVDD 3.0/AVDD ±100
DVDD DVDD ±100 DVDD
DVDD DVDD DVDD-
VP/2
Rev. Page
ADF4116/ADF4117/ADF4118
Parameter POWER SUPPLIES AVDD DVDD (AIDD DIDD) ADF4116 ADF4117 ADF4118 Low-Power Sleep Mode NOISE CHARACTERISTICS ADF4118 Normalized Phase Noise Floor Phase Noise Performance ADF4116 Output ADF4117 Output ADF4118 Output10 ADF4117 Output ADF4118 1750 Output ADF4118 1750 Output ADF4118 1960 Output Spurious Signals ADF4116 Output10 ADF4117 Output10 ADF4118 Output ADF4117 Output11 ADF4118 1750 Output12 ADF4118 1750 Output13 ADF4118 1960 Output14
Version 2.7/5.5 AVDD AVDD/6.0 -213 -88/-99 -90/-104 -91/-100 -80/-84 -88/-90 -65/-73 -80/-86
Version 2.7/5.5 AVDD AVDD/6.0
Unit min/V min/V dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
Test Conditions/Comments
AVDD typical typical typical 25°C
-213 -88/-99 -90/-104 -91/-100 -80/-84 -88/-90 -65/-73 -80/-86
output offset frequency offset frequency offset frequency offset frequency offset frequency offset frequency offset frequency kHz/400 frequency kHz/400 frequency kHz/400 frequency kHz/60 frequency kHz/400 frequency kHz/20 frequency kHz/400 frequency
Operating temperature range version -40°C +85°C. Operating temperature range version -40°C +125°C. This maximum operating frequency CMOS counters. coupling ensures AVDD/2 bias. Figure typical circuit. Guaranteed design. Sample tested ensure compliance. 25°C; AVDD DVDD RFIN ADF4116 MHz; RFIN ADF4117, ADF4118 MHz. synthesizer phase noise floor estimated measuring in-band phase noise output VCO, TOT, subtracting 20logN (where divider value) 10logFPFD: PNSYNTH PNTOT 10logFPFD 20logN. phase noise measured with EVAL-ADF411xEB Evaluation Board HP8562E Spectrum Analyzer. spectrum analyzer provides REFIN synthesizer (fREFOUT dBm). fREFIN MHz; fPFD kHz; offset frequency kHz; MHz; 2700; loop bandwidth kHz. fREFIN MHz; fPFD kHz; offset frequency kHz; MHz; 4500; loop bandwidth kHz. fREFIN MHz; fPFD kHz; offset frequency MHz; 27867; loop bandwidth kHz. fREFIN MHz; fPFD kHz; offset frequency kHz; 1750 MHz; 8750; loop bandwidth kHz. fREFIN MHz; fPFD kHz; offset frequency 1750 MHz; 175000; loop bandwidth kHz. fREFIN MHz; fPFD kHz; offset frequency kHz; 1960 MHz; 9800; loop bandwidth kHz.
Rev. Page
ADF4116/ADF4117/ADF4118
TIMING CHARACTERISTICS
AVDD DVDD 10%, 10%; AVDD AGND DGND CPGND TMIN TMAX, unless otherwise noted. Guaranteed design, production tested. Table
Parameter Limit TMIN TMAX Version) Unit Test Conditions/Comments DATA CLOCK setup time DATA CLOCK hold time CLOCK high duration CLOCK duration CLOCK setup time pulse width
CLOCK
DATA DB20 (MSB) DB19
(CONTROL (LSB) (CONTROL
00392-002
Figure Timing Diagram
Rev. Page
ADF4116/ADF4117/ADF4118 ABSOLUTE MAXIMUM RATINGS
25°C, unless otherwise noted. Table
Parameter AVDD GND1 AVDD DVDD AVDD Digital Voltage Analog Voltage REFIN, RFINA, RFINB RFINA RFINB Operating Temperature Range Industrial Version) Extended Version) Storage Temperature Range Maximum Junction Temperature TSSOP Thermal Impedance Reflow Soldering Peak Temperature Time Peak Temperature Transistor Count CMOS Bipolar
Rating -0.3 -0.3 +0.3 -0.3 -0.3 +5.5 -0.3 -0.3 -0.3 ±320 -40°C +85°C -40°C +125°C -65°C +150°C 150°C 112°C/W 260°C 6425
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. This device high performance integrated circuit with rating sensitive. Proper precautions should taken handling assembly.
TRANSISTOR COUNT
6425 (CMOS) (bipolar).
AGND DGND
CAUTION
(electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although this product features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
Rev. Page
ADF4116/ADF4117/ADF4118 CONFIGURATION FUNCTION DESCRIPTIONS
CPGND AGND RFINB RFINA AVDD REFIN
DVDD
ADF4116/ ADF4117/ ADF4118
VIEW (Not Scale)
MUXOUT DATA
DGND
Figure Configuration
Table Function Descriptions
Mnemonic CPGND AGND RFINB RFINA AVDD REFIN Description Fast Lock Switch Output. This used switch external resistor change loop filter bandwidth speed locking PLL. Charge Pump Output. When enabled, this provides external loop filter, which turn drives external VCO. Charge Pump Ground. This ground return path charge pump. Analog Ground. This ground return path prescaler. Complementary Input Prescaler. This point should decoupled ground plane with small bypass capacitor, typically Figure Input Prescaler. This small signal input ac-coupled from VCO. Analog Power Supply. This range from Decoupling capacitors analog ground plane should placed close possible this pin. AVDD must have same value DVDD. Reference Input. This CMOS input with nominal threshold VDD/2 equivalent input resistance Figure oscillator input driven from CMOS crystal oscillator, ac-coupled. Digital Ground. Chip Enable. logic this powers down device puts charge pump output into three-state mode. Taking high powers device depending status power-down Serial Clock Input. This serial clock used clock serial data registers. data latched into 21-bit shift register rising edge. This input high impedance CMOS input. Serial Data Input. serial data loaded first with LSBs control bits. This input high impedance CMOS input. Load Enable, CMOS Input. When goes high, data stored shift registers loaded into four latches, latch being selected using control bits. This multiplexer output allows either lock detect, scaled scaled reference frequency accessed externally. Digital Power Supply. This range from Decoupling capacitors digital ground plane should placed close possible this pin. DVDD must have same value AVDD. Charge Pump Power Supply. This should greater than equal VDD. systems where this supply used drive with tuning range
DGND DATA MUXOUT DVDD
Rev. Page
00392-003
ADF4116/ADF4117/ADF4118 TYPICAL PERFORMANCE CHARACTERISTICS
FREQ- PARAM-TYPE DATA-FORMAT KEYWORD IMPEDANCEUNIT OHMS FREQ 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 MagS11 0.89207 0.8886 0.89022 0.96323 0.90566 0.90307 0.89318 0.89806 0.89565 0.88538 0.89699 0.89927 0.87797 0.90765 0.88526 0.81267 0.90357 0.92954 AngS11 -2.0571 -4.4427 -6.3212 -2.1393 -12.13 -13.52 -15.746 -18.056 -19.693 -22.246 -24.336 -25.948 -28.457 -29.735 -31.879 -32.681 -31.522 -34.222 FREQ 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 MagS11 0.92087 0.93788 0.9512 0.93458 0.94782 0.96875 0.92216 0.93755 0.96178 0.94354 0.95189 0.97647 0.98619 0.95459 0.97945 0.98864 0.97399 0.97216 AngS11 -36.961 -39.343 -40.134 -43.747 -44.393 -46.937 -49.6 -51.884 -51.21 -53.55 -56.786 -58.781 -60.545 -61.43 -61.241 -64.051 -66.19 -63.775
PHASE NOISE (dBc/Hz)
10dB/DIVISION
-40dBc/Hz
NOISE 0.64°
0.64° -100 -110 -120 -130
00392-004 00392-007
-140 100Hz
FREQUENCY OFFSET FROM 900MHz CARRIER
1MHz
Figure S-Parameter Data ADF4118 Input GHz)
Figure ADF4118 Integrated Phase Noise MHz, kHz, kHz, Typical Lock Time:
10dB/DIVISION 0.575° -40dBc/Hz NOISE 0.575°
INPUT POWER (dBm)
PHASE NOISE (dBc/Hz)
00392-005
-40°C +85°C +25°C INPUT FREQUENCY (GHz)
-100 -110 -120 -130 -140 100Hz
00392-008
FREQUENCY OFFSET FROM 900MHz CARRIER
1MHz
Figure Input Sensitivity (ADF4118)
Figure ADF4118 Integrated Phase Noise MHz, kHz, kHz, Typical Lock Time:
REFERENCE LEVEL -3.8dBm
OUTPUT POWER (dB)
REFERENCE LEVEL -4.2dBm
FREQUENCY 200kHz
OUTPUT POWER (dB)
00392-006
FREQUENCY 200kHz LOOP BANDWIDTH 20kHz RES. BANDWIDTH 1kHz VIDEO BANDWIDTH 1kHz SWEEP SECONDS AVERAGES
LOOP BANDWIDTH 20kHz RES. BANDWIDTH 10Hz VIDEO BANDWIDTH 10Hz SWEEP SECONDS AVERAGES -90.2dBc/Hz
-91.5dBc
00392-009
-100 -400kHz -200kHz 900MHz +200kHz +400kHz
-100
-2kHz
-1kHz
900MHz
+1kHz
+2kHz
Figure ADF4118 Phase Noise MHz, kHz,
Figure ADF4118 Reference Spurs MHz, kHz,
Rev. Page
ADF4116/ADF4117/ADF4118
REFERENCE LEVEL -4.2dBm FREQUENCY 200kHz LOOP BANDWIDTH 35kHz OUTPUT POWER (dB) RES. BANDWIDTH 1kHz VIDEO BANDWIDTH 1kHz SWEEP SECONDS -90.67dBc
00392-010
REFERENCE LEVEL -7.0dBm
FREQUENCY 30kHz LOOP BANDWIDTH 5kHz RES. BANDWIDTH 300Hz VIDEO BANDWIDTH 300Hz SWEEP 4.2ms AVERAGES -72.3dBc
OUTPUT POWER (dB)
AVERAGES
00392-013
-100 -400kHz -200kHz 900MHz +200kHz +400kHz
-100
-60kHz
-30kHz
1750MHz
+30kHz
+60kHz
Figure ADF4118 Reference Spurs MHz, kHz,
OUTPUT POWER (dB) -71.5dBc/Hz
00392-011
Figure ADF4118 Reference Spurs 1750 MHz, kHz,
REFERENCE LEVEL -10.3dBm FREQUENCY 1MHz LOOP BANDWIDTH 100kHz RES. BANDWIDTH 10Hz VIDEO BANDWIDTH 10Hz SWEEP SECONDS -100 -2kHz -1kHz 2800MHz +1kHz +2kHz
00392-014
REFERENCE LEVEL -7.0dBm
FREQUENCY 30kHz LOOP BANDWIDTH 5kHz RES. BANDWIDTH 10kHz VIDEO BANDWIDTH 10kHz SWEEP 477ms AVERAGES
OUTPUT POWER (dB)
AVERAGES -85.2dBc/Hz
-100 -400kHz -200kHz 1750MHz +200kHz +400kHz
Figure ADF4118 Phase Noise 1750 MHz, kHz,
10dB/DIVISION 2.0°
Figure ADF4118 Phase Noise 2800 MHz, MHz,
NOISE 2.0°
10dB/DIVISION 1.55° -40dBc/Hz NOISE 1.552°
-40dBc/Hz
PHASE NOISE (dBc/Hz)
-100 -110 -120
00392-012
PHASE NOISE (dBc/Hz)
-100 -110 -120 -130 -140 100Hz
00392-015
-130 -140 100Hz
FREQUENCY OFFSET FROM 1.75GHz CARRIER
1MHz
FREQUENCY OFFSET FROM 2.8GHz CARRIER
1MHz
Figure ADF4118 Integrated Phase Noise 1750 MHz, kHz,
Figure ADF4118 Integrated Phase Noise 2800 MHz, MHz,
Rev. Page
ADF4116/ADF4117/ADF4118
OUTPUT POWER (dB) -77.3dBc
00392-016
REFERENCE LEVEL -9.3dBm
LOOP BANDWIDTH 100kHz RES. BANDWIDTH 3kHz VIDEO BANDWIDTH 3kHz SWEEP SECONDS AVERAGES FREQUENCY 1MHz
FIRST REFERENCE SPUR (dBc)
00392-019
-100 -2MHz -1MHz 2800MHz +1MHz +2MHz
-100
TEMPERATURE (°C)
Figure ADF4118 Reference Spurs 2800 MHz, MHz,
-130 -135 -140
Figure ADF4118 Reference Spurs Temperature MHz, kHz,
FIRST REFERENCE SPUR (dBc) -105
00392-020
PHASE NOISE (dBc/Hz)
-145 -150 -155 -160 -165 -170 -175
00392-017
1000 PHASE DETECTOR FREQUENCY (kHz)
10000
TURNING VOLTAGE
Figure ADF4118 Phase Noise (Referred Output) Frequency
PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz)
Figure ADF4118 Reference Spurs (200 kHz) VTUNE MHz, kHz,
00392-018 00392-021
-100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure ADF4118 Phase Noise Temperature MHz, kHz,
Figure ADF4118 Phase Noise Temperature MHz, kHz,
Rev. Page
ADF4116/ADF4117/ADF4118
FIRST REFERENCE SPUR (dBc)
SETTING:
(mA)
00392-022
-0.2 -0.4
-0.6 -0.8 -1.0 -1.2 (Volts)
00392-024
-100
TEMPERATURE (°C)
Figure ADF4118 Reference Spurs Temperature MHz, kHz,
Figure Charge Pump Output Characteristics ADF4116, ADF4117, ADF4118
DIDD (mA)
00392-023
PRESCALER OUTPUT FREQUENCY (MHz)
Figure DIDD Prescaler Output Frequency ADF4116, ADF4117, ADF4118
Rev. Page
ADF4116/ADF4117/ADF4118 CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
reference input stage shown Figure normally closed switches; normally open. When power-down initiated, closed opened. This ensures that there loading REFIN power-down.
POWER-DOWN CONTROL 100k COUNTER BUFFER
00392-025
COUNTERS
CMOS counters combine with dual-modulus prescaler allow wide ranging division ratio feedback counter. counters specified work when prescaler output less.
Pulse Swallow Function
counters, conjunction with dual-modulus prescaler, make possible generate output frequencies that spaced only reference frequency divided equation frequency follows:
REFIN
fVCO REFIN
where: fVCO output frequency external voltage controlled oscillator (VCO). preset modulus dual-modulus prescaler. preset divide ratio binary 13-bit counter 8191). preset divide ratio binary 5-bit swallow counter 31). fREFIN output frequency external reference frequency oscillator. preset divide ratio binary 14-bit programmable reference counter 16383).
Figure Reference Input Stage
INPUT STAGE
input stage shown Figure followed 2-stage limiting amplifier generate clock levels needed prescaler.
BIAS GENERATOR RFINA RFINB
00392-026
1.6V AVDD
AGND
COUNTER
14-bit counter allows input reference frequency divided down produce input clock phase frequency detector (PFD). Division ratios from 16,383 allowed.
13-BIT COUNTER PRESCALER LOAD LOAD 5-BIT COUNTER
Figure Input Stage
PRESCALER (P/P
dual-modulus prescaler (P/P along with counters, enables large division ratio, realized dual-modulus prescaler takes clock from input stage divides down manageable frequency CMOS counters. prescaler programmable. software ADF4116 32/33 ADF4117 ADF4118. based synchronous core.
FROM INPUT STAGE
Figure Counters
Rev. Page
00392-027
MODULUS CONTROL
ADF4116/ADF4117/ADF4118
PHASE FREQUENCY DETECTOR (PFD) CHARGE PUMP
takes inputs from counter counter produces output proportional phase frequency difference between them. Figure simplified schematic. includes fixed delay element that sets width antibacklash pulse. This typically This pulse ensures that there dead zone transfer function gives consistent reference spur level.
CHARGE PUMP
MUXOUT LOCK DETECT
output multiplexer ADF4116 family allows user access various internal points chip. state MUXOUT controlled function latch. Figure shows full truth table. Figure shows MUXOUT section block diagram form.
DVDD
ANALOG LOCK DETECT DIGITAL LOCK DETECT COUNTER OUTPUT COUNTER OUTPUT SDOUT
CONTROL
MUXOUT
CLR1
DGND
DELAY
Figure MUXOUT Circuit
Lock Detect
MUXOUT programmed both digital lock detect analog lock detect.
CLR2 DIVIDER
DOWN
CPGND
Digital lock detect active high. high when phase error three consecutive phase detector cycles less than stays high until phase error greater than detected subsequent cycle. channel open-drain analog lock detect should operated with external pull-up resistor nominal. When lock detected, high with narrow going pulses.
00392-028
DIVIDER
DIVIDER
OUTPUT
INPUT SHIFT REGISTER
ADF4116 family digital section includes 21-bit input shift register, 14-bit counter, 18-bit counter, comprising 5-bit counter 13-bit counter. Data clocked into 21-bit shift register each rising edge CLK. data clocked first. Data transferred from shift register four latches rising edge destination latch determined state control bits (C2, shift register. These LSBs, DB0, shown timing diagram Figure truth table these bits shown Figure Table summarizes latches programmed. Table Truth Table
Control Bits Data Latch Counter Counter Function Latch Initialization Latch
Figure Simplified Schematic Timing Lock)
Rev. Page
00392-029
DIVIDER
ADF4116/ADF4117/ADF4118
REFERENCE COUNTER LATCH
LOCK DETECT PRECISION
TEST MODE BITS
14-BIT REFERENCE COUNTER,
CONTROL BITS
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
COUNTER LATCH
GAIN
CONTROL BITS
13-BIT COUNTER
5-BIT COUNTER
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
FUNCTION LATCH
RESERVED RESERVED PHASE DETECTOR POLARITY FASTLOCK MODE FASTLOCK ENABLE COUNTER RESET
POWERDOWN
RESERVED
TIMER COUNTER CONTROL
MUXOUT CONTROL
POWERDOWN
THREESTATE
CONTROL BITS
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
INITIALIZATION LATCH
RESERVED RESERVED FASTLOCK MODE FASTLOCK ENABLE PHASE DETECTOR POLARITY COUNTER RESET
POWERDOWN
RESERVED
TIMER COUNTER CONTROL
MUXOUT CONTROL
POWERDOWN
THREESTATE
CONTROL BITS
Figure ADF4116 Family Latch Summary
Rev. Page
00392-030
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
ADF4116/ADF4117/ADF4118
LOCK DETECT PRECISION
TEST MODE BITS
14-BIT REFERENCE COUNTER,
CONTROL BITS
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DIVIDE RATIO
TEST MODE BITS SHOULD 0000 NORMAL OPERATION
OPERATION CONSECUTIVE CYCLES PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT SET. CONSECUTIVE CYCLES PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT SET.
Figure Reference Counter Latch
Rev. Page
00392-031
ADF4116/ADF4117/ADF4118
GAIN
13-BIT COUNTER
5-BIT COUNTER
CONTROL BITS
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
ADF4116
COUNTER DIVIDE RATIO COUNTER DIVIDE RATIO
ADF4117/ADF4118
COUNTER DIVIDE RATIO ALLOWED ALLOWED 8188 8189 8190 8191
CURRENT SETTINGS 250A
00392-032
PRESCALER VALUE. MUST GREATER THAN EQUAL CONTINUOUSLY ADJACENT VALUES FREF, NMIN (P2-P).
Figure Counter Latch
Rev. Page
ADF4116/ADF4117/ADF4118
RESERVED RESERVED FASTLOCK MODE FASTLOCK ENABLE PHASE DETECTOR POLARITY
RESERVED
TIMER COUNTER CONTROL
MUXOUT CONTROL
COUNTER RESET
POWERDOWN
POWERDOWN
THREESTATE
CONTROL BITS
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
MODE ASYNCHRONOUS POWER-DOWN NORMAL OPERATION ASYNCHRONOUS POWER-DOWN SYNCHRONOUS POWER-DOWN
COUNTER OPERATION NORMAL COUNTERS HELD RESET OUTPUT
THREE-STATE OUTPUT DIGITAL LOCK DETECT (ACTIVE HIGH) DIVIDER OUTPUT AVDD DIVIDER OUTPUT ANALOG LOCK DETECT CHANNEL OPEN DRAIN) SERIAL DATA OUTPUT (INVERSE POLARITY SERIAL DATA INPUT) DGND
FASTLOCK MODE FASTLOCK DISABLED FASTLOCK MODE FASTLOCK MODE TIMEOUT (PFD CYCLES)
PHASE DETECTOR POLARITY NEGATIVE POSITIVE
CHARGE PUMP OUTPUT NORMAL THREE-STATE
Figure Function Latch
Rev. Page
00392-033
ADF4116/ADF4117/ADF4118
RESERVED RESERVED PHASE DETECTOR POLARITY FASTLOCK MODE FASTLOCK ENABLE
RESERVED TIMER COUNTER CONTROL DB15 DB14 DB13 DB12 MUXOUT CONTROL
COUNTER RESET
POWERDOWN
POWERDOWN
THREESTATE
CONTROL BITS
DB20
DB19
DB18
DB17
DB16
DB11
DB10
MODE ASYNCHRONOUS POWER-DOWN NORMAL OPERATION ASYNCHRONOUS POWER-DOWN SYNCHRONOUS POWER-DOWN
COUNTER OPERATION NORMAL COUNTERS HELD RESET OUTPUT
THREE-STATE OUTPUT DIGITAL LOCK DETECT (ACTIVE HIGH) DIVIDER OUTPUT AVDD DIVIDER OUTPUT ANALOG LOCK DETECT CHANNEL OPEN DRAIN) SERIAL DATA OUTPUT (INVERSE POLARITY SERIAL DATA INPUT) DGND
FASTLOCK MODE FASTLOCK DISABLED FASTLOCK MODE FASTLOCK MODE TIMEOUT (PFD CYCLES)
PHASE DETECTOR POLARITY NEGATIVE POSITIVE
CHARGE PUMP OUTPUT NORMAL THREE-STATE
Figure Initialization Latch
Rev. Page
00392-034
ADF4116/ADF4117/ADF4118 FUNCTION LATCH
With respectively, on-chip function latch programmed. Figure shows input data format programming function latch.
CHARGE PUMP THREE-STATE
puts charge pump into three-state mode when programmed should normal operation.
COUNTER RESET
(F1) counter reset bit. When this counter counters reset. normal operation, this should power-up, needs disabled, counter resumes counting "close" alignment with counter. (The maximum error prescaler cycle.)
FASTLOCK ENABLE
function latch Fastlock enable bit. Fastlock enabled only when to1.
FASTLOCK MODE
DB11 function latch Fastlock mode bit. When Fastlock enabled, this determines which Fastlock mode used. Fastlock mode Fastlock Mode selected; Fastlock mode Fastlock Mode selected. Fastlock enabled (DB9 DB11 (ADF4116) determines state output. state same that programmed DB11.
POWER-DOWN
(PD1) DB19 (PD2) ADF4116 family provide programmable power-down modes. They enabled pin. When low, device immediately disabled regardless states PD1. programmed asynchronous power-down, device powers down immediately after latching into bit, with condition that loaded with programmed synchronous power-down, device power-down gated charge pump prevent unwanted frequency jumps. Once power-down enabled writing into condition that also loaded PD2), device goes into power-down after first successive charge pump event. When power-down activated (either synchronous asynchronous mode including pin-activated power-down), following events occur: active current paths removed. timeout counters forced their load state conditions. charge pump forced into three-state mode. digital clock detect circuitry reset. RFIN input debiased. oscillator input buffer circuitry disabled. input register remains active capable loading latching data.
Fastlock Mode
ADF4116 family, output level programmed state, charge pump current switched high value mA). used switch resistor loop filter ensure stability while Fastlock altering loop bandwidth. device enters Fastlock having written Gain register. device exits Fastlock having written Gain register.
Fastlock Mode
ADF4116 family, output level programmed state, charge pump current switched high value mA). used switch resistor loop filter ensure stability while Fastlock altering loop bandwidth. device enters Fastlock having written gain register. device exits Fastlock under control timer counter. After timeout period determined value TC1, gain register automatically reset device reverts normal mode instead Fastlock.
TIMER COUNTER CONTROL
ADF4116 family, user option switching between charge pump current values speed locking frequency. When using Fastlock feature with ADF4116 family, normal sequence events follows: user must make sure that Fastlock enabled. ADF4116 family user must also choose which Fastlock mode use.
MUXOUT CONTROL
on-chip multiplexer controlled ADF4116 family. Figure shows truth table.
PHASE DETECTOR POLARITY
(F2) function latch sets phase detector polarity. When characteristics positive, should When they negative, should
Rev. Page
ADF4116/ADF4117/ADF4118
discussed previous section, Fastlock Mode uses values timer counter determine timeout period before reverting normal mode operation after Fastlock. Fastlock Mode chosen setting DB11 ADF4116 family user must also decide long keep high current active before reverting current (250 This controlled Timer Counter Control Bits DB14 DB11 (TC4 TC1) function latch. truth table given Figure program output frequency, simply program counter latch with values same time, gain which sets charge pump period time determined TC1. When this time charge pump current reverts same time, gain counter latch reset ready next time that user wants change frequency. When initialization latch loaded, following occurs: function latch contents loaded. internal pulse resets timeout counters load state conditions also three-states charge pump. Note that prescaler band reference oscillator input buffer unaffected internal reset pulse, allowing close phase alignment when counting resumes. Latching first counter data after initialization word activates same internal reset pulse. Successive loads trigger internal reset pulse unless there another initialization.
Method
Apply VDD. Bring device into power-down. This asynchronous power-down that happens immediately. Program function latch (10). Program counter latch (00). Program counter latch (01). Bring high take device power-down.
INITIALIZATION LATCH
When both initialization latch programmed. This essentially same function latch that programmed when However, when initialization latch programmed, additional internal reset pulse applied counters. This pulse ensures that counter load point when counter data latched that device begins counting close phase alignment. latch programmed synchronous power-down high; high; low), internal pulse also triggers this power-down. prescaler reference oscillator input buffer unaffected internal reset pulse, close phase alignment maintained when counting resumes. When first counter data latched after initialization, internal reset pulse again activated. However, successive counter loads trigger internal reset pulse.
counters resume counting close alignment. Note that after goes high, duration required prescaler band voltage oscillator input buffer bias reach steady state. used power power down device check channel activity. input register does need reprogrammed each time device disabled enabled long programmed least once after initially applied.
Counter Reset Method
Apply VDD. function latch load LSBs). part this, load bit. This enables counter reset. counter load LSBs). counter load LSBs). function latch load LSBs). part this, load bit. This disables counter reset.
DEVICE PROGRAMMING AFTER INITIAL POWER-UP
After initial power-up, device programmed initialization latch method, method, counter reset method.
Initialization Latch Method
Apply VDD. Program initialization latch LSBs input word). Make sure that programmed load LSBs). load LSBs).
This sequence provides same close alignment initialization method. offers direct control over internal reset. Note that counter reset holds counters load point three-states charge pump, does trigger synchronous power-down. counter reset method requires extra function latch load compared initialization latch method.
Rev. Page
ADF4116/ADF4117/ADF4118 APPLICATIONS
LOCAL OSCILLATOR BASE STATION TRANSMITTER
Figure shows ADF4117/ADF4118 being used with produce base station transmitter. reference input signal applied circuit FREFIN and, this case, terminated typical system TCXO driving reference input without termination. have channel spacing (the standard), reference input must divided using on-chip reference divider ADF4117/ADF1118. charge pump output ADF4117/ADF1118 (Pin drives loop filter. calculating loop filter component values, number items need considered. this example, loop filter designed that overall phase margin system degrees. Other system specifications given below. MHz/V Loop Bandwidth FREF 4500 Extra Reference Spur Attenuation these specifications needed used produce loop filter components values shown Figure loop filter output drives VCO, which, turn, back input synthesizer; also drives output terminal. T-circuit configuration provides matching between output, output, RFIN terminal synthesizer. system, important know when system locked mode. Figure this accomplished using MUXOUT signal from synthesizer. MUXOUT programmed monitor various internal signals synthesizer. these lock-detect signal.
SHUTDOWN CIRCUIT
attached circuit Figure shows shut down both ADF4116 family accompanying VCO. ADG702 switch goes open-circuit when Logic applied input. low-cost switch available both SOT-23 MSOP packages.
DIRECT CONVERSION MODULATOR
some applications, direct conversion architecture used base station transmitters. Figure shows combination available from implement this solution. circuit diagram shows AD9761 being used with AD8346. dual integrated DACs, such AD9761 with specified ±0.02 ±0.004 gain offset matching characteristics, ensures minimum error contribution (over temperature) from this portion signal chain. local oscillator implemented using ADF4117/ ADF4118. this case, FOX801BH-130 provides stable reference frequency. system designed channel spacing output center frequency 1960 MHz. target application WCDMA base station transmitter. Typical phase noise performance from this dBc/Hz offset. port AD8346 driven single-ended fashion. LOIN ac-coupled ground with capacitor, LOIP driven through accoupling capacitor from source. drive level between required. circuit Figure gives typical level dBm. output designed drive load, must ac-coupled shown Figure inputs driven quadrature signals, resulting output power approximately dBm.
Rev. Page
ADF4116/ADF4117/ADF4118
100pF 1000pF 1000pF FREFIN 3.3k 620pF VCO190-902T 100pF AVDD DVDD REFIN 0.15nF RFOUT
ADF4117/ ADF4118
1.5nF
SPI-COMPATIBLE SERIAL
LOCK MUXOUT DETECT DATA 100pF RFINA RFINB 51**
CPGND
AGND
DGND
100pF
USED WHEN GENERATOR SOURCE IMPEDANCE **OPTIONAL MATCHING RESISTOR DEPENDING RFOUT FREQUENCY
DECOUPLING CAPACITORS (10F/10p) DVDD, ADF4117/ADF4118 VCO190-920T HAVE BEEN OMITTED FROM DIAGRAM CLARITY.
Figure Local Oscillator Base Station
POWER-DOWN CONTROL
RFOUT 100pF
ADG702
AVDD DVDD FREFIN REFIN
LOOP FILTER
100pF
ADF4116/ ADF4117/ ADF4118
RFINA
CPGND AGND DGND
100pF
RFINB
100pF
00392-036
DECOUPLING CAPACITORS INTERFACE SIGNALS HAVE BEEN OMITTED FROM DIAGRAM CLARITY.
Figure Local Oscillator Shutdown Circuit
Rev. Page
00392-035
ADF4116/ADF4117/ADF4118
0.1F REFIO IOUTA IOUTB IBBP IBBP VOUT 100pF RFOUT
LOW-PASS FILTER
MODULATED DIGITAL DATA
AD9761 TxDAC
QOUTA QOUTB LOW-PASS FILTER QBBP QBBP LOIN 100pF
AD8346
LOIP 100pF
3B1-13M0 TCXO REFIN 680pF 6.8nF RFINB 100pF RFINA 100pF 18pF VCO190-1960T
SERIAL DIGITAL NTERFACE
ADF4118
100pF
POWER SUPPLY CONNECTIONS DECOUPLING CAPACITORS OMITTED FROM DIAGRAM CLARITY.
Figure Direct Conversion Transmitter Solution
Rev. Page
00392-037
ADF4116/ADF4117/ADF4118
INTERFACING
ADF4116 family simple SPI®-compatible serial interface writing device. CLK, DATA, control data transfer. When (latch enable) goes high, bits that clocked into input register each rising edge transferred appropriate latch. Figure timing diagram Table latch truth table. maximum allowable serial clock rate MHz. This means that maximum update rate possible device update every microseconds. This more than adequate systems that have typical lock times hundreds microseconds. first applying power ADF4116 family, requires three writes (one each counter latch, counter latch, initialization latch) output become active. port lines ADuC812 also used control powerdown input) detect lock (MUXOUT configured lock detect polled port input). When operating mode described, maximum SCLOCK rate ADuC812 MHz. This means that maximum rate which output frequency changed kHz.
ADSP-21xx Interface
Figure shows interface between ADF4116 family ADSP-21xx digital signal processor. ADF4116 family needs 21-bit serial word each latch write. easiest accomplish this using ADSP-21xx family autobuffered transmit mode operation with alternate framing. This provides means transmitting entire block serial data before interrupt generated.
SCLK DATA
ADuC812 Interface
Figure shows interface between ADF4116 family ADuC812 MicroConverter®. Since ADuC812 based 8051 core, this interface used with 8051-based microcontroller. MicroConverter master mode with CPHA initiate operation, port driving brought low. Each latch ADF4116 family needs 24-bit word. This accomplished writing three 8-bit bytes from MicroConverter device. When third byte been written, input should brought high complete transfer.
SCLOCK DATA PORTS
ADSP-21xx
ADF4116/ ADF4117/ ADF4118
00392-039
FLAGS
MUXOUT (LOCK DETECT)
ADuC812
MOSI
ADF4116/ ADF4117/ ADF4118
00392-038
Figure ADSP-21xx ADF4116 Family Interface
MUXOUT (LOCK DETECT)
Figure ADuC812 ADF4116 Family Interface
word length bits three memory locations each 24-bit word. program each 21-bit latch, store three 8-bit bytes, enable autobuffered mode, write transmit register DSP. This last operation initiates autobuffer transfer.
Rev. Page
ADF4116/ADF4117/ADF4118 OUTLINE DIMENSIONS
5.10 5.00 4.90
4.50 4.40 4.30
6.40
1.20 0.20 0.09 0.65 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 0.75 0.60 0.45
0.15 0.05
COMPLIANT JEDEC STANDARDS MO-153AB
Figure 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown millimeters
ORDERING GUIDE
Model ADF4116BRU ADF4116BRU-REEL ADF4116BRU-REEL7 ADF4116BRUZ ADF4116BRUZ-REEL1 ADF4116BRUZ-REEL71 ADF4117BRU ADF4117BRU-REEL ADF4117BRU-REEL7 ADF4117BRUZ1 ADF4117BRUZ-RL1 ADF4117BRUZ-RL71 ADF4118BRU ADF4118BRU-REEL ADF4118BRU-REEL7 ADF4118BRUZ1 ADF4118BRUZ-RL1 ADF4118BRUZ-RL71 ADF4118YRUZ1 ADF4118YRUZ-RL1 ADF4118YRUZ-RL71 EVAL-ADF4118EB1 EVAL-ADF411XEB1
Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +125°C -40°C +125°C -40°C +125°C
Package Description 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) Evaluation Board Evaluation Board
Package Option RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16
Pb-free part.
Rev. Page
ADF4116/ADF4117/ADF4118 NOTES
Rev. Page
ADF4116/ADF4117/ADF4118 NOTES
Rev. Page
ADF4116/ADF4117/ADF4118 NOTES
Purchase licensed components Analog Devices sublicensed Associated Companies conveys license purchaser under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips.
2005 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners. D00392-0-11/05(C)
Rev. Page

ADF4116: ADF4117: ADF4118: power supply Separate allows extended tunin

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