2.4GHz Very Phase Noise Advance Information DS4875 November 1998

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2.4GHz Very Phase Noise Advance Information DS4875 November 1998

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SP5748
2.4GHz Very Phase Noise Advance Information
DS4875 November 1998
SP5748 single chip frequency synthesiser designed tuning systems optimized phase noise with comparison frequencies MHz. designed downwards software compatible with SP5658. programmable divider contains front dual modulus 16/17 functioning over full operating range allows coarse tuning upconverter application fine tuning downconverter. Comparison frequencies obtained either from crystal controlled on-chip oscillator from external source. buffered reference frequency output also available drive second SP5748. device also contains switching ports.
CHARGE PUMP CRYSTAL CRYSTAL ENABLE DATA CLOCK PORT P1/OC
SPOT REF.
DRIVE INPUT INPUT PORT P0/OP
MP14 Figure1 connections view
APPLICATIONS FEATURES
Complete single chip system (for faster device refer SP5768) Optimised phase noise, with comparison frequencies prescaler Selectable reference division ratio Reference frequency output Selectable charge pump current Integrated loop amplifier switching ports power replacement SP5658 5668 Downwards software compatible with SP5658 protection, (Normal handling procedures should observed) Cable tuning systems Communications systems
ORDERING INFORMATION
SP5748/KG/MP1S (Tubes) SP5748/KG/MP1T (Tape Reel)
SP5748 Advance Information
COUNT INPUT 16/17 COUNT
REFERENCE DIVIDER
CRYSTAL
PUMP DRIVE
LATCH
LATCH
DATA CLOCK ENABLE DATA INTERFACE
LATCH PORT/ TEST MODE INTERFACE
PORT P0/OP
PORT P1/OC
Figure SP5748 block diagram
ELECTRICAL CHARACTERISTICS
These characteristics guaranteed either production test design. They apply within specified ambient temperature supply voltage unless otherwise stated. TAMB -40°C 80°C, Characteristic Supply current Value 2400 Units Figure Conditions
input frequency range 11,12 input voltage input impedance Data, clock enable input high voltage input voltage input current hysterysis 11,12 11,12 5,6,4
input conditions
SP5748 Advance Information ELECTRICAL CHARACTERISTICS (continued)
These characteristics guaranteed either production test design. They apply within specified ambient temperature supply voltage unless otherwise stated. TAMB -40°C 80°C, Characteristic Clock rate timing data data hold enable enable hold clock enable Charge pump output current Charge pump output leakage Charge pump drive output current Crystal frequency Recommended crystal 5,6,4 Value Units Figure4 Figure Vpin1 +-10 Vpin1=2V Conditions
Vpin 14=0.7V
ppm/
Figure application parallel resonant crystal. series resistance
Oscillator temperature stability Oscillator supply voltage stability External reference input frequency External reference drive level Buffered reference frequency output output amplitude output impedance 0.35
ppm/V
Sinewave coupled through blocking capacitor Sinewave coupled through blocking capacitor coupled
2-20MHz
SP5748 Advance Information
ELECTRICAL CHARACTERISTICS
These characteristics guaranteed either production test design. They apply within specified ambient temperature supply voltage unless otherwise stated. TAMB -40°C 80°C, Characteristic Value Units Conditions
Comparison frequency Equivalent phase noise phase detector -148
dBc/Hz kHz, SSB, with comparison from crystal reference
division ratio Reference division ratio Output ports P0-P1# sink current leakage current
131071 figure
Vport 0.7V Vport
Reference output disabled connecting required Output ports high impedance power with data, clock enable logic
SP5748 Advance Information ABSOLUTE MAXIMUM RATINGS
voltages referred Characteristic Supply voltage, input voltage input offset Port voltage Charge pump offset Varactor drive offset Crystal offset Buffered output Data, clock enable offset Storage temperature Junction temperature MP14 thermal resistance, chip ambient chip case Power consumption Vcc=5.5V protection 11,12 11,12 5,6,4 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Vcc+0.3 Vcc+0.3 Vcc+0.3 Vcc+0.3 Vcc+0.3 Vcc+0.3 Vcc+0.3 +125 +150 Units Vp-p °C/W °C/W ports Mil-std 883B latest revision method 3015 cat.1. Differential across pins Conditions
Functional description
SP5748 contains elements necessary, with exception frequency reference, loop filter external high voltage transistor, control varicap tuned local oscillator, forming complete frequency synthesised source. device allows operation with high comparison frequency fabricated high speed logic, which enables generation loop with excellent phase noise performance, even with high comparison frequencies. package allocation shown Figure block diagram Figure SP5748 controlled standard 3-wire comprising data, clock enable inputs. programming word contains bits, which used port selection, programmable divider ratio, four bits select reference division ratio, bits R0-R2, Figure bits charge pump current, Figure remaining access test modes, Figure programming format shown Figure clock input disabled enable signal, data therefore only loaded into internal shift registers during enable high clocked into controlling buffers enable high transition. This load also synchronised with programmable divider giving smooth fine tuning. signal internal preamplifier, which provides gain reverse isolation from divider signals. output preamplifier fully programmable counter, which MN+A architecture. counter counter output programmable counter phase comparator where compared both phase frequency domain with comparison frequency. This frequency derived either from board crystal controlled oscillator from external reference source. both cases reference frequency divided down comparison frequency reference divider which programmable into1 ratios descried Figure output phase detector feeds charge pump loop amplifier section, which when used with external high voltage transistor loop filter integrates current pulses into varactor line voltage. charge pump current setting described Figure buffered crystal reference frequency suitable driving further synthesisers available from required this output disabled connecting programmable divider output divided Fpd/2 comparison frequency, Fcomp switched ports respectively switching device into test mode. test modes described Figure
SP5748 Advance Information
+j0.5
+j0.2
-j0.2 Normalised -j0.5
Frequency Markers 500MHz, 1GHz, 1.5GHz 2.4GHz
Figure input impedance
CLOCK
ENABLE
DATA
Frequency data
TIMING DIAGRAM
2^16 R2,R1,R0 P1,P0 C1,C0
Programmable divider ratio control bits Reference divider control bits Reference divider mode select Port control bits Charge pump current select Test mode enable
Figure Data format
Current
Figure Charge pump current
SP5748 Advance Information
SP5748
Figure Crystal oscillator application
Figure Reference division ratio
RATIO
don't care
FUNCTIONAL DESCRIPTION Normal operation Charge pump sink Charge pump source Charge pump disable Port Fcomp, Fpd/1
Figure Test modes
SP5748 Advance Information
INTO
OPERATING WINDOW
1000
2400
FREQUENCY (MHz)
Figure Typical input sensitivity
900MHz
1.6GHz
38.9MHz
1650-2700MHz 1650 -2400MHz
SP5748
10nF
Figure Example double conversion from VHF/UHF frequencies
SP5748
18pF 39pF 4MHz
+30V 68pF 15nF 13k3 BCW31
+12V
Optional application utilising on-board crystal controlled oscillator
REFERENCE CONTROL MICRO ENABLE DATA CLOCK
OSCILLATOR OUTPUT
TUNER
SP5748
Figure Typical application SP5748
SP5748 Advance Information APPLICATION NOTES
generic application notes AN168 designing withsynthesisers such SP5748 been written. This covers aspects such loop filter design decoupling. Thisapplication note also featured Media Data Book, refer Mitel Semiconductor Internet Site http://www.Mitelsemi.com. generic test/ demo board been produced which used SP5748. circuit diagram shown Figure board used following purposes: Measuring sensitivity performance. Indicating port function. Synthesising voltage controlled oscillator. Testing external reference. Measurement phase noise performance.
REFERENCE SOURCE
SP5748 offers optimal phase noise performance when operated with large step size. This fact that phase noise within loop bandwidth phase comparator frequency noise floor phase comparator frequency
Assuming phase comparator noise floor flat irrespective sampling frequency, this means that best performance will achieved when overall phase comparator division ratio minimum. There ways achieving higher phase comparator sampling frequency:- Reduce division ratio between reference source phase comparator higher reference source frequency. Approach preferred best performance since possible that noise floor reference oscillator degrade phase comparator performance reference division ratio very small.
LOOP BANDWIDTH
majority applications which SP5748 intended require loop filter bandwidth between 2kHz and10kHz. Typically phase noise will specified both 1kHz and10kHz offset. common practice arrange loop filter bandwidth such that 1kHz figure lies within loop bandwidth. Thus phase noise depends synthesiser comparator noise floor, rather than VCO. 10kHz offset figure should depend providing loop designed correctly, underdamped.
18pF 39pF Drive Output XTAL XTAL Input DATA Input BCW31 4n7F
SP5748
INPUT 100pF
POT2 4MHz
10nF
Clock Enable Data
WIRE DIP-2 10nF
LED1
HLMPK-150
100pF 100pF 100pF
HLMPK-150 LED2
COMP
PORT OUTPUTS
Figure Evaluation Board
100nF 100pF 4u7F +22V 100nF 4u7F POWER CONNECTOR
SP5748 Advance Information
13K3
FITTED NORMAL OPERATION 2n2F
POS-2000 TUNING RANGE 1370MHz 2000MHz VARACTOR
POS_2000
POS_2000
SP5748 Advance Information
view
Bottom view Figure
SP5748 Advance Information
VREF
CHARGE PUMP
INPUTS
DRIVE
inputs
Loop amplifier
PORT
BIAS
Disable, Enable, Data Clock inputs
Output Ports
CRYSTAL
CRYSTAL
1.2mA
Reference oscillator
Reference output
Figure Input/Output interface cicruits
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2.4GHz Very Phase Noise Advance Information DS4875 November 1998

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