2.7GHz 3-Wire Controlled Synthesiser Preliminary Information DS45

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2.7GHz 3-Wire Controlled Synthesiser Preliminary Information DS45

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SP5668
2.7GHz 3-Wire Controlled Synthesiser Preliminary Information
DS4538 January 1997
SP5668 single chip frequency synthesiser designed tuning systems 2.7GHz. preamplifer contains divide prescaler which disabled applications 2GHz enabling step size equal comparison frequency 2GHz twice comparison frequency 2.7GHz. Comparison frequencies obtained either from crystal controlled on-chip oscillator from external source. device contains three switching ports, together with 'in-lock' flag output. Various test modes including varactor disable charge pump disable also included.
CHARGE PUMP CRYSTAL ENABLE DATA CLOCK PORT PORT P1/OC
DRIVE INPUT INPUT LOCK PORT P0/OC
FEATURES Complete 2.7GHz single chip system Optimised phase noise Selectable divide prescaler Selectable reference division ratio Charge pump disable Varactor line disable `In-lock' flag selectable charge pump currents Three switching ports Reference frequency output protection (Normal handling procedures should observed)
MP16
Fig. connections view
APPLICATIONS SAT, Cable tuning systems Communications systems
ORDERING INFORMATION
SP5668/KG/MP1S (Tubes,) SP5668/KG/MP1T Tape Reel)
SP5668
Fref PROGRAMMABLE DIVIDER INPUTS 16/17 COUNT PHASE COMP Fcomp REFERENCE DIVIDER Table CRYSTAL CRYSTAL CHARGE PUMP DRIVE
COUNT
CHARGE PUMP LATCH LATCH (R0,R1,R2) LATCH
LATCH DISABLE
ENABLE CLOCK DATA
DATA INTERFACE
LATCH PORT INTERFACE
LATCH
FLOCK
LOCK
Fig. SP5668 block diagram
ELECTRICAL CHARACTERISTICS
TAMB 120°C +80°C, +4.5 +5.5V. Reference frequency 4MHz. These characteristics guaranteed either production test design. They apply within specified ambient temperature supply voltage ranges unless otherwise stated. Characteristic Supply current, input voltage 13,14 input impedance Data, Clock, Enable Input high voltage Input voltage Input high current Input current Hysteresis Clock Rate 4,5,6 Input voltage Input voltage Value mVrms mVrms mVrms Prescaler enabled, Prescaler disabled, 100MHz Prescaler enabled, Fig. 300MHz 2.7GHz Prescaler enabled, Fig. 100MHz 2.0GHz Prescaler disabled, Fig. Fig. Units Conditions
SP5668
ELECTRICAL CHARACTERISTICS (continued)
TAMB 120°C +80°C, +4.5 +5.5V. Reference frequency 4MHz. These characteristics guaranteed either production test design. They apply within specified ambient temperature supply voltage ranges unless otherwise stated. Characteristic timing Data Data hold, Enable Enable hold Clock enable, Charge pump output Current Charge pump output leakage Drive output current Drive output saturation Voltage when disabled External reference input frequency External reference input amplitude Crystal frequency Recommended crystal Series resistance mVp-p Fig. Fig. Fig. Fig. Fig. Table Vpin1 Vpin1 VPIN16 0.7V coupled sinewave coupled sinewave Value Units Conditions
Applies 4MHz crystal only. "Parallel resonant" crystal. Figure quoted under conditions
Reference oscillator bias current output voltage* Phase detector comparison frequency Equivalent phase noise phase detector division ratio Reference division ratio Output ports P0-P2 Sink current Leakage current Lock output Sink current Leakage current
mVp-p dBc/Hz
including start Fig. coupled, 4MHz reference frequency, Fig.
**Note Prescaler disabled Prescaler enabled Table
131071 262142
VPORT 0.7V VPORT 13.2V VPIN10 0.7V, 'out lock' lock'
output should connected unused Note: -148dB 1KHz offset with 1MHz comparison frequency measured phase comparator. When external reference used, high signal level required phase noise.
SP5668
ABSOLUTE MAXIMUM RATINGS
voltages referred Charateristics Supply voltage, input voltage input offset Port output voltage Total port current REFoutput offset Lock output offset Lock output current Charge pump offset Drive offset Crystal oscillator offset Data, Clock inputs Storage temperature Junction temperature MP16 Thermal resistance Chip ambient Chip case Power consumption 5.5V protection 4,5,6 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 VCC+0.3 VCC+0.3 VCC+0.3 VCC+0.3 VCC+0.3 VCC+0.3 VCC+0.3 +150 +150 Units Vp-p °C/W °C/W ports off, prescaler enabled MIL-STD TM3015 Port state Port state Conditions
FUNCTIONAL DESCRIPTION
SP5668 contains elements necessary, with exception frequency reference, loop filter external high voltage transistor, control varicap tuned local oscillator, forming complete frequency synthesised source. device allows operation with high comparison frequency fabricated high speed logic, which enables generation loop with good phase noise performance. preamplifier contains selectable divide operation above 2.0GHz. 2GHz input interfaces directly with programmable divider, eliminating degradation phase noise prescaler action. block diagram shown Fig.2. SP5668 controlled standard 3-wire comprising data, clock enable inputs. programming word contains bits. used port selection, programmable divider ratio select reference division ratio (Table1). sets charge pump current (Table remaining bits access test modes disable varactor drive (Table 2).The programming format shown Fig. clock input disabled enable signal, data therefore only clocked into internal shift registers during enable high loaded into controlling buffers enable high transition. This load also synchronised with programmable divider giving smooth fine tuning. signal internal preamplifier, which provides gain reverse isolation from divider signals. output preamplifier selectable prescaler then fully programmable divider, which MN+A architecture. counter counter prescaler disabled; control function cannot used dynamically. output programmable divider phase comparator where compared both phase frequency domain with comparison frequency. This frequency derived either from board crystal controlled oscillator from external source. both cases reference frequency divided down comparison frequency reference divider which programmable into ratios described Table output phase comparator feeds charge pump loop amplifier section, which when used with external high voltage transistor loop filter integrates current pulses into varactor line voltage. charge pump current selected described Table phase comparator also drives lock detect circuit which generates lock flag. 'In-lock' indicated high impedance state lock output. crystal frequency Fref available output. This used reference second synthesiser shown Fig. output disabled connecting output, VCC.
SP5668
PHASE NOISE
SP5668 been designed offer good phase noise performance even when operated with standard profile 4MHz crystal high comparison frequency, e.g. 2MHz. typical phase noise performance measured standard application contained Table been demonstrated that even higher levels performance will achieved tuner application.
TEST MODES
programmable divider output divided Fpd/2 comparison frequency Fcomp, switched ports respectively. charge pump forced either source sink current, disabled high impedance state. varactor DRIVE output disabled within data word, switching external transistor 'OFF' allowing external voltage written varactor line tuner alignment purposes. test modes described Table
CLOCK ENABLE DATA FREQUENCY DATA
Programmable divider ratio control bits Prescaler (Enable Disable Reference divider ratio control bits (see Table Port control bits Charge Pump current select (see Table Drive output disable switch Test mode enable (see Table
Fig. Data format timing
RATIO Comparison Frequency with 4MHz external reference 2MHz 1MHz 500kHz 250kHz 125kHz 62.5kHz 31.25kHz 15.625kHz
Table Reference division ratio
Don't care FUNCTIONAL DESCRIPTION Normal operation Charge pump sink. LOCK output Charge pump source. LOCK output Charge pump disable. LOCK output Port Fcomp: Port Fpd/2
Table Test modes
SP5668
0.23 0.68 CURRENT 0.30 0.90 0.37 1.12
Table Charge pump
Fcomp (4MHz XTAL)
Division RATIO
PHASE NOISE @1kHZ OFFSET (dBc/Hz)
EQUIVALENT PHASE NOISE PHASE DETECTOR (dBc/Hz) -146 -144
2GHz 2GHz
1MHz 2MHz
2000 1000
Table Typical phase noise
+j0.5
+j0.2
-j0.2
S11:Z NORMALISED
-j0.5
FREQUENCY MARKERS 100MHz, 500MHz, 1GHz 2.7GHz
Fig. Typical input impedance
SP5668
INTO
INTO
OPERATING WINDOW
OPERATING WINDOW
1000
2000
3000 3500
1000
2000
3000 3500 2700
FREQUENCY (MHz)
FREQUENCY (MHz)
Fig. Typical input sensitivity (Prescaler disabled, PE=0)
Fig. Typical input sensitivity (Prescaler enabled, PE=1)
1.6GHZ
900MHz
38.9MHz
1650-2700MHz
SP5668
10nF
Fig. Example double conversion from VHF/UHF frequencies
SP5668
18pF 39pF 4MHz
+30V 68pF 15nF 13k3 BCW31
+12V
Optional application utilising on-board crystal controlled oscillator
REFERENCE CONTROL MICRO ENABLE DATA CLOCK LOCK
OSCILLATOR OUTPUT
TUNER
SP5668
Fig. typical application, SP5668
SP5668
APPLICATION NOTES
generic application notes AN168 designing with synthesisers such SP5668 been written. This covers aspects such loop filter design decoupling. This application note also featured Media Handbook. generic test/demo board been produced which used SP5668. circuit diagram shown Fig. board used following purposes: Measuring sensitivity performance. Indicating port function Synthesising voltage controlled oscillator Testing external reference sources
100nF 68pF 47µF
+30V +12V 100nF 100nF 2n2F INPUT SKT1 47µF
EXTERNAL REFERENCE SKT2 10nF *(NOT FITTED)
15nF
13K3
BCW31
18pF 39pF ENABLE DATA CLOCK 100pF 100pF 4MHz
10nF
REFERENCE OUTPUT
LOCK
LOCK
Fig. Evaluation board
SP5668
LOOP BANDWIDTH majority applications which SP5668 intended require loop filter bandwidth between 2kHz 10kHz. Typically phase noise will specified both 1kHz and10kHz offset. common practice arrange loop filter bandwidth such that 1kHz figure lies within loop bandwidth. Thus phase noise depends synthesiser comparator noise floor, rather than VCO. 10kHz offset figure should depend providing loop designed correctly, underdamped.
REFERENCE SOURCE
SP5668 offers optimal phase noise performance when operated with large step size. This fact that phase noise within loop bandwidth phase comparator noise floor
frequency
phase comparator frequency
Assuming phase comparator noise floor flat irrespective sampling frequency, this means that best performance will achieved when overall phase comparator division ratio minimum. There ways achieving higher phase comparator sampling frequency:- reduce division ratio between reference source phase comparator higher reference source frequency. Approach preferred best performance since possible that noise floor reference oscillator degrade phase comparator performance reference division ratio very small.
SP5668
VREF
CHARGE PUMP
INPUTS (Output disable)
DRIVE OUTPUT
inputs
Loop amplifier
PORT/LOCK
BIAS
Disable, Enable, Data Clock inputs
Output Ports Lock Output
XTAL
1.2mA
Reference oscillator
Reference output
Fig.9 Input/Output interface circuits
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2.7GHz 3-Wire Controlled Synthesiser Preliminary Information DS45

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