Phase Noise Synthesiser Preliminary Information Supersedes March
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SP5659
Phase Noise Synthesiser Preliminary Information
Supersedes March 1996 version, DS4206-1.8 DS4296 June 1998
SP5659 single chip frequency synthesiser designed tuning systems preamplifier drives divide-by prescaler which disabled applications 2GHz, allowing direct interfacing with programmable divider, resulting step size equal comparison frequency. applications divide-by enabled give step size twice comparison frequency. comparison frequency obtained either from onchip crystal controlled oscillator from external source. oscillator frequency FREF comparison frequency FCOMP switched REF/COMP output; this feature ideally suited providing reference frequency second synthesiser such double conversion tuner (see Fig. synthesiser controlled responds four programmable addresses which selected applying specific voltage Address input. This feature enables more synthesisers used system. SP5659 contains four switching ports, P0-P3 5-level ADC, output which read bus. SP5659 also contains varactor line disable charge pump disable facility.
CHARGE PUMP CRYSTAL REF/COMP ADDRESS PORT PORT
DRIVE INPUT INPUT PORT PORT
SP5659
MP16
Fig. connections view
Protection: 4kV, Mil-Std-883C, Method 3015 Compatible with SP5658
Normal handling precautions should observed.
FEATURES
Complete Single Chip System Optimised Phase Noise Selectable prescaler Selectable Reference Division Ratio Selectable Reference/Comparison Frequency Output Selectable Charge Pump Current Varactor Drive Amplifier Disable 5-Level Variable Address Multi-tuner Applications
APPLICATIONS Satellite
High Cable Tuning Systems
THERMAL DATA
41°C/W 111°C/W
ORDERING INFORMATION
SP5659 KG/MP1S (Tubes) SP5659 KG/MP1T (Tape reel)
SP5659
ELECTRICAL CHARACTERISTICS
TAMB 220°C 180°C, reference frequency 4MHz. These Characteristics guaranteed either production test design. They apply within specified ambient temperature supply voltage ranges unless otherwise stated. Value Characteristic Supply current, input voltage 13,14 Min. Typ. Max. Units Conditions (note
mVrms 300MHz (prescaler enabled) Fig. mVrms 100MHz, (prescaler enabled) Fig. mVrms 100MHz (prescaler disabled) Fig. Fig. Fig.
input impedance input capacitance SDA, Input high voltage Input voltage Input high current Input current Leakage current Input hysteresis Output voltage Charge Pump Output current Output leakage current Drive output current Drive saturation voltage External reference input frequency External reference input amplitude Crystal frequency Crystal oscillator drive level Recommended crystal series resistance Crystal oscillator negative resistance REF/COMP output voltage, enabled Comparison frequency Equivalent phase noise phase detector division ratio Reference division ratio sink current leakage current input voltage input current Address input current high Address input current
13,14 13,14
Input voltage Input voltage Sink current
mVp-p mVp-p
Drive output disabled coupled sinewave coupled sinewave
Parallel resonant crystal (note Includes temperature process tolerances
mVp-p coupled, note dBC/Hz note Prescaler disabled, Table Prescaler enabled, Table Table VPORT VPORT Fig. Table >VINPUT >VEE Input voltage Input voltage
2142 7,8,9,10 131071 262142
NOTES Maximum power consumption 468mW with ports off. Resistance specified maximum under conditions including start REF/COMP output used, should left open circuit connected disabled setting logic 6kHz loop bandwidth, phase comparator frequency 250kHZ. Figure measured 1kHz offset (within loop bandwidth).
SP5659
ABSOLUTE MAXIMUM RATINGS
voltages referred Parameter Value Min. Max. 1150 1150 Units Conditions
Supply voltage input voltage input offset Port voltage
13,14 7-10 7-10
Port state Port state
Total port current input offset REF/COMP output offset Charge pump offset Drive offset Crystal oscillator offset Address offset SDA, input voltage Storage temperature Junction temperature
7-10
PREAMP
PROGRAMMABLE DIVIDER 13-BIT COUNT 4-BIT COUNT PHASE COMP
FCOMP REFERENCE DIVIDER (SEE TABLE
REF/COMP
42/1
416/17
FREF
CRYSTAL CHARGE PUMP DRIVE
LOCK CHARGE PUMP
1-BIT COUNT 17-BIT LATCH DIVIDE RATIO
2-BIT LATCH 2-BIT LATCH
MODE CONTROL
DISABLE
5-BIT LATCH MODE CONTROL LOGIC (SEE TABLE ADDRESS
FPD/2 TRANSCEIVER 3-BIT
4-BIT LATCH PORT INTERFACE
TEST CONTROL
POWER DETECT
Fig. Block diagram
SP5659
FUNCTIONAL DESCRIPTION
SP5659 contains elements necessary with exception frequency reference, loop filter external high voltage transistor control varactor tuned local oscillator, forming complete frequency synthesised source. device allows operation with high comparison frequency fabricated high speed logic which enables generation loop with good phase noise performance. block diagram shown Fig. input signal internal preamplifier, which provides gain reverse isolation from divider signals. output preamplifier interfaces with 17-bit fully programmable divider prescaler. applications input, prescaler disabled, eliminating degradation phase noise prescaler action. divider MN1A architecture, where counter bits counter bits. output programmable divider, FPD, phase comparator where compared phase frequency domains with comparison frequency FCOMP. This frequency derived either from on-chip crystal controlled oscillator from external reference source. either case, reference frequency FREF divided down comparison frequency reference divider, which programmable ratios detailed Table output phase detector feeds charge pump loop amplifier section which, when used with external high voltage transistor loop filter, integrates current pulses into varactor line voltage. invoking device test modes described Fig. Table varactor drive output disabled, switching external transistor off. This allows external voltage applied varactor line tuner alignment purposes. Similarly, charge also disabled high impedance state. programmable divider output FPD/2 switched port programming device into test mode Table next data byte then interpreted byte byte respectively. After complete data bytes have been received, additional data bytes entered, where byte interpretation follows same procedure without readdressing device. This procedure continues until STOP condition received. STOP condition generated after data byte; however, occurs during byte transmission then previous data retained. facilitate smooth fine tuning, frequency data bytes only accepted device after bits data have been received after generation STOP condition. Repeatedly sending bytes only will change frequency. frequency change when following data sequences sent addressed device: Bytes Bytes when STOP condition follows valid data bytes thus: Bytes STOP Bytes STOP Bytes STOP Bytes STOP Bytes STOP should noted that SP5569 must addressed initially with both frequency control byte data, since control byte contains reference divider information which must provided before chosen frequency synthesised. This implies that after initial turn bytes must sent followed STOP condition minimum requirement. Alternatively, bytes must sent port information also required.
READ Mode
When device read mode status byte read from device line takes form shown Fig. Table (POR) power-on reset indicator logic supply device dropped below 25°C), example, when device initially turned Ratio Invalid 800kHz 400kHz 200kHz 100kHz 50kHz 25kHz Comparison frequency 2MHz 1MHz 500kHz 250kHz 125kHz
PROGRAMMING
SP5659 controlled Bus. Data Clock lines respectively, defined format. synthesiser either accept data (write mode) send data (read mode). address byte (R/W) sets device into write mode read mode high. Tables Fig. illustrate format data. device programmed respond several addresses, which enables more than synthesiser system. Table Fig. shows address selected applying voltage address input. When device receives valid address byte, pulls line during acknowledge period, during following acknowledge periods after further data bytes programmed. When device programmed into read mode, controller accepting data must pull line during status byte acknowledge periods read another status byte. controller fails pull line during this period, device generates internal STOP condition, which inhibits further reading.
WRITE Mode (Frequency Synthesis)
With reference Table bytes contain frequency information bits inclusive. Auxiliary frequency bits byte most frequencies, only bytes will required. remainder byte byte control prescaler enable, reference divider ratio (see Fig. output ports test modes (see Table After reception acknowledgment valid address (byte first following byte determines whether byte interpreted byte (logic `0') byte (logic `1');
Table Reference division ratios (4MHz external reference)
SP5659
reset when read sequence terminated STOP command. When high VCC), programmed information lost output ports high impedance. (FL) indicates whether device phase locked, logic present device locked, logic device unlocked. Bits (A2, combine give output ADC. used feed information microprocessor bus. Charge pump current charge pump current programmed bits data byte defined Fig. Table Test mode test modes invoked setting logic logic within programming data selected bits TS2, shown Fig. Table When TS2, received, device retains previously data. Reference comparison frequency output reference frequency FREF switched REF/ COMP output (pin setting byte logic logic `0'. comparison frequency FCOMP switched REF/COMP output setting logic logic `1'. logic `0', output disabled high state. default logic during power-up, thus enabling FCOMP REF/COMP output.
Additional Programmable Features
Prescaler enable prescaler enabled setting byte logic `1'. logic disables prescaler, directly passing input 17-bit counter. static select only.
Address Programmable divider Programmable divider Control data Control data
Byte Byte Byte Byte Byte
P2/TS2 P1/TS1 P0/TS0
Table Write data format (MSB transmitted first)
Address Status byte Byte Byte
Table Read data format
Voltage input Address input voltage level Open circuit
Table levels
MA1, 216-20 TS2, TS1,
Table Address selection
Acknowledge Variable address bits (see Table Programmable division ratio control bits Prescaler enable Reference division ratio select (see Table Charge pump current select (see Table Reference oscillator output enable REF/COMP select when Test mode enable when (see Table Test mode control bits (valid when 1,see Table Port output state (always valid except when (see Table Ports output states Power reset indicator Phase lock flag data (see Table Don't care
Fig. Data formats
cont.
SP5659
REF/COMP mode Disabled high state Disabled high state Disabled high state
Test mode description Normal operation Charge pump sink, status byte Charge pump source, status byte
Disabled high state Charge pump disabled, status byte Disabled high state Disabled high state FREF switched FCOMP switched Port FPD/2 Varactor drive output disabled Normal operation Normal operation
Table REF/COMP output mode test modes
Current (µA) Min. 6195 6416 6900 Typ. 6120 6260 6555 61200 Max. 6150 6325 6694 61500
byte byte
Table Charge pump current Fig. Data formats (continued)
INTO
INTO
OPERATING WINDOW
OPERATING WINDOW
1000 2000 3000 3500
1000 2000 2700 3000 3500
FREQUENCY (MHz)
FREQUENCY (MHz)
Fig. Prescaler disabled, Fig. Typical input sensitivity
Fig. Prescaler enabled,
SP5659
DOUBLE CONVERSION TUNER SYSTEMS
high maximum operating frequency excellent noise characteristics SP5659 allow construction double conversion high tuners. typical shown Fig. uses SP5659 first local oscillator control full band conversion greater than 1GHz. wide range reference division ratios allows SP5659 used both converter local oscillator with high phase comparison frequency (hence phase noise) down converter which uses device lower comparison frequency mode, which gives fine step size.
50-900MHz
1650-2700MHz REFERENCE CLOCK FIRST SP8659 SECOND SP8659
Fig. Example double conversion from VHF/UHF frequencies
4MHz
SP5659
130V 112V
Optional application using on-chip crystal controlled oscillator
BCW31
TUNER
OSCILLATOR OUTPUT
REF/COMP
CONTROL MICRO
ADDRESS
SP5659
Fig. Typical application
APPLICATION NOTES
application note, AN168, available designing with synthesisers such SP5659. covers aspects such loop filter design decoupling. application note published Mitel Semiconductor Media Handbook. generic test/demonstration board been produced, which used SP5659. circuit diagram layout board shown Figs. board used following purposes: Measuring sensitivity performance Indicating port function Synthesising voltage controlled oscillator Testing external reference sources programming codes relevant these tests given Fig.
SP5659
EXTERNAL REFERENCE 100n 4MHz DISABLE/REF ENABLE DATA/SDA CLOCK/SCL 100p 100p
100n
130V
112V
100n
(NOT FITTED, NOTE
2N3904 RFINPUT
NOTES circuit diagram shown designed with number synthesisers. connected redundant when SP5659 used this board. external reference, capacitor must fitted capacitor removed from board.
112V
Fig. Test board circuit diagram
RJM51 BOTTOM SILK SCREEN COMPONENT LOCATION
Fig. Test board layout
SP5659
LOOP BANDWIDTH
Most applications which SP5659 intended require loop filter bandwidth between 2kHz 10kHz. Typically, phase noise will specified both 1kHz 10kHz offset. common practice arrange loop filter bandwidth such that 1kHz figure lies within loop bandwidth. phase noise therefore depends synthesiser comparator noise floor rather than 10kHz offset figure should depend provided that loop been designed correctly underdamped. Assuming phase comparator noise floor flat regardless sampling frequency, this means that best performance will achieved when overall local oscillator phase comparator division ratio minimum. ways achieving higher phase comparator sampling frequency: Reduce division ratio between reference source phase comparator higher reference source frequency second approach preferred best performance since possible that noise floor reference oscillator degrade phase comparator performance reference division ratio very small.
REFERENCE SOURCE
SP5659 offers optimal local oscillator phase noise performance when operated with large step size. This because local oscillator phase noise within loop bandwidth Phase comparator noise floor 120log10 FCOMP where local oscillator frequency FCOMP phase comparator frequency.
DRIVING SP5659s FROM COMMON REFERENCE
REF/COMP output allows synthesisers driven from common reference. this, first device should programmed setting driven device should programmed normal operation with devices should connected shown Fig.
4MHz
SP5659
SP5659
Fig. SP5659 devices using common reference
S11:ZO NORMALISED
FREQUENCY MARKERS 100MHz, 500MHz, 1GHz
Fig. Typical input impedance
SP5659
VREF
CHARGE PUMP
INPUT INPUT
(O/P DISABLE)
DRIVE OUTPUT
inputs
Loop amplifier
SCL/SDA/ADC ADDRESS
ONLY
SDA, Address input
PORT
REF/COMP ENABLE/ DISABLE CRYSTAL
Reference oscillator
Output ports
Fig. Input/output interface circuits
REF/COMP output
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