2.7GHz 3-Wire Controlled Frequency Synthesiser Advance Information

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2.7GHz 3-Wire Controlled Frequency Synthesiser Advance Information

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SP5658
2.7GHz 3-Wire Controlled Frequency Synthesiser Advance Information
Supersedes October 1996 Media Handbook HB3923-2 DS4064 March 1998
SP5658 single chip frequency synthesiser designed tuning systems 2.7GHz. preamplifer contains divide prescaler which disabled applications 2GHz enabling step size equal comparison frequency 2GHz twice comparison frequency 2.7GHz. Comparison frequencies obtained either from crystal controlled on-chip oscillator from external source. device contains switching ports, version four pin, together with ``in-lock" flag output. device also contains varactor line disable charge pump disable facility.
CHARGE PUMP CRYSTAL DISABLE ENABLE DATA CLOCK PORT P1/OC
DRIVE
SP5658F
INPUT INPUT LOCK PORT P0/OP
MP14
FEATURES Complete 2.7GHz single chip system Optimised phase noise Selectable divide prescaler Selectable reference division ratio Charge pump disable Varactor line disable `In-lock' flag switching ports version Four switching ports version compatible with SP5659 phase noise synthesiserPP protection (Normal handling procedures should observed) APPLICATIONS SAT, Cable tuning systems Communications systems
CHARGE PUMP CRYSTAL
DRIVE
ENABLE DATA CLOCK PORT PORT
SP5658S
DISABLE
INPUT INPUT LOCK PORT P0/OP PORT P1/OC
MP16
Fig. connections view
ORDERING INFORMATION
SP5658F/KG/MP1S (Tubes, lead SP5658S/KG/MP2S (Tubes, lead SP5658F/KG/MP1T (Tape Mounted) SP5658S/KG/MP2T (Tape Mounted)
SP5658
INPUTS
PROGRAMMABLE DIVIDER
PHASE COMP COUNT comp REFERENCE DIVIDER Table CRYSTAL
:-16/17
COUNT
CHARGE PUMP LATCH DISABLE LATCH LATCH (R0,R1,R2) LATCH
CHARGE PUMP DRIVE
DISABLE ENABLE DATA CLOCK
DATA INTERFACE LATCH PORT INTERFACE LATCH FLOCK
P1/0C P0/OP
LOCK
Fig. SP5658S block diagram
SP5658
ELECTRICAL CHARACTERISTICS
-20°C 80°C, 4.5V 5.5V. Reference frequency 4MHz. These characteristics guaranteed either production test design. They apply within specified ambient temperature supply voltage ranges unless otherwise stated.
Value Characteristics (SP5658S) Units mVrms Prescaler enabled, DE=1 Prescaler disabled, DE=0 300MHz 2.7GHz Prescaler enabled, DE=1, Fig. 80MHz Prescaler enabled, DE=1, Fig. 100MHz 2.0GHz Prescaler disabled, DE=0, Fig. 80MHz Prescaler disabled, DE=0, Fig. Refer Fig. Refer Fig. Conditions
Supply current,
input voltage
13,14
mVrms
mVrms
13,14
mVrms
input impedance input capacitance Data, Clock, Enable Disable Input high voltage Input voltage Input high current Input current Clock Rate Clock data enable input hysteresis
3,4,5,6
Input voltage Input voltage
4,5,6
SP5658
ELECTRICAL CHARACTERISTICS
-20°C 80°C, 4.5V 5.5V. Reference frequency 4MHz. These characteristics guaranteed either production test design. They apply within specified ambient temperature supply voltage ranges unless otherwise stated. Characteristics (SP5658S) Timing Data Data hold, Enable Enable hold, Clock enable, Charge pump output current Charge pump output leakage Charge pump drive output current Oscillator temperature stability Oscillator supply voltage stability External reference input frequency External reference input amplitude Crystal frequency Crystal oscillator drive level Recommended crystal series resistance ppm/°C ppm/V mVPP mVPP Applies 4MHz crystal only. ``Parallel resonant" crystal. Figure quoted under conditions including start Includes temperature process tolerances. coupled sinewave coupled sinewave 4,5,6 Fig. Fig. Fig. Fig. Fig. Table PIN1 PIN1 PIN16 0.7V Value Units Conditions
Crystal oscillator negative resistance Comparison frequency Phase noise phase detector
-142
dBC/
6kHz loop phase comparator freq 250kHz. Figure measured 1kHz offset, (within loop band width). Prescaler disabled, DE=0 Prescaler enabled, DE=1 Table
division ratio
131071 262142
Reference division ratio Output ports P0-P3 Sink current Leakage current Lock output Sink current Leakage current 7,8,9,10
PORT =0.7V PORT =13.2V
LOCK =0.7V, `out lock' lock'
Ports available SP5658F.
SP5658
ABSOLUTE MAXIMUM RATINGS
voltages referred
Characteristics
(SP5658S)
Units
Conditions
Supply voltage, input voltage input offset Port voltage Total port current Lock output offset Charge pump offset Drive offset Crystal offset Data, Clock, Enable Disable offset Storage temperature Junction temperature MP14 Thermal Resistance Chip ambient °C/W Chip case °C/W MP16 Thermal Resistance Chip ambient Chip case Power consumption =5.5V protection
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3
+0.3 +0.3 +0.3 +0.3 +0.3 +0.3 +125
coupled application Port state Port state
°C/W °C/W
ports off, prescaler enabled MIL-STD 3015
FUNCTIONAL DESCRIPTION
SP5658 contains elements necessary, with exception frequency reference, loop filter external high voltage transistor, control varicap tuned local oscillator, forming complete frequency synthesised source. device allows operation with high comparison frequency fabricated high speed logic, which enables generation loop with good phase noise performance. preamplifier contains selectable divide operation above 2.0GHz. 2GHz input interfaces directly with programmable divider, eliminating degradation phase noise prescaler action. block diagram shown Fig.2. SP5658 controlled standard 3-wire comprising data, clock enable inputs. programming word variant contains bits, four which used port selection, programmable divider ratio enable/disable prescaler, three bits select reference division ratio, bits R0-R2, charge pump current, remaining bits access test modes, disable varactor drive, data word variant identical except bits only required, which used port selection. programming format shown Fig. clock input disabled enable signal, data therefore only clocked into internal shift registers during enable high loaded into controlling buffers enable high transition. This load also synchronised with programmable divider giving smooth fine tuning. signal internal preamplifier, which provides gain reverse isolation from divider signals. output preamplifier selectable prescaler then fully programmable divider, which MN+A architecture. counter counter prescaler disabled; Note that control function cannot used dynamically. output programmable divider phase comparator where compared both phase frequency domain with comparison frequency. This frequency derived either from board crystal controlled oscillator from external source. both cases reference frequency divided down comparison frequency reference divider which programmable into ratios described Table output phase comparator feeds charge pump loop amplifier section, which when used with external high voltage transistor loop filter integrates current pulses into varactor line voltage. charge pump disabled high impedance state DISABLE input. varactor drive output also disabled within data word, switching external transistor `OFF' allowing external voltage written varactor line tuner alignment purposes. phase comparator also drives lock detect circuit which generates lock flag. `In-lock' indicated high impedance state lock output. programmable divider output divided comparison frequency, comp switched ports respectively switching device into test mode. test modes described Table
SP5658
CLOCK ENABLE DATA VARIANT FREQUENCY DATA DATA VARIANT 0.7V =Enable time =Data time =Data hold time =Clock-to-enable time =Enable hold time FREQUENCY DATA
TRANSMITTED FIRST
CLOCK
ENABLE
0.7V
0.7V
Programmable divider ratio control bits Prescaler (Enable Disable Reference divider ratio control bits (see Table1) Port control bits Charge Pump current select (see Table Drive output disable switch mode enable (see Table
Fig. Data format timing
RATIO
Comparison Frequency with 4MHz external reference.
2MHz 1MHz 500kHz 250kHz 125kHz 62.5kHz 31.25kHz 15.625kHz
Table Reference division ratios
SP5658
P0/OP
pd/2
P1/0C
comp
FUNCTIONAL DESCRIPTION
NORMAL OPERATION CHARGE PUMP DISABLE NORMAL OPERATION VARACTOR LINE DISABLE CHARGE PUMP VARACTOR LINE DISABLE PERMITTED
CONTROLLED BITS WITHIN DATA WORD
Table Test modes
0.23 0.68
CURRENT
0.37 1.12
Table Charge pump current
+j0.5
+j0.2
-j0.2
S11:Z0 NORMALISED
-j0.5
FREQUENCY MARKERS 100MHz, 500MHz, 1GHz 2.7GHz
Fig. Typical input impedance
INTO OPERA TING WINDOW
INTO OPERA TING WINDOW
1000
2000
3000 3500
1000
2000
3000 3500 2700
FREQUENCY (MHz)
FREQUENCY (MHz)
Fig. Typical input sensitivity (Prescaler disabled, DE=0)
Fig. Typical input sensitivity (Prescaler enabled, DE=1)
SP5658
DOUBLE CONVERSION TUNER SYSTEMS
high 2.7GHz maximum operating frequency excellent noise characteristics SP5658 enables construction double conversion high tuners. typical system shown Fig.7 will SP5658 first control full band upconversion greater than 1GHz. wide range reference division ratios allows SP5658 used both converter with high phase comparator frequency (hence phase noise) down converter which utilises device lower comparison frequency mode (which offers fine step size).
50-900MHz
1.6GHz
38.9MHz
1650-2700MHz First SP5658 Second SP5658
Fig. Example double conversion from VHF/UHF frequencies
+30V 4MHz 18pF 68pF 15nF 13k3 2N3904
Optional application utilising on-board crystal controlled oscillator
+12V
CONTROL MICRO ENABLE DATA CLOCK LOCK
OSCILLATOR OUTPUT
TUNER
SP5658F
Fig. Typical application, SP5658F
APPLICATION NOTES
generic application notes AN168 designing with synthesisers such SP5658 been written. This covers aspects such loop filter design decoupling. This application note also featured Media Handbook. generic test/demo board been produced which used SP5658. circuit diagram layout board shown Figs. board used following purposes: measuring sensitivity performance. Indicating port function. Synthesising voltage controlled oscillator. Testing external reference sources.
SP5658
EXTERNAL REFERENCE SKT2 10nF* *(NOT FITTED) 68pF
+30V +12V C7/C8/C9 100nF 2n2F INPUT SKT1
15nF
13K3
2N3904
4MHz DISABLE ENABLE DATA CLOCK 100pF 100pF 18pF
LOCK
Fig. Test board
Fig. Test board (layout)
SP5658
LOOP BANDWIDTH
majority applications which SP5658 intended require loop filter bandwidth between 2kHz 10kHz. Typically phase noise will specified both 1kHz and10kHz offset. common practice arrange loop filter bandwidth such that 1kHz figure lies within loop bandwidth. Thus phase noise depends synthesiser comparator noise floor, rather than VCO. 10kHz offset figure should depend providing loop designed correctly, underdamped.
REFERENCE SOURCE
SP5658 offers optimal phase noise performance when operated with large step size. This fact that phase noise within loop bandwidth phase comparator noise floor
frequency phase comparator frequency
Assuming phase comparator noise floor flat irrespective sampling frequency, this means that best performance will achieved when overall phase comparator division ratio minimum. There ways achieving higher phase comparator sampling frequency:- Reduce division ratio between reference source phase comparator higher reference source frequency. Approach preferred best performance since possible that noise floor reference oscillator degrade phase comparator performance reference division ratio very small.
SP5658
VREF
CHARGE PUMP
INPUTS (Output disable)
DRIVE OUTPUT
inputs
Loop amplifier
PORT/LOCK
BIAS
Disable, Enable, Data Clock inputs
Output Ports Lock Output
CRYSTAL
Reference oscillator
Fig. Input/Output interface circuits
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2.7GHz 3-Wire Controlled Frequency Synthesiser Advance Information

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