KS8721BL/SL 3.3V Single Power Supply 10/100BASE-TX/FX Physical La

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KS8721BL/SL 3.3V Single Power Supply 10/100BASE-TX/FX Physical La

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KS8721BL/SL
KS8721BL/SL
3.3V Single Power Supply 10/100BASE-TX/FX Physical Layer Transceiver
Rev.
General Description
Operating with 2.5V core meet low-voltage low-power requirements, KS8721BL KS8721SL 10BASET/100BASE-TX/FX Physical Layer Transceivers that RMII interfaces transmit receive data. They contain 10BASE-T Physical Medium Attachment (PMA), Physical Medium Dependent (PMD), Physical Coding Sub-layer (PCS) functions. KS8721BL/SL also have on-chip 10BASE-T output filtering. This eliminates need external filters allows single line magnetics used meet requirements both 100BASE-TX 10BASE-T. KS8721BL/SL automatically configures itself 10Mbps full- half-duplex operation, using on-chip auto-negotiation algorithm. ideal physical layer transceiver 100BASE-TX/10BASE-T applications.
Features
Single chip 100BASE-TX/100BASE-FX/10BASE-T physical layer solution 2.5V CMOS design; 2.5/3.3V tolerance 3.3V single power supply with built-in voltage regulator; Power consumption <340mW (including output driver current) Fully compliant IEEE 802.3u standard Supports Reduced (RMII) Supports 10BASE-T, 100BASE-TX, 100BASE-FX with Far_End_Fault Detection Supports power-down power-saving modes Configurable through serial management ports external control pins Supports auto-negotiation manual selection 10/100Mbps speed full-/half-duplex modes On-chip, built-in, analog front-end filtering both 100BASE-TX 10BASE-T
Functional Diagram
NRZ/NRZI MLT3 Encoder
4B/5B Encoder Scrambler Parallel/Serial
TXD3 TXD2 TXD1 TXD0 TXER
Transmitter
10/100 Pulse Shaper
Parallel/Serial Manchester Encoder
MII/RMII Registers Controller Interface
Adaptive Base Line Wander Correction MLT3 Decoder NRZI/NRZ
Clock Recovery
4B/5B Decoder Descrambler Serial/Parallel
Auto Negotiation
10BASE-T Receiver
Power Down Saving
Manchester Decoder Serial/Parallel
TXEN MDIO RXD3 RXD2 RXD1 RXD0 RXER RXDV
LINK
PWRDWN
Driver
Micrel, Inc. 2180 Fortune Drive Jose, 95131 (408) 944-0800 (408) 474-1000 http://www.micrel.com
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Features (continued)
outputs link, activity, full-/half-duplex, collision, speed Supports back-to-back, media converter applications Supports MDI/MDI-X auto-crossover KS8721BL drop-in replacement KS8721BT same footprint KS8721SL drop-in replacement KS8721B same footprint Commercial temperature range: +70°C Industrial temperature range: -40°C +85°C Available 48-pin SSOP LQFP
Ordering Information
Part Number KS8721BL KS8721SL KS8721BLI KS8721SLI KSZ8721BL KSZ8721SL KSZ8721BLI KSZ8721SLI Temp. Range +70°C +70°C -40°C +85°C -40°C +85°C +70°C +70°C -40°C +85°C -40°C +85°C
Package 48-Pin LQFP 48-Pin SSOP 48-Pin LQFP 48-Pin SSOP 48-Pin LQFP 48-Pin SSOP 48-Pin LQFP 48-Pin SSOP
Lead Finish Standard Standard Standard Standard Lead-Free Lead-Free Lead-Free Lead-Free
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Summary Changes Created. Initial release. Change format. part-ordering information. Editorial changes description, RMII, media converter operation. Update circuit design, reset timing, thermal resistance, electrical characteristics, strapping option circuit. Added product information. MDIO Pull-up resistor value changed 4.7k. Added note strapping option pins. Updated bits 1b.0 1b.7 self clearing. Updated electrical characteristics. Updated reference schematic strapping option configuration 3.3V. Crystal spec updated series resistance. Added additional magnetics qualified transformer table. lead-free part options. Added recommended reset circuit.
Revision History
Revision 0.90 Date 1/12/04 3/06/04
5/17/04 1/21/05
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Table Contents
Description Strapping Option.9 Configuration Introduction 100BASE-TX Transmit 100BASE-TX Receive Clock Synthesizer Scrambler/De-scrambler (100BASE-TX only) 10BASE-T Transmit 10BASE-T Receive Jabber Function (10BASE-T only) Auto-Negotiation Management Interface Data Interface.12 Transmit Clock Receive Clock Transmit Enable Receive Data Valid Error Signals.12 Carrier Sense Collision RMII (Reduced MII) Data Interface RMII Signal Definition.13 Reference Clock.13 Carrier Sense/Receive Data Valid.13 Receive Data.13 Transmit Enable Transmit Data Collision Detection RX_ER RMII Characteristics Unused RMII Pins Auto-Crossover (Auto-MDI/MDI-X) Power Management 100BT Mode Media Converter Operation Circuit Design Reference Power Supply Register Register Basic Control.18 Register Basic Status Register Identifier Register Identifier Register Auto-Negotiation Advertisement.19 Register Auto-Negotiation Link Partner Ability.19 Register Auto-Negotiation Expansion.20 Register Auto-Negotiation Next Page.20 Register Link Partner Next Page Ability
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Register (continued) Register 15h: RXER Counter.21 Register 1bh: Interrupt Control/Status Register Register 1fh: 100BASE-TX Controller Absolute Maximum Ratings Operating Ratings Electrical Characteristics Timing Diagrams Selection Isolation Transformer Selection Reference Crystal Package Information
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Name MDIO RXD3/ PHYAD Type(1) Ipd/O Function Management Independent Interface (MII) Data I/O. This requires external 4.7K pull-up resistor. Clock Input. This synchronous MDIO. Receive Data Output. [3.0], these bits synchronous with RXCLK. When RXDV asserted, [3.0] presents valid data through MII. [3.0] invalid when RXDV de-asserted. During reset, pull-up/pull-down value latched PHYADDR [1]. "Strapping Options" section details. Receive Data Output. During reset, pull-up/pull-down value latched PHYADDR[2]. "Strapping Options" section details. Receive Data Output. During reset, pull-up/pull-down value latched PHYADDR [3]. "Strapping Options" section details. Receive Data Output. During reset, pull-up/pull-down value latched PHYADDR [4]. "Strapping Options" section details. Digital /3.3V tolerant power supply. 3.3V power Input voltage regulator. "Circuit Design Ref. Power Supply" section details. Ground. Receive Data Valid Output. During reset, pull-up/pull-down value latched PCS_LPBK. "Strapping Options" section details. Receive Clock Output. Operating 25MHz 100Mbps, 2.5MHz 10Mbps. Receive Error Output. During reset, pull-up/pull-down value latched ISOLATE during reset. "Strapping Options" section details. Ground. Digital core 2.5V only power supply. "Circuit Design Ref. Power Supply" section details. Transmit Error Input. Transmit Clock Output. Input crystal external 50MHz clock. When REFCLK used clock interface, pull VDDPLL 2.5V resistor leave unconnected. Transmit Enable Input. Transmit Data Input. Transmit Data Input.
Description
Number
RXD2/ PHYAD2 RXD1/ PHYAD3 RXD0/ PHYAD4 VDDIO RXDV/ CRSDV/ PCS_LPBK RXER/ISO
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
VDDC TXER TXC/ REFCLK
Notes: Power supply. Ground. Input. Bidirectional.
TXEN TXD0 TXD1
Input internal pull-down. Ipd/O Input internal pull-down during reset, output otherwise. Input internal pull-up. Ipu/O Input internal pull-up during reset, output otherwise. Output.
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Number Name TXD2 TXD3 COL/RMII Type(1) Ipd/O Function Transmit Data Input. Transmit Data Input.
Collision Detect Output. During reset, pull-up/pull-down value latched RMII select. "Strapping Options" section details. Carrier Sense Output. During reset, pull-up/pull-down value latched RMII back-to-back mode when RMII mode selected. "Strapping Options" section details. Ground. Digital 2.5/3.3V tolerant power supply. 3.3V power input voltage regulator. "Circuit Design Ref. Power Supply" section details. Management Interface (MII) Interrupt Out. Interrupt level Register During reset, latched PHYAD[0]. "Strapping Options" section details. Link/Activity Output. external pull-down enable test mode only used factory test. Active low. Link/Act Link Link State Definition "Off" "On" "Toggle" PHYAD0
CRS/ RMII_BTB VDDIO INT#/ PHYAD0 LED0/TEST
Ipd/O
Ipu/O
Ipu/O
LED1/ SPD100/ nFEF
Ipu/O
Speed Output. Latched SPEED (Register during power-up/ reset. "Strapping Options" section details. Active low. Speed 10BT 100BT State Definition "Off" "On"
LED2/
Ipu/O
Full-duplex Output. Latched DUPLEX (register during power-up/ reset. "Strapping DUPLEX Options" section details. Active low. Duplex Half Full State Definition "Off" "On"
LED3/ NWAYEN
Ipu/O
Collision Output. Latched ANEG_EN (register during power-up/ reset. "Strapping Options" section details. Collison Collision Collision State Definition "Off" "On"
Notes:
Power Down. Normal operation, Power-down. Active low.
Power supply. Ground. Input. Bidirectional. Input internal pull-down. Ipd/O Input internal pull-down during reset, output otherwise. Input internal pull-up. Ipu/O Input internal pull-up during reset, output otherwise. Output.
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Number 10BASE-T. Name VDDRX RXRX+ FXSD/FXEN REXT VDDRCV TXTX+ VDDTX Type(1) Ipd/O Function
Analog 2.5V power supply. "Circuit Design Ref. Power Supply" section details. Receive Input. Differential receive input pins 100FX, 100BASE-TX, Receive Input: Differential receive input 100FX, 100BASE-TX, 10BASEFiber Mode Enable Signal Detect Fiber Mode. FXEN mode disable. default "0". "100BT Mode" section more details. Ground. Ground. External resistor (6.49kW connects REXT GND. Analog 2.5V power supply. 2.5V power output voltage regulator. "Circuit Design Ref. Power Supply" section details. Ground. Transmit Outputs: Differential transmit output 100FX, 100BASE-TX, 10BASE-T. Transmit Outputs: Differential transmit output 100FX, 100BASE-TX, 10BASETransmitter 2.5V power supply. "Circuit Design Ref. Power Supply" secfor details. Ground. Ground. XTAL feedback: Used with Xtal application. Crystal Oscillator Input: Input crystal external 25MHz clock. oscillator used, connects 3.3V tolerant oscillator, noconnect. Analog 2.5V power supply. "Circuit Design Ref. Power Supply" section details. Chip Reset. Active low, minimum 50µs pulse required.
tion
Notes: Power supply. Ground. Input. Bidirectional.
VDDPLL RST#
Input internal pull-down. Ipd/O Input internal pull-down during reset, output otherwise. Input internal pull-up. Ipu/O Input internal pull-up during reset, output otherwise. Output.
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Name PHYAD[4:1]/ RXD[0:3] PHYAD0/ INT# PCS_LPBK/ RXDV ISO/RXER RMII/COL RMII_BTB SPD100/ FEF/ Type(2) Ipd/O Ipu/O Ipd/O Ipd/O Ipd/O Ipd/O Ipu/O Enables PCS_LPBK mode power-up/reset. (default) Disable, Enable. Enables ISOLATE mode power-up/reset. (default) Disable, Enable. Enables RMII mode power-up/reset. (default) Disable, Enable. Enable RMII back-to-back mode power-up/reset. (default) Disable, Enable. Latched into Register during power-up/reset. 10Mbps, (default) 100Mbps. SPD100 asserted during power-up/reset, this also latched LED1 Speed Support register FXEN pulled latched value means Far_End _Fault.) Latched into Register during power-up/reset. Half-duplex, (default) Full-duplex. Duplex pulled during reset, this also latched Duplex support register Nway (auto-negotiation) Enable. Latched into Register during power-up/ reset. Disable Auto-Negotiation, (default) Enable Auto-Negotiation. Power-Down Enable. (default) Normal operation, Power-Down mode. Description Address latched power-up/reset. default address 00001.
Strapping Options(1)
Number 6,5, 9(3) 11(3) 21(3) 22(3)
DUPLEX/ LED2 NWAYEN/ LED3
Ipu/O
Notes:
Ipu/O
Strap-in latched during power-up reset. Input internal pull-up. Ipd/O Input internal pull-down during reset, output otherwise. Ipu/O Input internal pull-up during reset, output otherwise. "Reference Circuit" section pull-up/pull-down float information. Some devices drive pins that designated output (PHY) power-up, resulting incorrect strapping values latched reset. recmmended that external pull-down resistor used these applications augment 8721's internal pull-down.
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Configuration
MDIO R3D3/PHYAD1 RXD2/PHYAD2 RXD1/PHYAD3 RXD0/PHYAD4 RST# VDDPLL VDDTX TX39
VDDRCV
REXT
FXSD/FXEN RX31 VDDRX LED3/NWAYEN LED2/DUPLEX LED1/SPD100
LED0/TEST
INT#/PHYAD0
VDDIO RXDV/PCS_LPBK
RXER/ISO
VDDC TXER TXC/REF_CLK TXEN TXD0 TXD1 TXD2 TXD3 COL/RMII CRS/RMII_BTB
VDDIO
RST# VDDPLL VDDTX VDDRCV REXT
MDIO RXD1/PHYAD1 RXD2/PHYAD2 RXD1/PHYAD3 RXD0/PHYAD4 VDDIO RXDV/PCS_LPBK RXER/ISO
VDDC TXER TXC/REF_CLK TXEN TXD0 TXD1 TXD2 TXD3 COL/RMII CRS/RMII_BTB VDDIO
FXSD/FXEN VDDRX LED3/NWAYEN LED2/DUPLEX LED1/SPD100 LED0/TEST INT#/PHYAD0
48-Pin SSOP (SM)
48-Pin LQFP (LQ)
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Introduction
100BASE-TX Transmit
100BASE-TX transmit function performs parallel serial conversion, NRZ-to-NRZI conversion, MLT-3 encoding transmission. circuitry starts with parallel serial conversion that converts 25MHz, 4-bit nibbles into 125MHz serial stream. incoming data clocked positive edge signal. serialized data further converted from NRZI format, then transmitted MLT3 current output. output current external 6.49k resistor transformer ratio. typical rise/fall time complies with ANSI TP-PMD standard regarding amplitude balance, overshoot, timing jitter. wave-shaped 10BASE-T output driver also incorporated into 100BASE-TX driver.
100BASE-TX Receive
100BASE-TX receive function performs adaptive equalization, restoration, MLT-3 NRZI conversion, data clock recovery, NRZI-to-NRZ conversion, serial-to-parallel conversion. receiving side starts with equalization filter compensate inter-symbol interference (ISI) over twisted pair cable. Since amplitude loss phase distortion function length cable, equalizer adjust characteristic optimize performance. this design, variable equalizer will make initial estimation based comparisons incoming signal strength against some known cable characteristics, then tunes itself optimization. This ongoing process self-adjust environmental changes such temperature variations. equalized signal then goes through restoration data conversion block. restoration circuit used compensate effects base line wander improve dynamic range. differential data conversion circuit converts MLT3 format back NRZI. slicing threshold also adaptive. clock recovery circuit extracts 125MHz clock from edges NRZI signal. This recovered clock then used convert NRZI signal into format. Finally, serial data converted 4-bit parallel nibbles. synchronized 25MHz generated that nibbles clocked negative edge RCK25 valid receiver positive edge. When valid data present, clock recovery circuit locked 25MHz reference clock both clocks continue run.
Clock Synthesizer
KS8721BL/SL generates 125MHz, 25MHz, 20MHz clocks system timing. internal crystal oscillator circuit provides reference clock synthesizer.
Scrambler/De-scrambler (100BASE-TX only)
purpose scrambler spread power spectrum signal order reduce electromagnetic interference (EMI) baseline wander.
10BASE-T Transmit
When TXEN (transmit enable) goes high, data encoding transmission begins. KS8721BL/SL continues encode transmit data long TXEN remains high. data transmission ends when TXEN goes low. last transition occurs boundary cell last zero, center cell last one. output driver incorporated into 100BASE-T driver allow transmission with same magnetics. They internally wave-shaped pre-emphasized into outputs with typical 2.5V amplitude. harmonic contents least 27dB below fundamental when driven all-ones, Manchester-encoded signal.
10BASE-T Receive
receive side, input buffer level detecting squelch circuits employed. differential input receiver circuit performs decoding function. Manchester-encoded data stream separated into clock signal data. squelch circuit rejects signals with levels less than 300mV with short pulse widths order prevent noise input from falsely triggering decoder. When input exceeds squelch limit, locks onto incoming signal KS8721BL/SL decodes data frame. This activates carrier sense (CRS) RXDV signals makes receive data (RXD) available. receive clock maintained active during idle periods between data reception.
Jabber Function (10BASE-T only)
10BASE-T operation, short pulse after each packet transmitted. This required test 10BASE-T transmit/receive path called test. 10BASE-T transmitter disabled goes high TXEN high more than 20ms (Jabbering). TXEN then goes more than 250ms, 10BASE-T transmitter re-enabled goes low.
Auto-Negotiation
KS8721BL/SL performs auto-negotiation hardware strapping option (pin software (Register 0.12). automatically chooses mode operation advertising abilities comparing them with those received from link partner whenever auto-negotiation enabled. also configured advertise 100BASE-TX 10BASE-T either full- February 2005
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half-duplex mode (please refer "Auto-Negotiation"). Auto-negotiation disabled mode. During auto-negotiation, contents Register coded fast link pulse (FLP), sent link partner under conditions power-on, link-loss, restart. same time, KS8721BL/SL monitors incoming data determine mode operation. parallel detection circuit enabled soon either 10BASE-T normal link pulse (NLP) 100BASE-TX idle detected. operation mode configured based following priority: Priority 100BASE-TX, full-duplex Priority 100BASE-TX, half-duplex Priority 10BASE-T, full-duplex Priority 10BASE-T, half-duplex When KS8721BL/SL receives burst from link partner with three identical link code words (ignoring acknowledge bit), will store these code words Register wait next three identical code words. Once KS8721BL/SL detects second code words, then configures itself according above-mentioned priority. addition, KS8721BL/SL also checks 100BASE-TX idle 10BASE-T symbols. either detected, KS8721BL/SL automatically configures match detected operating speed.
Management Interface
KS8721BL/SL supports IEEE 802.3 Management Interface, also known Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices monitor control state KS8721BL/SL. MDIO interface consists following: physical connection including data line (MDIO), clock line (MDC), optional interrupt line (INTRPT). specific protocol that runs across above-mentioned physical connection that allows controller communicate with multiple KS8721BL/SL devices. Each KS8721BL/SL assigned address between PHYAD inputs. internal addressable fourteen 16-bit MDIO registers. Registers [0:6] required their functions specified IEEE 802.3 specifications. Additional registers provided expanded functionality. INTPRT functions management data interrupt MII. active High this indicates status change KS8721BL/SL based 1fh.9 level control. Register bits 1bh[15:8] interrupt enable bits. Register bits 1bh[7:0] interrupt condition bits. This interrupt cleared reading Register 1bh.
Data Interface
data interface consists separate channels transmitting data from 10/100 802.3 compliant Media Access Controller (MAC) KS8721BL/SL, receiving data from line. Normal data transmission implemented nibble mode (4-bit wide nibbles). Transmit Clock (TXC): transmit clock normally generated KS8721BL/SL from external 25MHz reference source input. transmit data control signals must always synchronized MAC. KS8721BL/SL normally samples these signals rising edge TXC. Receive Clock (RXC): 100BASE-TX links, receive clock continuously recovered from line. link goes down, auto-negotiation disabled, receive clock operates master input clock TXC). 10BASE-T links, receive clock recovered from line while carrier active, operates from master input clock when line idle. KS8721BL/SL synchronizes receive data control signals falling edge order stabilize signals rising edge clock with 10ns setup hold times. Transmit Enable: must assert TXEN same time first nibble preamble, de-assert TXEN after last packet. Receive Data Valid: KS8721BL/SL asserts RXDV when receives valid packet. Line operating speed mode will determine timing changes following way: 100BASE-TX links with mode, RXDV asserted from first nibble preamble last nibble data packet. 10BASE-T links, entire preamble truncated. RXDV asserted with first nibble "5D" remains asserted until packet. Error Signals: Whenever KS8721BL/SL receives error symbol from network, asserts RXER drives "1110" (4B) pins. When asserts TXER, KS8721BL/SL will drive symbols Transmit Error defined IEEE 802.3 4B/5B code group) line force signaling errors. Carrier Sense (CRS): 100BASE-TX links, start-of-stream delimiter, /J/K symbol pair causes assertion Carrier Sense (CRS). end-of-stream delimiter, /T/R symbol pair, causes de-assertion CRS. layer will also de-assert IDLE symbols received without /T/R, this case RXER will asserted clock cycle when de-asserted. 10BASE-T links, assertion based reception valid preamble, de-assertion reception
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end-of-frame (EOF) marker. Collision: Whenever line state half-duplex transmitter receiver active same time, KS8721BL/ asserts collision signal, which asynchronous clock.
RMII (Reduced MII) Data Interface
RMII interface specifies low-pin count, Reduced Media Independent Interface (RMII) intended between Ethernet PHYs Switch Repeater ASICs. fully compliant with IEEE 802.3u [2]. This interface following characteristics: capable supporting 10Mbps 100Mbps data rates. single clock reference sourced from from external source). provides independent 2-bit wide (di-bit) transmit receive data paths. uses signal levels compatible with common digital CMOS ASIC processes.
RMII Signal Definition
Signal Name REF_CLK CRS_DV RXD[1:0] TX_EN TXD[1:0] RX_ER Direction (w/respect PHY) Input Output Output Input Input Output Direction (w/respect MAC) Input Output Input Input Output Output Input (Not Required) Synchronous clock reference receive, transmit control interface Carrier Sense/Receive Data Valid Receive Data Transmit Enable Transmit Data Receive Error
Reference Clock (REF_CLK)
REF_CLK continuous 50MHz clock that provides timing reference CRS_DV, RXD[1:0], TX_EN, TXD[1:0], RX_E. REF_CLK sourced external source. Switch implementations choose provide REF_CLK input output depending whether they provide REF_CLK output rely external clock distribution device. Each device must have input corresponding this clock single clock input multiple PHYs implemented single
Carrier Sense/Receive Data Valid (CRS_DV)
CRS_DV asserted asynchronously detection carrier criteria relevant operating mode. That 10BASE-T mode, when squelch passed 100BASE-X mode when noncontiguous zeroes bits detected, carrier detected. Loss-of-carrier results de-assertion CRS_DV synchronous REF_CLK. carrier criteria met, CRS_DV remains continuously asserted from first recovered di-bit frame through final recovered di-bit negated prior first REF_CLK that follows final di-bit. data RXD[1:0] considered valid once CRS_DV asserted. However, since assertion CRS_DV asynchronous relative REF_CLK, data RXD[1:0] remains "00" until proper receive signal decoding takes place (see "Definition RXD[1:0] Behavior").
Receive Data [1:0] (RXD[1:0])
RXD[1:0] transitions synchronously REF_CLK. each clock period which CRS_DV asserted, RXD[1:0] transfers bits recovered data from PHY. some cases (e.g., before data recovery during error conditions), predetermined value RXD[1:0] transferred instead recovered data. RXD[1:0] remains "00" indicate idle when CRS_DV de-asserted. Values RXD[1:0] other than "00" when CRS_DV de-asserted reserved out-of-band signalling defined). Values other than "00" RXD[1:0] while CRS_DV de-asserted ignored MAC/repeater. Upon assertion CRS_DV, ensures that RXD[1:0]=00 until proper receive decoding takes place.
Transmit Enable (TX_EN)
Transmit Enable TX_EN indicates that presenting di-bits TXD[1:0] RMII transmission. TX_EN asserted synchronously with first nibble preamble remains asserted while transmitted di-bits presented RMII. TX_EN negated prior first REF_CLK following final di-bit frame. TX_EN transitions synchronously with respect REF_CLK.
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Transmit Data [1:0] (TXD[1:0])
Transmit Data TXD[1:0] transitions synchronously with respect REF_CLK. When TX_EN asserted, TXD[1:0] accepted transmission PHY. TXD[1:0] remains "00" indicate idle when TX_EN de-asserted. Values TXD[1:0] other than "00" when TX_EN de-asserted reserved out-of-band signalling defined). Values other than "00" TXD[1:0] while TX_EN de-asserted ignored PHY.
Collision Detection
Since definition CRS_DV TX_EN both contain accurate indication start frame, reliably regenerates signal ANDing TX_EN CRS_DV. During time following successful transmission frame, signal asserted some transceivers self-test. Signal Quality Error (SQE) function supported reduced lack signal. Historically, present indicate that transceiver located physically remote from functioning. Since reduced only supports chip-to-chip connections PCB, functionality required.
RX_ER
provides RX_ER output according rules specified IEEE 802.3u (see Clause Figure 2411- Receive State Diagram). RX_ER asserted more REF_CLK periods indicate that error (e.g., coding error error that capable detecting, that otherwise undetectable sublayer) detected somewhere frame presently being transferred from PHY. RX_ER transitions synchronously with respect REF_CLK. While CRS_DV de-asserted, RX_ER effect MAC.
RMII Characteristics
Symbol Parameter REF_CLK Frequency REF_CLK Duty Cycle TXD[1:0], TX_EN, RXD[1:0], CRS_DV, RXER TXD[1:0], TX_EN, RXD[1:0], CRS_DV, RXER Data Hold from REF_CLK Rising Edge Unit
Unused RMII Pins
Input Pins Output Pins TXD[2:3] TXER pull-down GND. RXD[2:3] connect. Note that RMII needs pulled enable RMII mode.
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Auto-Crossover (Auto-MDI/MDI-X)
Automatic MDI/MDI-X configuration intended eliminate need crossover cables between similar devices. assignment pinouts 10/100 BASE-T crossover function cable shown below. This feature eliminates confusion applications allowing both straight crossover cables. This feature controlled register 1f:13. "Register 1fh-100BASE-TX Controller" section details.
10/100 BASE-T Media Dependent Interface
10/100 BASE-T Media Dependent Interface
Transmit Pair
Receive Pair
Receive Pair
Transmit Pair
Modular Connector (RJ45)
Modular Connector (RJ45) (Repeater Switch)
Figure Straight Through Cable
10/100 BASE-T Media Dependent Interface
10/100 BASE-T Media Dependent Interface
Receive Pair
Receive Pair
Transmit Pair
Transmit Pair
Modular Connector (RJ45) (Repeater Switch)
Modular Connector (RJ45) (Repeater Switch)
Figure Crossover Cable
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Power Management
KS8721BL/SL offers following modes power management: Power-Down Mode: This mode achieved writing Register 0.11 pulling low. Power-Saving Mode: This mode disabled writing Register 1fh.10. KS8721BL/SL turns everything except Energy Detect circuits when cable installed. other words, KS8721BL/SL shuts down most internal circuits save power there link. Power-saving mode most effective state when auto-negotiation mode enabled.
100BT Mode
Please contact your local field application engineer (FAE) reference schematic fiber connection. 100BT mode activated when FXSD/FXEN higher than 0.6V (this default pull down). Under this mode, auto-negotiation auto-MDI-X features disabled. fiber operation, FXSD should connect signal detect (SD) output fiber module. internal threshold FXSD around ±50mV (1.25V ±0.05V). Above this level, fiber signal considered detected. operation summarized following table:
FXSD/FXEN Less than 0.6V Less than 1.25V, greater than 0.6V Greater than 1.25 Condition 100TX mode mode signal detected generated mode Signal detected
Table 100BT Mode ensure proper operation, swing fiber module should cover threshold variation. resistive voltage divider recommended adjust voltage range. Fault (FEF), repetition special pattern which consists 84-one 1-zero, generated under mode with signal detected." purpose notify sender faulty link. When receiving FEF, LINK will down indicate fault, even with fiber signal detected. transmitter affected receiving still sends normal transmit pattern from MAC. disabled strapping low. Refer "Strapping Options" section.
Media Converter Operation
KS8721BL/SL capable performing media conversion with parts back-to-back RMII loop-back mode indicated diagram. Both parts RMII mode with RMII asserted (pins strapped high). part operating mode other operating mode. Both parts share common 50MHz oscillator. Under this operation, auto-negotiation side prohibits 10BASE-T link-up. Additional options implemented under this operation. Disable transmitter tri-state controlling high TXD2 pin. order this, RXD2 TXD2 pins need connected inverter. When TXD2 high both copper fiber operation, disabled transmit. Meanwhile, RXD2 copper side serves energy detect indicate line signal detected. TXD3 should tied RXD3 float. Please contact your Micrel media converter reference design.
KS8721BL/SL
TxC/ Ref_CLK
TxC/ Ref_CLK
50MHz
KS8721BL/SL
(Fiber Mode)
Fiber Module
Figure Fiber Module
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Circuit Design Reference Power Supply
Micrel's integrated built-in, voltage regulator technology thoughtful implementation allows user save cost both existing future designs with KS8721BL/SL single supply, single port 10/100 Ethernet PHY.
Ferrite Bead
+3.3V
Ferrite Bead +2.5VA
+2.5V
+2.5VPLL
VDDRX
VDDI/O
VDDI/O
Voltage Regulator
KS8721BL/SL
Figure Circuit Design
circuit design Figure shows power connections power supply: 3.3V VDDI/O only input power source 2.5V VDDRCV, output voltage regulator that needs supply through rest 2.5V pins 2.5V power plane. 2.5V pins make drop-in replacement with existing KS8721B/BT part. Table shows drop-in replacement from existing KS8721B/BT KS8721SL/BL. Please contact your local Micrel Application Note AN-117, "Drop-in Replacement with KS8721BT."
2.5V/3.3V Supply Part Number KS8721B KS8721BT KS8721BI Package 48-SSOP 48-TQFP 48-SSOP 3.3V Supply with Built-in Regulator Part Number KS8721SL48-SSOP KS8721BL48-LQFP KS8721SLI 48-SSOP Package
Table Drop-In Replacement
February 2005
VDDRCV
VDDTX
VDDC
VDDPLL
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KS8721BL/SL
Description Basic Control Register Basic Status Register Identifier Identifier Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register Auto-Negotiation Next Page Register Link Partner Next Page Ability RXER Counter Register Interrupt Control/Status Register 100BASE-TX Control Register
Register
Register
Address 0.15 0.14 0.13 0.12 0.11 0.10 0.6:1
Name Reset Loop-Back Speed Select (LSB) Auto-Negotiation Enable Power Down Isolate Restart Auto-Negotiation Duplex Mode Collision Test Reserved Disable Transmitter 100BASE-T4 100BASE-TX Full-Duplex
Description software reset. self-clearing.
Mode(1)
Default RW/SC SPD100 NWAYEN DUPLEX
Register Basic Control loop-back mode; normal operation. 100Mbps; 10Mbps. Ignored Auto-Negotiation enabled (0.12
enable auto-negotiation process (override 0.13 0.8). disable auto-negotiation process. power-down mode; normal operation. electrical isolation from TX+/TX-. normal operation. restart auto-negotiation process. normal operation. self-clearing. full-duplex; half-duplex. enable test; disable test. enable transmitter. disable transmitter. capable; capable. capable 100BASE-X full-duplex. capable 100BASE-X full-duplex. RW/SC
Register Basic Status 1.15 1.14 1.13 1.12 1.11
Note: Read/Write, Read Only, Self Clear, Latch High, Latch Low. Some default values strap-in. "Strapping Options."
100BASE-TX Half-Duplex capable 100BASE-X half-duplex. capable 100BASE-X half-duplex. 10BASE-T Full-Duplex 10BASE-T Half-Duplex 10Mbps with full-duplex. 10Mbps with full-duplex capability. 10Mbps with half-duplex. 10Mbps with half-duplex capability.
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KS8721BL/SL
Address 1.10:7 2.15:0 Name Reserved Preamble preamble suppression; normal preamble. Auto-Negotiation Complete auto-negotiation process completed. auto-negotiation process completed. Remote Fault Auto-Negotiation Ability Link Status Jabber Detect Extended Capability Number remote fault; remote fault. capable perform auto-negotiation. unable perform auto-negotiation. link link down. jabber detected; jabber detected. Default low. supports extended capabilities registers. Description Mode(1) RO/LH RO/LL RO/LH Default 0022h
Register Identifier Assigned through 18th bits organizationally. unique identifier (OUI). Micrel's 0010A1 (hex). Assigned 19th through 24th bits organizationally unique identifier (OUI). Micrel's 0010A1 (hex). manufacturer's model number. Four manufacturer's model number. next page capable; next page capability. remote fault supported; remote fault. pause function supported; pause function. capable; capability. with full-duplex; full-duplex capability.
Register Identifier 3.15:10 3.9:4 3.3:0 4.15 4.14 4.13 4.12 4.10 Number Model Number Revision Number Next Page Reserved Remote Fault Reserved Pause 100BASE-T4 100BASE-TX Full-Duplex 000101 100001 1001 SPD100 DUPLEX SPD100 DUPLEX 00001
Register Auto-Negotiation Advertisement
4.4:0 5.15 5.14 5.13 5.12
Note:
100BASE-TX 10BASE-T Full-Duplex 10BASE-T Selector Field Next Page Acknowledge Remote Fault Reserved
capable; capability. 10Mbps with full-duplex. 10Mbps full-duplex capability. 10Mbps capable; 10Mbps capability. [00001] IEEE 802.3. next page capable; next page capability. link code word received from partner. link code word received. remote fault detected; remote fault.
Register Auto-Negotiation Link Partner Ability
Read/Write, Read Only, Self Clear, Latch High, Latch Low. Some default values strap-in. "Strapping Options."
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Address 5.11:10 Name Pause Description 5.10 PAUSE Asymmetric PAUSE (link partner) Symmetric PAUSE Symmetric Asymmetric PAUSE (local device) capable; capability. with full-duplex; full-duplex capability. capable; capability. 10Mbps with full-duplex. 10Mbps full-duplex capability. 10Mbps capable; 10Mbps capability. [00001] IEEE 802.3. Mode(1) Default
5.4:0 6.15:5
BASE-T4 100BASE-TX Full-Duplex 100BASE-TX 10BASE-T Full-Duplex 10BASE-T Selector Field Reserved Parallel Detection Fault Link Partner Next Page Able Next Page Able Page Received Link Partner Auto-Negotiation Able Next Page Reserved Message Page Acknowledge Toggle Message Field Next Page Acknowledge Message Page Acknowledge Toggle
00001
Register Auto-Negotiation Expansion fault detected parallel detection. fault detected parallel detection. link partner next page capability. link partner does have next page capability. local device next page capability. local device does have next page capability. page received; page received. link partner auto-negotiation capability. link partner does have auto-negotiation capability. additional next page(s) will follow; last page. message page; unformatted page. will comply with message. cannot comply with message. previous value transmitted link code word. equaled logic One; logic Zero. 11-bit wide field encode 2048 messages. additional next page(s) will follow; last page. successful receipt link word. successful receipt link word. Message Page; unformatted page. able information. able information. previous value transmitted link code word equal logic zero; previous value transmitted link code word equal logic one. RO/LH RO/LH
Register Auto-Negotiation Next Page 7.15 7.14 7.13 7.12 7.11 7.10:0 8.15 8.14 8.13 8.12 8.11
Register Link Partner Next Page Ability
8.10:0
Note:
Message Field
Read/Write, Read Only, Self Clear, Latch High, Latch Low. Some default values strap-in. "Strapping Options."
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KS8721BL/SL
Address 15.15:0 1b.15 1b.14 1b.13 1b.12 1b.11 1b.10 1b.9 1b.8 1b.7 1b.6 1b.5 1b.4 1b.3 1b.2 1b.1 1b.0 Name RXER Counter Jabber Interrupt Enable Receive Error Interrupt Enable Page Received Interrupt Enable Parallel Detect Fault Interrupt Enable Description Error counter RX_ER each package. Enable jabber interrupt; Disable jabber interrupt. Enable receive error interrupt. Disable receive error interrupt. Enable page received interrupt. Disable page received interrupt. Enable parallel detect fault interrupt. Disable parallel detect fault interrupt. Mode(1) RO/SC RO/SC RO/SC RO/SC RO/SC RO/SC RO/SC RO/SC Default 0000 Register RXER Counter Register Interrupt Control/Status Register
Link Partner Acknowledge Enable link partner acknowledge interrupt. Interrupt Enable Disable link partner acknowledge interrupt. Link Down Interrupt Enable Remote Fault Interrupt Enable Link Interrupt Enable Jabber Interrupt Receive Error Interrupt Page Receive Interrupt Parallel Detect Fault Interrupt Link Partner Acknowledge Interrupt Link Down Interrupt Remote Fault Interrupt Link Interrupt Enable link down interrupt. Disable link down interrupt. Enable remote fault interrupt. Disable remote fault interrupt. Enable link interrupt. Disable link interrupt. Jabber interrupt occurred. Jabber interrupt occurred. Receive error occurred. Receive error occurred. Page receive occurred. Page receive occurred. Parallel detect fault occurred. Parallel detect fault occurred. Link partner acknowledge occurred. Link partner acknowledge occurred. Link down occurred. Link down occurred. Remote fault occurred. Remote fault occurred. Link interrupt occurred. Link interrupt occurred.
Register 100BASE-TX Controller 1f.15:14 1f:13 1f.12 1f.11 Reserved Pairswap Disable Energy Detect Force Link Disable MDI/MDI-X; Enable MDI/MDI-X. Presence signal RX+/RX- analog wire pair. signal detected RX+/RX-. Force link pass; Normal link operation. This bypasses control logic allow transmitter send pattern even there link. Enable power-saving; Disable. Interrupt active high; Active low. Enable jabber counter; Disable.
1f.10 1f.9 1f.8 1f.7
Note:
Power-Saving Interrupt Level Enable Jabber
Auto-Negotiation Complete Auto-negotiation complete; complete.
Read/Write, Read Only, Self Clear, Latch High, Latch Low. Some default values strap-in. "Strapping Options."
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Address 1f.6 1f.5 1f.4:2 Name Enable Pause (Flow-Control Result) Isolate Operation Mode Indication Description Flow control capable; flow control. isolate mode; isolated. [000] Still auto-negotiation. [001] 10BASE-T half-duplex. [010] 100BASE-TX half-duplex. [011] Reserved [101] 10BASE-T full-duplex. [110] 100BASE-TX full-duplex. [111] PHY/MII isolate. Enable test; Disable. Disable scrambler; Enable. Mode(1) Default
1f.1 1f.0
Note:
Enable Test Disable Data Scrambling
Read/Write, Read Only, Self Clear, Latch High, Latch Low. Some default values strap-in. "Strapping Options."
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Micrel Supply Voltage (VDD_PLL, VDD_TX, VDD_RXC, VDD_RCV, VDDC) +2.5V (VDDIO) +3.3V Ambient Temperature (TA) Commercial +70°C Industrial -40°C +85°C Package Thermal Resistance(3) LQFP (JA) Airflow. 83.56°C/W SSOP (JA) Airflow. 75.19°C/W
Absolute Maximum Ratings(1)
Storage Temperature (TS) -55°C +150°C Supply Referenced .-0.5V +4.0V Pins .-0.5V +4.0V Important: Please read Notes bottom page.
Operating Ratings(2)
Electrical Characteristics(4)
Symbol IDD1 IDD2 IDD3 Inputs Outputs Output High Voltage Output Voltage Output Tri-State Leakage RX+/RX- Differential Input Resistance Propagation Delay Peak Differential Output Voltage Output Voltage Imbalance Rise/Fall Time Rise/Fall Time Imbalance from magnetics RDTX from each output 0.95 Input High Voltage Input Voltage Input Current -4mA
1/2VDD(I/O) 1/2VDD(I/O)
3.3V ±10%
Parameter
Test Condition Including 43mA output current Including 103mA output current Auto-negotiation Enable
Units
Total Supply Current (including output driver current)(5) Normal 100BASE-TX Normal 10BASE-T (independent utilization) Power Saving Mode Power Down Mode
IDD5
+0.2
+0.6
1.05
100BASE-TX Receive
|IOZ|
100BASE-TX Transmit (measured differentially after transformer) VIMB from each output
Notes: Exceeding absolute maximum rating(s) cause permanent damage device. Operating maximum conditions extended periods affect device reliability. device guaranteed function outside operating rating. Unused inputs must always tied appropriate logic voltage level (Ground VDD). (heat spreader) package. Specification packaged product only. There 100% data transmission full-duplex mode minimum with 130-meter cable.
February 2005
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KS8721BL/SL
Symbol Parameter Duty Cycle Distortion Overshoot VSET Reference Voltage ISET Propagation Delay Jitters 10BASE-TX Receive RX+/RX- Differential Input Resistance Squelch Threshold Peak Differential Output Voltage Jitters Added Rise/Fall Time Crystal Oscillator Receive Clock, 100TX Receive Clock, Receive Clock Jitters Transmit Clock, 100TX Transmit Clock, Transmit Clock Jitters 5MHz square wave from each output ±3.5 from TDTX magentics 0.75 Condition ±0.5 100BASE-TX Transmit (measured differentially after transformer)
Units ns(pp) ns(pp) ns(pp)
10BASE-TX Transmit (measured differentially after transformer) from each output
Clock Outputs RXC100 RXC10
TXC100 TXC10
M9999-022105
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Timing Diagrams
TXEN
TXD[3:0]
TXP/TXM
tHD2
tSU2
tSU1
tCRS1
Valid Data
tHD1
tCRS2
Timing
TXEN
tSQE
tSQEP
Figure 10BASE-T Transmit Timing
Symbol tSU1 tSU2 tHD1 tHD2 tCRS1 tCRS2 tLAT tSQE
Parameter [3:0] Set-Up High TXEN Set-Up High [3:0] Hold After High TXEN Hold After High TXEN High Asserted Latency TXEN De-Asserted Latency TXEN High TXP/TXM Output Latency) (SQE) Delay After TXEN De-Asserted (SQE) Pulse Duration
Units
BT(1)
tSQEP
Table 10BASE-T Transmit Timing Parameters
February 2005
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KS8721BL/SL
tSU2
TXEN
tHD2 tHD1
tSU1
TXD[3:0], TXER Data
tCRS1 tLAT
tCRS2
TX+/TX-
Symbol
Figure 100BASE-T Transmit Timing
Symbol tSU1 tSU2 tHD1 tHD2 tHD3 tCRS1 tCRS2 tLAT
Parameter [3:0] Set-Up High TXEN Set-Up High [3:0] Hold After High TXER Hold After High TXEN Hold After High TXEN High Asserted Latency TXEN De-Asserted Latency TXEN High TX+/TX- Output Latency)
Units
BT(1)
Table 100BASE-T Transmit Timing Parameters
Note: 10ns 100BASE-TX.
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RX+/RX-
Start Stream
Stream
tCRS1
tCRS2
tRLAT
RXDV
RXD[3:0] RXER
Figure 100BASE-T Receive Timing
Symbol
Parameter Period Pulse Width Pulse Width [3:0], RXER, RXDV Set-Up Rising Edge [3:0], RXER, RXDV Hold from Rising Edge Latency, Aligned "Start Stream" Asserted "End Stream" De-Asserted
Units
tRLAT
tCRS1 tCRS2
Table 100BASE-T Receive Timing Parameters
February 2005
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Burst
Burst
TX+/TX-
tFLPW
tBTB
Clock Pulse TX+/TX-
Data Pulse
Clock Pulse
Data Pulse
tCTD
tCTC
Figure Auto-Negotiation/Fast Link Pulse Timing
Symbol tBTB tFLPW tCTD tCTC
Parameter Burst Burst Burst Width Clock/Data Pulse Width Clock Pulse Data Pulse Clock Pulse Clock Pulse Number Clock/Data Pulses Burst
Units
Table Auto-Negotiation/Fast Link Pulse Timing
M9999-022105
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KS8721BL/SL
tMD1
(Into
tMD2
Valid Data
tMD3
Valid Data
(Out Chip)
Valid Data
Figure Serial Management Interface Timing
Symbol tMD1 tMD2 tMD3
Parameter Period MDIO Set-Up (MDIO Input) MDIO Hold After (MDIO Input) MDIO Valid (MDIO Output)
Units
Table Serial Management Interface Timing
February 2005
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KS8721BL/SL
Supply Voltage
RST_N
Strap-In Value
Figure Reset Timing
Symbol
Parameter Stable Supply Voltages Reset High
Units
Table Reset Timing Parameters
Reset Circuit Diagram
Micrel recommendeds following discrete reset circuit shown Figure when powering KS8721BL/SL device. application where reset circuit signal comes from another device (e.g., CPU, FPGA, etc), recommend reset circuit shown Figure
KS8721BL/SL
CPU/FPGA RST_OUT_n 1N4148
10µF
Figure Recommended Reset Circuit.
1N4148 KS8721BL/SL 10µF
Figure Recommended Circuit Interfacing with CPU/FPGA Reset power-on-reset, provide necessary ramp rise time reset Micrel device. reset from CPU/ FPGA provides warm reset after power also recommended power core voltage earlier than VDDIO voltage. worst case, both core VDDIO voltages should come same time.
M9999-022105
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KS8721BL/SL
Reference Circuit Strapping Option Configuration
Figure shows reference circuit strapping option pins.
3.3V
Pull-Up
KS8721BL/SL
3.3V
Pull-down
KS8721BL/SL
Reference circuits unmanaged programming through ports.
Figure Reference Circuit, Strapping Option Pins
February 2005
M9999-022105
KS8721BL/SL
Selection Isolation Transformer(1)
simple isolation transformer needed line interface. isolation transformer with integrated common-mode choke recommended exceeding requirements. following table gives recommended transformer characteristics.
Characteristic Turns Ratio Open-Circuit Inductance (min.) Leakage Inductance (max.) Inter-Winding Capacitance (max.) D.C. Resistance (max.) Insertion Loss (max.) HIPOT (min.)
Note: IEEE 802.3u standard 100BASE-TX assumes transformer loss 0.5dB. transmit line transformer, insertion loss 1.3dB compensated increasing line drive current means reducing ISET resistor value. Please select transformer that supports auto-MDI/MDI-X.
Value 350µH 0.4µH 12pF 1.0dB 1500Vrms
Test Condition 100mV, 100kHz, 1MHz (min.)
0MHz 65MHz
Selection Reference Crystal
oscillator crystal with following typical characteristics recommended.
Characteristic Frequency Frequency Tolerance (max.) Load Capacitance (max.) Series Resistance (max.) Value 25.00000 ±100 Units
Single Port Magnetic Manufacturer Pulse Fuse Transpower Delta LanKom Integrated Transformers Pulse Pulse
Part Number H1102 S558-5999-U7 PT163020 HB726 LF8505 LF-H41S J0011D21 J00-0061
Auto MDIX
Number Ports
Table Qualified Transformer Lists
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February 2005
KS8721BL/SL
Package Information
48-Pin SSOP (SM)
February 2005
M9999-022105
KS8721BL/SL
48-Pin LQFP (LQ)
(408) 944-0800 (408) 474-1000 http://www.micrel.com information furnished Micrel this data sheet believed accurate reliable. However, responsibility assumed Micrel use. Micrel reserves right change circuitry specifications time without notification customer.
Micrel Products designed authorized components life support appliances, devices systems where malfunction product reasonably expected result personal injury. Life support devices systems devices systems that intended surgical implant into body support sustain life, whose failure perform reasonably expected result significant injury user. Purchaser's sale Micrel Products life support appliances, devices systems Purchaser's risk Purchaser agrees fully indemnify Micrel damages resulting from such sale. 2004 Micrel, Incorporated.
MICREL, INC.
2180 FORTUNE DRIVE
JOSE, 95131
M9999-022105
February 2005

KS8721BL/SL 3.3V Single Power Supply 10/100BASE-TX/FX Physical La

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