DS2182A line monitor chip monolithic CMOS device designed monitor real
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DS2182A Line Monitor Chip
DS2182A line monitor chip monolithic CMOS device designed monitor real-time performance lines. DS2182A frames data line, counts errors, supplies detailed information about status condition line. Large on-board counters allow accumulation errors extended periods, which permits single monitor many lines. Output clocks that synchronized incoming data stream provided easy extraction S-bits, bits, signaling bits, channel data. DS2182A meets requirements ANSI T1.231.
FEATURES
Performs Framing Monitoring Functions Supports Superframe Extended Superframe Formats Four On-Board Error Counters: 16-Bit Bipolar Violation 8-Bit 8-Bit 8-Bit Frame Error Indication Following: Yellow Blue Alarms Incoming B8ZS Codewords Zero Strings Change-of-Frame Alignment Loss Sync Carrier Loss Simple Serial Interface Used Configuration, Control, Status Monitoring Burst Mode Allows Quick Access Counters Status Updates Automatic Counter Reset Feature Single Supply; Low-Power CMOS Technology Available 28-Pin 28-Pin PLCC Upward-Compatible from Original DS2182
ORDERING INFORMATION
PART DS2182 DS2182N DS2182Q DS2182QN TEMP RANGE +70°C -40°C +85°C +70°C -40°C +85°C PIN-PACKAGE PLCC PLCC
CONFIGURATION
VIEW SCLK N.C. RYEL RLINK RLCLK RCLK RCHCLK RSER N.C. DS2182A RLOS RFER RNEG RPOS TEST RSIGSEL RSIGFR RABCD RMSYNC RFSYNC
DS2182A includes following changes from original DS2182: Ability Count Excessive Zeros Severely Errored-Framing-Event Indication Updated Detection Updated Detection Alarm Clear Indications
(600 mil)
Note: Some revisions this device incorporate deviations from published specifications known errata. Multiple revisions device simultaneously available through various sales channels. information about device errata, click here: www.maxim-ic.com/errata.
REV: 120103
DS2182A Line Monitor Chip
Table Description
NAME
TYPE
FUNCTION Receive Alarm Interrupt. Flags host controller during alarm conditions. Active low; open-drain output. Serial Data Data on-board registers. Sampled rising edge SCLK. Serial Data Out. Control status information from on-board registers. Updated falling edge SCLK; tri-stated during serial port write when high. Chip Select. Must read write serial port. Serial Data Clock. Used read write serial port registers. Connect. internal connection. This connected either VDD, floated. Receive Yellow Alarm. Transitions high when yellow alarm detected; goes when alarm clears. Receive Link Data. Updated with extracted data RCLK before start frames (193E) held until next update. Updated with extracted S-bit data RCLK before start even frames (193S) held until next update. Receive Link Clock. 4kHz demand clock RLINK Receive Clock. 1.544MHz primary clock Receive Channel Clock. 192kHz clock; identifies timeslot (channel) boundaries Receive Serial Data. Received serial data; updated rising edges RCLK Receive Frame Sync. Extracted 8kHz clock, RCLK wide; F-bit position each frame Receive Multiframe Sync. Extracted multiframe sync; positive-going edge indicates start multiframe; duty cycle Receive ABCD Signaling. Extracted signaling data output; valid each channel signaling frames. non-signaling frames, RABCD outputs each channel word. Receive Signaling Frame. High during signaling frames; during nonsignaling frames (and during resync) Receive Signaling Select. 193E framing, .667kHz clock that identifies signaling frames 1.33kHz clock 193S Reset. high-low transition clears internal registers resets counters. high-low-high transition initiates resync. Receive Bipolar Data Inputs. Sampled falling RCLK. Connect together receive data disable bipolar violation monitoring circuitry. Receive Carrier Loss. High consecutive appear RPOS RNEG; goes upon seeing 12.5% density. Receive Bipolar Violation. High during accused time RSER. bipolar violation detected, otherwise. Receive Frame Error. High during F-bit time when errors occur (193S), when errors occur (193E). during resync. Receive Loss-of-Sync. Indicates sync status; high when internal resync progress, otherwise.
SCLK N.C. RYEL RLINK RLCLK RCLK RCHCLK RSER RFSYNC RMSYNC RABCD RSIGFR RSIGSEL
RPOS RNEG RFER RLOS
DS2182A Line Monitor Chip
Table Power Test Description
NAME TEST TYPE Signal Ground. Test Mode. Connect normal operation. Positive Supply. 5.0V FUNCTION
Table Register Summary
REGISTER BVCR2 BVCR1 CRCCR OOFCR FECR RSR1 RIMR1 RSR2 RIMR2 RCR1 RCR2 ADDRESS 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 FUNCTION Bipolar Violation Count Register 16-bit presettable counter that records individual bipolar violations. Bipolar Violation Count Register 16-bit presettable counter that records individual bipolar violations. Error Count Register. 8-bit presettable counter that records CRC6 errored words 193E frame mode. Count Register. 8-bit presettable counter that records events. events defined RCR1.5 RCR1.6. Frame Error Count Register. 8-bit presettable counter that records individual errors framing pattern. Receive Status Register Reports alarm conditions. Receive Interrupt Mask Register Allows masking individual alarmgenerated interrupts from RSR1. Receive Status Register Reports alarm conditions. Receive Interrupt Mask Register Allows masking individual alarmgenerated interrupts from RSR2. Receive Control Register Programs device operating characteristics. Receive Control Register Programs device operating characteristics.
DS2182A Line Monitor Chip
Figure Block Diagram
Dallas Semiconductor
DS2182A
DS2182A Line Monitor Chip
SERIAL PORT INTERFACE
port pins DS2182A serve serial port. Eleven on-board registers allow user update operational characteristics monitor device status through host controller, minimizing hardware interfaces. port DS2182A read from written time. Serial port reads writes independent line timing signals RCLK, RPOS, RNEG. However, RCLK needed clear RSR1 RSR2 after reads.
ADDRESS/COMMAND
Reading writing control, configuration, status registers requires writing address/command byte prior transferring register data. first written (LSB) address/command word specifies register read write. following four bits identify register address. next bits reserved must proper operation. last address/ command word enables burst mode when set. burst mode causes registers consecutively read written Data read written DS2182A first.
CHIP SELECT CLOCK CONTROL
data transfers initiated driving input low. Input data latched rising edge SCLK must valid during previous period SCLK prevent momentary corruption register data during writes. Data output falling edge SCLK held next falling edge. data transfers terminated input transitions high. Port control logic disabled tri-stated when high.
DATA
Following eight SCLK cycles that input address/command byte write, data byte strobed into addressed register rising edge next eight SCLK cycles. Following address/command word read, contents selected register output falling edges next eight SCLK cycles. tristated during device write connected applications where host processor bidirectional pin.
BURST MODE
burst mode allows on-board registers consecutively written read host processor. burst read used poll registers. RSR1 RSR2 contents unaffected. This feature minimizes device initialization time system power-up reset. Burst mode initiated when ACB.7 address 0000. burst terminated low-high transition
ACB: Address Command Byte
NAME ADD3 ADD0 POSITION ACB.7 ACB.6 ACB.5 ACB.4 ACB.1 ACB.0 ADD3 ADD2 ADD1 FUNCTION Burst Mode. (and register address 0000), burst read write enabled. Reserved; must operation Reserved; must operation register address register address Read/Write Select write addressed register read addressed register ADD0
DS2182A Line Monitor Chip
Figure Serial Port Read/Write
NOTE SAMPLED RISING EDGE SCLK. NOTE UPDATED FALLING EDGE SCLK.
OPERATION COUNTERS
four counters DS2182A preset user establish event-count interrupt threshold. counters count from preset value until they reach saturation. saturation, each additional event occurrence sets appropriate RSR2 generates interrupt enabled RIMR2. DS2182A contains auto-counter reset feature burst read mode. RCR1.4 set, then user burst read four counters (five registers), four counters automatically reset after read takes place. Since burst mode terminated time taking high, user option reading registers only counters. RCR1.4 set, then read registers, burst mode not, clears count four counters. user wishes read port clear counters, then RCR1.4 must cleared first. counter registers read written time with serial port, which operates totally asynchronously with monitoring line. Reading register does affect count long RCR1.4 cleared. dual buffer architecture DS2182A ensures that error events missed while serial port being accessed reads.
BVCR1: Bipolar Violation Count Register BVCR2: Bipolar Violation Counter Register
NAME POSITION BVCR.7 BVCR.0 FUNCTION bipolar violation count bipolar violation count
Bipolar violation count register (BVCR1) most significant word BVCR2 least significant word presettable 16-bit counter that records individual bipolar violations. B8ZS mode enabled (RCR2.2 then B8ZS codewords counted. BVCR also programmed count excessive setting RCR2.5 bit. this mode, BVCR counts occurrences eight consecutive when B8ZS enabled consecutive when B8Z5 disabled. This counter increments times disabled loss-of-sync condition (RLOS counter saturates 65,535 generates interrupt each occurrence after saturation RIMR2.0 set. Note: properly preset bipolar violation count register, BVCR2 must written before BVCR1 written
DS2182A Line Monitor Chip
CRCCR: Count Register
CRC7 NAME CRC7 CRC0 CRC6 CRC5 POSITION CRCCR.7 CRCCR.0 CRC4 CRC3 CRC2 FUNCTION CRC6 word error count CRC6 word error count CRC1 CRC0
count register (CRCCR) 8-bit presettable counter that records word errors cyclic redundancy check (CRC). This 8-bit binary counter saturates generates interrupt each occurrence after saturation RIMR2.1 set. count this register only valid 193E-framing mode (RCR2.4 reset disabled 193S-framing mode (RCR2.4 count disabled during loss-of-sync condition (RLOS
OOFCR: Count Register
OOF7 NAME OOF7 OOF0 OOF6 OOF5 POSITION OOFCR.7 OOFCR.0 event count event count OOF4 OOF3 OOF2 FUNCTION OOF1 OOF0
count register (OOFCR) 8-bit presettable counter that records out-of-frame (OOF) events. events defined RCR1.5 RCR1.6. This 8-bit counter saturates generates interrupt each occurrence after saturation RIMR2.2 set. count disabled during loss-of-sync condition (RLOS
FECR: Frame Error Count Register
NAME FFE0 POSITION FECR.7 FECR.0 frame error count frame error count FUNCTION
frame error count register (FECR) 8-bit presettable counter that records individual frame-bit errors. 193E mode (RCR2.4 FECR records errors framing pattern (001011). 193S mode (RCR2.4 FECR records errors both (101010) (001110) framing patterns RCR1.3 set. RCR1.3 cleared, then FECR only records errors pattern. This 8-bit counter saturates generates interrupt each occurrence after saturation RIMR2.3 set. count disabled during loss-of-sync condition (RLOS
DS2182A Line Monitor Chip
RSR1: Receive Status Register
NAME 16ZD RYEL RLOS B8ZSD COFA 16ZD POSITION RSR1.7 RSR1.6 RSR1.5 RSR1.4 RSR1.3 RSR1.2 RSR1.1 RSR1.0 RYEL RLOS B8ZSD FUNCTION Zero Detect. when string eight consecutive been received RPOS RNEG. Zero Detect. when string consecutive been received RPOS RNEG. Receive Carrier Loss. when string consecutive been received RPOS RNEG. Cleared when more possible positions received. Receive Yellow Alarm. when yellow alarm detected. format yellow alarm determined RCR2.3 RCR2.4. Receive Loss-of-Sync. when resync progress. B8ZS Codeword Detect. when B8ZS codeword received RPOS RNEG independent whether B8ZS mode enabled (RCR2.2). Receive Blue Alarm. when over window, five fewer received. Cleared when over window, more received. Change-of-Frame Alignment. when last resync resulted change-of-frame multiframe alignment. COFA
Note: Alarm 16ZD cleared next occurrence RPOS RNEG.
DS2182A Line Monitor Chip
RECEIVE STATUS REGISTERS
receive status registers (RSR1 RSR2) used either polled interrupt configuration. polled configuration, user reads regular intervals check alarms. interrupt configuration, user monitors pin. When goes low, alarm condition occurred been reported RSRs. processor then read RSRs find which bits have been set. bits receive status registers operate latched fashion. That once set, they remain until read. bits cleared when read unless read performed burst mode alarm condition still exists.
Yellow Alarm
193S
RCR2.4 RCR2.3 then DS2182A examines incoming channels presence yellow alarm. consecutive channels, then reception yellow alarm declared. alarm considered cleared when first channel with received.
193S S-Bit
RCR2.4 RCR2.3 then DS2182A examines S-bit position frame presence yellow alarm. DS2182A declares presence yellow alarm first occurrence S-bit frame being alarm considered cleared when this S-bit returns
193E
RCR2.4 then DS2182A examines repeating 00FF pattern. this pattern received consecutive times without error, then yellow alarm declared. alarm considered cleared soon pattern other than 00FF received.
DS2182A Line Monitor Chip
RIMR1: Receive Interrupt Mask Register
NAME 16ZD RYEL RLOS B8ZSD COFA 16ZD POSITION RIMR1.7 RIMR1.6 RIMR1.5 RIMR1.4 RIMR1.3 RIMR1.2 RIMR1.1 RIMR1.0 RYEL RLOS B8ZSD FUNCTION Zero Detect Mask interrupt enabled interrupt masked Zero Detect Mask interrupt enabled interrupt masked Receive Carrier Loss Mask interrupt enabled interrupt masked Receive Yellow Alarm Mask interrupt enabled interrupt masked Receive Loss-of-Sync Mask interrupt enabled interrupt masked B8ZS Codeword Detect Mask interrupt enabled interrupt masked Receive Blue Alarm Mask interrupt enabled interrupt masked Change-of-Frame Alignment Mask interrupt enabled interrupt masked COFA
DS2182A Line Monitor Chip
RSR2: Receive Status Register
SEFE NAME SEFE RCLC RBLC FERR FECS OOFCS CRCCS BPVCS RCLC POSITION RSR2.7 RSR2.6 RSR2.5 RSR2.4 RSR2.3 RSR2.2 RSR2.1 RSR2.0 RBLC FERR FECS OOFCS FUNCTION Severely Errored Framing Event. when framing bits FPS) received error. Receive Carrier Loss Clear. when carrier signal restored; remains until read. Receive Blue Alarm Clear. when Blue Alarm (AIS) longer detected; remains until read. Frame Error. when (193S) (193E) errors occur. Frame Error-Count Saturation. next frame error event after 8bit frame error-count register (FECR) saturates 255. Out-of-Frame Count Saturation. next event after 8-bit Count Register (OOFCR) saturates 255. Count Saturation. next error event after 8-bit Count Register (CRCCR) saturates 255. Bipolar Violation Count Saturation. next error event after 16-bit Bipolar Violation Count Register (BVCR) saturates 65,535. CRCCS BPVCS
DS2182A Line Monitor Chip
RIMR2: Receive Interrupt Mask Register
SEFE NAME SEFE RCLC RBLC FERR FECS OOFCS CRCCS BPVCS RCLC RBLC POSITION RIMR2.7 RIMR2.6 RIMR2.5 RIMR2.4 RIMR2.3 RIMR2.2 RIMR2.1 RIMR2.0 FERR FECS OOFCS FUNCTION Severely Errored Framing-Event Mask interrupt masked interrupt enabled Receive Carrier Loss Clear Mask interrupt masked interrupt enabled Receive Blue Alarm Clear Mask interrupt masked interrupt enabled Frame Error Mask interrupt enabled interrupt masked Frame Error-Count Saturation Mask interrupt enabled interrupt masked Out-of-Frame Count Saturation Mask interrupt enabled interrupt masked Count Saturation Mask interrupt enabled interrupt masked Bipolar Violation Count Saturation Mask interrupt enabled interrupt masked CRCCS BPVCS
DS2182A Line Monitor Chip
RCR1: Receive Control Register
NAME OOF1 OOF2 OOF1 POSITION RCR1.7 RCR1.6 RCR1.5 RCR1.4 OOF2 SYNCC SYNCT FUNCTION Auto Resync Criteria resync event only resync event Receive Carrier Loss (RCL) Out-of-Frame event description. Valid when RCR1.5 cleared. frame bits FPS) error frame bits FPS) error Out-of-Frame event description. frame bits FPS) error follow event described RCR1.6 Auto Counter Reset. When set, four counters reset when read. Sync Criteria. Determines type algorithm used receive synchronizer; differs each frame mode. 193S Framing (RCR2.4 synchronize frame boundaries using pattern, then search multiframe using cross couple patterns sync algorithm 193E Framing (RCR2.4 normal sync (uses only) validate alignment with before declaring sync Sync Time validate consecutive F-bits before declaring sync validate consecutive F-bits before declaring sync Sync Enable. clear, DS2182A automatically begins resync conditions described RCR1.7 met. set, auto resync occurs. Resync. When toggled high, DS2182A initiates resync immediately. must cleared again subsequent resyncs. SYNCE RESYNC
SYNCC
RCR1.3
SYNCT SYNCE RESYNC
RCR1.2 RCR1.1 RCR1.0
DS2182A Line Monitor Chip
SYNCHRONIZER
heart monitor receive synchronizer. This circuit serves purposes: monitors incoming data stream loss-of-frame multiframe alignment, searches frame alignment pattern when sync loss detected. When sync loss detected, synchronizer begins off-line search alignment. output timing signals remain alignment with exception RSIGFR, which forced during resync. When only candidate qualified, output timing moves alignment beginning next multiframe. frame later, RLOS transitions low, indicating valid sync resumption normal sync-monitoring mode. Several bits RCR1 allow tailoring resync algorithm user. These bits described below.
Sync Criteria (RCR1.3)
193E
RCR1.3 determines which sync algorithm used when resync progress (RLOS 193E framing, when RCR1.3 synchronizer locks only pattern moves frame multiframe alignment after framing candidate qualified. RLOS goes frame after move alignment. When RCR1.3 alignment further tested CRC6 code match. RLOS transitions after CRC6 match occurs. CRC6 match occurs three attempts (three multiframes), algorithm resets search pattern begins. takes synchronizer check first CRC6 code after alignment been loaded. Each additional CRC6 test takes 3ms. Regardless state RCR1.3, more than candidate exists after 24ms, synchronizer begins eliminating emulators testing their CRC6 codes order find true framing candidate.
193S
193S framing, when RCR1.3 synchronizer crosschecks pattern with pattern help eliminate false-framing candidates such digital milliwatts. patterns compared repeating pattern .00111000111000.(00111x0 RCR2.3 this mode, must correctly identified synchronizer before sync declared. Clearing RCR1.3 causes synchronizer search pattern (101010.) without cross-coupling pattern. Frame sync established using information, while multiframe sync established only valid information present. valid pattern identified, synchronizer moves alignment, RLOS goes low, false multiframe position indicated RMSYNC. RFER indicates when received S-bit pattern does match assumed internal multiframe alignment. This mode used applications where nonstandard S-bit patterns exist. such applications, multiframe alignment information decoded externally using S-bits present RLINK.
Sync Time (RCR1.2)
RCR1.2 determines number consecutive framing pattern bits qualified before SYNC declared. RCR1.2 algorithm validates bits; RCR1.2 bits validated. Validating bits results superior false-framing protection while 10-bit testing minimizes reframe time. either case, synchronizer only establishes resync when only candidate found (Table
Table Average Reframe Time
FRAME MODE 193S 193E 3.0ms 6.0ms RCR1.2 3.75ms 7.5ms 4.5ms 9.0ms 6.5ms 13.0ms RCR1.2 7.25ms 14.5ms 8.0ms 16.0ms
Note: Average reframe time defined here average time takes from start resync (rising edge RLOS) actual loading alignment multiframe edge) into output receive timing.
DS2182A Line Monitor Chip
Sync Enable (RCR1.1)
When RCR1.1 cleared, receiver initiates automatic resync event occurs carrier loss (192 consecutive 0's) occurs (depends RCR1.7). When RCR1.1 set, automatic resync circuitry disabled. this case, resync only initiated setting RCR1.0 externally transitioning from high. Note that using initiate resync resets output timing while low; RCR1.1 does affect output timing until alignment located.
Resync (RCR1.0)
0-to-1 transition RCR1.0 causes synchronizer search framing pattern sequence immediately, regardless internal sync status. initiate another resync command, this must cleared then again.
RCR2: Receive Control Register
NAME BVCRF SFYEL B8ZS BVCRF POSITION RCR2.7 RCR2.6 RCR2.5 RCR2.4 RCR2.3 RCR2.2 RCR2.1 RCR2.10 SFYEL B8ZS FUNCTION Reserved; must proper operation Reserved; must proper operation Bipolar Violation Count Register Function Select count excessive count excessive Frame Mode Extended Superframe (193E, frames Superframe) Superframe (193S frames Superframe) Yellow Mode Select S-bit position frame channels Bipolar Eight-Zero Substitution B8ZS enabled B8ZS disabled Reserved; must proper operation Reserved; must proper operation
DS2182A Line Monitor Chip
Figure 193S Receive Multiframe Timing
NOTE SIGNALING DATA UPDATED DURING SIGNALING FRAMES CHANNEL BOUNDARIES. RABCD EACH CHANNEL WORD NONSIGNALING FRAMES. NOTE RLINK DATA (S-BIT) UPDATED BIT-TIME PRIOR S-BIT FRAMES HELD FRAMES.
Figure 193E Receive Multiframe Timing
NOTE SIGNALING DATA UPDATED DURING SIGNALING FRAMES CHANNEL BOUNDARIES. RABCD EACH CHANNEL WORD NONSIGNALING FRAMES. NOTE RLINK DATA (FDL DATA) UPDATED BIT-TIME PRIOR FRAMES HELD FRAMES.
DS2182A Line Monitor Chip
Figure Receive Multiframe Boundary Timing
NOTE RLINK TIMING SHOWN 193E; 193S, RLINK UPDATED EVEN FRAME BOUNDARIES HELD ACROSS MULTIFRAME EDGES. NOTE TOTAL DELAY FROM RPOS RNEG RSER OUTPUT RCLK PERIODS.
DS2182A Line Monitor Chip
ALARM OUTPUTS
transceiver also provides direct alarm outputs applications when additional decoding demuxing required supplement on-board alarm logic.
RLOS Output
receive loss-of-sync output indicates status receiver synchronizer circuitry. When high, off-line resynchronization progress high-low transition indicates that resync complete. RLOS (RSR1.3) latched version RLOS output. auto-resync mode selected (RCR1.1 RLOS real-time indication carrier loss event occurrence.
RYEL Output
yellow alarm output transitions high when yellow alarm detected. high-low transition indicates alarm condition been cleared. RYEL (RSR1.4) latched version RYEL output.
Output
bipolar violation output transitions high when accused emerges RSER. goes next time additional violations detected.
RFER Output
receive frame-error output transitions high F-bit time held high 2-bit periods when frame error occurs. 193S, framing patterns tested. pattern tested 193E framing. Additionally, 193E framing, RFER reports CRC6 codeword errors low-high-low transition (1-bit period-wide) one-half RCLK period before low-high transition RMSYNC (Figure
Reset (RST)
high-low transition clears registers forces immediate resync when returns high. must held system power-up ensure proper initialization counters registers. Following reset, host processor should restore control modes writing appropriate registers with control data.
DS2182A Line Monitor Chip
Figure Alarm Output Timing
NOTE RFER TRANSITIONS HIGH DURING F-BIT TIME RECEIVED FRAMING PATTERN ERROR. (FRAME F-BITS 193S IGNORED RCR2.3 ALSO, 193E, RFER TRANSITIONS HIGH ONEHALF BIT-TIME BEFORE RISING EDGE RMSYNC INDICATE CRC6 ERROR PREVIOUS MULTIFRAME. NOTE INDICATES RECEIVED BIPOLAR VIOLATION TRANSITIONS HIGH WHEN ACCUSED EMERGES FROM RSER. B8ZS ENABLED, DOES REPORT ZERO REPLACEMENT CODE. NOTE TRANSITIONS HIGH WHEN CONSECUTIVE BITS TRANSITIONS UPON RECEPTION 12.5% DENSITY. NOTE RLOS TRANSITIONS HIGH DURING F-BIT TIME THAT CAUSED EVENT AUTO-RESYNC ENABLED (RCR1.1 RESYNC ALSO OCCURS WHEN LOSS-OF-CARRIER DETECTED (RCL RCR1.7 WHEN RCR1.1 RLOS REMAINS UNTIL RESYNC OCCURS, REGARDLESS CARRIER LOSS FLAGS. THIS SITUATION, RESYNC INITIATED ONLY WHEN RCR1.0 TRANSITIONS LOW-TO-HIGH TRANSITIONS HIGH-LOW-HIGH.
DS2182A Line Monitor Chip
ABSOLUTE MAXIMUM RATINGS
Voltage Range Relative Ground.-0.1V +7.0V Operating Temperature Range.0°C +70°C Storage Temperature Range.-55°C +125°C Soldering Temperature.See IPC/JEDEC J-STD-020A
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device.
RECOMMENDED OPERATING CONDITIONS
+70°C) PARAMETER Input Logic Input Logic Supply SYMBOL -0.3 4.50 +0.8 5.50 UNITS NOTES
ELECTRICAL CHARACTERISTICS
(VDD ±10%, +70°C.) PARAMETER Supply Current Input Leakage Output Current (2.4V) Output Current (0.4V) Output Leakage SYMBOL -1.0 -1.0 +4.0 -1.0 +1.0 +1.0 UNITS NOTES
CAPACITANCE
+25°C) PARAMETER Input Capacitance Output Capacitance
Note Note Note Note Note Note Note
SYMBOL COUT
UNITS
NOTES
RCLK, SCLK, (MIN) 2.4V. RCLK 1.544MHz Outputs open. outputs except INT, which open-collector. outputs. Applies when tri-stated.
DS2182A Line Monitor Chip
CHARACTERISTICS-SERIAL PORT
(VDD ±10%, +70°C.) (Notes (See Figure Figure PARAMETER SCLK Setup SCLK Hold SCLK Falling Edge SCLK Time SCLK High Time SCLK Rise Fall Times
SCLK Setup
SYMBOL tCHD tCCH tCWH tCDV tCDZ
UNITS
SCLK Hold
Inactive Time
SCLK Valid
High-Z
Note Note
Measured 10ns maximum rise fall time. Output load capacitance 100pF.
DS2182A Line Monitor Chip
ELECTRICAL CHARACTERISTICS-RECEIVE
(VDD 5.0V ±10%, +70°C) (Notes (See Figure PARAMETER Propagation Delay RCLK RMSYNC, RFSYNC, RSISEL, RSIGFR, RLCLK, RCHCLK Propagation Delay RCLK RSER, RABCD, RLINK Transition Time, Outputs RCLK Period RCLK Pulse Width RCLK Rise Fall Times RPOS, RNEG Setup RCLK Falling RPOS, RNEG Hold RCLK Falling Propagation Delay RCLK RLOS, RYEL, RBV, RCL, RFER Minimum Pulse Width
Note Note
SYMBOL tPRS tPRD tTTR tCCH tSRD tHRD tPRA tRST
UNITS
Measured 10ns maximum rise fall time. Output load capacitance 100pF.
DS2182A Line Monitor Chip
Figure Serial Port Write Timing Diagram
NOTE SHADED REGIONS INDICATE "DON'T CARE" STATES INPUT. NOTE DATA BYTE BITS MUST VALID ACROSS CLOCK PERIODS PREVENT TRANSIENTS OPERATING MODES.
Figure Serial Port Read Timing Diagram
NOTE: SERIAL PORT WRITE MUST PRECEDE PORT READ PROVIDE ADDRESS INFORMATION.
DS2182A Line Monitor Chip
Figure Receive Timing Diagram
REVISION HISTORY
DATE
092299 Original release. Changed typo Description ESIGRF RSIGFR. 080802 Added Note Input Logic spec Recommended Operating Characteristics table. [Note RCLK, SCLK, (MIN) 2.4V.] Note added match device characteriztion. changes were made fit, form, function production units. Changed ordering information.
DESCRIPTION
120103
DS2182A Line Monitor Chip
PACKAGE INFORMATION
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information,
28-Pin DS2182 LINE MONITOR
INCHES 1.445 1.470 0.530 0.550 0.140 0.160 0.600 0.625 0.015 0.040 0.120 0.145 0.090 0.110 0.600 0.680 0.008 0.012 0.015 0.022
DS2182A Line Monitor Chip
PACKAGE INFORMATION (continued)
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information,
28-Pin PLCC DS2182Q LINE MONITOR
INCHES 0.165 0.180 0.090 0.120 0.020 0.026 0.033 0.013 0.021 0.009 0.012 0.485 0.495 0.450 0.456 0.390 0.430 0.485 0.495 0.450 0.456 0.390 0.430 0.060 0.050 0.042 0.048
Maxim/Dallas Semiconductor cannot assume responsibility circuitry other than circuitry entirely embodied Maxim/Dallas Semiconductor product. circuit patent licenses implied. Maxim/Dallas Semiconductor reserves right change circuitry specifications without notice time.
Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600
2003 Maxim Integrated Products Printed
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