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Hitachi Single-Chip Microcomputer
H8S/2199 Series
H8S/2199
HD6432199
H8S/2198
HD6432198
H8S/2197
HD6432197
H8S/2196
HD6432196
H8S/2199F-ZTATHD64F2199
Hardware Manual
ADE-602-191 2/15/00 Hitachi, Ltd.
Cautions
Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products.
Contents
Section
Overview. Overview Internal Block Diagram Arrangement Functions. 1.3.1 Arrangement 1.3.2 Functions.
Section
Overview 2.1.1 Features. 2.1.2 Differences between H8S/2600 H8S/2000 CPU. 2.1.3 Differences from H8/300 CPU. 2.1.4 Differences from H8/300H Operating Modes Address Space. Register Configuration 2.4.1 Overview. 2.4.2 General Registers 2.4.3 Control Registers. 2.4.4 Initial Register Values Data Formats 2.5.1 General Register Data Formats 2.5.2 Memory Data Formats Instruction Set. 2.6.1 Overview. 2.6.2 Instructions Addressing Modes. 2.6.3 Table Instructions Classified Function. 2.6.4 Basic Instruction Formats 2.6.5 Notes Bit-Manipulation Instructions. Addressing Modes Effective Address Calculation 2.7.1 Addressing Mode 2.7.2 Effective Address Calculation. Processing States. 2.8.1 Overview. 2.8.2 Reset State. 2.8.3 Exception-Handling State 2.8.4 Program Execution State. 2.8.5 Power-Down State. Basic Timing
Rev. 1.0, 02/00, page
2.9.1 2.9.2 2.9.3
Overview On-Chip Memory (ROM, RAM). On-Chip Supporting Module Access Timing.
Section
Operating Modes Overview. 3.1.1 Operating Mode Selection 3.1.2 Register Configuration. Register Descriptions 3.2.1 Mode Control Register (MDCR). 3.2.2 System Control Register (SYSCR). Operating Mode (Mode Address Each Operating Mode
Section
Power-Down State Overview. 4.1.1 Register Configuration. Register Descriptions 4.2.1 Standby Control Register (SBYCR) 4.2.2 Low-Power Control Register (LPWRCR) 4.2.3 Timer Register (TMA) 4.2.4 Module Stop Control Register (MSTPCR) Medium-Speed Mode. Sleep Mode. 4.4.1 Sleep Mode 4.4.2 Clearing Sleep Mode Module Stop Mode 4.5.1 Module Stop Mode Standby Mode. 4.6.1 Standby Mode 4.6.2 Clearing Standby Mode 4.6.3 Setting Oscillation Settling Time after Clearing Standby Mode Watch Mode 4.7.1 Watch Mode. 4.7.2 Clearing Watch Mode. Subsleep Mode 4.8.1 Subsleep Mode 4.8.2 Clearing Subsleep Mode Subactive Mode 4.9.1 Subactive Mode. 4.9.2 Clearing Subactive Mode. 4.10 Direct Transition. 4.10.1 Overview Direct Transition
Rev. 1.0, 02/00, page
Section
Exception Handling Overview 5.1.1 Exception Handling Types Priority. 5.1.2 Exception Handling Operation 5.1.3 Exception Sources Vector Table Reset 5.2.1 Overview. 5.2.2 Reset Sequence. 5.2.3 Interrupts after Reset Interrupts Trap Instruction Stack Status after Exception Handling Notes Stack
Section Interrupt Controller
Overview 6.1.1 Features. 6.1.2 Block Diagram 6.1.3 Configuration 6.1.4 Register Configuration. Register Descriptions 6.2.1 System Control Register (SYSCR). 6.2.2 Interrupt Control Registers (ICRA ICRD) 6.2.3 Enable Register (IENR). 6.2.4 Edge Select Registers (IEGR). 6.2.5 Status Register (IRQR). 6.2.6 Port Mode Register (PMR1) Interrupt Sources. 6.3.1 External Interrupts 6.3.2 Internal Interrupts 6.3.3 Interrupt Exception Vector Table Interrupt Operation. 6.4.1 Interrupt Control Modes Interrupt Operation. 6.4.2 Interrupt Control Mode 6.4.3 Interrupt Control Mode 6.4.4 Interrupt Exception Handling Sequence 6.4.5 Interrupt Response Times Usage Notes. 6.5.1 Contention between Interrupt Generation Disabling 6.5.2 Instructions that Disable Interrupts. 6.5.3 Interrupts during Execution EEPMOV Instruction.
Rev. 1.0, 02/00, page
Section
Overview. 7.1.1 Block Diagram Overview Flash Memory. 7.2.1 Features. 7.2.2 Block Diagram 7.2.3 Flash Memory Operating Modes. 7.2.4 Configuration 7.2.5 Register Configuration. Flash Memory Register Descriptions 7.3.1 Flash Memory Control Register (FLMCR1) 7.3.2 Flash Memory Control Register (FLMCR2) 7.3.3 Erase Block Register (EBR1). 7.3.4 Erase Block Register (EBR2). 7.3.5 Serial/Timer Control Register (STCR) On-Board Programming Modes. 7.4.1 Boot Mode 7.4.2 User Program Mode Programming/Erasing Flash Memory 7.5.1 Program Mode (n=1 when target address range H'00000 H'3FFFF when target address range H'40000 H'47FFF) 7.5.2 Program-Verify Mode 7.5.3 Erase Mode when target address range H'00000 H'3FFFF when target address range H'40000 H'47FFF) 7.5.4 Erase-Verify Mode when target address range H'00000 H'3FFFF when target address range H'40000 H'47FFF) Flash Memory Protection 7.6.1 Hardware Protection. 7.6.2 Software Protection 7.6.3 Error Protection. Interrupt Handling when Programming/Erasing Flash Memory. Flash Memory Writer Mode 7.8.1 Writer Mode Setting 7.8.2 Socket Adapters Memory 7.8.3 Writer Mode Operation. 7.8.4 Memory Read Mode. 7.8.5 Auto-Program Mode. 7.8.6 Auto-Erase Mode 7.8.7 Status Read Mode. 7.8.8 Status Polling 7.8.9 Writer Mode Transition Time 7.8.10 Notes Memory Programming
Rev. 1.0, 02/00, page
Notes when Converting F-ZTAT Application Software Mask-ROM Versions
Section
Overview 8.1.1 Block Diagram
Section
Clock Pulse Generator Overview 9.1.1 Block Diagram 9.1.2 Register Configuration. Register Descriptions 9.2.1 Standby Control Register (SBYCR) 9.2.2 Low-Power Control Register (LPWRCR) Oscillator 9.3.1 Connecting Crystal Resonator 9.3.2 External Clock Input. Duty Adjustment Circuit Medium-Speed Clock Divider Master Clock Selection Circuit Subclock Oscillator Circuit 9.7.1 Connecting 32.768 Crystal Resonator 9.7.2 When Subclock Needed. Subclock Waveform Shaping Circuit. Notes Resonator
Section Port
10.1 Overview 10.1.1 Port Functions 10.1.2 Port Input 10.1.3 Pull-Up Transistors. 10.2 Port 10.2.1 Overview. 10.2.2 Register Configuration. 10.2.3 Functions. 10.2.4 States 10.3 Port 10.3.1 Overview. 10.3.2 Register Configuration. 10.3.3 Functions. 10.3.4 States 10.4 Port 10.4.1 Overview.
Rev. 1.0, 02/00, page
10.5
10.6
10.7
10.8
10.9
10.4.2 Register Configuration. 10.4.3 Functions 10.4.4 States Port 10.5.1 Overview 10.5.2 Register Configuration. 10.5.3 Functions 10.5.4 States Port 10.6.1 Overview 10.6.2 Register Configuration. 10.6.3 Functions 10.6.4 States Port 10.7.1 Overview 10.7.2 Register Configuration. 10.7.3 Functions 10.7.4 Operation 10.7.5 States Port 10.8.1 Overview 10.8.2 Register Configuration. 10.8.3 Functions 10.8.4 Operation 10.8.5 States Port 10.9.1 Overview 10.9.2 Register Configuration. 10.9.3 Functions 10.9.4 States
Section Timer
11.1 Overview. 11.1.1 Features. 11.1.2 Block Diagram 11.1.3 Register Configuration. 11.2 Register Descriptions 11.2.1 Timer Mode Register (TMA) 11.2.2 Timer Counter (TCA) 11.2.3 Module Stop Control Register (MSTPCR) 11.3 Operation. 11.3.1 Operation Interval Timer. 11.3.2 Operation Clock Timer.
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11.3.3
Initializing Counts.
Section Timer
12.1 Overview 12.1.1 Features. 12.1.2 Block Diagram 12.1.3 Configuration 12.1.4 Register Configuration. 12.2 Register Descriptions 12.2.1 Timer Mode Register (TMB). 12.2.2 Timer Counter (TCB). 12.2.3 Timer Load Register (TLB). 12.2.4 Port Mode Register (PMRA). 12.2.5 Module Stop Control Register (MSTPCR) 12.3 Operation. 12.3.1 Operation Interval Timer. 12.3.2 Operation Auto Reload Timer 12.3.3 Event Counter
Section Timer 13.1 Overview 13.1.1 Features. 13.1.2 Block Diagram 13.1.3 Configuration 13.1.4 Register Configuration. 13.2 Register Descriptions 13.2.1 Timer Mode Register (TMJ). 13.2.2 Timer Control Register (TMJC). 13.2.3 Timer Status Register (TMJS) 13.2.4 Timer Counter (TCJ). 13.2.5 Timer Counter (TCK) 13.2.6 Timer Load Register (TLJ). 13.2.7 Timer Load Register (TLK) 13.2.8 Module Stop Control Register (MSTPCR) 13.3 Operation. 13.3.1 8-bit Reload Timer (TMJ-1). 13.3.2 8-bit Reload Timer (TMJ-2). 13.3.3 Remote Controlled Data Transmission 13.3.4 TMJ-2 Expansion Function.
Section Timer 14.1 Overview 14.1.1 Features.
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14.1.2 Block Diagram 14.1.3 Register Configuration. 14.2 Register Descriptions 14.2.1 Timer Mode Register (LMR). 14.2.2 Linear Time Counter (LTC). 14.2.3 Reload/Compare Match Register (RCR) 14.2.4 Module Stop Control Register (MSTPCR) 14.3 Operation. 14.3.1 Compare Match Clear Operation.
Section Timer
15.1 Overview. 15.1.1 Features. 15.1.2 Block Diagram 15.1.3 Configuration 15.1.4 Register Configuration. 15.2 Register Descriptions 15.2.1 Timer Mode Register (TMRM1). 15.2.2 Timer Mode Register (TMRM2). 15.2.3 Timer Control/Status Register (TMRCS). 15.2.4 Timer Capture Register (TMRCP1) 15.2.5 Timer Capture Register (TMRCP2) 15.2.6 Timer Load Register (TMRL1). 15.2.7 Timer Load Register (TMRL2). 15.2.8 Timer Load Register (TMRL3). 15.2.9 Module Stop Control Register (MSTPCR) 15.3 Operation. 15.3.1 Reload Timer Counter Equipped with Capturing Function TMRU-1. 15.3.2 Reload Timer Counter Equipped with Capturing Function TMRU-2. 15.3.3 Reload Counter Timer TMRU-3 15.3.4 Mode Identification 15.3.5 Reeling Controls. 15.3.6 Acceleration Braking Processes Capstan Motor. 15.3.7 Slow Tracking Mono-Multi Function. 15.4 Interrupt Cause 15.5 Settings Respective Functions. 15.5.1 Mode Identification 15.5.2 Reeling Controls. 15.5.3 Slow Tracking Mono-Multi Function. 15.5.4 Acceleration Braking Processes Capstan Motor.
Section Timer 16.1 Overview.
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16.2
16.3
16.4 16.5 16.6 16.7
16.1.1 Features. 16.1.2 Block Diagram 16.1.3 Configuration 16.1.4 Register Configuration. Register Descriptions 16.2.1 Free Running Counter (FRC) 16.2.2 Output Comparing Registers (OCRA OCRB). 16.2.3 Input Capture Registers Through (ICRA Through ICRD). 16.2.4 Timer Interrupt Enabling Register (TIER). 16.2.5 Timer Control/Status Register (TCSRX) 16.2.6 Timer Control Register (TCRX). 16.2.7 Timer Output Comparing Control Register (TOCR) 16.2.8 Module Stop Control Register (MSTPCR) Operation. 16.3.1 Operation Timer 16.3.2 Counting Timing 16.3.3 Output Comparing Signal Outputting Timing. 16.3.4 Clearing Timing 16.3.5 Input Capture Signal Inputting Timing 16.3.6 Input Capture Flag (ICFA through ICFD) Setting Timing 16.3.7 Output Comparing Flag (OCFA OCFB) Setting Timing 16.3.8 Overflow Flag (CVF) Setting Timing Operation Mode Timer Interrupt Causes Exemplary Uses Timer Precautions when Using Timer 16.7.1 Competition between Writing Clearing with 16.7.2 Competition between Writing Counting with FRC. 16.7.3 Competition between Writing Comparing Match with 16.7.4 Changing Over Internal Clocks Counter Operations
Section Watchdog Timer (WDT) 17.1 Overview 17.1.1 Features. 17.1.2 Block Diagram 17.1.3 Register Configuration. 17.2 Register Descriptions 17.2.1 Watchdog Timer Counter (WTCNT). 17.2.2 Watchdog Timer Control/Status Register (WTCSR). 17.2.3 System Control Register (SYSCR). 17.2.4 Notes Register Access. 17.3 Operation. 17.3.1 Watchdog Timer Operation.
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17.3.2 Interval Timer Operation 17.3.3 Timing Setting Overflow Flag (OVF) 17.4 Interrupts 17.5 Usage Notes. 17.5.1 Contention between Watchdog Timer Counter (WTCNT) Write Increment 17.5.2 Changing Value CKS2 CKS0 17.5.3 Switching between Watchdog Timer Mode Interval Timer Mode.
Section 8-Bit 18.1 Overview. 18.1.1 Features. 18.1.2 Block Diagram 18.1.3 Configuration 18.1.4 Register Configuration. 18.2 Register Descriptions 18.2.1 8-bit Data Registers (PWR0, PWR1, PWR2, PWR3). 18.2.2 8-bit Control Register (PW8CR) 18.2.3 Port Mode Register (PMR3) 18.2.4 Module Stop Control Register (MSTPCR) 18.3 8-Bit Operation. Section 12-Bit 19.1 Overview. 19.1.1 Features. 19.1.2 Block Diagram 19.1.3 Configuration 19.1.4 Register Configuration. 19.2 Register Descriptions 19.2.1 12-Bit Control Registers (CPWCR, DPWCR) 19.2.2 12-Bit Data Registers (DPWDR, CPWDR) 19.3 Operation. 19.3.1 Output Waveform. Section 14-Bit 20.1 Overview. 20.1.1 Features. 20.1.2 Block Diagram 20.1.3 Configuration 20.1.4 Register Configuration. 20.2 Register Descriptions 20.2.1 Control Register (PWCR) 20.2.2 Data Registers (PWDRU, PWDRL).
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20.2.3 Module Stop Control Register (MSTPCR) 20.3 14-Bit Operation
Section Prescalar Unit.
21.1 Overview 21.1.1 Features. 21.1.2 Block Diagram 21.1.3 Configuration 21.1.4 Register Configuration. 21.2 Registers. 21.2.1 Input Capture Register (ICR1) 21.2.2 Prescalar Unit Control/Status Register (PCSR). 21.2.3 Port Mode Register (PMR1). 21.3 Noise Cancel Circuit 21.4 Operation. 21.4.1 Prescalar (PSS). 21.4.2 Prescalar (PSW). 21.4.3 Stable Oscillation Wait Time Count 21.4.4 8-bit 21.4.5 8-bit Input Capture Using Pin. 21.4.6 Frequency Division Clock Output
Section Serial Communication Interface (SCI1)
22.1 Overview 22.1.1 Features. 22.1.2 Block Diagram 22.1.3 Configuration 22.1.4 Register Configuration. 22.2 Register Descriptions 22.2.1 Receive Shift Register (RSR1) 22.2.2 Receive Data Register (RDR1). 22.2.3 Transmit Shift Register (TSR1). 22.2.4 Transmit Data Register (TDR1) 22.2.5 Serial Mode Register (SMR1) 22.2.6 Serial Control Register (SCR1) 22.2.7 Serial Status Register (SSR1). 22.2.8 Rate Register (BRR1). 22.2.9 Serial Interface Mode Register (SCMR1) 22.2.10 Module Stop Control Register (MSTPCR) 22.3 Operation. 22.3.1 Overview. 22.3.2 Operation Asynchronous Mode. 22.3.3 Multiprocessor Communication Function.
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22.3.4 Operation Synchronous Mode. 22.4 Interrupts 22.5 Usage Notes.
Section Interface (IIC)
23.1 Overview. 23.1.1 Features. 23.1.2 Block Diagram 23.1.3 Configuration 23.1.4 Register Configuration. 23.2 Register Descriptions 23.2.1 Data Register (ICDR). 23.2.2 Slave Address Register (SAR) 23.2.3 Second Slave Address Register (SARX) 23.2.4 Mode Register (ICMR) 23.2.5 Control Register (ICCR) 23.2.6 Status Register (ICSR) 23.2.7 Serial/Timer Control Register (STCR) 23.2.8 Switch Register (DDCSWR). 23.2.9 Module Stop Control Register (MSTPCR) 23.3 Operation. 23.3.1 Data Format. 23.3.2 Master Transmit Operation 23.3.3 Master Receive Operation. 23.3.4 Slave Receive Operation. 23.3.5 Slave Transmit Operation 23.3.6 IRIC Setting Timing Control 23.3.7 Automatic Switching from Formatless Transfer Format Transfer. 23.3.8 Noise Canceler 23.3.9 Sample Flowcharts 23.3.10 Initializing Internal Status. 23.4 Usage Notes.
Section Converter
24.1 Overview. 24.1.1 Features. 24.1.2 Block Diagram 24.1.3 Configuration 24.1.4 Register Configuration. 24.2 Register Descriptions 24.2.1 Software-Triggered Result Register (ADR) 24.2.2 Hardware-Triggered Result Register (AHR)
Rev. 1.0, 02/00, page
24.2.3 Control Register (ADCR). 24.2.4 Control/Status Register (ADCSR) 24.2.5 Trigger Select Register (ADTSR) 24.2.6 Port Mode Register (PMR0). 24.2.7 Module Stop Control Register (MSTPCR) 24.3 Interface Master 24.4 Operation. 24.4.1 Software-Triggered Conversion. 24.4.2 Hardware- External-Triggered Conversion 24.5 Interrupt Sources.
Section Address Trap Controller (ATC) 25.1 Overview 25.1.1 Features. 25.1.2 Block Diagram 25.1.3 Register Configuration. 25.2 Register Descriptions 25.2.1 Address Trap Control Register (ATCR) 25.2.2 Trap Address Register (TAR2 TAR0). 25.3 Precautions Usage 25.3.1 Basic Operations 25.3.2 Enabling. 25.3.3 Instruction 25.3.4 Instruction. 25.3.5 Instruction 25.3.6 Instruction 25.3.7 Instruction 25.3.8 SLEEP Instruction. 25.3.9 Competing Interrupt
26.1 Overview 26.1.1 Functions. 26.1.2 Block Diagram 26.2 Servo Port. 26.2.1 Overview. 26.2.2 Block Diagram 26.2.3 Configuration 26.2.4 Register Configuration. 26.2.5 Register Description 26.2.6 DFG/DPG Input Signals 26.3 Reference Signal Generators 26.3.1 Overview.
Section Servo Circuits
Rev. 1.0, 02/00, page xiii
26.4
26.5
26.6
26.7
26.8
26.9
26.3.2 Block Diagram 26.3.3 Register Configuration. 26.3.4 Register Description 26.3.5 Operation (Head-switch) Timing Generator. 26.4.1 Overview 26.4.2 Block Diagram 26.4.3 Timing Generator Configuration. 26.4.4 Register Configuration. 26.4.5 Register Description 26.4.6 Operation 26.4.7 Interrupts. 26.4.8 Cautions. High-Speed Switching Circuit Four-Head Special Playback 26.5.1 Overview 26.5.2 Block Diagram 26.5.3 Configuration 26.5.4 Register Description Drum Speed Error Detector. 26.6.1 Overview 26.6.2 Block Diagram 26.6.3 Register Configuration. 26.6.4 Register Description 26.6.5 Operation 26.6.6 Correction Trick Play Mode Drum Phase Error Detector 26.7.1 Overview 26.7.2 Block Diagram 26.7.3 Register Configuration. 26.7.4 Register Description 26.7.5 Operation 26.7.6 Phase Comparison Capstan Speed Error Detector 26.8.1 Overview 26.8.2 Block Diagram 26.8.3 Register Configuration. 26.8.4 Register Description 26.8.5 Operation Capstan Phase Error Detector. 26.9.1 Overview 26.9.2 Block Diagram 26.9.3 Register Configuration. 26.9.4 Register Description
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26.9.5 Operation 26.10 X-Value Tracking Adjustment Circuit. 26.10.1 Overview. 26.10.2 Block Diagram 26.10.3 Register Description 26.11 Digital Filters. 26.11.1 Overview. 26.11.2 Block Diagram 26.11.3 Arithmetic Buffer 26.11.4 Register Configuration. 26.11.5 Register Description 26.11.6 Filter Characteristics. 26.11.7 Operations Case Transient Response. 26.11.8 Initialization 26.12 Additional Signal Generator 26.12.1 Overview. 26.12.2 Configuration 26.12.3 Register Configuration. 26.12.4 Register Description 26.12.5 Additional Pulse Signal. 26.13 Circuit 26.13.1 Overview. 26.13.2 Block Diagram 26.13.3 Configuration 26.13.4 Register Configuration. 26.13.5 Register Description 26.13.6 Operation 26.13.7 Input Section 26.13.8 Duty Discriminator. 26.13.9 Output Section. 26.13.10 Trapezoid Waveform Circuit 26.13.11 Note Interrupt 26.14 Frequency Dividers. 26.14.1 Overview. 26.14.2 Frequency Divider. 26.14.3 Frequency Divider. 26.14.4 Noise Removal Circuit 26.15 Sync Signal Detector. 26.15.1 Overview. 26.15.2 Block Diagram 26.15.3 Configuration 26.15.4 Register Configuration. 26.15.5 Register Description
Rev. 1.0, 02/00, page
26.15.6 Noise Detection. 26.15.7 Activation Sync Signal Detector. 26.16 Servo Interrupt. 26.16.1 Overview 26.16.2 Register Configuration. 26.16.3 Register Description
Section Sync Separator Data Slicer
27.1 Overview. 27.1.1 Features. 27.1.2 Block Diagram 27.1.3 Configuration 27.1.4 Register Configuration. 27.2 Register Description. 27.2.1 Sync Separation Input Mode Register (SEPIMR) 27.2.2 Sync Separation Control Register (SEPCR). 27.2.3 Sync Separation Control Register (SEPACR) 27.2.4 Horizontal Sync Signal Threshold Register (HVTHR). 27.2.5 Vertical Sync Signal Threshold Register (VVTHR). 27.2.6 Field Detection Window Register (FWIDR). 27.2.7 Complement Mask Timing Register (HCMMR). 27.2.8 Noise Detection Counter (NDETC). 27.2.9 Noise Detection Level Register (NDETR). 27.2.10 Data Slicer Detection Window Register (DDETWR). 27.2.11 Internal Sync Frequency Register (INFRQR) 27.3 Operation. 27.3.1 Selecting Source Signals Sync Separation. 27.3.2 Vsync Separation. 27.3.3 Hsync Separation. 27.3.4 Field Detection. 27.3.5 Noise Detection. 27.3.6 Automatic Frequency Controller (AFC) 27.3.7 Module Stop Control Register (MSTPCR)
Section Data Slicer 28.1 Overview. 28.1.1 Features. 28.1.2 Block Diagram 28.1.3 Configuration 28.1.4 Register Configuration. 28.1.5 Data Slicer Conditions 28.2 Register Description. 28.2.1 Slice Even- (Odd-) Field Mode Register (SEVFD, SODFD).
Rev. 1.0, 02/00, page
28.2.2 Slice Line Setting Registers (SLINE1 SLINE4) 28.2.3 Slice Detection Registers (SDTCT1 SDTCT4). 28.2.4 Slice Data Registers (SDATA1 SDATA4). 28.2.5 Module Stop Control Register (MSTPCR) 28.2.6 Monitor Output Setting Register (DOUT) 28.3 Operation. 28.3.1 Slice Line Specification 28.3.2 Slice Sequence
Section On-Screen Display (OSD)
29.1 Overview 29.1.1 Features. 29.1.2 Block Diagram 29.1.3 Configuration 29.1.4 Register Configuration. 29.1.5 Formats Display Modes. 29.2 Description Display Functions. 29.2.1 Superimposed Mode Text Display Mode 29.2.2 Character Configuration. 29.2.3 On-Screen Display Configuration 29.3 Settings Character Units 29.3.1 Character Configuration. 29.3.2 Character Colors. 29.3.3 Halftones/Cursors. 29.3.4 Blinking 29.3.5 Button Display 29.3.6 Character Data (OSDROM) 29.3.7 Display Data (OSDRAM) 29.4 Settings Units. 29.4.1 Button Patterns 29.4.2 Display Enlargement 29.4.3 Character Brightness. 29.4.4 Cursor Color, Brightness, Halftone Levels 29.4.5 Registers (CLINEn, rows 29.5 Settings Screen Units 29.5.1 Display Positions. 29.5.2 Turning Display 29.5.3 Display Method. 29.5.4 Blinking Period 29.5.5 Borders 29.5.6 Background Color Brightness. 29.5.7 Character, Cursor, Background Chroma Saturation 29.5.8 Display Position Registers (HPOS VPOS)
Rev. 1.0, 02/00, page xvii
29.5.9 Screen Control Register (DCNTL). 29.6 Other Settings 29.6.1 Format 29.6.2 Display Data Control 29.6.3 Timing Display Updates Using Register Rewriting. 29.6.4 4fsc/2fsc. 29.6.5 OSDV Interrupts 29.6.6 Format Register (DFORM) 29.7 Digital Output. 29.7.1 Outputs 29.7.2 Outputs 29.7.3 Digital Output Specification Register (DOUT). 29.7.4 Module Stop Control Register (MTSTPCR). 29.8 Notes Font Creation. 29.8.1 Note Font Creation (Font Width). 29.8.2 Note Font Creation (Borders) 29.8.3 Note Font Creation (Blinking). 29.8.4 Note Font Creation (Buttons) 29.9 Oscillator, AFC, Clock 29.9.1 Sync Signals 29.9.2 Circuit. 29.9.3 Clock. 29.9.4 4/2fsc 29.10 Operation Operation Modes. 29.11 Character Data (OSDROM) Access 29.11.1 Serial Timer Control Register (STCR)
Section Electrical Characteristics
30.1 Absolute Maximum Ratings. 30.2 Electrical Characteristics HD6432199, HD6432198, HD6432197, HD6432196 30.2.1 Characteristics HD6432199, HD6432198, HD6432197, HD6432196 30.2.2 Allowable Output Currents HD6432199, HD6432198, HD6432197, HD6432196 30.2.3 Characteristics HD6432199, HD6432198, HD6432197, HD6432196 30.2.4 Serial Interface Timing HD6432199, HD6432198, HD6432197, HD6432196 30.2.5 Converter Characteristics HD6432199, HD6432198, HD6432197, HD6432196 30.2.6 Servo Section Electrical Characteristics HD6432199, HD6432198, HD6432197, HD6432196.
Rev. 1.0, 02/00, page xviii
Electrical Characteristics HD6432199, HD6432198, HD6432197, HD6432196 30.3 Electrical Characteristics HD64F2199 30.3.1 Characteristics HD64F2199. 30.3.2 Allowable Output Currents HD64F2199 30.3.3 Characteristics HD64F2199. 30.3.4 Serial Interface Timing HD64F2199 30.3.5 Converter Characteristics HD64F2199 30.3.6 Servo Section Electrical Characteristics HD64F2199 30.3.7 Electrical Characteristics HD64F2199
30.2.7
Appendix Instruction
Instructions Instruction Codes Operation Code Map. Number Execution States Status during Instruction Execution Change Condition Codes.
Appendix Internal Registers
Addresses Function List.
Appendix Circuit Diagrams 1116
Circuit Diagrams. 1116
Appendix Port States Each Processing State 1130
Circuit Diagrams. 1130
Appendix Usage Notes 1131
Power Supply Rise Fall Order. 1131 Sample External Circuits. 1133 Handling Pins When Used. 1138
Appendix Product Lineup 1140 Appendix Package Dimensions. 1141
Rev. 1.0, 02/00, page
Section Overview
Overview
H8S/2199 Series comprise microcomputers (MCUs) built around H8S/2000 CPU, employing Hitachi's proprietary architecture, equipped with supporting modules on-chip. H8S/2000 internal 32-bit architecture, provided with sixteen 16-bit general registers concise, optimized instruction designed high-speed operation, address 16-Mbyte linear address space. instruction upward-compatible with H8/300 H8/300H instructions object-code level, facilitating migration from H8/300, H8/300L, H8/300H Series. H8S/2199 Series equipped with digital servo circuit, sync separator, OSD, data slicer, ROM, RAM, seven types timers, three types PWM, types serial communication interface, interface, converter, port on-chip supporting modules. on-chip either flash memory (F-ZTATTM*) mask ROM, with capacity 128, 112, kbytes. connected 16-bit data bus, enabling both byte word data accessed state. Instruction fetching been speeded processing speed increased. features H8S/2199 Series shown table 1.1. Note: F-ZTATis trademark Hitachi, Ltd.
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Table
Item
Features H8S/2199 Series
Specifications General-register architecture Sixteen 16-bit general registers (also usable sixteen 8-bit registers eight 32-bit registers) High-speed operation suitable real-time control Maximum operating frequency: MHz/4 High-speed arithmetic operations 8/16/32-bit register-register add/subtract: (10-MHz operation) 16-bit register-register multiply: 2000 (10-MHz operation) 16-bit register-register divide: 2000 (10-MHz operation) Instruction suitable high-speed operation Sixty-five basic instructions 8/16/32-bit transfer/arithmetic logic instructions Unsigned/signed multiply divide instructions Powerful bit-manipulation instructions operating modes Advanced mode: 16-Mbyte address space Seven types timer incorporated Timer 8-bit interval timer Clock source selected among types internal clock which frequencies divided from system clock subclock (SUB) Functions clock time base subclock input Functions 8-bit interval timer reload timer Clock source selected among types internal clock external event input Functions 8-bit down counters 16-bit down counter (reload timer/event counter timer/timer output, etc., types operation modes) Remote controlled transmit function Take up/Supply Reel Pulse Frequency division
Timer
Timer
Timer
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Item Timer
Specifications Timer 8-bit up/down counter Clock source selected among types internal clock, frequency division signal, REC-CTL (control pulse) Compare-match clearing function/auto reload function Three reload timers Mode discrimination Reel control Capstan motor acceleration/deceleration detection function Slow tracking mono-multi 16-bit free-running counter Clock source selected among types internal clock DVCFG output compare outputs Four input capture inputs Functions watchdog timer 8-bit interval timer Generates reset signal overflow
Prescaler unit
Timer
Timer
Watchdog timer
Divides system clock frequency generates frequency division clock supporting module functions Divides subclock frequency generates input clock Timer (clock time base) Generates 8-bit frequency duty period 8-bit input capture external signal edge Frequency division clock output enabled
Three types incorporated 14-bit PWM: Pulse resolution type channel 8-bit PWM: Duty control type channels 12-bit PWM: Pulse pitch control type channels
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Item Serial communication interface (SCI) interface channels)
Specifications Asynchronous mode synchronous mode selectable Desired rate selectable with built-in baud rate generator Multiprocessor communication function Conforms Phillips interface standard
Start stop conditions generated automatically Selection acknowledge output levels when receiving, automatic loading acknowledge when transmitting Selection acknowledgement mode serial mode (without acknowledge bit)
converter
Resolution: bits Input: channels High-speed conversion: 13.4 minimum conversion time operation) Sample-and-hold function conversion activated software external trigger
Address trap controller
Interrupt occurs when preset address found during cycle To-be-trapped addresses individually three different locations input/output pins input-only pins switched each supporting module
port
Servo circuit
Digital servo circuits on-chip Input output circuits Error detection circuit Phase gain compensation
Sync signal (servo)
On-chip sync signal detection circuit separately detect horizontal vertical sync signals Noise detection function
Sync separator data slicer
Sync separator including Horizontal vertical sync signals separated from composite video signal Noise detection Selection sync separation methods
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Item Screen Display)
Specifications Screen characters lines types characters Character configuration: dots lines Character colors: Cursor colors: Halftone display Button display Eight hues Eight hues Background colors: Eight hues
Data slicer
Slice lines: Four lines Slice levels: Seven levels Sampling clock generated Slice interrupt Error detection
Memory
Flash memory mask (Refer product line-up) High-speed static Product Name H8S/2199 H8S/2198 H8S/2197 H8S/2196 Medium-speed mode Sleep mode Module stop mode Standby mode Subclock operation Subactive mode, watch mode, subsleep mode bytes bytes bytes bytes bytes bytes bytes bytes
Power-down state
Interrupt controller
external interrupt pins (,54 ,54) internal interrupt sources Three priority levels settable
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Item Clock pulse generator
Specifications types clock pulse generator on-chip System clock pulse generator: Subclock pulse generator: 32.768 112-pin plastic (FP-112) Product Code Series H8S/2199 Mask Versions HD6432199 F-ZTAT Versions HD64F2199 ROM/RAM (bytes) (256 Packages FP-112
Packages Product lineup
HD6432198 HD6432197 HD6432196 Note: F-ZTAT version
FP-112 FP-112 FP-112
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Internal Block Diagram
Figure shows internal block diagram H8S/2199 Series.
OSC1 OSC2
External address
External address
External data
External data
P27/SYNCI P26/SCL0 P25/SDA0 P24/SCL1 P23/SDA1 P22/SCK1 P21/SO1 P20/SI1 P17/TMOW P16/ P15/ P14/ P13/ P12/ P11/ P10/ P07/AN7 P06/AN6 P05/AN5 P04/AN4 P03/AN3 P02/AN2 P01/AN1 P00/AN0 AVCC AVSS P87/DPG P86/EXTTRG P85/COMP/B P84/H.Amp SW/G P83/C.Rotary/R P82/EXCTL P81/EXCAP/YBO P80/YCO SVCC SVSS
Port
H8S/2000
Internal data Internal address
Port
P37/TMO P36/BUZZ P35/PWM3 P34/PWM2 P33/PWM1 P32/PWM0 P31/SV2 P30/SV1 P47/RPTRG P46/FTOB P45/FTOA P44/FTID P43/FTIC P42/FTIB P41/FTIA P40/PWM14 P67/RP7/TMBI P66/RP6/ P65/RP5 P64/RP4 P63/RP3 P62/RP2 P61/RP1 P60/RP0 P77/PPG7/RPB P76/PPG6/RPA P75/PPG5/RP9 P74/PPG4/RP8 P73/PPG3 P72/PPG2 P71/PPG1 P70/PPG0
Subclock pulse generator Subclock pulse pulse generator
controller Address trap controller Prescaler unit Timer
Port Port Port
Interrupt controller 14-bit 12-bit 8-bit Watchdog timer
Port
Timer Timer SCI1 interface Timer
Analog port
Timer converter
Timer
Servo circuit
Port
Data slicer
Sub-carrier oscillator
Sync signal detection
Port
4fscin/2fscin 4fscout/2fscout
Servo pins (CTL input/output amplifier, three-level output, etc.)
DRMPWM CAPPWM CTL(+) CTL(-) CTLBias CTLAmp(o) CTLSMT(i) AUDIO VIDEO Vpulse
(Analog input/output)
CVin1 CVout
Sync separation
Csync/Hsync
CVin2
Figure Internal Block Diagram H8S/2199 Series
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Hsync(Csync)
VLPF/Vsync
OVCC OVSS
1.3.1
Arrangement Functions
Arrangement
Figure shows arrangement H8S/2199 Series.
P40/PWM14 P41/FTIA P42/FTIB P43/FTIC P44/FTID P45/FTOA P46/FTOB P47/RPTRG P20/SI1 P21/SO1 P22/SCK1 P23/SDA1 P24/SCL1 P25/SDA0 P26/SCL0 P27/SYNCI P33/PWM1 P34/PWM2 OSC2 OSC1
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SVSS CTLREF CTL(+) CTL(-) CTLBias CTLFB CTLAmp(o) CTLSMT(i) SVCC AFCpc AFCosc AFCLPF Csync/Hsync VLPF/Vsync CVin2 CVin1 OVCC CVout OVSS 4fscout/2fscout 4fscin/2fscin AVSS P07/AN7
P32/PWM0 P31/SV2 P30/SV1 P70/PPG0 P71/PPG1 P72/PPG2 P73/PPG3 P74/PPG4/RP8 P75/PPG5/RP9 P76/PPG6/RPA P77/PPG7/RPB P80/YCO P81/EXCAP/YBO P82/EXCTL P83/C.Rotary/R P84/H.Amp SW/G P85/COMP/B P86/EXTTRG P87/DPG VIDEO AUDIO Vpulse Csync
FP-112 (Top view)
P35/PWM3 P36/BUZZ P37/TMO P60/RP0 P61/RP1 P62/RP2 P63/RP3 P64/RP4 P65/RP5 P66/RP6/ P67/RP7/TMBI P17/TMOW P16/ P15/ P14/ P13/ P12/ P11/ P10/ AVCC P00/AN0 P01/AN1 P02/AN2 P03/AN3 P04/AN4 P05/AN5 P06/AN6
Figure Arrangement H8S/2199 Series
1.3.2
Functions
Table summarizes functions H8S/2199 Series pins. Table
Type Power supply
Functions
Symbol Input Name Function Power supply: pins should connected system power supply (+5V) Ground: pins should connected system power supply (0V) Servo power supply: SVcc should connected servo analog power supply (+5V) Servo ground: SVss should connected servo analog power supply (0V) Analog power supply: Power supply converter. should connected system power supply (+5V) when converter used Analog ground: Ground converter. should connected system power supply (0V) power supply: VCC(OSD) should connected analog power supply ground: (OSD) should connected analog power supply Smoothing capacitor connection: Connect 0.1-µF power-smoothing capacitance between Connected crystal oscillator. also input external clock. section Clock Pulse Generator, typical connection diagrams crystal oscillator external clock input Connected 32.768 crystal oscillator. section Clock Pulse Generator, typical connection diagrams
Input
SVCC
Input
SVSS
Input
AVCC
Input
AVSS
Input
OVCC
Input
OVSS
Input
Input
Clock
OSC1 OSC2
Input Output
Input Output
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Type Operating mode control System control
Symbol
Input
Name Function Mode pin: This sets operating mode. This should changed while operation Reset input: When this driven low, chip reset Flash memory enable: Enables/disables flash memory programming. This available only with with flash memory on-chip. mask type, connect anything this External interrupt request External interrupt input which rising edge sense, falling edge sense both edges sense selectable External interrupt requests External interrupt input pins which rising falling edge sense selectable
Input Input
Interrupts
Input
Prescaler unit
Input
TMOW
Input Output
Input capture input: Input capture input prescaler unit Frequency division clock output: Output clock which frequency divided prescaler Timer event input: Input events input Timer counter Timer event input: Input events input Timer RDT1or RDT-2 counter Timer timer output: Output toggle underflow RDT-1 Timer remote controlled transmit data Timer buzzer output: Output toggle which selectable among fixed frequency, frequency divided from subclock kHz), frequency division signal
Timers
TMBI
Input
Input
Output
BUZZ
Output
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Type Timers
Symbol
Input
Name Function Timer input capture: Input input capture Timer TMRU-1 TMRU-2 Timer output compare output: Output output compare Timer Timer input capture input: Input input capture Timer 8-bit square waveform output: Output waveform generated 8-bit 14-bit square waveform output: Output waveform generated 14-bit clock input/output: Clock input pins receive data input: Receive data input pins transmit data output: Transmit data output pins interface clock input/output: Clock input/output interface interface data input/output: Data input/output interface interface clock input: formalless serial clock input
FTOA FTOB FTIA FTIB FTIC FTID PWM0 PWM1 PWM2 PWM3 PWM14
Output
Input
Output
Output
Serial communication interface (SCI)
SCK1
Input /output Input Output Input /output Input /output Input
interface
SCL0 SCL1 SDA0 SDA1 SYNCI
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Type converter
Symbol
Input
Name Function Analog input channels Analog data input pins. conversion started software triggering Analog input channels Analog data input pins. conversion started external trigger, hardware trigger, software conversion external trigger input: conversion analog data input pins started external trigger Audio Output audio head switching signal Video Output video head switching signal Capstan mix: 12-bit output giving result capstan speed error phase error after filtering Drum mix: 12-bit output giving result drum speed error phase error after filtering Additional pulse: Three-level output additional signal synchronized Video signal Color rotary signal: Output color signal processing control signal four-head special-effects playback Head-amp switch: Output preamplifier output select signal four-head special-effects playback. Compare input: Input signal giving result preamplifier output comparison four-head special-effects playback. head pins: pins signals primary bias supply: Bias supply primary
Input
$'75*
Input
Servo circuits
AUDIO VIDEO CAPPWM
Output Output Output
DRMPWM
Output
Vpulse
Output
C.Rotary
Output
H.AmpSW
Output
COMP
Input
Bias
Input /output Input
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Type Servo circuits
Symbol CTLFB
Output Input Input
Name Function output: Output Schmitt input: Input Schmitt feedback input: Input high-range characteristics control reference voltage output: Output 1/2Vcc (SV) Capstan input: Schmitt comparator input signal Drum input: Schmitt input signal Drum input: Schmitt input signal External input: Input external signal Mixed sync signal input: Input mixed sync signal Capstan external sync signal input: Signal input external synchronization capstan phase control External trigger signal input: Signal input synchronization with reference signal generator Servo monitor output Output servo module internal signal Servo monitor output Output servo module internal signal PPG: Output timing generator. used when head switching required well Audio Video
CTLREF EXCTL Csync EXCAP
Output Input Input Input Input Input Input
EXTTRG
Input
PPG7 PPG0
Output Output Output
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Type Sync separator
Symbol Csync/ Hsync VLPF/ Vsync
Input/ output Input
Name Function Sync signal input/output: Composite sync signal input/output horizontal sync signal input Sync signal input: connecting external vertical sync signal input vertical sync signal oscillation: connecting external circuit oscillation oscillation: connecting external circuit oscillation connecting external oscillation: Input subcarrier oscillator. 4fsc 2fsc selected fsc: Subcarrier frequency oscillation: Output subcarrier oscillator. 4fsc 2fsc selected fsc: Subcarrier frequency Composite video input: Composite video signal input. Input 2-Vp-p composite video signal, sync signal clamped about Composite video input: Composite video signal input OSD. Input 2Vp-p composite video signal, sync signal clamped about Composite video output: Composite video signal output OSD. 2-Vp-p composite video signal output digital output: Color signal output digital output: Color signal output digital output: Color signal output
Input/ output Input/ output Input/ output Input
out/
Output
CVin2
Input
CVin1
Input
CVout
Output
Output Output Output
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Type
Symbol
Output Output Input
Name Function digital output: Character data output digital output: Character display position output Composite video input: Composite video signal input. Input 2-Vp-p composite video signal, sync signal clamped about Port 8-bit input pins Port 8-bit pins Port 8-bit pins Port 8-bit pins Port 8-bit pins Port 8-bit pins Port 8-bit pins Port 8-bit pins Realtime output port: 8-bit realtime output pins Realtime output port: 4-bit realtime output pins Realtime output port trigger input: Input realtime output port trigger
Data slicer
CVin2
port
RPTRG
Input Input /output Input /output Input /output Input /output Input /output Input /output Input /output Output Output Input
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Section
Overview
H8S/2000 high-speed central processing unit with internal 32-bit architecture that upward-compatible with H8/300 H8/300H CPUs. H8S/2000 sixteen 16-bit general registers, address 16-Mbyte (architecturally 4-Gbyte) linear address space, ideal realtime control. 2.1.1 Features
H8S/2000 following features. Upward-compatible with H8/300 H8/300H CPUs execute H8/300 H8/300H object programs General-register architecture Sixteen 16-bit general registers (also usable sixteen 8-bit registers eight 32-bit registers) Sixty-five basic instructions 8/16/32-bit arithmetic logic instructions Multiply divide instructions Powerful bit-manipulation instructions Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) @(d:32,ERn)] Register indirect with post-increment pre-decrement [@ERn+ @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, @aa:32] Immediate [#xx:8, #xx:16, #xx:32] Program-counter relative [@(d:8,PC) @(d:16,PC)] Memory indirect [@@aa:8] 16-Mbyte address space Program: Mbytes Data: Mbytes Gbytes architecturally) High-speed operation frequently-used instructions execute states Maximum clock rate: 8/16/32-bit register-register add/subtract: 8-bit register-register multiply: 1200
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8-bit register-register divide: 1200 16-bit register-register multiply: 2000 16-bit register-register divide: 2000 operating modes Normal mode*/Advanced mode Power-down state Transition power-down state SLEEP instruction clock speed selection Note: Normal mode available this LSI. 2.1.2 Differences between H8S/2600 H8S/2000
differences between H8S/2600 H8S/2000 shown below. Register configuration register supported only H8S/2600 CPU. Basic instructions four instructions MAC, CLRMAC, LDMAC, STMAC supported only H8S/2600 CPU. Number execution states number execution states MULXU MULXS instructions differ follows.
Number Execution States Instruction MULXU MULXS Mnemonic MULXU.B MULXU.W MULXS.B MULXS.W H8S/2600 H8S/2000
There also differences address space, register functions, power-down state, etc., depending product. 2.1.3 Differences from H8/300
comparison H8/300 CPU, H8S/2000 following enhancements. More general registers control registers Eight 16-bit extended registers, 8-bit control register, have been added.
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Expanded address space Normal mode supports same 64-kbyte address space H8/300 CPU. Advanced mode supports maximum 16-Mbyte address space. Enhanced addressing mode addressing modes have been enhanced make effective 16-Mbyte address space. Enhanced instructions Addressing modes bit-manipulation instructions have been enhanced. Signed multiply divide instructions have been added. Two-bit shift instructions have been added. Instructions saving restoring multiple registers have been added. test instruction been added. Higher speed Basic instructions execute twice fast. 2.1.4 Differences from H8/300H
comparison H8/300H CPU, H8S/2000 following enhancements. Additional control register 8-bit control register been added. Enhanced instructions Addressing modes bit-manipulation instructions have been enhanced. Two-bit shift instructions have been added. Instructions saving restoring multiple registers have been added. test instruction been added. Higher speed Basic instructions execute twice fast.
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Operating Modes
H8S/2000 operating modes: normal advanced. Normal mode supports maximum 64-kbyte address space. Advanced mode supports maximum 16-Mbyte total address space (architecturally maximum total address space Gbytes, with maximum Mbytes program area maximum Gbytes data area). mode selected mode pins microcontroller.
Maximum kbytes program data areas combined
Normal mode*
operating mode
Advanced mode Note: Normal mode available this LSI.
Maximum Mbytes program data areas combined
Figure Operating Modes Normal Mode (Not available this LSI) exception vector table stack have same structure H8/300 CPU. Address Space maximum address space kbytes accessed. Extended Registers (En) extended registers used 16-bit registers, upper 16-bit segments 32-bit registers. When used 16-bit register contain value, even when corresponding general register (Rn) used address register. general register referenced register indirect addressing mode with predecrement (@-Rn) post-increment (@Rn+) carry borrow occurs, however, value corresponding extended register (En) will affected. Instruction instructions addressing modes used. Only lower bits effective addresses (EA) valid.
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Exception Vector Table Memory Indirect Branch Addresses normal mode area starting H'0000 allocated exception vector table. branch address stored bits. configuration exception vector table normal mode shown figure 2.2. details exception vector table, section Exception Handling.
H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B
Reset exception vector
(Reserved system use)
Exception vector table
Exception vector Exception vector
Figure Exception Vector Table (Normal Mode) memory indirect addressing mode (@@aa:8) employed instructions uses 8-bit absolute address included instruction code specify memory operand that contains branch address. normal mode operand 16-bit word operand, providing 16-bit branch address. Branch addresses stored area from H'0000 H'00FF. Note that this area also used exception vector table.
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Stack Structure When program counter (PC) pushed onto stack subroutine call, condition-code register (CCR) pushed onto stack exception handling, they stored shown figure 2.3. extended control register (EXR) pushed onto stack. details, section Exception Handling.
bits)
CCR* bits)
Subroutine Branch Note: Ignored when returning.
Exception Handling
Figure Stack Structure Normal Mode Advanced Mode Address Space Linear access provided 16-Mbyte maximum address space (architecturally maximum 16-Mbyte program area maximum 4-Gbyte data area, with maximum Gbytes program data areas combined). Extended Registers (En) extended registers used 16-bit registers, upper 16-bit segments 32-bit registers address registers. Instruction instructions addressing modes used.
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Exception Vector Table Memory Indirect Branch Addresses advanced mode area starting H'00000000 allocated exception vector table units bits. each bits, upper bits ignored branch address stored lower bits (figure 2.4). details exception vector table, section Exception Handling.
H'00000000
Reserved
Reset exception vector
H'00000003 H'00000004
Reserved
H'00000007 H'00000008
Exception vector table
H'0000000B H'0000000C
(Reserved system use)
H'00000010
Reserved Exception vector
Figure Exception Vector Table (Advanced Mode) memory indirect addressing mode (@@aa:8) employed instructions uses 8-bit absolute address included instruction code specify memory operand that contains branch address. advanced mode operand 32bit longword operand, providing 32-bit branch address. upper bits these bits reserved area that regarded H'00. Branch addresses stored area from H'00000000 H'000000FF. Note that first part this range also exception vector table.
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Stack Structure advanced mode, when program counter (PC) pushed onto stack subroutine call, condition-code register (CCR) pushed onto stack exception handling, they stored shown figure 2.5. extended control register (EXR) pushed onto stack. details, section Exception Handling.
Reserved bits)
bits)
Subroutine Branch
Exception Handling
Figure Stack Structure Advanced Mode
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Address Space
Figure shows memory H8S/2000 CPU. H8S/2000 provides linear access maximum 64-kbyte address space normal mode, maximum 16-Mbyte (architecturally 4-Gbyte) address space advanced mode.
H'0000 H'00000000
H'FFFF
Program area
H'00FFFFFF
Data area
Cannot used with this
H'FFFFFFFF Normal mode* Advanced mode
Note: Normal mode available this LSI.
Figure Memory
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2.4.1
Register Configuration
Overview
internal registers shown figure 2.7. There types registers: general registers control registers.
General Registers (Rn) Extended Registers (En) (SP) Control Registers (CR) [Legend]
Stack pointer Program counter Extended control register Trace Interrupt mask bits Condition-code register Interrupt mask User interrupt mask
Half-carry flag User Negative flag Zero flag Overflow flag Carry flag
Note: Does affect operation this LSI.
Figure Registers
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2.4.2
General Registers
eight 32-bit general registers. These general registers functionally alike used both address registers data registers. When general register used data register, accessed 32-bit, 16-bit, 8-bit register. When general registers used 32-bit registers address registers, they designated letters (ER0 ER7). registers divide into 16-bit general registers designated letters R7). These registers functionally equivalent, providing maximum sixteen 16-bit registers. registers also referred extended registers. registers divide into 8-bit general registers designated letters (R0H R7H) (R0L R7L). These registers functionally equivalent, providing maximum sixteen 8-bit registers. Figure illustrates usage general registers. usage each register selected independently.
Address registers 32-bit registers
16-bit registers
8-bit registers
registers (extended registers) registers (ER0 ER7) registers registers (R0L R7L) registers (R0H R7H)
Figure Usage General Registers General register function stack pointer (SP) addition general-register function, used implicitly exception handling subroutine calls. Figure shows stack.
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Free area (ER7)
Stack area
Figure Stack 2.4.3 Control Registers
control registers 24-bit program counter (PC), 8-bit extended control register (EXR), 8-bit condition-code register (CCR). Program Counter (PC) This 24-bit counter indicates address next instruction will execute. length instructions bytes (one word), least significant ignored. (When instruction fetched, least significant regarded Extended Control Register (EXR) 8-bit register. this LSI, this register does affect operation. Trace This reserved. this LSI, this does affect operation. Bits Reserved These bits reserved. They always read Bits Interrupt Mask Bits These bits reserved. this LSI, these bits affect operation. Condition: Code Register (CCR) This 8-bit register contains internal status information, including interrupt mask half-carry (H), negative (N), zero (Z), overflow (V), carry flags. Interrupt Mask Masks interrupts other than when (NMI accepted regardless setting.) hardware start exception-handling sequence. details, section Interrupt Controller.
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User Interrupt Mask (UI) written read software using LDC, STC, ANDC, ORC, XORC instructions. This also used interrupt mask bit. details, section Interrupt Controller. Half-Carry Flag When ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, NEG.B instruction executed, this flag there carry borrow cleared otherwise. When ADD.W, SUB.W, CMP.W, NEG.W instruction executed, flag there carry borrow cleared otherwise. When ADD.L, SUB.L, CMP.L, NEG.L instruction executed, flag there carry borrow cleared otherwise. User written read software using LDC, STC, ANDC, ORC, XORC instructions. Negative Flag Stores value most significant (sign bit) data. Zero Flag indicate zero data, cleared indicate non-zero data. Overflow Flag when arithmetic overflow occurs, cleared otherwise. Carry Flag when carry occurs, cleared otherwise. Used instructions, indicate carry Subtract instructions, indicate borrow Shift rotate instructions, store carry carry flag also used accumulator bit-manipulation instructions. Some instructions leave some flag bits unchanged. action each instruction flag bits, section Appendix A.1, List Instructions. Operations performed bits LDC, STC, ANDC, ORC, XORC instructions. flags used branching conditions conditional branch (Bcc) instructions. 2.4.4 Initial Register Values
Reset exception handling loads CPU's program counter (PC) from vector table, clears trace sets interrupt mask bits other bits general registers initialized. particular, stack pointer (ER7) initialized. stack pointer should therefore initialized MOV.L instruction executed immediately after reset.
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Data Formats
process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), 32-bit (longword) data. Bit-manipulation instructions operate 1-bit data accessing byte operand data. decimal-adjust instructions treat byte data digits 4bit data. 2.5.1 General Register Data Formats
Figure 2.10 shows data formats general registers.
Data type
General Register
Data Format Don't care
1-bit data
1-bit data Don't care
4-bit data
Don't care
Upper digit Lower digit
4-bit data
Don't care
Upper digit Lower digit
Byte data
Don't care
Byte data
Don't care
Figure 2.10 General Register Data Formats
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Data Type
General Register
Data format
Word data
Word data
Longword data
[Legend] General register General register General register
General register General register Most significant Least significant
Figure 2.11 General Register Data Formats
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2.5.2
Memory Data Formats
Figure 2.12 shows data formats memory. access word data longword data memory, word longword data must begin even address. attempt made access word longword data address, address error occurs least significant address regarded access starts preceding address. This also applies instruction fetches.
Data Type Address 1-bit data Address
Data Format
Byte data
Address
Word data
Address Address 2M+1
Longword data
Address Address 2N+1 Address 2N+2 Address 2N+3
Figure 2.12 Memory Data Formats When (SP) used address register access stack, operand size should word size longword size.
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2.6.1
Instruction
Overview
H8S/2000 types instructions. instructions classified function table 2.1. Table
Function Data transfer
Instruction Classification
Instructions PUSH LDM, SMOVFPE, MOVTPE
Size
Types
Arithmetic
ADD, SUB, CMP, ADDX, SUBX, DAA, INC, ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS
Logic operations Shift manipulation
AND, XOR, SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR RSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR Bcc*2, JMP, BSR, JSR, TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, EEPMOV
Branch System control Block data transfer
Total: types
Notes: byte size; word size; longword size. POP.W PUSH.W identical MOV.W @SP+, MOV.W @SP. POP.L PUSH.L identical MOV.L @SP+, MOV.L ERn, @-SP. general name conditional branch instructions.
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2.6.2
Instructions Addressing Modes
Table indicates combinations instructions addressing modes that H8S/2000 use. Table Combinations Instructions Addressing Modes
Addressing Modes
@-ERn/@ERn+ Function @(d:16, ERn) @(d:32, ERn) @(d:8, @(d:16,
@aa:16
@aa:24
@aa:32
@aa:8
@ERn
@@aa:8
Instruction
POP, PUSH LDM, SMOVFPE, MOVTPE* ADD, ADDX, SUBX ADDS, SUBS INC, DAA, MULXU, DIVXU MULXS, DIVXS EXTU, EXTS AND,
Data transfer
Shift manipulation Bcc, Branch JMP, TRAPA SLEEP ANDC, ORC, XORC Block data transfer
System control
Logic operation
Arithmetic operations
[Legend] Byte Work Longword Note: Cannot used this LSI.
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2.6.3
Table Instructions Classified Function
Tables 2.10 summarize functions instructions. notation used table defined below.
Operation Notation (EAd) (EAs) #IMM Disp :8/:16/:24/:32 General register (destination)* General register (source)* General register* General register (32-bit register) Destination operand Source operand Extended control register Condition-code register (negative) flag (zero) flag (overflow) flag (carry) flag Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical Logical Logical exclusive Move (logical complement) 16-, 24-, 32-bit length
Note: General registers include 8-bit registers (R0H R7H, R7L), 16-bit registers E7), 32-bit registers (ER0 ER7).
Rev. 1.0, 02/00, page 1141
Table
Instruction
Data Transfer Instructions
Size* B/W/L Function (EAs) (EAd) Moves data between general registers between general register memory, moves immediate data general register
MOVFPE MOVTPE
Cannot used this Cannot used this @SP+ Pops general register from stack POP.W identical MOV.W @SP+, POP.L identical MOV.L @SP+,
PUSH
@-SP Pushes general register onto stack PUSH.W identical MOV.W @-SP PUSH.L identical MOV.L ERn, @-SP
S
@SP+ (register list) Pops more general registers from stack (register list) @-SP Pushes more general registers onto stack
Note: Size refers operand size. Byte Word Longword
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Table
Instruction
Arithmetic Instructions
Size* B/W/L Function #IMM Performs addition subtraction data general registers, immediate data data general register. (Immediate byte data cannot subtracted from byte data general register. SUBX instruction) #IMM Performs addition subtraction with carry byte data general registers, immediate data data general register B/W/L Increments decrements general register (Byte operands incremented decremented only) Adds subtracts value from data 32-bit register decimal adjust Decimal-adjusts addition subtraction result general register referring produce 4-bit data Performs unsigned multiplication data general registers: either bits bits bits bits bits bits
ADDX SUBX
ADDS SUBS MULXU
MULXS
Performs signed multiplication data general registers: either bits bits bits bits bits bits
DIVXU
Performs unsigned division data general registers: either bits bits 8-bit quotient 8-bit remainder bits bits 16-bit quotient 16-bit remainder
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Instruction DIVXS
Size*
Function Performs signed division data general registers: either bits bits 8-bit quotient 8-bit remainder bits bits 16-bit quotient 16-bit remainder
B/W/L
#IMM Compares data general register with data another general register with immediate data, sets bits according result
B/W/L
Takes two's complement (arithmetic complement) data general register
EXTU
(zero extension) Extends lower bits 16-bit register word size, lower bits 32-bit register longword size, padding with zeros left
EXTS
(sign extension) Extends lower bits 16-bit register word size, lower bits 32-bit register longword size, extending sign
@ERd (<bit @ERd) Tests memory contents, sets most significant (bit
Note: Size refers operand size. Byte Word Longword
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Table
Instruction
Logic Instructions
Size* B/W/L Function #IMM Performs logical operation general register another general register immediate data
B/W/L
#IMM Performs logical operation general register another general register immediate data
B/W/L
#IMM Performs logical exclusive operation general register another general register immediate data
B/W/L
Takes one's complement (logical complement) general register contents
Note: Size refers operand size. Byte Word Longword
Table
Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR
Shift Instructions
Size* B/W/L Function (shift) Performs arithmetic shift general register contents 1-bit 2-bit shift possible B/W/L (shift) Performs logical shift general register contents 1-bit 2-bit shift possible B/W/L (rotate) Rotates general register contents 1-bit 2-bit rotation possible B/W/L (rotate) Rotates general register contents through carry flag 1-bit 2-bit rotation possible
Note: Size refers operand size. Byte Word Longword
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Table
Instruction BSET
Manipulation Instructions
Size* Function (<bit-No.> <EAd>) Sets specified general register memory operand number specified 3-bit immediate data lower three bits general register
BCLR
(<bit-No.> <EAd>) Clears specified general register memory operand number specified 3-bit immediate data lower three bits general register
BNOT
(<bit-No.> <EAd>) (<bit-No.> <EAd>) Inverts specified general register memory operand. number specified 3-bit immediate data lower three bits general register
BTST
(<bit-No.> <EAd>) Tests specified general register memory operand sets clears flag accordingly. number specified 3-bit immediate data lower three bits general register
BAND
(<bit-No.> <EAd>) ANDs carry flag with specified general register memory operand stores result carry flag
BIAND
[~(<bit-No.> <EAd>)] ANDs carry flag with inverse specified general register memory operand stores result carry flag number specified 3-bit immediate data
(<bit-No.> <EAd>) carry flag with specified general register memory operand stores result carry flag
BIOR
[~(<bit-No.> <EAd>)] carry flag with inverse specified general register memory operand stores result carry flag number specified 3-bit immediate data
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Instruction BOXR
Size*
Function (<bit-No.> <EAd>) Exclusive-ORs carry flag with specified general register memory operand stores result carry flag
BIXOR
(<bit-No.> <EAd>)] Exclusive-ORs carry flag with inverse specified general register memory operand stores result carry flag number specified 3-bit immediate data
(<bit-No.> <EAd>) Transfers specified general register memory operand carry flag
BILD
(<bit-No.> <EAd>) Transfers inverse specified general register memory operand carry flag number specified 3-bit immediate data
(<bit-No.> <EAd>) Transfers carry flag value specified general register memory operand
BIST
(<bit-No.> <EAd>) Transfers inverse carry flag value specified general register memory operand number specified 3-bit immediate data
Note: Size refers operand size. Byte
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Table
Instruction
Branch Instructions
Size* Function Branches specified address specified condition true branching conditions listed below Mnemonic (BT) (BF) (BHS) (BLO) Description Always (True) Never (False) HIgh Same Carry Clear (High Same) Carry (LOw) Equal EQual oVerflow Clear oVerflow PLus MInus Greater Equal Less Than Greater Than Less Equal Condition Always Never NV=1
Branches unconditionally specified address Branches subroutine specified address Branches subroutine specified address Returns from subroutine
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Table
Instruction TRAPA SLEEP
System Control Instructions
Size* Function Starts trap-instruction exception handling Returns from exception-handling routine Causes transition power-down state (EAs) CCR, (EAs) Moves contents general register memory immediate data EXR. Although 8-bit registers, word-size transfers performed between them memory. upper bits valid
(EAd), (EAd) Transfers contents general register memory. Although 8-bit registers, word-size transfers performed between them memory. upper bits valid
ANDC XORC
#IMM CCR, #IMM Logically ANDs contents with immediate data #IMM CCR, #IMM Logically contents with immediate data #IMM CCR, #IMM Logically exclusive-ORs contents with immediate data
Only increments program counter
Note: Size refers operand size. Byte Word
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Table 2.10 Block Data Transfer Instructions
Instruction EEPMOV.B Size* Function then Repeat @ER5+@er6+ R4L-1R4L Until else next; then Repeat @ER5+@er6+ R4-1R4 Until else next; Transfers data block according parameters general registers ER5, size block (bytes) ER5: starting source address ER6: starting destination address Execution next instruction begins soon transfer completed
EEPMOV.W
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2.6.4
Basic Instruction Formats
instructions consist 2-byte (1-word) units. instruction consists operation field field), register field field), effective address extension field), condition field (cc). Figure 2.13 shows examples instruction formats.
Operation field only NOP, RTS, etc.
Operation field register fields ADD.B etc.
Operation field, register fields, effective address extension (disp) Operation field, effective address extension, condition field (disp) d:16, etc. MOV.B@(d:16, Rn), etc.
Figure 2.13 Instruction Formats (Examples) Operation Field Indicates function instruction, addressing mode, operation carried operand. operation field always includes first four bits instruction. Some instructions have operation fields. Register Field Specifies general register. Address registers specified bits, data registers bits bits. Some instructions have register fields. Some have register field. Effective Address Extension Eight, bits specifying immediate data, absolute address, displacement. Condition Field Specifies branching condition instructions.
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2.6.5
Notes Bit-Manipulation Instructions
BSET, BCLR, BNOT, BST, BIST instructions read byte data, carry manipulation, then write back byte data. Caution therefore required when using these instructions register containing write-only bits, port. BCLR instruction used clear internal register flags this case, relevant flag need read beforehand clear that been interrupt handling routine, etc.
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2.7.1
Addressing Modes Effective Address Calculation
Addressing Mode
supports eight addressing modes listed table 2.11. Each instruction uses subset these addressing modes. Arithmetic logic instructions register direct immediate modes. Data transfer instructions addressing modes except programcounter relative memory indirect. Bit-manipulation instructions register direct, register indirect, absolute addressing mode specify operand, register direct (BSET, BCLR, BNOT, BTST instructions) immediate (3-bit) addressing mode specify number operand. Table 2.11 Addressing Modes
Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/#@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8
Register Direct-Rn register field instruction code specifies 16-, 32-bit general register containing operand. specified 8-bit registers. specified 16-bit registers. specified 32-bit registers. Register Indirect-@Ern register field instruction code specifies address register (ERn) which contains address operand memory. address program instruction address, lower bits valid upper bits assumed (H'00). Register Indirect with Displacement-@(d:16, ERn) @(d:32, ERn) 16-bit 32-bit displacement contained instruction added address register (ERn) specified register field instruction, gives address memory operand. 16-bit displacement sign-extended when added.
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Register Indirect with Post-Increment Pre-Decrement-@ERn+ @-ERn Register indirect with post-increment-@ERn+ register field instruction code specifies address register (ERn) which contains address memory operand. After operand accessed, added address register contents stored address register. value added byte access, word access, longword access. word longword access, register value should even. Register indirect with pre-decrement-@-ERn value subtracted from address register (ERn) specified register field instruction code, result becomes address memory operand. result also stored address register. value subtracted byte access, word access, longword access. word longword access, register value should even. Absolute Address-@aa:8, @aa:16, @aa:24, @aa:32 instruction code contains absolute address memory operand. absolute address bits long (@aa:8), bits long (@aa:16), bits long (@aa:24), bits long (@aa:32). access data, absolute address should bits (@aa:8), bits (@aa:16), bits (@aa:32) long. 8-bit absolute address, upper bits assumed (H'FFFF). 16-bit absolute address upper bits sign extension. 32-bit absolute address access entire address space. 24-bit absolute address (@aa:24) indicates address program instruction. upper bits assumed (H'00). Table 2.12 indicates accessible absolute address ranges. Table 2.12 Absolute Address Access Ranges
Absolute Address Data address bits (@aa:8) bits (@aa:16) bits (@aa:32) Program instruction address bits (@aa:24) Normal Mode H'FF00 H'FFFF H'0000 H'FFFF Advanced Mode H'FFFF00 H'FFFFFF H'000000 H007FFF, H'FF8000 H'FFFFFF H'000000 H'FFFFFF
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Immediate-#xx:8, #xx:16, #xx:32 instruction contains 8-bit (#xx:8), 16-bit (#xx:16), 32-bit (#xx:32) immediate data operand. ADDS, SUBS, INC, instructions contain immediate data implicitly. Some manipulation instructions contain 3-bit immediate data instruction code, specifying number. TRAPA instruction contains 2-bit immediate data instruction code, specifying vector address. Program-Counter Relative-@(d:8, @(d:16, This mode used instructions. 8-bit 16-bit displacement contained instruction sign-extended added 24-bit contents generate branch address. Only lower bits this branch address valid; upper bits assumed (H'00). value which displacement added address first byte next instruction, possible branching range -126 +128 bytes (-63 words) -32766 +32768 bytes (-16383 +16384 words) from branch instruction. resulting value should even number. Memory Indirect-@@aa:8 This mode used instructions. instruction code contains 8bit absolute address specifying memory operand. This memory operand contains branch address. upper bits absolute address assumed address range (H'0000 H'00FF normal mode, H'000000 H'0000FF advanced mode). normal mode memory operand word operand branch address bits long. advanced mode memory operand longword operand, first byte which assumed (H'00). Note that first part address range also exception vector area. further details, section Exception Handling.
Specified @aa:8
Branch address
Specified @aa:8
Reserved Branch address
Normal Mode*
Advanced Mode
Note: available this
Figure 2.14 Branch Address Specification Memory Indirect Mode
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address specified word longword memory access, branch address, least significant regarded causing data accessed instruction code fetched address preceding specified address. (For further information, section 2.5.2, Memory Data Formats.) 2.7.2 Effective Address Calculation
Table 2.13 indicates effective addresses calculated each addressing mode. normal mode upper bits effective address ignored order generate 16-bit address.
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Table 2.13 Effective Address Calculation
Addressing Mode Instruction Format Register direct (Rn)
Effective Address Calculation
Effective Address (EA) Operand general register contents
Register indirect (@ERn)
General register contents Don't care
Register indirect with displacement @(d:16, ERn) @(d:32, ERn)
General register contents disp Sign extension disp Don't care
Register indirect with post-increment pre-decrement Register indirect with post-increment @ERn+
General register contents Don't care
Register indirect with pre-decrement @-ERn
General register contents Operand Size Byte Word Longword Value Added Don't care
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Addressing Mode Instruction Format Absolute address
@aa:8
Effective Address Calculation
Effective Address (EA)
H'FFFF
Don't care
@aa:16
Don't care
Sign extension
@aa:24
Don't care
@aa:32
Don't care
Immediate #xx:8/#xx:16/#xx:32
Operand immediate data
Program-counter relative @(d:8, PC)/@(d:16,
contents
disp
Sign extension
disp
Don't care
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Addressing Mode Instruction Format Memory indirect @@aa:8 Normal mode
Effective Address Calculation
Effective Address (EA)
H'000000
Don't care Memory contents
H'00
Advanced mode
H'000000
Memory contents
Don't care
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2.8.1
Processing States
Overview
four main processing states: reset state, exception-handling state, program execution state, power-down state. Figure 2.15 shows diagram processing states. Figure 2.16 indicates state transitions.
Reset state on-chip supporting modules have been initialized stopped. Exception-handling state transient state which changes normal processing flow response reset, interrupt trap instruction. Processing states Program execution state executes program instructions sequence.
Sleep mode Power-down state operation stopped conserve power.* Standby mode
Note: power-down state also includes medium-speed mode, modue stop mode, sub-active mode,
sub-sleep mode watch mode.
Figure 2.15 Processing States
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Program execution state
ling
stru
Sleep mode
stru
Exception-handling state
External interrupt request
Standby mode
Power-down state*2 High
Reset state
Notes:
From state, transition reset state occurs whenever goes low. transition also made reset state when watchdog timer overflows. power-down state also includes watch mode, subactive mode, subsleep mode, etc. details, section Power-Down State.
Figure 2.16 State Transitions 2.8.2 Reset State
When input goes current processing stops enters reset state. interrupts disabled reset state. Reset exception handling starts when signal changes from high. reset state also entered watchdog timer overflow. details, section Watchdog Timer.
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2.8.3
Exception-Handling State
exception-handling state transient state that occurs when alters normal processing flow reset, interrupt, trap instruction. fetches start address (vector) from exception vector table branches that address. Types Exception Handling Their Priority Exception handling performed resets, interrupts, trap instructions. Table 2.14 indicates types exception handling their priority. Trap instruction exception handling always accepted program execution state. Exception handling stack structure depend interrupt control mode SYSCR. Table 2.14 Exception Handling Types Priority
Priority High Type Exception Reset Detection Timing Synchronized with clock Start Exception Handling Exception handling starts immediately after low-to-high transition pin, when watchdog timer overflows When interrupt requested, exception handling starts current instruction current exception-handling sequence Exception handling starts when trap (TRAPA) instruction executed*2
Interrupt
instruction execution exception-handling sequence*1 When TRAPA instruction executed
Trap instruction
Notes: Interrupts detected ANDC, ORC, XORC, instructions, immediately after reset exception handling. Trap instruction exception handling always accepted program execution state.
Reset Exception Handling After gone reset state been entered, when goes high again, reset exception handling starts. When reset exception handling starts fetches start address (vector) from exception vector table starts program execution from that address. interrupts, including NMI, disabled during reset exception handling after ends. Interrupt Exception Handling Trap Instruction Exception Handling When interrupt trap-instruction exception handling begins, references stack pointer (ER7) pushes program counter other control registers onto stack. Next, alters settings interrupt mask bits control registers. Then fetches start address (vector) from exception vector table program execution starts from that start address.
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Figure 2.17 shows stack after exception handling ends.
Normal Mode
Advanced Mode
CCR*1 bits)
bits)
Notes:
Ignored when returning. Normal mode available this LSI.
Figure 2.17 Stack Structure after Exception Handling (Examples) 2.8.4 Program Execution State
this state executes program instructions sequence.
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2.8.5
Power-Down State
power-down state includes both modes which stops operating modes which does stop. There five modes which stops operating: sleep mode, standby mode, subsleep mode, watch mode. There also three other power-down modes: medium-speed mode, module stop mode, subactive mode. medium-speed mode, operates medium-speed clock. Module stop mode permits halting operation individual modules, other than CPU. Subactive mode, subsleep mode, watch mode power-down modes that subclock input. details, section Power-Down State. Sleep Mode transition sleep mode made SLEEP instruction executed while software standby (SSBY) standby control register (SBYCR) LSON lowpower control register (LPWRCR) both cleared sleep mode, operations stop immediately after execution SLEEP instruction. contents registers retained. Standby Mode transition standby mode made SLEEP instruction executed while SSBY SBYCR LSON LPWRCR TMA3 (timer both cleared standby mode, clock halt operations stop. long specified voltage supplied, contents registers on-chip retained.
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2.9.1
Basic Timing
Overview
driven system clock, denoted symbol period from rising edge next referred "state." memory cycle cycle consists states. Different methods used access on-chip memory on-chip supporting modules. 2.9.2 On-Chip Memory (ROM, RAM)
On-chip memory accessed state. data bits wide, permitting both byte word transfer instruction. Figure 2.18 shows on-chip memory access cycle.
cycle Internal address Internal read signal Read access Internal data Internal write signal Write access Internal data Write data Read data Address
Figure 2.18 On-Chip Memory Access Cycle
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2.9.3
On-Chip Supporting Module Access Timing
on-chip supporting modules accessed states. data either bits bits wide, depending particular internal register being accessed. Figure 2.19 shows access timing on-chip supporting modules.
cycle Internal address Internal read signal Read access Internal data Internal write signal Write access Internal data Write data Read data Address
Figure 2.19 On-Chip Supporting Module Access Cycle
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Section Operating Modes
3.1.1
Overview
Operating Mode Selection
This operating mode (mode This mode selected depending settings mode (MD0). Table lists operating modes. Table Operating Mode Selection
Operating Mode Advanced Description Single-chip mode
Operating Mode
CPU's architecture allows Gbytes address space, this actually accesses maximum Mbytes. Mode operation starts single-chip mode after reset release. This only used mode This means that mode pins must mode changes inputs mode pins during operation.
3.1.2
Register Configuration
This mode control register (MDCR) that indicates inputs mode (MD0) system control register (SYSCR) that controls operation this LSI. Table summarizes these registers. Table
Name Mode control register System control register
Registers
Abbreviation MDCR SYSCR Initial Value Undetermined H'09 Address* H'FFE9 H'FFE8
Note: Lower bits address.
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3.2.1
Register Descriptions
Mode Control Register (MDCR)
MDS0
Initial value
Note: Determined
MDCR 8-bit read-only register monitors current operating mode this LSI. Reserved. These bits cannot modified always read Mode Select (MDS0) This indicates value which reflects input levels mode (MD0) (the current operating mode). MDS0 corresponds pin. They read-only bits-they cannot written mode (MD0) input levels latched into these bits when MDCR read. 3.2.2 System Control Register (SYSCR)
Initial value INTM1 INTM0 XRST
Bits 6Reserved: These bits cannot modified always read
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Bits 4Interrupt control modes (INTM1, INTM0) These bits selecting interrupt control mode interrupt controller. details interrupt control modes, section 6.4.1, Interrupt Control Modes Interrupt Operation.
INTM1 INTM0 Interrupt Control Mode
Description Interrupt controlled Cannot used this Cannot used this (Initial value)
Interrupt controlled bits
3External Reset (XRST): Indicates reset source. When watchdog timer used, reset generated watchdog timer overflow well external reset input. XRST read-only bit. external reset cleared watchdog timer overflow.
XRST Description reset generated watchdog timer overflow reset generated external reset (Initial value)
Bits 1Reserved: These bits cannot modified always read 0Reserved: This always read
Operating Mode (Mode
access Mbyte address space advanced mode.
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Address Each Operating Mode
H8S/2196 H'000000 Vector area H'0000FF On-chip kbytes) H'007FFF H'013FFF H'017FFF H'040000 H'045FFF H'040000 H'045FFF H8S/2197
Absolute address, bits
Memory indirect branch address
H'000000 Vector area
On-chip kbytes)
kbytes)
kbytes)
H'FF8000
Absolute address, bits
H'FFD000 Internal register H'FFD2FF H'FFD800 (768 bytes) H'FFDAFF H'FFF3B0
H'FFD000 Internal register H'FFD2FF H'FFD800 (768 bytes) H'FFDAFF H'FFF3B0
kbytes
H'FFFF00 H'FFFFAF H'FFFFB0 Internal register H'FFFFFF
Absolute address, bits
On-chip
On-chip
H'FFFFAF H'FFFFB0 Internal register H'FFFFFF
Figure Address
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H8S/2198 H'000000 Vector area H'000000
H8S/2199
Vector area
On-chip (112 kbytes)
On-chip (128 kbytes)
H'01BFFF H'040000 H'045FFF H'01FFFF H'040000 H'045FFF kbytes)
kbytes)
H'FFD000 Internal register H'FFD2FF H'FFD800 (768 bytes) H'FFDAFF H'FFF3B0
H'FFD000 Internal register H'FFD2FF H'FFD800 (768 bytes) H'FFDAFF H'FFF3B0
On-chip
On-chip
H'FFFFAF H'FFFFB0 Internal register H'FFFFFF
H'FFFFAF H'FFFFB0 Internal register H'FFFFFF
Figure Address
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Section Power-Down State
Overview
addition normal program execution state, this power-down state which operation oscillator halted power dissipation reduced. Low-power operation achieved individually controlling CPU, on-chip supporting modules, This operating modes follows: High-speed mode Medium-speed mode Sub-active mode Sleep mode Sub-sleep mode Watch mode Module stop mode Standby mode
these, power-down modes. Certain combinations these modes set. After reset, high-speed mode. Table shows internal chip states each mode, table shows conditions transition various modes. Figure shows mode transition diagram.
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Table
Function System clock operation External interrupts
H8S/2199 Series Internal States Each Mode
MediumHigh-Speed Speed Sleep Module Stop Watch Sub-active Sub-sleep Standby Halted Subclock operation Halted Halted Retained Halted Halted Retained
Functioning Functioning Functioning Functioning Halted Functioning Mediumspeed Halted Retained Functioning Halted Retained
Subclock pulse generator Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Instructions Registers IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 On-chip supporting module operation Timer Functioning Functioning Retained Functioning Halted Functioning Retained Subclock operation Halted (retained) Subclock operation Halted (retained) Halted Halted (retained) Halted (retained) Functioning Functioning Functioning Functioning Subclock /halted operation (retained) Functioning Functioning Functioning Functioning Halted /halted (retained) (retained) Functioning Halted /halted (reset) (reset) Functioning Functioning Functioning Functioning Halted (retained)
Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Halted Halted Functioning Halted
Timer Timer Timer Timer Timer Watchdog timer 8-bit 12-bit PWM* 14-bit SCI1
Halted (reset) Halted (retained) Halted (retained)
Halted (reset) Halted (retained) Halted (retained)
Halted (reset) Halted (retained) Halted (retained)
Functioning Functioning Functioning Functioning Halted /halted (retained) (retained) Functioning Functioning Functioning Functioning Subclock /halted operation Functioning Functioning Functioning Functioning Halted* /halted*
Subclock operation Halted*
Subclock operation Halted*
Halted Halted*
Functioning Halted /halted (retained) (retained) Functioning Halted /halted (reset) (reset) Functioning Functioning Halted (reset) Functioning Functioning Halted (retained) Functioning Functioning Halted (reset) Functioning Halted /halted (reset) (reset) Functioning Halted /halted (retained) (retained) Functioning Halted /halted (reset) (reset)
Halted (retained) Halted (reset) Halted (reset) Halted (retained) Halted (reset)
Halted (retained) Halted (reset) Halted (reset) Halted (retained) Halted (reset)
Halted (retained) Halted (reset) Halted (reset) Halted (retained) Halted (reset)
Servo
Sync separator Data slicer
Notes: "Halted (retained)" means that internal register values retained. internal state "operation suspended." "Halted (reset)" means that internal register values internal states initialized. module stop mode, only modules which stop setting been made halted (reset retained).
Rev. 1.0, 02/00, page 1141
power-down mode, analog section servo circuits turned off, therefore (Servo) current does low. When power-down needed, externally shut down analog system power. SCI1 status differs from internal register. details, refer section Serial Communication Interface state 12-bit same that servo circuit.
Reset state Program-halted state Program execution state Program-halted state
Standby mode
SLEEP instruction Interrupt SLEEP instruction Interrupt SLEEP instruction
Active (high-speed) mode
SLEEP instruction
SLEEP instruction Interrupt SLEEP instruction
Sleep (high-speed) mode
Interrupt
SLEEP instruction
Active (medium-speed) mode
SLEEP instruction
SLEEP instruction Interrupt
Sleep (medium-speed) mode
SLEEP Interrupt instruction SLEEP instruction Interrupt
Watch mode
Subactive mode
SLEEP instruction Interrupt
Subsleep mode
Power-down mode
Conditions mode transition
Flag LSON SSBY TMA3 DTON
Conditions mode transition
Interruption factor
IRQ0 IRQ0 Timer interruption interruption (excluding servo system) IRQ0 Timer interruption
SCK1 SCK1 (either
Note: Don't care
Note: When transition made between modes means interrupt, transition cannot made interrupt source generation alone. Ensure that interrupt handling performed after accepting interrupt request
Figure Mode Transitions
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Table
Power-Down Mode Transition Conditions
Control States Time Transition SSBY TMA3 LSON DTON
State before Transition High-speed/ mediumspeed
State after Transition SLEEP Instruction Sleep Standby Watch Watch Subactive Subsleep Watch Watch High-speed/ medium-speed*2
State after Return Interrupt High-speed/ medium-speed*1 High-speed/ medium-speed*1 High-speed/ medium-speed*1 Subactive Subactive High-speed/ medium-speed*2 Subactive
Subactive
Notes: Don't care set. Returns state before transition. Mode varies depending state SCK1 SCK0.
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4.1.1
Register Configuration
power-down state controlled SBYCR, LPWRCR, (Timer MSTPCR registers. Table summarizes these registers. Table
Name Standby control register Low-power control register Module stop control register Timer mode register
Power-Down State Registers
Abbreviation SBYCR LPWRCR MSTPCRH MSTPCRL Initial Value H'00 H'00 H'FF H'FF H'30 Address* H'FFEA H'FFEB H'FFEC H'FFED H'FFBA
Note: Lower bits address.
Rev. 1.0, 02/00, page 1141
4.2.1
Register Descriptions
Standby Control Register (SBYCR)
SSBY Initial value STS2 STS1 STS0 SCK1 SCK0
SBYCR 8-bit readable/writable register that performs power-down mode control. SBYCR initialized H'00 reset. 7Software Standby (SSBY): Determines operating mode, combination with other control bits, when power-down mode transition made executing SLEEP instruction. SSBY setting changed mode transition interrupt, etc.
SSBY Description Transition sleep mode after execution SLEEP instruction high-speed mode medium-speed mode Transition subsleep mode after execution SLEEP instruction subactive mode (Initial value) Transition standby mode, subactive mode, watch mode after execution SLEEP instruction high-speed mode medium-speed mode Transition watch mode high-speed mode after execution SLEEP instruction subactive mode
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Bits 4Standby Timer Select (STS2 STS0): These bits select time waits clock stabilize when standby mode, watch mode, subactive mode cleared transition made high-speed mode medium-speed mode means specific interrupt instruction. With crystal oscillation, table make selection according operating frequency that standby time least (the oscillation settling time).
STS2 STS1 STS0 Description Standby time 8192 states Standby time 16384 states Standby time 32768 states Standby time 65536 states Standby time 131072 states Standby time 262144 states Reserved
Note: Don't care
Bits 2Reserved: These bits cannot modified always read Bits 0System Clock Select (SCK1, SCK0): These bits select clock master high-speed mode medium-speed mode.
SCK1 SCK0 Description master high-speed mode (Initial value) Medium-speed clock Medium-speed clock Medium-speed clock
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4.2.2
Low-Power Control Register (LPWRCR)
DTON Initial value LSON NESEL
LPWRCR 8-bit readable/writable register that performs power-down mode control. LPWRCR initialized H'00 reset. 7Direct-Transfer Flag (DTON): Specifies whether direct transition made between high-speed mode, medium-speed mode, subactive mode when making power-down transition executing SLEEP instruction. operating mode which transition made after SLEEP instruction execution determined combination other control bits.
DTON Description When SLEEP instruction executed high-speed mode medium-speed mode, transition made sleep mode, standby mode, watch mode When SLEEP instruction executed subactive mode, transition made subsleep mode watch mode (Initial value) When SLEEP instruction executed high-speed mode medium-speed mode, transition made directly subactive mode, transition made sleep mode standby mode When SLEEP instruction executed subactive mode, transition made directly high-speed mode, transition made subsleep mode
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6Low-Speed Flag (LSON): Determines operating mode combination with other control bits when making power-down transition executing SLEEP instruction. Also controls whether transition made high-speed mode subactive mode when watch mode cleared.
LSON Description When SLEEP instruction executed high-speed mode medium-speed mode, transition made sleep mode, standby mode, watch mode When SLEEP instruction executed subactive mode, transition made watch mode, directly high-speed mode After watch mode cleared, transition made high-speed mode (Initial value) When SLEEP instruction executed high-speed mode transition made watch mode, subactive mode, sleep mode standby mode When SLEEP instruction executed subactive mode, transition made subsleep mode watch mode After watch mode cleared, transition made subactive mode
5Noise Elimination Sampling Frequency Select (NESEL): Selects frequency which subclock generated subclock pulse generator sampled with clock generated system clock oscillator. When higher, clear this
NESEL Description Sampling divided Sampling divided
Bits 2Reserved: These bits cannot modified always read Bits 0Subactive Mode Clock Select (SA1, SA0): These bits select operating clock subactive mode. These bits cannot modified subactive mode.
Description Operating clock Operating clock Operating clock (Initial value)
Note: Don't care
Rev. 1.0, 02/00, page 1141
4.2.3
Timer Register (TMA)
TMAOV Initial value R/(W)* TMAIE TMA3 TMA2 TMA1 TMA0
Note: Only written, clear flag.
timer register (TMA) controls timer interrupts selects input clock. Only explained here. details other bits, section 11.2.1, Timer Mode Register readable/writable register which initialized H'30 reset. 3Clock Source, Prescaler Select (TMA3): Selects timer clock source between PSW. also controls transition operation power-down mode. operation mode which transited after SLEEP instruction execution determined combination with other control bits. details, description clock select section 11.2.1, Timer Mode Register
TMA3 Description Timer counts -based prescaler (PSS) divided clock pulses When SLEEP instruction executed high-speed mode medium-speed mode, transition made sleep mode software standby mode (Initial value) Timer counts w-based prescaler (PSW) divided clock pulses When SLEEP instruction executed high-speed mode medium-speed mode, transition made sleep mode, watch mode, subactive mode When SLEEP instruction executed subactive mode, transition made subsleep mode, watch mode, high-speed mode
Rev. 1.0, 02/00, page 1141
4.2.4
Module Stop Control Register (MSTPCR)
MSTPCRH Initial value MSTPCRL
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
MSTPCR comprises 8-bit readable/writable registers that perform module stop mode control. MSTPCR initialized H'FFFF reset. MSTRCRH MSTPCRL Bits 0Module Stop (MSTP MSTP These bits specify module stop mode. table method selecting on-chip supporting modules.
MSTPCRH, MSTPCRL Bits MSTP MSTP Description Module stop mode cleared Module stop mode (Initial value)
Rev. 1.0, 02/00, page 1141
Medium-Speed Mode
When SCK1 SCK0 bits SBYCR high-speed mode, operating mode changes medium-speed mode cycle. medium-speed mode, operates operating clock (16, specified SCK1 SCK0 bits. on-chip supporting modules other than always operate high-speed clock medium-speed mode, access executed specified number states with respect master operating clock. example, selected operating clock, onchip memory accessed states, internal registers states. Medium-speed mode cleared clearing both bits SCK1 SCK0 transition made high-speed mode medium-speed mode cleared current cycle. SLEEP instruction executed when SSBY SBYCR LSON LPWRCR cleared transition made sleep mode. When sleep mode cleared interrupt, medium-speed mode restored. SLEEP instruction executed when SSBY SBYCR LSON LPWRCR TMA3 (Timer both cleared transition made software standby mode. When standby mode cleared external interrupt, medium-speed mode restored. When driven low, transition made reset state, medium-speed mode cleared. same applies case reset caused overflow watchdog timer. Figure shows timing transition clearance medium-speed mode.
Medium-speed mode Internal supporting module clock
clock
Internal address
SBYCR
SBYCR
Internal write signal
Figure Medium-Speed Mode Transition Clearance Timing
Rev. 1.0, 02/00, page 1141
4.4.1
Sleep Mode
Sleep Mode
SLEEP instruction executed when SSBY SBYCR LSON LPWRCR both cleared will enter sleep mode. sleep mode, operation stops contents CPU's internal registers retained. Other supporting modules (excluding some functions) stop. 4.4.2 Clearing Sleep Mode
Sleep mode cleared interrupt, with pin. Clearing with Interrupt: When interrupt request signal input, sleep mode cleared interrupt exception handling started. Sleep mode will cleared interrupts disabled, interrupts other than have been masked CPU. Clearing with Pin: When driven low, reset state entered. When driven high after prescribed reset input period, begins reset exception handling.
Rev. 1.0, 02/00, page 1141
4.5.1
Module Stop Mode
Module Stop Mode
Module stop mode individual on-chip supporting modules. When corresponding MSTP MSTPCR module operation stops cycle transition made module stop mode. continues operating independently. Table shows MSTP bits on-chip supporting modules. When corresponding MSTP cleared module stop mode cleared module starts operating again cycle. module stop mode, internal states modules excluding some modules retained. After reset release, modules module stop mode. When on-chip supporting module module stop mode, read/write access registers disabled. Table
Register MSTPCRH
MSTP Bits Corresponding On-Chip Supporting Modules
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 Module Timer Timer Timer Timer Timer Timer Sync separator Serial communication interface (SCI1) interface (IIC0) interface (IIC1) 14-bit 8-bit Data slicer converter Servo circuit
MSTPCRL
MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Rev. 1.0, 02/00, page 1141
4.6.1
Standby Mode
Standby Mode
SLEEP instruction executed when SSBY SBYCR LSON LPWRCR cleared TMA3 (Timer cleared standby mode will entered. this mode, CPU, on-chip supporting modules, oscillator (except subclock oscillator) stop. However, contents CPU's internal registers data on-chip RAM, well on-chip peripheral circuits (with some exceptions), maintained current state. (Timer SCI1 partially reset.) port, this time, caused high impedance state. this mode oscillator stops, therefore power dissipation significantly reduced. 4.6.2 Clearing Standby Mode
Standby mode cleared external interrupt (pin ,54), means pin. Clearing with Interrupt: When interrupt request signal input, clock oscillation starts, after elapse time bits STS2 STS0 SYSCR, stable clocks supplied entire chip, standby mode cleared, interrupt exception handling started. Standby mode cannot cleared with interrupt corresponding enable been cleared been masked CPU. Clearing with Pin: When driven low, clock oscillation started. same time clock oscillation starts, clocks supplied entire chip. Note that must held until clock oscillation stabilizes. When goes high, begins reset exception handling. 4.6.3 Setting Oscillation Settling Time after Clearing Standby Mode
Bits STS2 STS0 SBYCR should described below. Using Crystal Oscillator: bits STS2 STS0 that standby time least (the oscillation settling time). Table shows standby times different operating frequencies settings bits STS2 STS0.
Rev. 1.0, 02/00, page 1141
Table
STS2
Oscillation Settling Time Settings
STS1 STS0 Standby Time 8192 states 16384 states 32768 states 65536 states 131072 states 262144 states Reserved 13.1 26.2
16.4*1 32.8
Unit
Notes: Don't care Recommended time setting
Using External Clock: value set.
Rev. 1.0, 02/00, page 1141
4.7.1
Watch Mode
Watch Mode
SLEEP instruction executed high-speed mode, medium-speed mode subactive mode when SSBY SBYCR DTON LPWRCR cleared TMA3 (Timer will make transition watch mode. this mode, on-chip supporting modules except timer stop. long prescribed voltage supplied, contents registers, some on-chip supporting module registers, on-chip RAM, retained, ports placed high-impedance state. 4.7.2 Clearing Watch Mode
Watch mode cleared interrupt (Timer interrupt, ,54), means pin. Clearing with Interrupt: When interrupt request signal input, watch mode cleared transition made high-speed mode medium-speed mode LSON LPWRCR cleared subactive mode LSON When making transition medium-speed mode, after elapse time bits STS2 STS0 SBYCR, stable clocks supplied entire chip, interrupt exception handling started. Watch mode cannot cleared with interrupt corresponding enable been cleared with on-chip supporting module interrupt acceptance relevant interrupt been disabled interrupt enable register masked CPU. section 4.6.3, Setting Oscillation Settling Time after Clearing Standby Mode, oscillation settling time setting when making transition from watch mode high-speed mode medium-speed mode. Clearing with Pin: Clearing with section 4.6.2, Clearing Standby Mode.
Rev. 1.0, 02/00, page 1141
4.8.1
Subsleep Mode
Subsleep Mode
SLEEP instruction executed subactive mode when SSBY SBYCR cleared LSON LPWRCR TMA3 (Timer will make transition subsleep mode. this mode, on-chip supporting modules other than Timer stop. long prescribed voltage supplied, contents registers, some on-chip supporting module registers, on-chip RAM, retained, ports placed highimpedance state. 4.8.2 Clearing Subsleep Mode
Subsleep mode cleared interrupt (Timer interrupt, ,54), means pin. Clearing with Interrupt: When interrupt request signal input, subsleep mode cleared interrupt exception handling started. Subsleep mode cannot cleared with interrupt corresponding enable been cleared with on-chip supporting module interrupt acceptance relevant interrupt been disabled interrupt enable register masked CPU. Clearing with Pin: Clearing with section 4.6.2, Clearing Standby Mode.
Rev. 1.0, 02/00, page 1141
4.9.1
Subactive Mode
Subactive Mode
SLEEP instruction executed high-speed mode when SSBY SBYCR, DTON LPWRCR, TMA3 (timer will make transition subactive mode. When interrupt generated watch mode, LSON LPWRCR transition made subactive mode. When interrupt generated subsleep mode, transition made subactive mode. subactive mode, performs sequential program execution speed subclock. this mode, on-chip supporting modules other than timer stop. 4.9.2 Clearing Subactive Mode
Subsleep mode cleared SLEEP instruction, means pin. Clearing with SLEEP Instruction: When SLEEP instruction executed while SSBY SBYCR DTON LPWRCR cleared TMA3 (timer subactive mode cleared transition made watch mode. When SLEEP instruction executed while SSBY SBYCR cleared LSON LPWRCR TMA3 (timer transition made subsleep mode. When SLEEP instruction executed while SSBY SBYCR DTON LSON cleared LPWRCR, TMA3 (timer transition made directly high-speed medium-speed mode. details direct transition, section 4.10, Direct Transition. Clearing with Pin: Clearing with section 4.6.2, Clearing Standby Mode.
Rev. 1.0, 02/00, page 1141
4.10
4.10.1
Direct Transition
Overview Direct Transition
There three operating modes which executes programs: high-speed mode, medium-speed mode, subactive mode. transition between high-speed mode subactive mode without halting program* called direct transition. direct transition carried setting DTON LPWRCR executing SLEEP instruction. After transition, direct transition interrupt exception handling started. Direct Transition from High-Speed Mode Subactive Mode: SLEEP instruction executed high-speed mode while SSBY SBYCR, LSON DTON LPWRCR, TMA3 (Timer transition made subactive mode. Direct Transition from Subactive Mode High-Speed Mode/Medium-Speed Mode: SLEEP instruction executed subactive mode while SSBY SBYCR LSON cleared DTON LPWRCR, TMA3 (timer after elapse time bits STS2 STS0 SBYCR, transition made directly high-speed mode medium-speed mode. Note: time transition from subactive mode high- medium-speed mode, oscillation stabilization wait time generated.
Rev. 1.0, 02/00, page 1141
Section Exception Handling
5.1.1
Overview
Exception Handling Types Priority
table indicates, exception handling caused reset, trap instruction, interrupt. Exception handling prioritized shown table 5.1. more exceptions occur simultaneously, they accepted processed order priority. Trap instruction exceptions accepted times program execution state. Exception handling sources, stack structure, operation vary depending interrupt c
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