February 2001 Revised June 2005 74LCXH16374 Voltage 16-Bit D-Type

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February 2001 Revised June 2005 74LCXH16374 Voltage 16-Bit D-Type

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74LCXH16374 Voltage 16-Bit D-Type Flip-Flop with Bushold
February 2001 Revised June 2005
74LCXH16374 Voltage 16-Bit D-Type Flip-Flop with Bushold
LCXH16374 contains sixteen non-inverting D-type flipflops with 3-STATE outputs intended oriented applications. device byte controlled. buffered clock (CP) Output Enable (OE) common each byte shorted together full 16-bit operation. LCXH16374 designed voltage (2.5V 3.3V) applications. LCXH16374 fabricated with advanced CMOS technology achieve high speed operation while maintaining CMOS power dissipation. LCXH16374 data inputs include active bushold circuitry, eliminating need external pull-up resistors hold unused floating data inputs valid logic level.
Features
tolerant control inputs outputs 2.3V-3.6V specifications provided (VCC
3.3V),
Bushold inputs eliminating need external pull-up/pull-down resistors Power down high impedance outputs output drive (VCC
3.0V)
Implements patented noise/EMI reduction circuitry Latch-up performance exceeds performance:
Human body model 2000V Machine model 200V
Also packaged plastic Fine-Pitch Ball Grid Array (FBGA)
Ordering Code:
Order Number 74LCXH16374G (Note 1)(Note 74LCXH16374MEA (Note 74LCXH16374MTD (Note Package Number BGA54A MS48A MTD48 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note Ordering code indicates Trays. Note Devices also available Tape Reel. Specify appending suffix letter ordering code.
Logic Symbol
trademark Fairchild Semiconductor Corporation.
2005 Fairchild Semiconductor Corporation
DS500441
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74LCXH16374
Connection Diagrams
Assignment SSOP TSSOP
Descriptions
Names I0-I15 O0-O15 Description Output Enable Input (Active LOW) Clock Pulse Input Bushold Inputs Outputs Connect
FBGA Assignments
Truth Tables
Inputs Assignment FBGA Outputs I0-I7 O0-O7 Outputs I8-I15 O8-O15 Inputs
(Top Thru View)
HIGH Voltage Level Voltage Level Immaterial High Impedance Previous before HIGH-to-LOW
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74LCXH16374
Functional Description
LCXH16374 consists sixteen edge-triggered flip-flops with individual D-type inputs 3-STATE true outputs. device byte controlled with each byte functioning identically, independent other. control pins shorted together obtain full 16-bit operation. Each byte buffered clock buffered Output Enable common flip-flops within that byte. description which follows applies each byte. Each flip-flop will store state their individual inputs that meet setup hold time requirements LOW-to-HIGH Clock (CPn) transition. With Output Enable (OEn) LOW, contents flip-flops available outputs. When HIGH, outputs high impedance state. Operation input does affect state flip-flops.
Logic Diagrams
Byte (0:7)
Byte (8:15)
Please note that this diagram provided only understanding logic operations should used estimate propagation delays.
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74LCXH16374
Absolute Maximum Ratings(Note
Symbol IGND TSTG Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Source/Sink Current Supply Current Supply Ground Current Ground Storage Temperature OE1, Parameter Value Conditions Units 3-STATE Output HIGH State (Note
0.5V 7.0V r100 r100
Recommended Operating Conditions (Note
Symbol IOH/IOL Supply Voltage Input Voltage Output Voltage Output Current HIGH State 3-STATE Free-Air Operating Temperature Input Edge Rate, 0.8V-2.0V, 3.0V 3.0V 3.6V 2.7V 3.0V 2.3V 2.7V Parameter Operating Data Retention Units
ns/V
't/'V
Note Absolute Maximum Ratings those values beyond which safety device cannot guaranteed. device should operated these limits. parametric values defined Electrical Characteristics tables guaranteed Absolute Maximum Ratings. "Recommended Operating Conditions" table will define conditions actual device operation. Note Absolute Maximum Rating must observed. Note Floating unused control inputs must HIGH LOW.
Electrical Characteristics
Symbol Parameter HIGH Level Input Voltage Level Input Voltage HIGH Level Output Voltage Level Output Voltage Input Leakage Current Data Control Conditions
40qC 85qC
Units
0.55
r5.0 r5.0
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74LCXH16374
Electrical Characteristics
Symbol II(HOLD) Parameter Bushold Input Minimum Drive Hold Current
(Continued)
0.7V 1.7V 0.8V 2.0V
Conditions
40qC 85qC
Units
II(OD)
Bushold Input Over-Drive Current Change State
(Note (Note (Note (Note
r5.0
IOFF
3-STATE Output Leakage Power-Off Leakage Current Quiescent Supply Current Increase Input
5.5V 0.6V
3.6V 5.5V (Note
'ICC
Note Outputs disabled 3-STATE only. Note external driver must source least specified current switch from LOW-to-HIGH. Note external driver must sink least specified current switch from HIGH-to-LOW.
Electrical Characteristics
Symbol Parameter fMAX tPHL tPLH tPZL tPZH tPLZ tPHZ tOSHL tOSLH Setup Time Hold Time Pulse Width Output Output Skew (Note Output Disable Time Maximum Clock Frequency Propagation Delay Output Enable time 3.3V 0.3V
85qC,
2.7V
500: 2.5V 0.2V Units
Note Skew defined absolute value differences between actual propagation delay separate outputs same device. specification applies outputs switching same direction, either HIGH-to-LOW (tOSHL) LOW-to-HIGH (tOSLH). Parameter guaranteed design.
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak Quiet Output Dynamic Valley Conditions 3.3V, 2.5V, 3.3V, 2.5V, 25qC Typical Units
Capacitance
Symbol COUT Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter Open, 3.3V, 3.3V, Conditions VCC, Typical Units
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74LCXH16374
LOADING WAVEFORMS Generic Family
FIGURE Test Circuit includes probe capacitance) Test tPLH, tPHL tPZL, tPLZ tPZH, tPHZ Switch Open 0.3V, 2.7V 0.2V
Waveform Inverting Non-Inverting Functions
3-STATE Output High Enable Disable Times Logic
Propagation Delay. Pulse Width trec Waveforms
Setup Time, Hold Time Recovery Time Logic
3-STATE Output Enable Disable Times Logic FIGURE Waveforms (Input Characteristics; =1MHz, 3ns) Symbol 3.3V 0.3V 1.5V 1.5V 0.3V 0.3V 2.7V 1.5V 1.5V 0.3V 0.3V
trise tfall
2.5V 0.2V VCC/2 VCC/2 0.15V 0.15V
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74LCXH16374
Schematic Diagram Generic LCXH Family (with Bushold)
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74LCXH16374
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A
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74LCXH16374
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A
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74LCXH16374 Voltage 16-Bit D-Type Flip-Flop with Bushold
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48
Fairchild does assume responsibility circuitry described, circuit patent licenses implied Fairchild reserves right time without notice change said circuitry specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT FAIRCHILD SEMICONDUCTOR CORPORATION. used herein: Life support devices systems devices systems which, intended surgical implant into body, support sustain life, whose failure perform when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. www.fairchildsemi.com critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness. www.fairchildsemi.com

February 2001 Revised June 2005 74LCXH16374 Voltage 16-Bit D-Type

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