FM27C512 524,288-Bit (64K High Performance CMOS EPROM FM27C512 hi
|
|
|
Top Searches for this datasheet
FM27C512 524,288-Bit (64K High Performance CMOS EPROM
FM27C512 524,288-Bit (64K High Performance CMOS EPROM
FM27C512 high performance 512K Erasable Electrically Programmable Read Only Memory (EPROM). manufactured using Fairchild's proprietary CMOS AMGEPROM technology excellent combination speed economy while providing excellent reliability. FM27C512 provides microprocessor-based systems storage capacity portions operating system application software. access time provides wait-state operation with high-performance CPUs. FM27C512 offers single chip solution code storage requirements 100% firmwarebased equipment. Frequently-used software routines quickly executed from EPROM storage, greatly enhancing system utility. FM27C512 configured standard JEDEC EPROM pinout which provides easy upgrade path systems which currently using standard EPROMs. FM27C512 member high density EPROM Family which range densities Megabit.
Features
High performance CMOS access time Fast turn-off microprocessor compatibility Manufacturers identification code JEDEC standard configuration 28-pin PDIP package 32-pin chip carrier 28-pin CERDIP package
Block Diagram
CE/PGM Output Enable Chip Enable Logic Output Buffers Data Outputs
Decoder
524,288-Bit Cell Matrix
Address Inputs
Decoder
DS800035-1 trademark WSI, Inc.
1998 Fairchild Semiconductor Corporation FM27C512
www.fairchildsemi.com
FM27C512 524,288-Bit (64K High Performance CMOS EPROM
Connection Diagrams
27C040 27C010 27C256 XX/VPP XX/VPP
FM27C512
OE/VPP CE/PGM
27C256 27C010 27C040 CE/PGM XX/PGM CE/PGM
DS800035-2
Compatible EPROM configurations shown blocks adjacement FM27C512 pins.
Commercial Temp Range (0°C +70°C)
Parameter/Order Number
FM27C512 FM27C512 FM27C512
Names
A0-A15 CE/PGM O0-O7 Addresses Chip Enable/Program Output Enable Outputs Don't Care (During Read)
Access Time (ns)
Industrial Temp Range (-40°C +85°C)
Parameter/Order Number
FM27C512 FM27C512 Quartz-Windowed Ceramic Package Plastic Package PLCC Package packages conform JEDEC standard. versions guaranteed function slower speeds.
PLCC
Access Time (ns)
OE/VPP CE/PGM
DS800035-3
FM27C512
www.fairchildsemi.com
FM27C512 524,288-Bit (64K High Performance CMOS EPROM
Absolute Maximum Ratings (Note
Storage Temperature Input Voltages Except with Respect Ground with Respect Ground Supply Voltage with Respect Ground -65°C +150°C
Protection (MIL Std. 883, Method 3015.2) Output Voltages with Respect Ground
>2000V 1.0V -0.6V
-0.6V -0.7V +14V -0.6V
Operating Range
Range
Commercial Industrial
Temperature
+70°C -40°C +85°C
Tolerance
±10% ±10%
Read Operation Electrical Characteristics
Symbol
ISB1 ISB2 ICC1 ICC2
Parameter
Input Level Input High Level Output Voltage Output High Voltage Standby Current (CMOS) Standby Current Active Current Active Current CMOS Inputs Supply Current Read Voltage Input Load Current Output Leakage Current
Test Conditions
-0.5
Units
-2.5 ±0.3V
GND, Inputs GND, Temp Ranges
5.5V VOUT 5.5V
Electrical Characteristics
Symbol
tACC
Parameter
Address Output Delay Output Delay Output Delay Output Disable Output Float Output Hold from Addresses, Whichever Occurred First
Units
FM27C512
www.fairchildsemi.com
FM27C512 524,288-Bit (64K High Performance CMOS EPROM
Capacitance +25°C, (Note
Symbol
CIN1 COUT CIN2
Parameter
Input Capacitance except OE/VPP Output Capacitance OE/VPP Input Capacitance
Conditions
VOUT
Units
Test Conditions
Output Load Gate (Note 0.45V 2.4V 0.8V 0.8V Input Rise Fall Times Input Pulse Levels Timing Measurement Reference Level (Note Inputs Outputs
Waveforms (Notes
ADDRESS
0.8V
Address Valid
0.8V
(Note
0.8V
(Note
(Note
Valid Output
OUTPUT
0.8V
Hi-Z
(Note
Hi-Z
DS800035-4
Note Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Note This parameter only sampled 100% tested. Note delayed tACC -tOE after falling edge without impacting tACC. Note compare level determined follows: High TRI-STATE, measured VOH1 (DC) 0.10V; TRI-STATE, measured VOL1 (DC) 0.10V. Note TRI-STATE attained using Note power switching characteristics EPROMs require careful device decoupling. recommended that least ceramic capacitor used every device between GND. Note outputs must restricted 1.0V avoid latch-up device damage. Note Gate: -400 includes fixture capacitance. Note Inputs outputs undershoot -2.0V Max.
FM27C512
www.fairchildsemi.com
FM27C512 524,288-Bit (64K High Performance CMOS EPROM
Programming Characteristics (Note (Note
Symbol
tOES tVCS tOEH tPRT tOUT
Parameter
Address Setup Time Setup Time Data Setup Time Setup Time Address Hold Time Data Hold Time Chip Enable Output Float Delay Program Pulse Width Hold Time Data Valid from Pulse Rise Time during Programming Recovery Time Supply Current during Programming Pulse Supply Current Temperature Ambient Power Supply Voltage Programming Supply Voltage Input Rise, Fall Time Input Voltage Input High Voltage Input Timing Reference Voltage Output Timing Reference Voltage
Conditions
Units
6.25 12.5 0.45 12.75 6.75
Programming Waveforms
Program Addresses 2.0V 0.8V 2.0V Data 0.8V 12.75V 0.8V tPRT CE/PGM 6.25V Data Stable Hi-Z 2.0V 0.8V Data Valid Address Program Verify
OE/VPP
DS800035-5
Note Fairchild's standard product warranty applies devices programmed specifications described herein. Note must applied simultaneously before removed simultaneously after VPP. EPROM must inserted into removed from board with voltage applied VCC. Note maximum absolute allowable voltage which applied during programming 14V. Care must taken when switching supply prevent overshoot from exceeding this maximum specification. least capacitor required across suppress spurious voltage transients which damage device.
FM27C512
www.fairchildsemi.com
FM27C512 524,288-Bit (64K High Performance CMOS EPROM
Turbo Programming Algorithm Flow Chart
6.5V 12.75V ADDRESS FIRST LOCATION
PROGRAM 50µs PULSE INCREMENT
DEVICE FAILED
FAIL
VERIFY BYTE
PASS
LAST ADDRESS
INCREMENT ADDRESS
ADDRESS FIRST LOCATION
VERIFY BYTE INCREMENT ADDRESS
PASS
FAIL
PROGRAM PULSE
LAST ADDRESS
CHECK BYTES 1ST: 6.0V 2ND: 4.3V
Note: standard National Semiconductor algorithm also used will take longer programming time. DS800035-6
FIGURE
FM27C512
www.fairchildsemi.com
FM27C512 524,288-Bit (64K High Performance CMOS EPROM
Functional Description
DEVICE OPERATION
modes operation EPROM listed Table1. should noted that inputs modes levels. power supplies required OE/VPP. OE/VPP power supply must 12.75V during three programming modes, must other three modes. power supply must 6.5V during three programming modes, other three modes.
EPROM programming mode when OE/VPP 12.75V. required that least capacitor placed across ground suppress spurious voltage transients which damage device. data programmed applied bits parallel data output pins. levels required address data inputs TTL. When address data stable, active low, program pulse applied CE/PGM input. program pulse must applied each address location programmed. EPROM programmed with Turbo Programming Algorithm shown Figure Each Address programmed with series pulses until verifies good, maximum pulses. Most memory cells will program with single pulse. (The standard National Semiconductor Algorithm also used will have longer programming time.) EPROM must programmed with signal applied CE/PGM input. Programming multiple EPROM parallel with same data easily accomplished simplicity programming requirements. Like inputs parallel EPROM connected together when they programmed with same data. level pulse applied CE/PGM input programs paralleled EPROM.
Read Mode
EPROM control functions, both which must logically active order obtain data outputs. Chip Enable (CE/PGM) power control should used device selection. Output Enable (OE/VPP) output control should used gate data output pins, independent device selection. Assuming that addresses stable, address access time (tACC) equal delay from output (tCE). Data available outputs after falling edge assuming that been addresses have been stable least tACC tOE.
Standby Mode
EPROM standby mode which reduces active power dissipation over 99%, from 0.55 EPROM placed standby mode applying CMOS high signal CE/PGM input. When standby mode, outputs high impedance state, independent input.
Program Inhibit
Programming multiple EPROMs parallel with different data also easily accomplished. Except CE/PGM like inputs (including OE/VPP) parallel EPROMs common. level program pulse applied EPROM's CE/PGM input with OE/VPP 12.75V will program that EPROM. high level CE/PGM input inhibits other EPROMs from being programmed.
Output Disable
EPROM placed output disable applying high signal input. When output disable circuitry enabled, except outputs high impedance state (TRISTATE).
Program Verify
verify should performed programmed bits determine whether they were correctly programmed. verify accomplished with OE/VPP VIL. Data should verified after falling edge
Output OR-Typing
Because EPROM usually used larger memory arrays, Fairchild provided 2-line control function that accommodates this multiple memory connections. 2-line control function allows for: lowest possible memory power dissipation, complete assurance that output contention will occur. most efficiently these control lines, recommended that CE/PGM decoded used primary device selecting function, while OE/VPP made common connection devices array connected READ line from system control bus. This assures that deselected memory devices their power standby modes that output pins active only when data desired from particular memory device.
AFTER PROGRAMMING
Opaque labels should placed over EPROM window prevent unintentional erasure. Covering window will also prevent temporary functional failure generation photo currents.
MANUFACTURER'S IDENTIFICATION CODE
EPROM manufacturer's identification code programming. When device inserted EPROM programmer socket, programmer reads code then automatically calls specific programming algorithm part. This automatic programming control only possible with programmers which have capability reading code. Manufacturer's Identification code, shown Table specifically identifies manufacturer device type. code FM27C512 "8F85", where "8F" designates that made Fairchild Semiconductor, "85" designates 512K part. code accessed applying ±0.5V address Addresses A1-A8, A10-A16, control pins
Programming
CAUTION: Exceeding (OE/VPP) will damage EPROM. Initially, after each erasure, bits EPROM "1's" state. Data introduced selectively programming "0's" into desired locations. Although only "0's" will programmed, both "1's" "0's" presented data word. only change ultraviolet light erasure.
FM27C512
www.fairchildsemi.com
FM27C512 524,288-Bit (64K High Performance CMOS EPROM
Functional Description (Continued)
held VIL. Address held manufacturer's code, held device code. code read eight data pins, Proper code access only guaranteed 25°C ±5°C.
Lamps lose intensity they age. When lamp changed, distance changed, lamp aged, system should checked make certain full erasure occurring. Incomplete erasure will cause symptoms that misleading. Programmers, components, even system designs have been erroneously suspected when incomplete erasure problem.
ERASURE CHARACTERISTICS
erasure characteristics device such that erasure begins occur when exposed light with wavelengths shorter than approximately 4000 Angstroms should noted that sunlight certain types fluorescent lamps have wavelengths range. recommended erasure procedure EPROM exposure short wave ultraviolet light which wavelength integrated dose (i.e., intensity exposure time) erasure should minimum 15W-sec/cm2. EPROM should placed within inch lamp tubes during erasure. Some lamps have filter their tubes which should removed before erasure erasure system should calibrated periodically. distance from lamp device should maintained inch. erasure time increases square distance from lamp distance doubled erasure time increases factor
SYSTEM CONSIDERATION
power switching characteristics EPROMs require careful decoupling devices. supply current, ICC, three segments that interest system designer: standby current level, active current level, transient current peaks that produced voltage transitions input pins. magnitude these transient current peaks dependent output capacitance loading device. associated transient voltage peaks suppressed properly selected decoupling capacitors. recommended that least ceramic capacitor used every device between GND. This should high frequency capacitor inherent inductance. addition, least bulk electrolytic capacitor should used between each eight devices. bulk capacitor should located near where power supply connected array. purpose bulk capacitor overcome voltage drop caused inductive effects board traces.
Mode Selection
modes operation FM27C512 listed Table single power supply required read mode. inputs levels excepts device signature.
TABLE Mode Selection Pins Mode
Read Output Disable Standby Programming Program Verify Program Inhibit
Note VIH.
CE/PGM
(Note
OE/VPP
12.75V 12.75V
5.0V 5.0V 5.0V 6.25V 6.25V 6.25V
Outputs
DOUT High High DOUT High
TABLE Manufacturer's Identification Code Pins
Manufacturer Code Device Code
(10)
(24)
(19)
(18)
(17)
(16)
(15)
(13)
(12)
(11)
Data
FM27C512
www.fairchildsemi.com
FM27C512 524,288-Bit (64K High Performance CMOS EPROM
Physical Dimensions inches (millimeters) unless otherwise noted
1.465 [37.211]
0.025 [0.635] 0.515-0.530 [13.081-13.462]
0.030-0.055 [0.762-1.397]
0.290-0.310 [7.366-7.874] U.V. WINDOW 0.050-0.060 [1.270-1.524] GLASS SEALANT
0.010 [0.254] 0.180 [4.572]
0.590-0.620 [14.99-15.75]
0.225 [5.715]
0.125 [3.175] 0.060-0.100 [1.524-2.540] 0.090-0.110 [2.286-2.794]
86°-94° 0.015-0.021 [0.381-0.533] 0.033-0.045 [0.838-1.143] 0.015-0.060 [0.381-1.524]
90°-100° 0.008-0.012 [0.203-0.305] +0.025 0.685 -0.060 +0.635 [17.399 -1.524
Window Cavity Dual-In-Line Cerdip Package (JQ) Order Number FM27C512Q Package Number J28CQ
0.030 (0.762) 0.600 0.620 (15.24 15.75) 0.062 (1.575)
0.510 ±0.005 (12.95 ±0.127)
0.580 (14.73) +0.025 0.625 -0.015 0.008-0.015 (0.229-0.381) IDENT
1.393 1.420 (35.38 36.07)
0.050 (1.270) 0.125-0.165 (3.175-4.191) 0.20 (0.508)
(15.88 +0.635 -0.381
0.053 0.069 (1.346 1.753)
0.050 ±0.015 (1.270 ±0.381)
0.108 ±0.010 (2.540 ±0.254)
0.018 ±0.003 (0.457 ±0.076)
0.125-0.145 (3.175-3.583)
28-Lead Plastic One-Time-Programmable Dual-In-Line Order Number FM27C512N Package Number N28B
FM27C512
www.fairchildsemi.com
FM27C512 524,288-Bit (64K High Performance CMOS EPROM
Physical Dimensions inches (millimeters) unless otherwise noted
0.485-0.495 [12.32-12.57]
0.007[0.18]
0.449-0.453 [11.40-11.51] -A0.045 [1.143] 0.000-0.010 [0.00-0.25] Polished Optional
0.106-0.112 [2.69-2.84] 0.023-0.029 [0.58-0.74]
Base Plane
0.015 [0.38]
0.007[0.18] 0.002[0.05] 0.541-0.545 [13.74-13-84]
[10.16]
0.400
0.490-0530 [12.45-13.46] 0.015[0.38] D-E,
0.549-0.553 [13.94-14.05] -B0.585-0.595 [14.86-15.11]
-FSee detail -J13
0.002[0.05] 0.007[0.18]
0.013-0.021 [0.33-0.53] 0.007[0.18] 0.078-0.095 [1.98-2.41] -C0.004[0.10] 0.020 [0.51] 0.005 [0.13] 0.0100 [0.254] D-E,
0.007[0.18]
0.118-0.129 [3.00-3.28] 0.010[0.25] D-E, 0.042-0.048 45°X [1.07-1.22]
0.026-0.032 [0.66-0.81]
0.007[0.18] D-E,
0.025 [0.64] 0.006-0.012 [0.15-0.30] 0.019-0.025 [0.48-0.64]
0.050
0.123-0.140 [3.12-3.56]
0.045 [1.14] 0.025 [0.64] 0.021-0.027 [0.53-0.69]
Detail Typical Rotated
0.030-0.040 [0.76-1.02]
0.065-0.071 [1.65-1.80]
0.053-0.059 [1.65-1.80] 0.031-0.037 [0.79-0.94] 0.027-0.033 [0.69-0.84]
Section Typical
32-Lead Plastic Leaded Chip Carrier (PLCC) Order Number FM27C512V Package Number VA32A
Life Support Policy
Fairchild's products authorized critical components life support devices systems without express written approval President Fairchild Semiconductor Corporation. used herein: Life support devices systems devices systems which, intended surgical implant into body, support sustain life, whose failure perform, when properly used accordance with instructions provided labeling, reasonably expected result significant injury user.
Fairchild Semiconductor Americas Customer Response Center Tel. 1-888-522-5372 Fairchild Semiconductor Europe Fax: 1793-856858 Deutsch Tel: 8141-6102-0 English Tel: 1793-856856 Tel: 1-6930-3696 Italiano Tel: 2-249111-1
critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness.
Fairchild Semiconductor Hong Kong 8/F, Room 808, Empire Centre Mody Road, Tsimshatsui East Kowloon. Hong Kong Tel; +852-2722-8338 Fax: +852-2722-8383
Fairchild Semiconductor Japan Ltd. Natsume Bldg. 2-18-6, Yushima, Bunkyo-ku Tokyo, 113-0034 Japan Tel: 81-3-3818-8840 Fax: 81-3-3818-8841
Fairchild does assume responsibility circuitry described, circuit patent licenses implied Fairchild reserves right time without notice change said circuitry specifications.
FM27C512
www.fairchildsemi.com
Other recent searches
LSI5464E - LSI5464E LSI5464E Datasheet
IRFSL9N6 - IRFSL9N6 IRFSL9N6 Datasheet
DSN-2000A-219+ - DSN-2000A-219+ DSN-2000A-219+ Datasheet
2SB1434 - 2SB1434 2SB1434 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
