November 1983 Revised August 2000 CD4051BC CD4052BC CD4053BC Sing

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November 1983 Revised August 2000 CD4051BC CD4052BC CD4053BC Sing

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CD4051BC CD4052BC CD4053BC Single 8-Channel Analog Multiplexer/Demultiplexer Dual 4-Channel Analog Multiplexer/Demultiplexer Triple 2-Channel Analog Multiplexer/Demultiplexer
November 1983 Revised August 2000
CD4051BC CD4052BC CD4053BC Single 8-Channel Analog Multiplexer/Demultiplexer Dual 4-Channel Analog Multiplexer/Demultiplexer Triple 2-Channel Analog Multiplexer/Demultiplexer
CD4051BC, CD4052BC, CD4053BC analog multiplexers/demultiplexers digitally controlled analog switches having "ON" impedance very "OFF" leakage currents. Control analog signals 15Vp-p achieved digital signal amplitudes 3-15V. example, -5V, analog signals from controlled digital inputs 0-5V. multiplexer circuits dissipate extremely quiescent power over full VDD-VSS VDD-VEE supply voltage ranges, independent logic state control signals. When logical present inhibit input terminal channels "OFF". CD4051BC single 8-channel multiplexer having three binary control inputs. inhibit input. three binary signals select channels turned "ON" connect input output. CD4052BC differential 4-channel multiplexer having binary control inputs, inhibit input. binary input signals select pairs channels turned connect differential analog inputs differential outputs. CD4053BC triple 2-channel multiplexer having three separate digital control inputs, inhibit input. Each control input selects pair channels which connected single-pole double-throw configuration.
Features
Wide range digital analog signal levels: digital 15V, analog 15Vp-p "ON" resistance: (typ.) over entire 15Vp-p signal-input range High "OFF" resistance: channel leakage (typ.) Logic level conversion digital addressing signals (VDD 15V) switch analog signals Vp-p (VDD 15V) Matched switch characteristics: (typ.) Very quiescent power dissipation under digital-control input supply conditions: (typ.) Binary address decoding chip
Ordering Code:
Order Number CD4051BCM CD4051BCSJ CD4051BCMTC CD4051BCN CD4052BCM CD4052BCSJ CD4052BCN CD4053BCM CD4053BCSJ CD4053BCN Package Number M16A M16D MTC16 N16E M16A M16D N16E M16A M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available Tape Reel. Specify appending suffix letter ordering code.
2000 Fairchild Semiconductor Corporation
DS005662
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CD4051BC CD4052BC CD4053BC
Connection Diagrams
Assignments SOIC CD4051BC CD4052BC
CD4053BC
Truth Table
INPUT STATES INHIBIT
*Don't Care condition.
"ON" CHANNELS CD4051B NONE NONE CD4052B CD4053B NONE
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CD4051BC CD4052BC CD4053BC
Logic Diagrams
CD4051BC
CD4052BC
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CD4051BC CD4052BC CD4053BC
Logic Diagrams
(Continued) CD4053BC
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CD4051BC CD4052BC CD4053BC
Absolute Maximum Ratings(Note
Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (soldering, seconds) 260°C (Note
-0.5 -0.5 +0.5 -65°C +150°C
Recommended Operating Conditions
Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) CD4051BC/CD4052BC/CD4053BC
-40°C +85°C
Note "Absolute Maximum Ratings" those values beyond which safety device cannot guaranteed. Except "Operating Temperature Range" they meant imply that devices should operated these limits. Electrical Characteristics tables provide conditions actual device operation.
Electrical Characteristics
Symbol Parameter Control Inhibit Input Current 15V, 15V, Quiescent Device Current Signal Inputs (VIS) Outputs (VOS) "ON" Resistance (Peak VDD) (any channel selected)
Conditions
-40°C
+25° -0.1
+85°C
Units
-0.1
-10-5 10-5
-1.0
2.5V, -2.5V 10V, 7.5V, -7.5V 15V, 1050 1200
"ON" Resistance Between Channels
(any channel selected)
2.5V, -2.5V 10V, 7.5V, -7.5V 15V,
"OFF" Channel Leakage "OFF" Channel Leakage Current, channels "OFF" (Common OUT/IN) Control Inputs Inhibit
VDD=7.5V, Inhibit 7.5V 7.5V, -7.5V, ±7.5V
VEE=-7.5V ±200 ±200 ±200 ±0.01 ±0.08 ±0.04 ±0.02 ±200 ±200 ±200 ±500 ±2000 ±2000 ±2000 CD4051 D4052 CD4053
Current, channel "OFF" O/I=±7.5V, I/O=0V
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CD4051BC CD4052BC CD4053BC
Electrical Characteristics
Symbol Parameter Level Input Voltage
(Continued)
-40°C +25° +85°C
Conditions IIS<2 Channels thru
Units
-0.1
-0.1
HIGH Level Input Voltage
Input Current
15V, 15V,
-1.0
10-5
Note voltages measured with respect unless otherwise specified.
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CD4051BC CD4052BC CD4053BC
Electrical Characteristics
25°C, unless otherwise specified. Symbol tPZH, tPZL tPHZ, tPLZ Parameter Propagation Delay Time from Inhibit Signal Output (channel turning Propagation Delay Time from Inhibit Signal Output (channel turning off) Input Capacitance Control input Signal Input (IN/OUT) COUT Output Capacitance (common OUT/IN) CD4051 CD4052 CD4053 CIOS Feedthrough Capacitance Power Dissipation Capacitance CD4051 CD4052 CD4053 Signal Inputs (VIS) Outputs (VOS) Sine Wave Response (Distortion) Vp-p
(Note
Conditions 1200 Units
0.04
Frequency Response, Channel "ON" (Sine Wave Input) Feedthrough, Channel "OFF" Crosstalk Between Channels (frequency tPHL tPLH Propagation Delay Signal Input Signal Output 5Vp-p, log10 VOS/VIS 5Vp-p, log10 VOS/VIS VIS(A) 5Vp-p log10 VOS(B)/VIS(A) (Note Control Inputs, Inhibit Control Input Signal Crosstalk tPHL, tPLH Propagation Delay Time from Address Signal Output (channels "ON" "OFF")
Note Parameters guaranteed correlated testing. Note arbitrary channels with turned "ON" "OFF".
both ends channel. Input Square Wave Amplitude 1000 (peak)
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CD4051BC CD4052BC CD4053BC
Special Considerations
certain applications external load-resistor current include both signal-line components. avoid drawing current when switch current flows into IN/OUT pin, voltage drop across bidirectional switch must exceed 0.6V 25°C, 0.4V 25°C (calculated from values shown). current will flow through switch current flows into OUT/IN pin.
Typical Performance Characteristics
"ON" Resistance Signal Voltage 25°C "ON" Resistance Function Temperature VDD-
"ON" Resistance Function Temperature VDD-
"ON" Resistance Function Temperature
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Switching Time Waveforms
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Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A
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CD4051BC CD4052BC CD4053BC
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE 5.3mm Wide Package Number M16D
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CD4051BC CD4052BC CD4053BC
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16
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CD4051BC CD4052BC CD4053BC Single 8-Channel Analog Multiplexer/Demultiplexer Dual 4-Channel Analog Multiplexer/Demultiplexer Triple 2-Channel Analog Multiplexer/Demultiplexer
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E
Fairchild does assume responsibility circuitry described, circuit patent licenses implied Fairchild reserves right time without notice change said circuitry specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT FAIRCHILD SEMICONDUCTOR CORPORATION. used herein: Life support devices systems devices systems which, intended surgical implant into body, support sustain life, whose failure perform when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness. www.fairchildsemi.com
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November 1983 Revised August 2000 CD4051BC CD4052BC CD4053BC Sing

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