Internal Address Data Latches Bytes Internal Control Timer Fast Write

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Internal Address Data Latches Bytes Internal Control Timer Fast Write

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Single 3.3V Supply Fast Read Access Time Automatic Page Write Operation
Internal Address Data Latches Bytes Internal Control Timer Fast Write Cycle Time Page Write Cycle Time Maximum 128-Byte Page Write Operation Power Dissipation Active Current CMOS Standby Current Hardware Software Data Protection DATA Polling Write Detection High Reliability CMOS Technology Endurance: 100,000K Cycles Data Retention: Years JEDEC Approved Byte-Wide Pinout Commercial, Industrial Automotive Temperature Ranges Green (Pb/Halide-free) Packaging Option
1-Megabit (128K Voltage Paged Parallel EEPROMs AT28LV010
Description
AT28LV010 high-performance 3-volt only Electrically Erasable Programmable Read-Only Memory. megabit memory organized 131,072 words bits. Manufactured with Atmel's advanced nonvolatile CMOS technology, device offers access times with power dissipation just When device deselected, CMOS standby current less than AT28LV010 accessed like Static read write cycle without need external components. device contains 128-byte page register allow writing bytes simultaneously. During write cycle, address bytes data internally latched, freeing address data other operations. Following initiation write cycle, device will automatically write latched data using internal control timer. write cycle detected DATA polling I/O7. Once write cycle been detected access read write begin. Atmel's 28LV010 additional features ensure high quality manufacturability. device utilizes internal error correction extended endurance improved data retention characteristics. Software data protection implemented guard against inadvertent writes. device also includes extra bytes EEPROM device identification tracking.
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AT28LV010
Configurations
Name I/O0 I/O7 Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs Connect Don't Connect
32-lead PLCC View
32-lead TSOP View
I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
32-lead PDIP View
I/O0 I/O1 I/O2 I/O7 I/O6 I/O5 I/O4 I/O3
I/O1 I/O2 I/O3 I/O4 I/O5 I/O6
I/O0
I/O7
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AT28LV010
Block Diagram
Device Operation
Read
AT28LV010 accessed like Static RAM. When high, data stored memory location determined address pins asserted outputs. outputs high impedance state when either high. This dual-line control gives designers flexibility preventing contention their system.
Write
write operation AT28LV010 allows bytes data written into device during single internal programming period. Each write operation must preceded software data protection (SDP) command sequence. This sequence series three unique write command operations that enable internal write circuitry. command sequence data written must conform software protected write cycle timing. Addresses latched falling edge whichever occurs last data latched rising edge whichever occurs first. Each successive byte must written within (tBLC) previous byte. tBLC limit exceeded AT28LV010 will cease accepting data commence internal programming operation. more than data byte written during single programming operation, they must reside same page defined state inputs. each high transition during page write operation, must same. inputs used specify which bytes within page written. bytes loaded order altered within same load period. Only bytes which specified writing will written; unnecessary cycling other bytes within page does occur.
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DATA Polling
AT28LV010 features DATA Polling indicate write cycle. During byte page write cycle attempted read last byte written will result complement written data presented I/O7. Once write cycle been completed, true data valid outputs, next write cycle begin. DATA Polling begin anytime during write cycle.
Toggle
addition DATA Polling AT28LV010 provides another method determining write cycle. During write operation, successive attempts read data from device will result I/O6 toggling between zero. Once write completed, I/O6 will stop toggling valid data will read. Reading toggle begin time during write cycle.
Data Protection
precautions taken, inadvertent writes occur during transitions host system power supply. Atmel incorporated both hardware software features that will protect memory against inadvertent writes.
4.5.1
Hardware Protection Hardware features protect against inadvertent writes AT28LV010 following ways: power-on delay once reached 2.0V (typical) device will automatically time (typical) before allowing write; write inhibit holding low, high high inhibits write cycles; noise filter pulses less than (typical) inputs will initiate write cycle. Software Data Protection AT28LV010 incorporates industry standard software data protection (SDP) function. Unlike standard 5-volt only EEPROM's, AT28LV010 enabled times. Therefore, write operations must preceded command sequence. data 3-byte command sequence written device; addresses command sequence utilized just like other location device. attempt write device without 3-byte sequence will start internal timers. data will written device. However, duration tWC, read operations will effectively polling operations.
4.5.2
AT28LV010
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AT28LV010
Operating Range
AT28LV010-20 Com. Operating Temperature (Case) Power Supply Ind. Automotive 70°C -40°C 85°C -40°C 125°C 3.3V 3.3V AT28LV010-25 70°C -40°C 85°C
Operating Modes
Mode Read Write
DOUT High
Standby/Write Inhibit Write Inhibit Write Inhibit Output Disable Notes: VIH. Refer Programming Waveforms.
High
Absolute Maximum Ratings*
Temperature Under Bias. -55°C +125°C Storage Temperature -65°C +150°C Input Voltages (including Pins) with Respect Ground .-0.6V +6.25V Output Voltages with Respect Ground .-0.6V 0.6V Voltage with Respect Ground .-0.6V +13.5V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability
Characteristics
Symbol Parameter Input Load Current Output Leakage Current Standby Current CMOS Active Current Input Voltage Input High Voltage Output Voltage Output High Voltage 3.0V -100 3.0V 0.45 Condition VI/O Com. 0.3V Ind. Units
MHz; IOUT 3.6V
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Read Characteristics
AT28LV010-20 Symbol tACC
AT28LV010-25 Units
Parameter Address Output Delay Output Delay Output Delay Output Float Output Hold from Address, Whichever Occurred First
tOE(2) tDF(3)(4)
Read Waveforms(1)(2)(3)(4)
Notes:
delayed tACC after address transition without impact tACC. delayed after falling edge without impact tACC after address change without impact tACC. specified from whichever occurs first pF). This parameter characterized 100% tested.
AT28LV010
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AT28LV010
Input Test Waveforms Measurement Level
Output Test Load
Capacitance
MHz, 25°C(1)
Symbol COUT Note: Units Conditions VOUT
This parameter characterized 100% tested.
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Write Characteristics(1)
Symbol tAS, tOES tDH, tOEH Note: Parameter Address, Set-up Time Address Hold Time Chip Select Set-up Time Chip Select Hold Time Write Pulse Width Data Set-up Time Data, Hold Time Units
write operations must preceded command sequence.
Write Waveforms
15.1 Controlled
15.2
Controlled
AT28LV010
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AT28LV010
Software Protected Write Characteristics
Symbol tBLC tWPH Parameter Write Cycle Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Write Pulse Width Byte Load Cycle Time Write Pulse Width High Units
Programming Algorithm
LOAD DATA ADDRESS 5555
LOAD DATA ADDRESS 2AAA
LOAD DATA ADDRESS 5555
WRITES ENABLED(2)
LOAD DATA ADDRESS(3)
LOAD LAST BYTE LAST ADDRESS(3)
ENTER DATA PROTECT STATE
Notes:
Data Format: I/O7 I/O0 (Hex); Address Format: (Hex). Data protect state will re-activated program cycle. bytes data loaded.
Software Protected Program Cycle Waveforms(1)(2)(3)
Notes:
must conform addressing sequence first three bytes shown above. After command sequence been issued page write operation follows, page address inputs A16) must same each high transition CE). must high only when both low.
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Data Polling Characteristics(1)
Symbol tOEH Notes: Parameter Data Hold Time Hold Time Output Delay
Units
Write Recovery Time These parameters characterized 100% tested. Read Characteristics
Data Polling Waveforms
Toggle Characteristics(1)
Symbol tOEH tOEHP Notes: Parameter Data Hold Time Hold Time Output Delay High Pulse Write Recovery Time These parameters characterized 100% tested. Read Characteristics
Units
Toggle Waveforms
Notes:
Toggling either both will operate toggle bit. Beginning ending state I/O6 will vary. address location used address should vary.
AT28LV010
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AT28LV010
Ordering Information(1)
23.1 Standard Package
(mA) Active Standby 0.02 Ordering Code AT28LV010-20JC AT28LV010-20PC AT28LV010-20TC AT28LV010-20JI AT28LV010-20PI AT28LV010-20TI AT28LV010-20TA AT28LV010-25JC AT28LV010-25PC AT28LV010-25TC AT28LV010-25JI AT28LV010-25PI AT28LV010-25TI Package 32P6 32P6 32P6 32P6 Operation Range Commercial 70°C) Industrial (-40° 85°C) Automotive (-40° 125°C) Commercial 70°C) Industrial (-40° 85°C) tACC (ns)
0.05
0.05 0.02
0.05
Note:
"Valid Part Numbers" below.
23.2
Green Package Option (Pb/Halide-free)
(mA) Active Standby 0.05 Ordering Code AT28LV010-20JU AT28LV010-20TU Package Operation Range Industrial (-40° 85°C)
tACC (ns)
Package Type 32P6 32-Lead, Plastic J-Leaded Chip Carrier (PLCC) 32-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 32-Lead, Plastic Thin Small Outline Package (TSOP)
Valid Part Numbers
following table lists standard Atmel products that ordered.
Device Numbers AT28LV010 AT28LV010 Speed Package Temperature Combinations
Products
Reference Section: Parallel EEPROM Products
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Packaging Information
26.1 PLCC
1.14(0.045)
IDENTIFIER
1.14(0.045) 0.318(0.0125) 0.191(0.0075)
0.51(0.020)MAX (3X)
COMMON DIMENSIONS (Unit Measure SYMBOL
3.175 1.524 0.381 12.319 11.354 9.906 14.859 13.894 12.471 0.660 0.330
1.270
3.556 2.413 12.573 11.506 10.922 15.113 14.046 13.487 0.813 0.533
NOTE
Note
Notes:
This package conforms JEDEC reference MS-016, Variation Dimensions include mold protrusion. Allowable protrusion .010"(0.254 side. Dimension include mold mismatch measured extreme material condition upper lower parting line. Lead coplanarity 0.004" (0.102 maximum.
Note
10/04/01 2325 Orchard Parkway Jose, 95131 TITLE 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING REV.
AT28LV010
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AT28LV010
26.2 32P6 PDIP
SEATING PLANE
SYMBOL
COMMON DIMENSIONS (Unit Measure 0.381 41.783 15.240 13.462 0.356 1.041 3.048 0.203 15.494 2.540 4.826 42.291 15.875 13.970 0.559 1.651 3.556 0.381 17.526 Note Note NOTE
Note:
Dimensions include mold Flash Protrusion. Mold Flash Protrusion shall exceed 0.25 (0.010").
09/28/01 2325 Orchard Parkway Jose, 95131 TITLE 32P6, 32-lead (0.600"/15.24 Wide) Plastic Dual Inline Package (PDIP) DRAWING 32P6 REV.
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26.3
TSOP
Identifier
SEATING PLANE
GAGE PLANE
SYMBOL Notes: This package conforms JEDEC reference MO-142, Variation Dimensions include mold protrusion. Allowable protrusion 0.15 side 0.25 side. Lead coplanarity 0.10 maximum.
COMMON DIMENSIONS (Unit Measure 0.05 0.95 19.80 18.30 7.90 0.50 1.00 20.00 18.40 8.00 0.60 0.25 BASIC 0.17 0.10 0.22 0.50 BASIC 0.27 0.21 1.20 0.15 1.05 20.20 18.50 8.10 0.70 Note Note NOTE
10/18/01 2325 Orchard Parkway Jose, 95131 TITLE 32T, 32-lead Package) Plastic Thin Small Outline Package, Type (TSOP) DRAWING REV.
AT28LV010
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Atmel Corporation
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0395C-PEEPR-04/05

Internal Address Data Latches Bytes Internal Control Timer Fast Write

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