Phase Noise Frequency Synthesiser Data Sheet Complete Single Chip
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SP5730
Phase Noise Frequency Synthesiser Data Sheet
Complete Single Chip System Digital Terrestrial Television Applications Selectable Reference Division Ratio, Compatible with Requirements Optimised Phase Noise, with Comparison Frequencies Prescaler Selectable Reference/Comparison Frequency Output Four Selectable Addresses Fast Mode Compliant with Logic Levels Four Switching Ports Functional Replacement SP5659 (except ADC) Compatible with SP5655 Power Consumption 120mW with Ports Protection min., MIL-STD-883B Method 3015 Cat.1 (Normal handling procedures should observed)
Ordering Information SP5730A/KG/QP1T QSOP SP5730A/KG/QP1S QSOP SP5730A/KG/MP1S SOIC SP5730A/KG/MP2S SOIC* SP5730A/KG/QP2T QSOP* SP5730A/KG/MP1T SOIC SP5730A/KG/MP2T SOIC* SP5730A/KG/QP2S QSOP* Free Matte
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prescaler phase noise degradation over full operating range. comparison frequency obtained either from on-chip crystal controlled oscillator, from external source. oscillator frequency, fREF, phase comparator frequency, fCOMP, switched REF/ COMP output providing reference second frequency synthesiser. synthesiser controlled fast mode compliant. hard wired respond four addresses enable more synthesisers used common bus. device contains four switching ports
Applications
Digital Satellite, Cable Terrestrial Tuning Systems Communications Systems
Absolute Maximum Ratings
voltages referred Supply voltage, differential input voltage port offsets offset Storage temperature -55°C +150°C Junction temperature +150°C QP16 thermal resistance Chip ambient, 80°C/W Chip case, 20°C/W
Description
SP5730 single chip frequency synthesiser designed tuning systems optimised digital terrestrial applications. preamplifier interfaces direct with programmable divider, which MN1A construction giving step size equal loop comparison frequency
REF/COMP CRYSTAL CRYSTAL CHARGE PUMP DRIVE
INPUT
12-BIT COUNT
REFERENCE DIVIDER
ENABLE/ SELECT
48/9
3-BIT COUNT
LOCK fPD/2
PUMP
MODE
DISABLE
15-BIT LATCH ADDRESS
TRANSCEIVER 4-BIT LATCH PORT INTERFACE
fPD/2 SELECT
Figure SP5730 block diagram
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SP5730
Datasheet
CHARGE PUMP CRYSTAL CRYSTAL PORT P3/LOGLEV PORT PORT
5730
DRIVE INPUT RFINPUT REF/COMP ADDRESS PORTP0
CHARGE PUMP CRYSTAL CRYSTAL PORT P3/LOGLEV PORT PORT
5730
DRIVE INPUT RFINPUT REF/COMP ADDRESS PORTP0
MP16
Figure connections view
QP16
Table Electrical Characteristics
Test Conditions: TAMB -40°C +85°C, These characteristics guaranteed either production test design. They apply within specified ambient temperature supply voltage ranges unless otherwise stated. Value Characteristic Supply current input Input voltage Input impedance SDA, Input high voltage Input voltage Input high current Input current Leakage current Input hysteresis output voltage clock rate Charge pump Output current Output leakage Drive output current Crystal Frequency External reference Input frequency Drive level Buffered REF/COMP Output amplitude Output impedance Phase Detector Comparison frequency Equivalent phase noise phase detector division ratio Reference division ratio 13,14
Min.
Typ.
Max.
Units
Conditions
mVrms 100MHz Figure mVrms 50MHz 100MHz, Figure Figure logic selected logic selected logic selected logic selected Input voltage Input voltage ISINK ISINK
0.35 -152 -158 32767
Vp-p Vp-p
Table VPIN1 VPIN1 TAMB 25°C VPIN16 Figure application
Sinewave coupled 10nF blocking capacitor Sinewave coupled 10nF blocking capacitor coupled, Note 20MHz Enabled
dBc/Hz fCOMP 2MHz, SSB, Note dBc/Hz fCOMP 125kHz, SSB, Note Table cont.
Datasheet
Table Electrical Characteristics (continued)
Value Characteristic Output Ports Sink current Leakage current Address select Input high current Input current Logic level select Input high level Input level Input current
SP5730
Min. Typ.
Max.
Units
Conditions
VPORT VPORT Note Table Note logic level selected logic level selected
NOTES Output ports high impedance power-up, with logic `0'. REF/COMP output used, output should left open circuit connected disabled setting `0'. Bi-dectional port. When used output, input logic state ignored. When used input, port should switched into high impedance (off) state. Figures measured 2kHz deviation, (within loop bandwidth).
Functional Description
SP5730 contains elements necessary, with exception frequency reference, loop filter external high voltage transistor, control varactor tuned local oscillator, forming complete frequency synthesised source. device allows operation with high comparison frequency fabricated high speed logic, which enables generation loop with good phase noise performance. also operated with comparison frequencies appropriate frequency offsets required digital terrestrial television (DTT) receivers. input signal internal preamplifier, which provides gain reverse isolation from divider signals. output preamplifier interfaces with 15-bit fully programmable divider which MN1A architecture, where dual modulus prescaler 48/9, counter bits, counter bits. output programmable divider applied phase comparator where compared both phase frequency domains with comparison frequency. This frequency derived either from on-chip crystal controlled oscillator from external reference source. both cases reference frequency divided down comparison frequency reference divider which programmable into ratios detailed inTable output phase detector feeds charge pump loop amplifier section, which when used with external high voltage transistor loop filter, integrates current pulses into varactor line voltage. programmable divider output fPD/2 switched port programming device into test mode. test modes described inTable Programming SP5730 controlled data compatible with both standard fast mode formats with data generated from nominal sources. logic level selected bi-directional port LOGLEV. logic levels selected connecting LOGLEV leaving open circuit; logic levels connecting P3/LOGLEV ground. this port used input data should programmed high impedance. used output only logic levels used, which case logic state imposed port input ignored. Data clock lines respectively defined format synthesiser either accept data (write mode), send data (read mode). address byte (R/W) sets device into write mode low, read mode high. Tables illustrate format data. device programmed respond several addresses, which enables more than synthesiser system. Table shows address selected applying voltage address input. When device receives valid address byte, pulls line during acknowledge period, during following acknowledge periods after further data bytes received. When device programmed into read mode, controller accepting data must pulled during status byte acknowledge periods read another status byte. controller fails pull line during this period, device generates internal STOP condition, which inhibits further reading.
SP5730
Datasheet
logic indicating byte logic indicating byte Having interpreted this byte either byte following data byte will interpreted byte respectively. Having received complete data bytes, additional data bytes entered, where byte interpretation follows same procedure, without readdressing device. This procedure continues until STOP condition received. STOP condition generated after data byte; however, occurs during byte transmission, previous byte data retained. facilitate smooth fine tuning, frequency data bytes only accepted device after bits frequency data have been received, after generation STOP condition. Read mode When device read mode, status byte read from device takes form shown Table (POR) power-on reset indicator, this logic supply device dropped below 25°C e.g. when device initially turned reset when read sequence terminated STOP command. When high this indicates programmed information corrupted device reset power condition. (FL) indicates whether device phase locked, logic'1'is present device locked, logic not.
Table Reference division ratios
Division ratio Illegal state Illegal state Illegal state
Programable features
programmable divider Function described above. Reference programmable divider Function described above. Charge pump current charge pump current programmed bits within data byte defined Table Test mode test modes invoked setting bits described Table Reference/Comparison frequency output reference frequency comparison frequency fCOMP switched REF/COMP output, function defined Table default logic'1'during device power thus enabling comparison frequency fCOMP REF/COMP output.
Write mode With reference Table bytes contain frequency information bits 214-20 inclusive. Bytes control reference divider ratio (see Table charge pump setting (see Table REF/COMP output (see Table output ports test modes (see Table After reception acknowledgement correct address (byte first following byte determines whether byte interpreted byte
Datasheet
Table Write data format (MSB transmitted first)
Address Programmable divider Programmable divider Control data Control data
SP5730
Byte Byte Byte Byte Byte
Table Acknowledge MA1, Variable address bits (see Table 214-20 Programmable division ratio control bits R4-R0 Reference division ratio select (see Table Charge pump current select (see Table Reference oscillator output enable REF/COMP output select when RE=1 (see Table T1-T0 Test mode control bits (see Table P3-P0 port output states
Table Read data format (MSB transmitted first)
Address Status byte Byte Byte
table Acknowledge MA1, Variable address bits (see Table Power Reset indicator Phase lock flag
Table Address selection
Address input voltage level Open circuit
Table Test modes
Test mode description Normal operation Normal operation, fPD/2 Charge pump sink*, Charge pump source*, Charge pump disabled*,
Programmed connecting resistor from
Table Charge pump current
Current (µA) Min. ±116 ±247 ±517 ±1087 Typ. ±155 ±330 ±690 ±1450 Max. ±194 ±412 ±862 ±1812
Clocks need present crystal inputs enable
charge pump test modes toggle Status byte don't care
Table REF/COMP output
REF/COMP output High impedance fREF selected fCOMP selected
don't care
SP5730
Datasheet
(mVRMS INTO
12.5
OPERATING WINDOW
1000 FREQUENCY (MHz)
1300
Figure Typical input sensitivity
j0.5
j0.2
50MHz 500MHz
2j0.2
1GHz 2j0.5
S11: Normalised
Figure input impedance
SP5730
Figure Crystal oscillator application
POWER CONNECTOR 130V 130V SDA5
Figure SP5730 evaluation board
CON1 INPUT tuning range 500MHz 900MHz
VARACTOR
5730
SCL5
LED1 LED2
LED3 LED4
Datasheet
COMP OUTPUT
PORT OUTPUTS
SP5730
SP5730
Datasheet
Component Value/type 18pF 68pF 10nF 100nF 100nF 100pF 100pF 100pF 100pF 10nF 39pF 100pF Component Value/type 100pF HLMPK-150 HLMPK-150 DIP-2 BCW31 POS_900 4MHz
Table Component values Figure
Datasheet
SP5730
view
Bottom view Figure SP5730 evaluation board layout
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