Available 2.5-V, 3-V, 3.3-V, 4.85-V, Fixed-Output Adjustable Versions
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TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION
Available 2.5-V, 3-V, 3.3-V, 4.85-V, Fixed-Output Adjustable Versions Integrated Precision Supply-Voltage Supervisor Monitoring Regulator Output Voltage Active-Low Reset Signal with 200-ms Pulse Width Very Dropout Voltage Maximum (TPS7350) Quiescent Current Independent Load Extremely Sleep-State Current, Tolerance Over Full Range Load, Line, Temperature Fixed-Output Output Current Range TSSOP Package Option Offers Reduced Component Height Critical Applications
PACKAGE (TOP VIEW)
RESET SENSE/FB
PACKAGE (TOP VIEW)
RESET SENSE
description
TPS73xx devices members family micropower low-dropout (LDO) voltage regulators. They differentiated from TPS71xx TPS72xx LDOs their integrated delayed microprocessor-reset function. precision delayed reset required, TPS71xx TPS72xx should
AVAILABLE OPTIONS OUTPUT VOLTAGE 4.75 40°C 125°C 3.23 2.94 2.425 4.85 4.95 3.37 3.06 2.575 4.55 2.868 2.58 2.23 1.101 4.65 2.934 2.64 2.32 1.123 4.75 2.39 1.145 NEGATIVE-GOING RESET THRESHOLD VOLTAGE SMALL OUTLINE TPS7350QD TPS7348QD TPS7333QD TPS7330QD TPS7325QD TPS7301QD PACKAGED DEVICES PLASTIC TPS7350QP TPS7348QP TPS7333QP TPS7330QP TPS7325QP TPS7301QP TSSOP (PW) TPS7350QPW TPS7348QPW TPS7333QPW TPS7330QPW TPS7325QPW TPS7301QPW CHIP FORM
internal connection SENSE Fixed voltage options only (TPS7325, TPS7330, TPS7333, TPS7348, TPS7350) Adjustable version only (TPS7301)
TPS7350Y TPS7348Y TPS7333Y TPS7330Y TPS7325Y TPS7301Y
Adjustable 9.75
packages available taped reeled. suffix device type (e.g., TPS7350QDR). TPS7301Q programmable using external resistor divider (see application information). chip form tested 25°C. TPS7325 tolerance over full temperature range. TPS71xx TPS72xx 500-mA 250-mA output regulators respectively, offering performance similar that TPS73xx without delayed-reset function. TPS72xx devices further differentiated availability 8-pin thin-shrink small-outline packages (TSSOP) applications requiring minimum package size.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 1999, Texas Instruments Incorporated
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description (continued)
RESET output TPS73xx initiates reset microcomputer microprocessor systems event undervoltage condition. internal comparator TPS73xx monitors output voltage regulator detect undervoltage condition regulated output voltage. that occurs, RESET output (open-drain NMOS) turns taking RESET signal low. RESET stays duration undervoltage condition. Once undervoltage condition ceases, 200-ms (typ) time-out begins. completion 200-ms delay, RESET goes high. order magnitude reduction dropout voltage quiescent current over conventional performance achieved replacing typical pass transistor with PMOS device. Because PMOS device behaves low-value resistor, dropout voltage very (maximum output current TPS7350) directly proportional output current (see Figure Additionally, since PMOS pass element voltage-driven device, quiescent current remains constant, independent output loading (typically over full range output current, mA). These specifications yield significant improvement operating life battery-powered systems. family also features sleep mode; applying logic high signal (enable) shuts down regulator, reducing quiescent current maximum 25°C. TPS73xx offered 2.5-V, 3-V, 3.3-V, 4.85-V, fixed-voltage versions adjustable version (programmable over range 9.75 Output voltage tolerance specified maximum over line, load, temperature ranges adjustable version). TPS73xx family available PDIP pin), pin) TSSOP pin) packages. TSSOP maximum height
25°C 0.25 TPS7333 Dropout Voltage TPS7325 TPS7348 TPS7350 0.05 TPS7325, TPS7330, TPS7333, TPS7348, TPS7350 (fixed-voltage options) Capacitor selection nontrivial. application information section details. TPS73xxPW TPS7330 0.15 SENSE RESET System Reset
Output Current
Figure Dropout Voltage Versus Output Current
Figure Typical Application Configuration
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TPS73xxY chip information
These chips, when properly assembled, display characteristics similar those TPS73xxQ. Thermal compression ultrasonic bonding used doped aluminum bonding pads. Chips mounted with conductive epoxy gold-silicon preform.
BONDING ASSIGNMENTS TPS73xx CHIP THICKNESS: TYPICAL BONDING PADS: MINIMUM TJmax 150°C TOLERANCES 10%. DIMENSIONS MILS. SENSE Fixed voltage options only (TPS7325, TPS7330, TPS7333, TPS7348, TPS7350) Adjustable version only (TPS7301) NOTE most applications, SENSE should tied together close possible device; other implementations, refer SENSE-pin connection discussion applications information section this data sheet. SENSE RESET
functional block diagram
RESET RESISTOR DIVIDER OPTIONS DEVICE TPS7301 TPS7325 TPS7330 TPS7333 TPS7348 TPS7350 UNIT
Vref
Delayed Reset
NOTE Resistors nominal values only.
COMPONENT COUNT transistors Bilpolar transistors Diodes Capacitors Resistors
most applications, SENSE should externally connected close possible device. other implementations, refer SENSE-pin connection discussion applications information section. Switch positions shown with (active).
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timing diagram
Vres Threshold Voltage RESET Output Delay Delay
Vres
Output Undefined
Vres minimum input voltage valid RESET. symbol Vres currently listed within JEDEC standards semiconductor symbology.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Input voltage RESET, SENSE, Output current, Continuous total power dissipation Dissipation Rating Tables Operating virtual junction temperature range, 55°C 150°C Storage temperature range, Tstg 65°C 150°C Lead temperature (1/16 inch) from case seconds 260°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. voltage values with respect network terminal ground.
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Output Undefined
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION
DISSIPATION RATING TABLE FREE-AIR TEMPERATURE (SEE FIGURE PACKAGE 25°C POWER RATING 1175 DERATING FACTOR ABOVE 25°C mW/°C mW/°C mW/°C 70°C POWER RATING 125°C POWER RATING
DISSIPATION RATING TABLE CASE TEMPERATURE (SEE FIGURE PACKAGE 25°C POWER RATING 2188 2738 DERATING FACTOR ABOVE 25°C mW/°C 21.9 mW/°C 70°C POWER RATING 1765 1752 125°C POWER RATING 1248
4025 32.2 mW/°C 2576 Refer Thermal Information section detailed power dissipation considerations when using TSSOP package.
MAXIMUM CONTINUOUS DISSIPATION FREE-AIR TEMPERATURE
1400 Maximum Continuous Dissipation Maximum Continuous Dissipation 1200 4800 4400 4000 3600 3200 2800 2400 2000 1600 1200
MAXIMUM CONTINUOUS DISSIPATION CASE TEMPERATURE
1000
Package 37°C/W
Package 106°C/W
Package 172°C/W
Package 46°C/W
Package 178°C/W
Package 57°C/W
Free-Air Temperature
Case Temperature
Figure
Figure
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recommended operating conditions
TPS7301Q TPS7325Q Input voltage voltage, TPS7330Q TPS7333Q TPS7348Q TPS7350Q High-level input voltage Low-level input voltage Output current range, 2.47 3.77 5.33 UNIT
Operating virtual junction temperature range, Minimum input voltage defined recommended operating conditions maximum specified output voltage plus dropout voltage, VDO, maximum specified load range. Since dropout voltage function output current, usable range extended lighter loads. calculate minimum input voltage maximum load current used given application, following equation: I(min) O(max) DO(max load) Because TPS7301 programmable, rDS(on) should used calculate before applying above equation. equation calculating from rDS(on) given Note TPS7301 electrical characteristics table. minimum value 2.97 absolute lower limit recommended input voltage range TPS7301.
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electrical characteristics (CSR SENSE/FB shorted (unless otherwise noted)
PARAMETER Ground current (active mode) Input current (standby mode) Output current limit Pass-element leakage current standby mode RESET leakage current Output voltage temperature coefficient Thermal shutdown junction temperature logic high (standby mode) logic (active mode) hysteresis voltage input current Minimum active pass element Minimum valid RESET IO(RESET) 40°C 125°C 25°C 40°C 125°C 25°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 2.05 0.001 TEST 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C Normal operation RESET operation, 40°C 125°C 40°C 125°C 0.02 0.01 0.01 UNIT ppm/°C
(compensation series resistance) refers total series resistance, including equivalent series resistance (ESR) capacitor, series resistance added externally, trace resistance Pulse-testing techniques used maintain virtual junction temperature close possible ambient temperature; thermal effects must taken into account separately.
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TPS7301Q electrical characteristics (CSR shorted device leads (unless otherwise noted)
PARAMETER Reference voltage (measured Reference voltage temperature coefficient Input regulation Note Note Output regulation Note Ripple rejection Note Output noise-spectral density Output noise voltage RESET trip-threshold RESET hysteresis RESET output input current VO(FB) decreasing Measured VO(FB) 2.13 IO(RESET) TEST CONDITIONS Note 25°C 40°C 125°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 25°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 25°C 25°C 25°C 40°C 125°C 25°C 25°C 40°C 125°C 25°C 40°C 125°C 1.101 1.145 µVrms µV/Hz 0.32 0.23 0.52 0.83 1.182 1.147 1.217 0.85 0.85 UNIT ppm/°C
Pass-element series resistance (See Note
refers total series resistance, including capacitor, series resistance added externally, trace resistance Pulse-testing techniques used maintain virtual junction temperature close possible ambient temperature; thermal effects must taken into account separately. Output voltage programmed with closed-loop configuration (see application information). NOTES: When simultaneously, pass element rDS(on) increases (see Figure point where resulting dropout voltage prevents regulator from maintaining specified tolerance range. calculate dropout voltage, equation: rDS(on) rDS(on) function both output current input voltage. This parametric table lists rDS(on) which corresponds dropout conditions programmed output voltages respectively. other programmed values, refer Figure
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TPS7325Q electrical characteristics (CSR SENSE shorted (unless otherwise noted)
PARAMETER Output voltage TEST CONDITIONS Dropout Pass-element Pass element series Input regulation (2.97 Output regulation Ripple rejection Output noise-spectral density Output noise voltage RESET trip-threshold voltage RESET output voltage decreasing IO(RESET) 2.97 2.97 2.97 2.97 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 25°C 25°C 25°C 40°C 125°C 25°C 40°C 125°C 2.23 2.32 0.14 2.39 µVrms µV/Hz 2.45 2.425 2.55 2.575 UNIT
refers total series resistance, including capacitor, series resistance added externally, trace resistance Pulse-testing techniques used maintain virtual junction temperature close possible ambient temperature; thermal effects must taken into account separately. Dropout test pass-element series resistance test production tested. Test method requires SENSE terminal disconnected from output voltage.
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TPS7330Q electrical characteristics (CSR SENSE shorted (unless otherwise noted)
PARAMETER Output voltage TEST CONDITIONS Dropout voltage Pass-element Pass element series resistance Input regulation (2.94 VO)/IO, Output regulation Ripple rejection Output noise-spectral density Output noise voltage RESET trip-threshold voltage RESET output voltage decreasing IO(RESET) 2.94 2.94 2.94 2.94 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 25°C 25°C 25°C 40°C 125°C 25°C 40°C 125°C 2.58 2.64 0.14 µVrms µV/Hz 2.94 3.06 UNIT
refers total series resistance, including capacitor, series resistance added externally, trace resistance Pulse-testing techniques used maintain virtual junction temperature close possible ambient temperature; thermal effects must taken into account separately.
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TPS7333Q electrical characteristics (CSR SENSE shorted (unless otherwise noted)
PARAMETER Output voltage TEST CONDITIONS Dropout voltage Pass-element Pass element series resistance Input regulation (3.23 VO)/IO, 3.23 3.23 3.23 3.23 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C Output noise voltage RESET trip-threshold voltage RESET hysteresis voltage RESET output voltage IO(RESET) decreasing 25°C 25°C 25°C 40°C 125°C 25°C 25°C 40°C 125°C 2.868 0.17 µVrms µV/Hz 0.44 3.23 3.37 UNIT
Output regulation Ripple rejection Output noise-spectral density
refers total series resistance, including capacitor, series resistance added externally, trace resistance Pulse-testing techniques used maintain virtual junction temperature close possible ambient temperature; thermal effects must taken into account separately.
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TPS7348Q electrical characteristics 5.85 (CSR SENSE shorted (unless otherwise noted)
PARAMETER Output voltage TEST CONDITIONS 5.85 Dropout voltage Pass-element Pass element series resistance Input regulation (4.75 VO)/IO, 5.85 4.75 4.75 4.75 4.75 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C Output noise voltage RESET trip-threshold voltage RESET hysteresis voltage RESET output voltage IO(RESET) mA,VI 4.12 decreasing 25°C 25°C 25°C 40°C 125°C 25°C 25°C 40°C 125°C µVrms µV/Hz 0.28 4.75 4.85 4.95 0.37 0.52 UNIT
5.85 Output regulation 5.85 Ripple rejection Output noise-spectral density
refers total series resistance, including capacitor, series resistance added externally, trace resistance Pulse-testing techniques used maintain virtual junction temperature close possible ambient temperature; thermal effects must taken into account separately.
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TPS7350Q electrical characteristics (CSR SENSE shorted (unless otherwise noted)
PARAMETER Output voltage TEST CONDITIONS Dropout voltage Pass-element Pass element series resistance Input regulation (4.88 VO)/IO, Output regulation Ripple rejection Output noise-spectral density Output noise voltage RESET trip-threshold voltage RESET hysteresis voltage RESET output voltage IO(RESET) 4.25 decreasing 4.88 4.88 4.88 4.88 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 25°C 25°C 25°C 40°C 125°C 25°C 25°C 40°C 125°C 4.55 0.15 4.75 µVrms µV/Hz 0.27 0.35 UNIT
refers total series resistance, including capacitor, series resistance added externally, trace resistance Pulse-testing techniques used maintain virtual junction temperature close possible ambient temperature; thermal effects must taken into account separately.
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switching characteristics
PARAMETER TEST CONDITIONS 25°C 40°C 125°C TPS7301Q, TPS7333Q TPS7348Q, TPS7350Q RESET time delay time-out Figure UNIT
electrical characteristics (CSR 25°C, SENSE/FB shorted (unless otherwise noted)
PARAMETER TEST CONDITIONS Normal operation, 0.001 2.05 RESET TPS7301Y, TPS7333Y TPS7348Y, TPS7350Y Ground current (active mode) Input current (standby mode) Output current limit Pass-element leakage current standby mode RESET leakage current Thermal shutdown junction temperature logic (active mode) hysteresis voltage input current Minimum active pass element 0.01 0.01 0.02 UNIT
IO(RESET) Minimum valid RESET (compensation series resistance) refers total series resistance, including equivalent series resistance (ESR) capacitor, series resistance added externally, trace resistance Pulse-testing techniques used maintain virtual junction temperature close possible ambient temperature; thermal effects must taken into account separately.
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TPS7301Y electrical characteristics (CSR 25°C, shorted device leads (unless otherwise noted)
PARAMETER Reference voltage (measured Pass-element series resistance (See Note Note Note Note Output noise voltage RESET hysteresis RESET output input current Measured VO(FB) 2.13 IO(RESET) Note TEST CONDITIONS 1.182 0.83 0.52 0.32 0.23 µVrms µV/Hz UNIT
Input regulation
Output regulation
Ripple rejection Output noise-spectral density
refers total series resistance, including capacitor, series resistance added externally, trace resistance Pulse-testing techniques used maintain virtual junction temperature close possible ambient temperature; thermal effects must taken into account separately. Output voltage programmed with closed-loop configuration (see application information). NOTES: When simultaneously, pass element rDS(on) increases (see Figure point where resulting dropout voltage prevents regulator from maintaining specified tolerance range. calculate dropout voltage, equation: rDS(on) rDS(on) function both output current input voltage. parametric table lists rDS(on) which corresponds dropout conditions programmed output voltages respectively. other programmed values, refer Figure
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TPS7325Y electrical characteristics (CSR 25°C, SENSE shorted (unless otherwise noted)
PARAMETER Output voltage Dropout (2.97 VO)/IO, Output noise voltage 2.97 2.97 2.97 2.97 TEST CONDITIONS µVrms µV/Hz UNIT
Pass-element series Input regulation Output regulation Ripple rejection Output noise-spectral density
IO(RESET) 0.14 RESET output voltage refers total series resistance, including capacitor, series resistance added externally, trace resistance Pulse-testing techniques used maintain virtual junction temperature close possible ambient temperature; thermal effects must taken into account separately. Dropout test pass-element series resistance test production tested. Test method requires SENSE terminal disconnected from output voltage.
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TPS7330Y electrical characteristics (CSR 25°C, SENSE shorted (unless otherwise noted)
PARAMETER Output voltage (2.94 VO)/IO, Output noise voltage 2.94 2.94 2.94 2.94 TEST CONDITIONS µVrms µV/Hz UNIT
Dropout voltage
Pass-element series resistance Input regulation Output regulation Ripple rejection Output noise-spectral density
IO(RESET) 0.14 RESET output voltage refers total series resistance, including capacitor, series resistance added externally, trace resistance Pulse-testing techniques used maintain virtual junction temperature close possible ambient temperature; thermal effects must taken into account separately.
TPS7333Y electrical characteristics (CSR 25°C, SENSE shorted (unless otherwise noted)
PARAMETER Output voltage (3.23 VO)/IO, Output noise voltage RESET hysteresis voltage 3.23 3.23 3.23 3.23 TEST CONDITIONS 0.44 µVrms µV/Hz UNIT
Dropout voltage
Pass-element series resistance Input regulation Output regulation Ripple rejection Output noise-spectral density
IO(RESET) 0.17 RESET output voltage refers total series resistance, including capacitor, series resistance added externally, trace resistance Pulse-testing techniques used maintain virtual junction temperature close possible ambient temperature; thermal effects must taken into account separately.
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TPS7348Y electrical characteristics 5.85 (CSR 25°C, SENSE shorted (unless otherwise noted)
PARAMETER Output voltage (4.75 VO)/IO, 5.85 Output noise voltage RESET hysteresis voltage 4.75 4.75 4.75 4.75 5.85 5.85 TEST CONDITIONS 4.85 0.28 µVrms µV/Hz UNIT
Dropout voltage
Pass-element series resistance Input regulation Output regulation Ripple rejection Output noise-spectral density
IO(RESET) 4.12 RESET output voltage refers total series resistance, including capacitor, series resistance added externally, trace resistance Pulse-testing techniques used maintain virtual junction temperature close possible ambient temperature; thermal effects must taken into account separately.
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TPS7350Y electrical characteristics (CSR 25°C, SENSE shorted (unless otherwise noted)
PARAMETER Output voltage (4.88 VO)/IO, Output noise voltage RESET hysteresis voltage RESET output voltage IO(RESET) 4.25 4.88 4.88 4.88 4.88 TEST CONDITIONS 0.27 0.15 µVrms 0.35 µV/Hz UNIT
Dropout voltage
Pass-element series resistance Input regulation Output regulation Ripple rejection Output noise-spectral density
refers total series resistance, including capacitor, series resistance added externally, trace resistance Pulse-testing techniques used maintain virtual junction temperature close possible ambient temperature; thermal effects must taken into account separately.
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PARAMETER MEASUREMENT INFORMATION
VIT+ RESET SENSE TEST CIRCUIT VOLTAGE WAVEFORMS RESET RESET Timeout Delay Reset
Figure Test Circuit Voltage Waveforms
Load SENSE Ccer
Ceramic capacitor
Figure Test Circuit Typical Regions Stability (Refer Figures through
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TYPICAL CHARACTERISTICS Table Graphs
Output current Input voltage TPS7348 TPS7325 Free-air temperature Input voltage Free-air temperature Output current Free-air temperature TPS7301 Output current Free-air temperature Input voltage TPS7325 TPS7301 TPS7325 Output voltage TPS7330 TPS7333 TPS7348 TPS7350 Output voltage response from enable (EN) TPS7301 TPS7333 TPS7325 Load transient response TPS7348 TPS7350 TPS7301 TPS7333 TPS7348 TPS7350 Ripple rejection Output spectral noise density Frequency Frequency Output current Added ceramic capacitance Output current Added ceramic capacitance Input voltage Free-air temperature Free-air temperature Input voltage Free-air temperature Input voltage Output current Output current Output current Output current Output current Output current
Quiescent current Quiescent current Quiescent current Dropout voltage Change dropout voltage Dropout voltage Change output voltage Output voltage Output voltage Line regulation
Compensation series resistance (CSR)
rDS(on) VIT- IOL(RESET)
Pass-element resistance Minimum input voltage valid RESET Negative-going reset threshold RESET output current Reset time delay Distribution reset delay
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TYPICAL CHARACTERISTICS
QUIESCENT CURRENT OUTPUT CURRENT
Quiescent Current TPS7350, TPS7330, TPS7325, TPS7348, 5.85 25°C TPS73xx, Quiescent Current TPS7333 Output Current Input Voltage TPS7301 With Programmed TPS7348 TPS7350 25°C
QUIESCENT CURRENT INPUT VOLTAGE
TPS7333,
Figure
TPS7348 QUIESCENT CURRENT FREE-AIR TEMPERATURE
5.85 Quiescent Current
Figure
TPS7325 QUIESCENT CURRENT INPUT VOLTAGE
Quiescent Current
125°C 85°C 25°C -40°C
Free-Air Temperature Input Voltage
Figure
Figure
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TYPICAL CHARACTERISTICS
TPS7325 QUIESCENT CURRENT FREE-AIR TEMPERATURE
Quiescent Current Dropout Voltage 0.25 TPS7333 TPS7325 25°C TPS7330
DROPOUT VOLTAGE OUTPUT CURRENT
0.15
TPS7348
TPS7350
0.05
Output Current
Free-Air Temperature
Figure
Figure
TPS7301
CHANGE DROPOUT VOLTAGE FREE-AIR TEMPERATURE
VDO- Change Dropout Voltage Dropout Voltage 25°C
DROPOUT VOLTAGE OUTPUT CURRENT
9.65
Free-Air Temperature
Output Current
Figure
Figure
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TYPICAL CHARACTERISTICS
CHANGE OUTPUT VOLTAGE FREE-AIR TEMPERATURE
Free-Air Temperature VO(nom) Output Voltage TPS7348 25°C TPS7350
OUTPUT VOLTAGE INPUT VOLTAGE
Change Output Voltage
TPS7333 TPS7301 With Programmed TPS7325
Input Voltage
Figure
TPS7325
Figure
OUTPUT VOLTAGE INPUT VOLTAGE
25°C Output Voltage Change Output Voltage
LINE REGULATION
25°C
TPS7350 TPS7325 Input Voltage TPS7348
TPS7333
Input Voltage
Figure
Figure
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TYPICAL CHARACTERISTICS
TPS7301 TPS7325
OUTPUT VOLTAGE OUTPUT CURRENT
2.52 2.515 2.51 2.505 2.495 2.49 2.485 2.48 Output Current 25°C Programmed 2.52 2.515 Output Voltage 2.51 2.505 2.495
OUTPUT VOLTAGE OUTPUT CURRENT
Output Voltage
2.49 2.485 2.48 Output Current
Figure
TPS7330
Figure
TPS7333
OUTPUT VOLTAGE OUTPUT CURRENT
3.15 3.12 3.09 Output Voltage 3.06 3.03 2.97 2.94 2.91 2.88 2.85 3.27 3.26 Output Voltage 25°C 3.34 25°C 3.33 3.32 3.31 3.29 3.28
OUTPUT VOLTAGE OUTPUT CURRENT
Output Current
Output Current
Figure
Figure
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TYPICAL CHARACTERISTICS
TPS7348 TPS7350
OUTPUT VOLTAGE OUTPUT CURRENT
4.92 4.91 Output Voltage Output Voltage 4.89 4.88 4.87 4.86 4.85 4.84 4.83 4.82 4.81 5.85 25°C 5.06 5.05 5.04 5.03 5.02 5.01 4.99 4.98 4.97 4.96 4.95 4.94 Output Current 25°C
OUTPUT VOLTAGE OUTPUT CURRENT
Output Current
Figure
OUTPUT VOLTAGE RESPONSE FROM ENABLE (EN)
Output Voltage 25°C (CSR Input Capacitance VO(nom)
Figure
Voltage
Time
Figure
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TYPICAL CHARACTERISTICS
TPS7301 (WITH PROGRAMMED TPS7333 Change Output Voltage
LOAD TRANSIENT RESPONSE
25°C (CSR
Time
Figure
TPS7325
LOAD TRANSIENT RESPONSE
Change Output Voltage -150 -200 -300 -200 -100 25°C
Time
Figure
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Output Current
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION
TYPICAL CHARACTERISTICS
TPS7348 TPS7350 Change Output Voltage
LOAD TRANSIENT RESPONSE
25°C
Time
Figure
Change Output Voltage TPS7301 WITH PROGRAMMED
LINE TRANSIENT RESPONSE
25°C (CSR Input Voltage
6.25 5.75
Time
Figure
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Output Current
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION
TYPICAL CHARACTERISTICS
TPS7333 Change Output Voltage
LINE TRANSIENT RESPONSE
25°C (CSR 6.25 5.75 Input Voltage Input Voltage
Time
Figure
TPS7348 TPS7350 Change Output Voltage
LINE TRANSIENT RESPONSE
25°C (CSR 6.25 5.75
Time
Figure
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TYPICAL CHARACTERISTICS
RIPPLE REJECTION FREQUENCY
TPS7333 Ripple Rejection Output Spectral-Noise Density 25°C Input Capacitance Added (CSR TPS7301 With Programmed 25°C Input Capacitance Added (CSR (CSR
OUTPUT SPECTRAL-NOISE DENSITY FREQUENCY
TPS7348/ TPS7350
(CSR 0.01 Frequency
Frequency
Figure
TYPICAL REGIONS STABILITY
Figure
TYPICAL REGIONS STABILITY
COMPENSATION SERIES RESISTANCE (CSR) OUTPUT CURRENT
Compensation Series Resistance Region Instability Compensation Series Resistance
COMPENSATION SERIES RESISTANCE (CSR) ADDED CERAMIC CAPACITANCE
Region Instability 25°C Input Capacitor Added
25°C Added Ceramic Capacitance Input Capacitance Added Region Instability
Region Instability
0.01
0.01 Added Ceramic Capacitance
Output Current
Figure
Figure
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TYPICAL CHARACTERISTICS
TYPICAL REGIONS STABILITY TYPICAL REGIONS STABILITY
COMPENSATION SERIES RESISTANCE (CSR) OUTPUT CURRENT
Compensation Series Resistance Compensation Series Resistance Region Instability
COMPENSATION SERIES RESISTANCE (CSR) ADDED CERAMIC CAPACITANCE
Region Instability 25°C Input Capacitor Added
25°C Added Ceramic Capacitance Input Capacitor Added
Region Instability 0.01 Output Current
Region Instability 0.01 Added Ceramic Capacitance
Figure
PASS-ELEMENT RESISTANCE INPUT VOLTAGE
25°C VI(FB) 1.12 Minimum Input Voltage Valid RESET rDS(on) Pass-Element Resistance Input Voltage
Figure
MINIMUM INPUT VOLTAGE VALID RESET FREE-AIR TEMPERATURE
1.09
1.08
1.07
1.06
Figure
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1.05
Free-Air Temperature
Figure
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION
TYPICAL CHARACTERISTICS
NEGATIVE-GOING RESET THRESHOLD FREE-AIR TEMPERATURE
VIT- Negative-Going Reset Threshold RESET Output Current TPS7350 TPS7348 TPS7333 Input Voltage 25°C
RESET OUTPUT CURRENT INPUT VOLTAGE
Reset Delay Time
Percentage Units
Free-Air Temperature
Figure
RESET DELAY TIME FREE-AIR TEMPERATURE
Figure
DISTRIBUTION RESET DELAY
25°C Devices
Free-Air Temperature
Reset Delay Time
Figure
Figure
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THERMAL INFORMATION
response system-miniaturization trends, integrated circuits being offered low-profile fine-pitch surface-mount packages. Implementation many today's high-performance devices these packages requires special attention power dissipation. Many system-dependent issues such thermal coupling, airflow, added heat sinks convection surfaces, presence other heat-generating components affect power-dissipation limits given component. Three basic approaches enhancing thermal performance illustrated this discussion: Improving power-dissipation capability design Improving thermal coupling component Introducing airflow system Figure example thermally enhanced layout 20-lead TSSOP package. This layout involves adding copper conduct heat away from device. (thermal resistance, junction-to-ambient) this component board system illustrated Figure family curves illustrates effect increasing size copper-heat-sink surface area. standard board inch inch 0.062 inch); board traces heat sink area 1-oz (per square foot) copper. Figure shows thermal resistance same system with addition thermally-conductive compound between body TSSOP package copper routed directly beneath device. thermal conductivity compound used this analysis 0.815 Using these figures determine system allows maximum power-dissipation limit calculated with equation:
RJ(max) D(max)
qJA(system)
Where TJ(max) maximum allowable junction temperature; 150°C absolute maximum 125°C maximum recommended operating temperature specified operation. This limit should then applied internal power dissipated TPS73xx regulator. equation calculating total internal power dissipation TPS73xx D(total)
Because quiescent current TPS73xx family very low, second term negligible, further simplifying equation D(total)
20-lead TSSOP board system with thermally conductive compound between board device body, where 55°C, airflow /min, copper heat sink area cm2, maximum power-dissipation limit calculated. indicated Figure system 94°C/W; therefore, maximum power-dissipation limit
RJ(max) D(max)
qJA(system)
12594C
system implements TPS7348 regulator where internal power dissipation D(total)
4.85)
0.150
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THERMAL INFORMATION
Comparing PD(total) with PD(max) reveals that power dissipation this example does exceed maximum limit. When does, corrective actions taken. power-dissipation limit raised increasing either airflow heat-sink area. Alternatively, internal power dissipation regulator lowered reducing either input voltage load current. either case, above calculations should repeated with system parameters.
Copper Heat Sink
Figure Thermally Enhanced Layout (not scale) 20-Pin TSSOP
THERMAL RESISTANCE, JUNCTION-TO-AMBIENT FLOW
Flow /min Component /Board System 20-Lead TSSOP
Thermal Resistance, Junction-to-Ambient °C/W
THERMAL RESISTANCE, JUNCTION-TO-AMBIENT FLOW
Thermal Resistance, Junction-to-Ambient °C/W Flow /min Component /Board System 20-Lead TSSOP Includes Thermally Conductive Compound Between Body Board
Figure
Figure
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TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION
APPLICATION INFORMATION
TPS73xx series low-dropout (LDO) regulators overcome many shortcomings earlier generation LDOs, while adding features such power-saving shutdown mode supply-voltage supervisor. TPS73xx family includes five fixed-output voltage regulators: TPS7325 (2.5 TPS7330 TPS7333 (3.3 TPS7348 (4.85 TPS7350 family also offers adjustable device, TPS7301 (adjustable from 9.75
device operation
TPS73xx, unlike many other LDOs, features very quiescent currents that remain virtually constant even with varying loads. Conventional regulators pnp-pass element, base current which directly proportional load current through regulator IC/). Close examination data sheets reveals that such devices typically specified under near no-load conditions; actual operating currents much higher evidenced typical quiescent current versus load current curves (see Figure TPS73xx uses PMOS transistor pass current; because gate PMOS element voltage driven, operating currents invariable over full load range. TPS73xx specifications reflect actual performance under load. Another pitfall associated with pnp-pass element tendency saturate when device goes into dropout. resulting drop forces increase maintain load. During power-up, this translates large start-up currents. Systems with limited supply current fail start battery-powered systems, means rapid battery discharge when voltage decays below minimum required regulation. TPS73xx quiescent current remains even when regulator drops out, thus eliminating both problems. Included TPS73xx family 4.85-V regulator, TPS7348. Designed specifically cellular systems, 4.85-V output, regulated within allows operation within low-end limit systems specified tolerance; therefore, maximum regulated operating lifetime obtained from battery pack before device drops out, adding crucial talk minutes between charges. TPS73xx family also features shutdown mode that places output high-impedance state (essentially equal feedback-divider resistance) reduces quiescent current under When shutdown feature used, should tied ground. Response enable transition quick; regulated output voltage reestablished typically
minimum load requirements
TPS73xx family stable even zero load; minimum load required operation.
SENSE connection
SENSE terminal fixed-output devices must connected regulator output proper functioning regulator. Normally, this connection should short possible; however, connection made near critical circuit (remote sense) improve performance that point. Internally, SENSE connects high-impedance wide-bandwidth amplifier through resistor-divider network, noise pickup feeds through regulator output. essential route SENSE connection such minimize/avoid noise pickup. Adding network between SENSE filter noise recommended because cause regulator oscillate.
external capacitor requirements
input capacitor required; however, ceramic bypass capacitor (0.047 improves load transient response noise rejection when TPS73xx located more than inches from power supply. higher-capacitance electrolytic capacitor necessary large (hundreds milliamps) load transients with fast rise times anticipated.
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APPLICATION INFORMATION external capacitor requirements (continued)
with most regulators, TPS73xx family requires output capacitor stability. low-ESR 10-µF solid-tantalum capacitor connected from regulator output ground sufficient ensure stability over full load range (see Figure 42). Adding high-frequency ceramic film capacitors (such power-supply bypass capacitors digital analog ICs) cause regulator become unstable unless tantalum capacitor less than over temperature. Capacitors with published specifications such TPSD106M035R0300 Sprague 593D106X0035D2W work well because maximum 25°C (typically, solid-tantalum capacitors increases factor less when temperature drops from 25°C 40°C). Where component height and/or mounting area problem, physically smaller, 10-µF devices screened ESR. Figures through show stable regions operation using different values output capacitance with various values ceramic load capacitance. applications with little high-frequency bypass capacitance µF), output capacitance reduced provided maintained between Because capacitor minimum seldom ever specified, necessary 0.5- resistor series with capacitor limit maximum. shown graphs (Figures through 32), minimum problem when using 10-µF larger output capacitors. Below partial listing surface-mount capacitors usable with TPS73xx family. This information, along with graphs, included assist selection suitable capacitance user's application. When necessary achieve height requirements along with high output current and/or high ceramic load capacitance, several higher capacitors used parallel meet guidelines above. load temperature conditions with added ceramic load capacitance: PART T421C226M010AS 593D156X0025D2W 593D106X0035D2W MFR. Kemet Sprague Sprague VALUE VALUE VALUE SIZE SIZE SIZE
TPSD106M035R0300 PART 592D156X0020R2T 595D156X0025C2T 595D106X0025C2T 293D226X0016D2W PART 195D106X06R3V2T 195D106X0016X2T 595D156X0016B2T 695D226X0015F2T 695D156X0020F2T 695D106X0035G2T MFR. Sprague Sprague Sprague Sprague MFR. Sprague Sprague Sprague Sprague Sprague Sprague
Load ceramic load capacitance full temperature range:
Load ceramic load capacitance full temperature range:
Size maximum resistance 25°C. Listings sorted height.
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APPLICATION INFORMATION external capacitor requirements (continued)
TPS73xxPW SENSE RESET System Reset
TPS7333, TPS7348, TPS7350 (fixed-voltage options)
Figure Typical Application Circuit
programming TPS7301 adjustable regulator
Programming adjustable regulators accomplished using external resistor divider shown Figure equation governing output voltage
Vref
Where Vref reference voltage, 1.182
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APPLICATION INFORMATION
Resistors should chosen approximately 7-µA divider current. recommended value with adjusted desired output voltage. Smaller resistors used, offer inherent advantage consume more power. Larger values should avoided leakage currents will introduce error. Solving yields more useful equation choosing appropriate resistance:
OUTPUT VOLTAGE PROGRAMMING GUIDE System Reset OUTPUT VOLTAGE UNIT
TPS7301 <0.5 RESET
>2.7
Figure TPS7301 Adjustable Regulator Programming
undervoltage supervisor function
RESET output TPS73xx initiates reset microcomputer microprocessor systems event undervoltage condition. internal comparator TPS73xx monitors output voltage regulator detect undervoltage condition. When that occurs, RESET output transistor turns taking RESET signal low. power output voltage tracks input voltage. RESET output becomes active (low) approaches minimum required valid RESET signal (specified 25°C over full recommended operating temperature range). When output voltage reaches appropriate positive-going input threshold (VIT+), 200-ms (typical) timeout period begins during which RESET output remains low. Once timeout expired, RESET output becomes inactive. Since RESET output open-drain NMOS, pullup resistor should used ensure that logic-high signal indicated. supply-voltage-supervisor function also activated during power-down. input voltage decays after dropout voltage reached, output voltage tracks linearly with decaying input voltage. When output voltage drops below specified negative-going input threshold (VIT- electrical characteristics tables), RESET output becomes active (low). important note that input voltage decays below minimum required valid RESET, RESET undefined. Since circuit monitoring regulator output voltage, RESET output also triggered disabling regulator fault condition that causes output drop below VIT-. Examples fault conditions include short circuit output input voltage. Once output voltage reestablished, either reenabling regulator removing fault condition, then internal timer initiated, which holds RESET signal active during 200-ms (typical) timeout period.
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APPLICATION INFORMATION undervoltage supervisor function (continued)
Transient loads line pulses also cause reset occur proper care taken selecting input output capacitors. Load transients that faster than cause reset high-ESR output capacitors (greater than approximately used. 1-µs transient causes reset when using output capacitor with greater than ESR. Note that output-voltage spike during transient drop well below reset threshold still trip transient duration short. 1-µs transient must drop least below threshold before tripping reset circuit. 2-µs transient trips RESET just below threshold. Lower-ESR output capacitors help reducing drop output voltage during transient should used when fast transients expected.
NOTE: VIT+ +Hysteresis
output noise
TPS73xx very output noise, with spectral noise density This important when noise-susceptible systems, such audio amplifiers, powered regulator.
regulator protection
TPS73xx PMOS-pass transistor built-in back diode that safely conducts reverse currents when input voltage drops below output voltage (e.g., during power down). Current conducted from output input internally limited. extended reverse voltage anticipated, external limiting might appropriate. TPS73xx also features internal current limiting thermal protection. During normal operation, TPS73xx limits output current approximately When current limiting engages, output voltage scales back linearly until overcurrent condition ends. While current limiting designed prevent gross device failure, care should taken exceed power dissipation ratings package. temperature device exceeds 165°C, thermal-protection circuitry shuts down. Once device cooled, regulator operation resumes.
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MECHANICAL DATA
(R-PDSO-G**)
SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 0.008 (0,20) 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) 0.010 (0,25)
Gage Plane
0.010 (0,25) 0.044 (1,12) 0.016 (0,40)
Seating Plane 0.069 (1,75) 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS
0.197 (5,00) 0.189 (4,80)
0.344 (8,75) 0.337 (8,55)
0.394 (10,00) 0.386 (9,80) 4040047 10/96
NOTES:
linear dimensions inches (millimeters). This drawing subject change without notice. Body dimensions include mold flash protrusion, exceed 0.006 (0,15). Falls within JEDEC MS-012
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MECHANICAL DATA
(R-PDIP-T8)
0.400 (10,60) 0.355 (9,02)
PLASTIC DUAL-IN-LINE PACKAGE
0.260 (6,60) 0.240 (6,10)
0.070 (1,78) 0.020 (0,51) 0.310 (7,87) 0.290 (7,37)
0.200 (5,08) Seating Plane 0.125 (3,18)
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) 0.010 (0,25)
4040082 03/95 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Falls within JEDEC MS-001
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MECHANICAL DATA
(R-PDSO-G**)
SHOWN 0,30 0,19
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,10
0,15 4,50 4,30 6,60 6,20 Gage Plane 0,25 0,75 0,50
Seating Plane 1,20 0,15 0,05 0,10
PINS
3,10
5,10
5,10
6,60
7,90
9,80
2,90
4,90
4,90
6,40
7,70
9,60 4040064 08/96
NOTES:
linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0,15. Falls within JEDEC MO-153
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PACKAGING INFORMATION
Orderable Device TPS7301QD TPS7301QDG4 TPS7301QDR TPS7301QDRG4 TPS7301QP TPS7301QPE4 TPS7301QPW TPS7301QPWG4 TPS7301QPWLE TPS7301QPWR TPS7301QPWRG4 TPS7325QD TPS7325QDR TPS7325QDRG4 TPS7325QP TPS7325QPE4 TPS7325QPW TPS7325QPWR TPS7330QD TPS7330QDG4 TPS7330QDR TPS7330QDRG4 TPS7330QP TPS7330QPE4 TPS7330QPW Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type SOIC SOIC SOIC SOIC PDIP PDIP TSSOP TSSOP TSSOP TSSOP TSSOP SOIC SOIC SOIC PDIP PDIP TSSOP TSSOP SOIC SOIC SOIC SOIC PDIP PDIP TSSOP Package Drawing Pins Package Plan Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS Sb/Br) Lead/Ball Finish NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU Call NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU Peak Temp Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Type Type Level-1-260C-UNLIM Level-1-260C-UNLIM Call Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Type Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Type Type Level-1-260C-UNLIM
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Orderable Device TPS7330QPWR TPS7333QD TPS7333QDG4 TPS7333QDR TPS7333QDRG4 TPS7333QP TPS7333QPE4 TPS7333QPW TPS7333QPWG4 TPS7333QPWLE TPS7333QPWR TPS7333QPWRG4 TPS7348QD TPS7348QDR TPS7348QDRG4 TPS7348QP TPS7348QPE4 TPS7348QPW TPS7348QPWG4 TPS7348QPWLE TPS7348QPWR TPS7348QPWRG4 TPS7350QD TPS7350QDG4 TPS7350QDR TPS7350QDRG4 TPS7350QP
Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type TSSOP SOIC SOIC SOIC SOIC PDIP PDIP TSSOP TSSOP TSSOP TSSOP TSSOP SOIC SOIC SOIC PDIP PDIP TSSOP TSSOP TSSOP TSSOP TSSOP SOIC SOIC SOIC SOIC PDIP
Package Drawing
Pins Package Plan Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Pb-Free
Lead/Ball Finish NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU Call NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU Call NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU
Peak Temp Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Type Type Level-1-260C-UNLIM Level-1-260C-UNLIM Call Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Type Type Level-1-260C-UNLIM Level-1-260C-UNLIM Call Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Type
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Orderable Device
Status
Package Type PDIP TSSOP TSSOP TSSOP TSSOP
Package Drawing
Pins Package Plan (RoHS) Pb-Free (RoHS) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
Lead/Ball Finish
Peak Temp
TPS7350QPE4 TPS7350QPW TPS7350QPWLE TPS7350QPWR TPS7350QPWRG4
ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE
NIPDAU NIPDAU Call NIPDAU NIPDAU
Type Level-1-260C-UNLIM Call Level-1-260C-UNLIM Level-1-260C-UNLIM
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
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