SLAS482A AUGUST 2005 REVISED NOVEMBER 2005 WIDE-INPUT SYNCHRONOUS
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TPS40054-Q1, TPS40055-Q1, TPS40057-Q1
SLAS482A AUGUST 2005 REVISED NOVEMBER 2005
WIDE-INPUT SYNCHRONOUS BUCK CONTROLLER
FEATURES
Qualified Automotive Applications Customer-Specific Configuration Control Supported Along With Major-Change Approval Operating Input Voltage Input Voltage Feed-Forward Compensation Internal 0.7-V Reference Programmable Fixed-Frequency 1-MHz Voltage Mode Controller Internal Gate Drive Outputs High-Side Synchronous N-Channel MOSFETs 16-Pin PowerPADPackage 25°C/W) Thermal Shutdown Externally Synchronizable Programmable High-Side Sense Short-Circuit Protection Programmable Closed-Loop Soft-Start TPS40054 Source Only (Product Preview) TPS40055 Source/Sink (Product Preview) TPS40057 Source/Sink With VOUT Prebias
DESCRIPTION
TPS4005x family high-voltage, wide input synchronous, step-down converters. TPS4005x family offers design flexibility with variety user programmable functions, including soft-start, UVLO, operating frequency, voltage feed-forward, high-side current limit, loop compensation. TPS4005x also synchronizable external supply. TPS4005x incorporates MOSFET gate drivers external N-channel high-side synchronous rectifier (SR) MOSFETs. Gate drive logic incorporates anti-cross conduction circuitry prevent simultaneous high-side synchronous rectifier conduction. TPS4005x uses voltage feed-forward control techniques provide good line regulation over wide (4:1) input voltage range fast response input line transients with near constant gain with input variation which eases loop compensation. externally programmable current limit provides pulse-by-pulse current limit, well hiccup mode operation utilizing internal fault counter longer duration overloads.
APPLICATIONS
Power Modules Networking/Telecom Industrial/Servers Automotive Telematics
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. PowerPAD trademark Texas Instruments.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2005, Texas Instruments Incorporated
TPS40054-Q1, TPS40055-Q1, TPS40057-Q1
SLAS482A AUGUST 2005 REVISED NOVEMBER 2005
SIMPLIFIED APPLICATION DIAGRAM
TPS4005xPWP SYNC SGND SS/SD COMP ILIM BOOST HDRV BP10 LDRV PGND
ORDERING INFORMATION
-40°C 125°C APPLICATION SOURCE SOURCE/SINK SOURCE/SINK with prebias Application Information section. Product Preview PACKAGE Plastic HTSSOP (PWP) Plastic HTSSOP (PWP) Plastic HTSSOP (PWP) PART NUMBER TPS40054QPWPRQ1 TPS40055QPWPRQ1 TPS40057QPWPRQ1
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE UNIT VFB, SYNC Input voltage range transient KFF, with IIN(max) VOUT IOUT Tstg Output voltage range Input current Output current Storage temperature Lead temperature (1/16 inch) from case seconds COMP, -0.3 -0.3 -2.5 -0.3 -0.3 -55°C 140°C -55°C 150°C 260°C
Operating junction temperature range
Stresses beyond those listed under absolute maximum ratings cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under recommended operating conditions implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. Long-term high-temperature storage and/or extended maximum recommended operating conditions result overall device life. http://www.ti.com/ep_quality additional information enhanced plastic packaging.
RECOMMENDED OPERATING CONDITIONS
Input voltage Operating junction temperature UNIT
TPS40054-Q1, TPS40055-Q1, TPS40057-Q1
SLAS482A AUGUST 2005 REVISED NOVEMBER 2005
ELECTRICAL CHARACTERISTICS
-40°C 125°C, Vdc, 90.9 IKFF kHz, parameters zero power dissipation (unless otherwise noted)
PARAMETER INPUT SUPPLY VBP5 fOSC VRAMP ISYNC Output voltage Accuracy ramp voltage High-level input voltage, SYNC Low-level input voltage, SYNC Input current, SYNC Pulse width, SYNC voltage Maximum duty cycle Minimum duty cycle VKFF IKFF tDSCH BP10 VBP10 Output voltage IOUT 25°C AVOL IBIAS ISINK Feedback input voltage Gain bandwidth Open loop gain High-level output source current Low-level output source current High-level output voltage Low-level output voltage Input bias current Current limit sink current Propagation delay output Switch leading-edge blanking pulse time VILIM 23.7 (VILIM- VILIM 23.7 (VILIM- ISOURCE ISINK 125°C -40°C 125°C 0.698 0.689 0.689 1.85 1.95 0.37 12.2 10.45 0.704 0.717 0.719 ERROR AMPLIFIER Feed-forward voltage Feed-forward current operating Soft-start source current Soft-start clamp voltage Discharge time Soft-start time range 0.75 3.35 2.35 3.48 2.37 1200 2.59 IOUT VPEAK- VVAL OSCILLATOR/RAMP GENERATOR Input voltage range Quiescent current Output drivers switching, 0.75 OPERATING CURRENT TEST CONDITIONS UNIT
SOFT START
CURRENT LIMIT
IKFF increases with SYNC frequency, IKFF decreases with maximum duty cycle. Ensured design. production tested.
TPS40054-Q1, TPS40055-Q1, TPS40057-Q1
SLAS482A AUGUST 2005 REVISED NOVEMBER 2005
ELECTRICAL CHARACTERISTICS (continued)
-40°C 125°C, Vdc, 90.9 IKFF kHz, parameters zero power dissipation (unless otherwise noted)
PARAMETER tOFF time during fault VILIM 23.6 25°C VILIM 23.6 125°C Offset voltage ILIM VILIM 23.6 -40°C 125°C VILIM 11.6 25°C VILIM 11.6 125°C VILIM 11.6 -40°C 125°C OUTPUT DRIVER tLRISE tLFALL tHRISE tHFALL Low-side driver rise time Low-side driver fall time High-side driver rise time High-side driver fall time High-level output voltage, HDRV Low-level output voltage, HDRV High-level output voltage, LDRV Low-level output voltage, LDRV Minimum controllable pulse width SS/SD SHUTDOWN VBOOST ILEAK Shutdown threshold voltage Device active threshold voltage Output voltage Switch voltage Leakage current Shutdown temperature Hysteresis programmable threshold voltage UVLO, fixed UVLO, hysteresis Ensured design. production tested. RKFF 28.7 6.85 7.05 0.46 7.95 LDRV output Outputs 30.8 32.2 33.9 CLOAD 2200 CLOAD 2200 (HDRV IHDRV -0.1 (HDRV IHDRV (HDRV ILDRV -0.1 ILDRV BP10 -1.8 BP10 BOOST BOOST -1.9 0.85 -120 -155 -155 -140 -165 -165 TEST CONDITIONS UNIT cycle
BOOST REGULATOR RECTIFIER ZERO CURRENT COMPARATOR (TPS40054 ONLY) NODE THERMAL SHUTDOWN UVLO VUVLO
TPS40054-Q1, TPS40055-Q1, TPS40057-Q1
SLAS482A AUGUST 2005 REVISED NOVEMBER 2005
TYPICAL CHARACTERISTICS
OFFSET VOLTAGE (VLIM TEMPERATURE
Offset Voltage (VLIM
VLim 23.6 VLim 11.6 -100
-120
Temperature
Figure
DEVICE INFORMATION
PACKAGE(1)(2) (TOP VIEW)
SYNC SGND SS/SD COMP
THERMAL
ILIM BOOST HDRV BP10 LDRV PGND
more information package, Texas Instruments Technical Brief (SLMA002) PowerPAD heat slug must connected SGND (pin electrically isolated from other pins.
TERMINAL FUNCTIONS
TERMINAL NAME BOOST BP10 COMP HDRV DESCRIPTION Gate drive voltage high side N-channel MOSFET. BOOST voltage greater than input voltage. 0.1-µF ceramic capacitor should connected from this drain lower MOSFET. reference. This should bypassed ground with 0.1-µF ceramic capacitor. This used with external load less. 10-V reference used gate drive N-channel synchronous rectifier. This should bypassed 1-µF ceramic capacitor. This used with external load less. Output error amplifier, input comparator. feedback network connected from this compensate overall loop. COMP internally clamped above peak ramp improve large signal transient response. Floating gate drive high-side N-channel MOSFET. This switches from BOOST (MOSFET (MOSFET off).
TPS40054-Q1, TPS40055-Q1, TPS40057-Q1
SLAS482A AUGUST 2005 REVISED NOVEMBER 2005
DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS (continued)
TERMINAL NAME ILIM LDRV PGND SGND DESCRIPTION Current limit used overcurrent threshold. internal current sink from this ground sets voltage drop across external resistor connected from this VCC. voltage this compared voltage drop (VIN -SW) across high side MOSFET during conduction. resistor connected from this program amount voltage feed-forward. current into this internally divided used control slope ramp. Gate drive N-channel synchronous rectifier. This switches from BP10 (MOSFET ground (MOSFET off). Power ground reference device. There should low-impedance path from this source(s) lower MOSFET(s). resistor connected from this ground internal oscillator switching frequency. Signal ground reference device Soft-start programming pin. capacitor connected from this ground programs soft-start time. capacitor charged with internal current source resulting voltage ramp used second non-inverting input error amplifier. output voltage begins rise when VSS/SD approximately 0.85 output continues rise reaches regulation when VSS/SD approximately 1.55 controller considered shut down when VSS/SD less. internal circuitry inactive. internal circuitry enabled when VSS/SD greater. When VSS/SD less than approximately 0.85 outputs cease switching output voltage (VOUT) decays while internal circuitry remains active. This connected switched node converter used overcurrent sensing. TPS40054 TPS40057 versions this zero current sensing well. Synchronization input device. This used synchronize oscillator external master frequency. synchronization used, connect this SGND. Inverting input error amplifier. normal operation, voltage this equal internal reference voltage, Supply voltage device
SS/SD
SYNC
TPS40054-Q1, TPS40055-Q1, TPS40057-Q1
SLAS482A AUGUST 2005 REVISED NOVEMBER 2005
SIMPLIFIED BLOCK DIAGRAM
ILIM 10-V Regulator BP10 BP10
Clock Oscillator
VREF
BOOST
SYNC
Ramp Generator
Reference Voltages VREF VREF
VREF7
COMP VREF SS/SD VREF Fault
Restart SGND
3-bit up/down Fault Counter BP10 Zero Current Detector (TPS40054 Only) PGND N-channel Driver BPN10 HDRV Restart Fault N-channel Driver LDRV
UDG-05007
TPS40054-Q1, TPS40055-Q1, TPS40057-Q1
SLAS482A AUGUST 2005 REVISED NOVEMBER 2005
APPLICATION INFORMATION
TPS40054/55/57 family parts allows user optimize controller specific application. TPS40055 controller choice synchronous buck designs, which includes most applications. quadrant operations will source sink output current. This provides best transient response. TPS40054 operates quadrant sources output current only, allowing paralleling converters ensures that converter does sink current from another converter. This controller also emulates standard buck converter light loads where inductor current goes discontinuous. continuous output inductor currents, controller operates synchronous buck converter optimize efficiency. TPS40057 operates quadrant standard buck converter during start After output reached regulation point, controller operates quadrant modes synchronous buck configuration. This useful applications that have output voltage prebiased some voltage before controller enabled. When TPS40057 controller enabled does sink current during start which would pull current from prebiased voltage supply.
SETTING SWITCHING FREQUENCY (PROGRAMMING CLOCK OSCILLATOR)
TPS4005x independent clock oscillator ramp generator circuits. clock oscillator serves master clock ramp generator circuit. switching frequency, kHz, clock oscillator single resistor ground. clock frequency related Equation relationship charted Figure
17.82
PROGRAMMING RAMP GENERATOR CIRCUIT
ramp generator circuit provides actual ramp used comparator. ramp generator provides voltage feed-forward control varying ramp slope with line voltage, while maintaining constant ramp magnitude. Varying ramp directly with line voltage provides excellent response line variations since does have wait loop delays before changing duty cycle. (See Figure
RAMP COMP
UDG-02131
Figure Voltage Feed-Forward Effect Duty Cycle ramp must faster than master clock frequency prevented from starting. ramp time programmed single resistor RKFF) pulled VIN. RKFF related minimum input voltage (VIN(min)) through following:
TPS40054-Q1, TPS40055-Q1, TPS40057-Q1
SLAS482A AUGUST 2005 REVISED NOVEMBER 2005
APPLICATION INFORMATION (continued)
(min) 58.14 1340
where: VIN(min) ensured minimum start-up voltage. actual start-up voltage nominally about lower 25°C. timing resistance curve showing RKFF required given switching frequency (fSW) shown Figure input voltage high duty cycle applications, voltage feed-forward limit duty cycle prematurely. This does occur most applications. voltage control loop controls duty cycle regulates output voltage. more information large duty cycle operation, application note (SLUA310).
SWITCHING FREQUENCY TIMING RESISTANCE
RKFF Feed-Forward Impedance
FEED-FORWARD IMPEDANCE SWITCHING FREQUENCY
Timing Resistance
1000
1000
Switching Frequency
Switching Frequency
Figure
Figure
UVLO OPERATION
TPS4005x uses variable (user programmable) UVLO protection. UVLO circuit holds soft-start until input voltage exceeded user programmable undervoltage threshold. TPS4005x uses feed-forward pin, KFF, user programmable low-line UVLO detection. This variable low-line TPS4005x uses variable (user programmable) UVLO protection. UVLO circuit holds soft-start until input voltage exceeded user programmable undervoltage threshold. UVLO threshold compares ramp duration oscillator clock period. undervoltage condition exists TPS4005x receives clock pulse before ramp reached full amplitude. ramp duration function ramp slope, which directly related current into pin. current function input voltage resistance from input voltage. resistor referenced oscillator frequency described Equation
(min) 58.14 1340
where: desired start-up (UVLO) input voltage
TPS40054-Q1, TPS40055-Q1, TPS40057-Q1
SLAS482A AUGUST 2005 REVISED NOVEMBER 2005
APPLICATION INFORMATION (continued)
timing resistance variable UVLO function uses 3-bit full adder prevent spurious shut-downs turn-ons spikes fast line transients. When adder reaches total seven counts which ramp duration shorter than clock cycle power-good signal asserted soft-start initiated upper lower MOSFETS turned off. Once soft-start initiated, UVLO circuit must total count seven cycles which ramp duration longer than clock cycle before undervoltage condition declared. (See Figure
UVLO Threshold
Clock RAMP
PowerGood
Figure Undervoltage Lockout Operation tolerance UVLO point also affects maximum duty cycle achievable. UVLO starts device below nominal start voltage, maximum duty cycle reduced approximately nominal start voltage. impedance input voltage cause input voltage, controller, when converter starts operate draw current from input source. Therefore, there voltage hysteresis that prevents nuisance shutdowns UVLO point. With chosen select operating frequency RKFF chosen select start-up voltage, approximate amount hysteresis voltage shown Figure
TPS40054-Q1, TPS40055-Q1, TPS40057-Q1
SLAS482A AUGUST 2005 REVISED NOVEMBER 2005
APPLICATION INFORMATION (continued)
UNDERVOLTAGE LOCKOUT THRESHOLD HYSTERESIS
VUVLO Hysteresis
VUVLO Undevoltage Lockout Threshold
Figure
BP10 INTERNAL VOLTAGE REGULATORS
Start-up characteristics BP10 regulators over different temperature ranges shown Figure Figure Slight variations occurs dependent upon switching frequency. Variation BP10 regulation characteristics also based load presented switching external MOSFETs.
TPS40054-Q1, TPS40055-Q1, TPS40057-Q1
SLAS482A AUGUST 2005 REVISED NOVEMBER 2005
APPLICATION INFORMATION (continued)
INPUT VOLTAGE VOLTAGE INPUT VOLTAGE BP10 VOLTAGE
110°C VBP10 BP10 Voltage VBP5 Voltage
-55°C
110°C 25°C
25°C
-55°C
VIN- Input Voltage
Figure
VIN- Input Voltage
Figure
SELECTING INDUCTOR VALUE
inductor value determines magnitude ripple current output capacitors well load current which converter enters discontinuous mode. large inductance results lower ripple current physically larger same load current. small inductance results larger ripple currents greater number more expensive output capacitors for) same output ripple voltage requirement. good compromise select inductance value such that converter does enter discontinuous mode until load approximated somewhere between rated output. inductance value described Equation
(Henries)
where: output voltage peak-to-peak inductor current
CALCULATING OUTPUT CAPACITANCE
output capacitance depends output ripple voltage requirement, output ripple current, well output voltage deviation requirement during load transient. output ripple voltage function both output capacitance capacitor ESR. worst case output ripple described Equation
VP*P
output ripple voltage typically between component.
TPS40054-Q1, TPS40055-Q1, TPS40057-Q1
SLAS482A AUGUST 2005 REVISED NOVEMBER 2005
APPLICATION INFORMATION (continued)
output capacitance requirement typically increases presence load transient requirement. During step load, output capacitance must provide energy load (light-to-heavy load step) absorb excess inductor energy (heavy-to-light load step) while maintaining output voltage within acceptable limits. amount capacitance depends magnitude load step, speed loop size inductor. Stepping load from heavy load light load results output overshoot. Excess energy stored inductor must absorbed output capacitance. energy stored inductor described Equation (Joules) where:
(Amperes)
output current under heavy load conditions output current under light load conditions Some applications require additional circuit prevent false restarts UVLO voltage level. This applies applications which have high impedance input voltage line which have excessive ringing line. input voltage impedance cause input voltage enough start-up cause UVLO shutdown subsequent restart. Excessive ringing also affect voltage seen device cause UVLO shutdown restart. simple external circuit provides selectable amount hysteresis prevent nuisance UVLO shutdown. Assuming hysteresis current IKFF peak detector charges VIN(min) value calculated Equation using RKFF 71.5 RKFF 3.5) IN(min)
chosen maintain peak voltage between switching cycles. keep capacitor charge from drooping from 3.5) value calculate less than some standard value works adequately. diode small signal switching diode Schottky rated more then Figure illustrates typical implementation using small switching diode. tolerance UVLO point also affects maximum duty cycle achievable. UVLO starts device below nominal start voltage, maximum duty cycle reduced approximately nominal start voltage.
TPS40054-Q1, TPS40055-Q1, TPS40057-Q1
SLAS482A AUGUST 2005 REVISED NOVEMBER 2005
APPLICATION INFORMATION (continued)
RKFF 71.5 SYNC SGND COMP ILIM BOOST HDRV BP10 LDRV PGND 1N914, 1N4150 Type Signal Diode
UDG-03034
Figure Hysteresis Programmable UVLO Energy capacitor described Equation (Joules) where:
(10)
Volts2
(11)
where: final peak capacitor voltage initial capacitor voltage Substituting Equation into Equation then substituting Equation into Equation then setting Equation equal Equation then solving yields capacitance described Equation
(Farads)
(12)
PROGRAMMING SOFT START
TPS4005x uses closed-loop approach ensure controlled ramp output during start-up. Soft-start programmed charging external capacitor CSS) internally generated current source. voltage minus 0.85 into separate non-inverting input error amplifier addition 0.7-V VREF). loop closed lower CSS- 0.85 voltage internal reference voltage (0.7-V VREF). Once CSS- 0.85 voltage rises above internal reference voltage, regulation based internal reference. ensure controlled ramp-up output voltage soft-start time should greater than L-CO time constant described Equation
TPS40054-Q1, TPS40055-Q1, TPS40057-Q1
SLAS482A AUGUST 2005 REVISED NOVEMBER 2005
APPLICATION INFORMATION (continued)
START (seconds)
(13)
There direct correlation between tSTART input current required during start-up. faster tSTART, higher input current required during start-up. This relationship describe more detail section titled, Programming Current Limit which follows. soft-start capacitance, CSS, described Equation START (Farads) (14) applications which supply ramps slowly, (typically between necessary increase soft-start time between approximately prevent nuisance UVLO tripping. soft-start time should longer than time that supply transitions between
PROGRAMMING CURRENT LIMIT
TPS4005x uses two-tier approach overcurrent protection. first tier pulse-by-pulse protection scheme. Current limit implemented high-side MOSFET sensing voltage drop across MOSFET when gate driven high. MOSFET voltage compared voltage dropped across resistor connected from ILIM when driven constant current sink. voltage drop across MOSFET exceeds voltage drop across ILIM resistor, switching pulse immediately terminated. MOSFET remains until next switching cycle initiated. second tier consists fault counter. fault counter incremented overcurrent pulse decremented clock cycle without overcurrent pulse. When counter reaches seven, restart issued seven soft-start cycles initiated. Both upper lower MOSFETs turned during this period. counter decremented each soft-start cycle. When counter decremented zero, re-enabled. fault been removed output starts normally. output still present, counter counts seven overcurrent pulses re-enters second-tier fault mode. Figure typical overcurrent protection waveforms. minimum current limit setpoint (ILIM) depends tSTART, load current turn-on (IL).
START (Amperes)
(15)
HDRV
CLOCK tBLANKING VILIM VVIN-VSW
CURRENT LIMIT TRIPS (HDRV CYCLE TERMINATED CURRENT LIMIT TRIP)
SOFT-START CYCLES
UDG-02136
Figure Typical Current Limit Protection Waveforms
TPS40054-Q1, TPS40055-Q1, TPS40057-Q1
SLAS482A AUGUST 2005 REVISED NOVEMBER 2005
APPLICATION INFORMATION (continued)
current limit programming resistor RILIM) calculated using Equation Care must taken choosing values used ISINK equation. order assure output current overcurrent level, minimum value ISINK maximum value must used. RDS(on)[max] ILIM SINK SINK (16) where: ISINK current into ILIM minimum overcurrent setpoint which output current plus one-half peak inductor current overcurrent comparator offset maximum
SYNCHRONIZING EXTERNAL SUPPLY
TPS4005x synchronized external clock through SYNC pin. Synchronization occurs falling edge SYNC signal. synchronization frequency should range higher than programmed free-run frequency. clock frequency SYNC replaces master clock generated oscillator circuit. Pulling SYNC programs TPS4005x freely frequency programmed higher synchronization must factored when programming ramp generator circuit. ramp interrupted SYNC pulse, UVLO condition declared becomes disabled. Typically this concern under low-line conditions only. case, RKFF needs adjusted higher switching frequency. order specify correct value RKFF synchronizing frequency, calculate dummy value that would cause oscillator synchronizing frequency. this value design.
T(dummy) SYNC 17.82
(17)
value RT(dummy) calculate value RKFF.
VIN(min) 58.14 RT(dummy) 1340
(18)
This value RKFF ensures that UVLO engaged when operating synchronization frequency. RT(dummy)
Loop Compensation
Voltage-mode buck-type converters typically compensated using Type networks. Since TPS4005x uses voltage feedforward control, gain modulator with voltage feedforward circuit must included. modulator gain described Figure with being minimum input voltage required cause ramp excursion cover entire switching period described Equation MOD(dB)
(19)
Duty cycle varies from control voltage )VC) varies from minimum ramp voltage maximum ramp voltage (VS). Also, synchronous buck converter, VIN. control voltage output voltage modulator gain terms input voltage ramp voltage: (20) Calculate Poles Zeros buck converter using voltage mode control, there double pole output L-CO. double pole located frequency calculated Equation
TPS40054-Q1, TPS40055-Q1, TPS40057-Q1
SLAS482A AUGUST 2005 REVISED NOVEMBER 2005
APPLICATION INFORMATION (continued)
(Hertz)
(21)
There also zero created output capacitance associated ESR. zero located frequency calculated Equation (Hertz) (22) Calculate value RBIAS output voltage (VOUT). BIAS VOUT maximum crossover frequency loop gain) calculated Equation (Hertz)
(23)
(24)
Typically, selected close midpoint between L-CO double pole zero. this frequency, control output gain slope (-40 dB/decade), while Type topology slope dB/decade), resulting overall closed loop slope (-20 dB/decade). Figure shows modulator gain, filter, output capacitor zero, resulting response compensated.
MODULATOR RELATIONSHIPS
MODULATOR GAIN SWITCHING FREQUENCY
Zero,
AMOD Modulator Gain
Resultant,
Filter,
Switching Frequency
Figure
Figure
Type topology, shown Figure zero-pole pairs addition pole origin. gain phase boost Type topology shown Figure zeros used compensate L-CO double pole provide phase boost. double pole used compensate zero provide controlled gain roll-off. many cases, second pole eliminated amplifier's gain roll-off used roll-off overall gain higher frequencies. Figure
TPS40054-Q1, TPS40055-Q1, TPS40057-Q1
SLAS482A AUGUST 2005 REVISED NOVEMBER 2005
APPLICATION INFORMATION (continued)
(optional) GAIN -90° VOUT RBIAS COMP -270° 180° PHASE
VREF
UDG-02189
Figure Type Compensation Configuration
Figure Type Compensation Gain Phase
poles zeros Type network described Equation (Hertz) (Hertz)
(Hertz) (Hertz)
(25)
value somewhat arbitrary, influences other component values. value between usually yields reasonable values. unity gain frequency described Equation (Hertz) where reciprocal modulator gain modulator gain function frequency described Equation
AMOD(f) AMOD
(26)
AMOD(f)
(27)
Minimum Load Resistance Care must taken load down output error amplifier with feedback resistor, that small. error amplifier finite output source sink current, which must considered when sizing small value does allow output swing over full range. (max) (MIN) 1750 SOURCE (min)
(28)
CALCULATING BOOST BP10 BYPASS CAPACITOR
BOOST capacitance provides local, impedance source high-side driver. BOOST capacitor should good quality, high-frequency capacitor. size bypass capacitor depends total gate charge MOSFET amount droop allowed bypass capacitor. BOOST capacitance described Equation BOOST (Farads) (29) 10-V reference pin, BP10V provides energy both synchronous MOSFET high-side MOSFET BOOST capacitor. Neglecting efficiency penalty, BP10V capacitance described Equation
TPS40054-Q1, TPS40055-Q1, TPS40057-Q1
SLAS482A AUGUST 2005 REVISED NOVEMBER 2005
APPLICATION INFORMATION (continued)
BP10 (Farads)
(30)
dv/dt INDUCED TURN-ON
MOSFETs susceptible dv/dt turn-on particularly high-voltage (VDS) applications. turn-on caused capacitor divider that formed CGS. High dv/dt conditions drain-to-source voltage, MOSFET causes current flow through causes gate-to-source voltage rise. gate-to-source voltage rises above MOSFET threshold voltage, MOSFET turns resulting large shoot-through currents. Therefore, MOSFET should chosen that capacitance smaller than capacitance.
HIGH SIDE MOSFET POWER DISSIPATION
power dissipated external high-side MOSFET comprised conduction switching losses. conduction losses function IRMS current through MOSFET RDS(on) MOSFET. high-side MOSFET conduction losses defined Equation
COND
DS(on)
(Watts)
(31)
where: temperature coefficient MOSFET RDS(on) varies depending MOSFET technology manufacturer, typically ranges between 0.0035 ppm/°C 0.010 ppm/°C. IRMS current high side MOSFET described Equation
ARMS
(32)
switching losses high-side MOSFET described Equation SW(fsw) (Watts) where: dc-output current switching rise time, typically switching frequency Typical switching waveforms shown Figure
(33)
TPS40054-Q1, TPS40055-Q1, TPS40057-Q1
SLAS482A AUGUST 2005 REVISED NOVEMBER 2005
APPLICATION INFORMATION (continued)
BODY DIODE CONDUCTION BODY DIODE CONDUCTION
ANTI-CROSS CONDUCTION
SYNCHRONOUS RECTIFIER
HIGH SIDE
UDG-02139
Figure Inductor Current Node Waveforms maximum allowable power dissipation MOSFET determined Equation
(Watts)
(34)
where: PCOND PSW(fsw) (Watts) package thermal impedance.
(35)
SYNCHRONOUS RECTIFIER MOSFET POWER DISSIPATION
power dissipated synchronous rectifier MOSFET comprised three components: RDS(on) conduction losses, body diode conduction losses, reverse recovery losses. RDS(on) conduction losses found using Equation current through synchronous rectifier MOSFET described Equation
Amperes
(36)
body-diode conduction losses forward conduction body diode during anti-cross conduction delay time. body diode conduction losses described Equation DELAY (Watts) (37) where: body diode forward voltage tDELAY delay time just before node rises 2-multiplier used because body diode conducts twice during each cycle (once rising edge once falling edge). reverse recovery losses time takes body diode recovery from forward bias reverse blocking state. reverse recovery losses described Equation (Watts) (38) where: reverse recovery charge body diode always described MOSFET's data sheet, obtained from MOSFET vendor. total synchronous rectifier MOSFET power dissipation described Equation
TPS40054-Q1, TPS40055-Q1, TPS40057-Q1
SLAS482A AUGUST 2005 REVISED NOVEMBER 2005
APPLICATION INFORMATION (continued)
PCOND (Watts)
(39)
TPS4005x POWER DISSIPATION
power dissipation TPS4005x largely dependent MOSFET driver currents input voltage. driver current proportional total gate charge, external MOSFETs. Driver power (neglecting external gate resistance, refer calculated from Equation (Watts driver) (40) total power dissipation TPS4005x, assuming same MOSFET selected both high-side synchronous rectifier described Equation (Watts)
(41)
(Watts)
(42)
where: quiescent operating current (neglecting drivers) maximum power capability device's PowerPad package dependent layout well flow. thermal impedance from junction air, assuming copper trace thermal with solder flow. 36.515 (43)
maximum allowable package power dissipation related ambient temperature Equation (Watts)
(44)
Substituting Equation into Equation solving yields maximum operating frequency TPS4005x. result described Equation
(Hz)
(45)
LAYOUT CONSIDERATIONS PowerPADPACKAGE
PowerPAD package provides thermal impedance heat removal from device. PowerPAD derives name thermal impedance from large bonding bottom device. maximum thermal performance, circuit board must have area solder-tinned-copper underneath package. dimensions this area depends size PowerPAD package. 16-pin TSSOP (PWP) package, dimensions circuit board area [2]. dimensions package shown Figure Thermal vias connect this area internal external copper planes should have drill diameter sufficiently small that hole effectively plugged when barrel plated with copper. This plug needed prevent wicking solder away from interface between package body solder-tinned area under device during solder reflow. Drill diameters 0,33 mils) works well when 1-oz copper plated surface board while simultaneously plating barrel via. thermal vias
TPS40054-Q1, TPS40055-Q1, TPS40057-Q1
SLAS482A AUGUST 2005 REVISED NOVEMBER 2005
LAYOUT CONSIDERATIONS (continued)
plugged when copper plating performed, then solder mask material should used vias with diameter equal diameter minimum. This capping prevents solder from being wicked through thermal vias potentially creating solder void under package. PowerPAD Thermally Enhanced Package[2] mechanical illustration this document more information PowerPAD package.
5,10 4,90 Thermal
2,46 1,86
4,50 6,60 4,30 6,20
2,31 1,75
Figure PowerPAD Dimensions
MOSFET PACKAGING
MOSFET package selection depends MOSFET power dissipation projected operating conditions. general, surface-mount applications, DPAK style package provides lowest thermal impedance (JA) and, therefore, highest power dissipation capability. However, effectiveness DPAK depends proper layout thermal management. specified MOSFET data sheet refers given copper area thickness. most cases, lowest thermal impedance 40°C/W requires square inch 2-ounce copper G-10/FR-4 board. Lower thermal impedances achieved expense board area. selected MOSFET's data sheet more information regarding proper mounting.
GROUNDING CIRCUIT LAYOUT CONSIDERATIONS
TPS4005x provides separate signal ground (SGND) power ground (PGND) pins. important that circuit grounds properly separated. Each ground should consist plane minimize impedance possible. high power noisy circuits such output, synchronous rectifier, MOSFET driver decoupling capacitor (BP10), input capacitor should connected PGND plane input capacitor. Sensitive nodes such resistor divider ILIM should connected SGND plane. SGND plane should only make single point connection PGND plane. Component placement should ensure that bypass capacitors (BP10 BP5) located close possible their respective power ground pins. Also, sensitive circuits such ILIM should located near high dv/dt nodes such HDRV, LDRV, BOOST, switch node (SW).
TPS40054-Q1, TPS40055-Q1, TPS40057-Q1
SLAS482A AUGUST 2005 REVISED NOVEMBER 2005
DESIGN EXAMPLE
Input Voltage: Output voltage: (3.234 3.366) Output current: (maximum, steady state), (surge, 10-ms duration, duty cycle maximum) Output ripple: mVP-P Output load response: step load change, from Operating temperature: -40°C 85°C
Calculate maximum minimum duty cycles O(min) O(max) 3.324 0.135 3.366 0.337 VIN(max) IN(min) Select switching frequency
(46)
switching frequency based minimum duty cycle ratio propagation delay current limit comparator. order maintain current limit capability, time upper MOSFET (tON) must greater than (see Electrical Characteristics table). Therefore, O(min) IN(max)
(47)
VO(min) IN(max)
(48)
Using provide margin, 0.135 Since oscillator vary 10%, decrease therefore choose frequency kHz. Select this case, chosen that converter enters discontinuous mode nominal load. Calculate power losses
(49)
(50)
(51)
Power losses high-side MOSFET (Si7860DP) 24-VIN where switching losses dominate calculated from Equation
0.135 2.93
(52)
substituting Equation into Equation yields COND 2.932 0.008 0.007 (150 25)) 0.129 from Equation switching losses determined. SW(fsw)
1.152
(53)
(54)
TPS40054-Q1, TPS40055-Q1, TPS40057-Q1
SLAS482A AUGUST 2005 REVISED NOVEMBER 2005
DESIGN EXAMPLE (continued)
MOSFET junction temperature found substituting Equation into Equation PCOND (0.129 1.152)
(55)
Calculate synchronous rectifier losses synchronous rectifier MOSFET loss components: conduction diode reverse recovery losses. conduction losses IRMS losses, well body diode conduction losses during dead time associated with anti-cross conduction delay. IRMS current through synchronous rectifier from Equation
0.135 7.44
(56)
synchronous MOSFET conduction loss from Equation
COND DS(on) 7.44 0.008 0.007(150 25)) 0.83
(57)
body diode conduction loss from Equation DELAY
0.384
(58)
body diode reverse recovery loss from Equation
0.108
(59)
total power dissipated synchronous rectifier MOSFET from Equation PCOND 0.108 0.83 0.384 1.322 junction temperature synchronous rectifier 85°C (1.322)
(60)
(61)
typical applications, paralleling synchronous rectifier MOSFET with Schottky rectifier increases overall converter efficiency approximately lower power dissipation during body diode conduction reverse recovery periods. Calculate inductor value inductor value calculated from Equation 2.96 2.9-µH Coev DXM1306-2R9 2.6-µH Panasonic ETQ-P6F2R9LFA used. Setting switching frequency clock frequency with resistor from ground. value found from Equation with kHz.
17.82
(63)
(62)
Programming ramp generator circuit ramp programmed through resistor RKFF) from VIN. ramp generator also controls input UVLO voltage. undervoltage level RKFF calculated from Equation
VIN(min) 58.14 1340 72.5 71.5
(64)
Calculating output capacitance this example output capacitance determined load response requirement step load. calculated using Equation
TPS40054-Q1, TPS40055-Q1, TPS40057-Q1
SLAS482A AUGUST 2005 REVISED NOVEMBER 2005
DESIGN EXAMPLE (continued)
(3.3) (3.0)
(65)
Using Equation calculate required meet output ripple requirements.
(66) (67)
10.3 3.33 6.97
this design example, Panasonic EEFUEOJ1B1R capacitors, (6.3 used. Calculate soft-start capacitor CSS) This design requires soft-start time (tSTART) calculated Equation 3.29 3300 Calculate current limit resistor RILIM) current limit point depends tSTART, ILOAD start-up shown Equation this design, (69) this design, ILIM minimum. From Equation with equal dc-output surge current plus one-half ripple current RDS(on) increased (1.3 0.008) allow MOSFET heating. 0.02) ILIM 12.6 0.0104W 15.2 12.9 (70) Calculate loop compensation values Calculate modulator gain from Equation AMOD(dB) Calculate output filter L-CO poles zeros from Equation Equation 4.93
0.006 73.7
(73)
(68)
(71)
(72)
Select close-loop crossover frequency (fC). this example, kHz. Select double zero location Type compensation network output filter double pole 4.93 kHz. Select double pole location Type compensation network output capacitor zero 73.7 kHz. amplifier gain crossover frequency determined reciprocal modulator gain AMOD crossover frequency from Equation
MOD(f) AMOD
4.93
0.304
(74)
also from Equation
TPS40054-Q1, TPS40055-Q1, TPS40057-Q1
SLAS482A AUGUST 2005 REVISED NOVEMBER 2005
DESIGN EXAMPLE (continued)
3.29 0.304 MOD(f)
(75)
Choose poles zeros type network described Equation Equation choose 4.93 6.55 choose 6.49 73.3
24.2 choose 3.29 98.2 choose 97.6 73.3 97.6 4.93 choose
(76) (77) (78) (79) (80)
Calculate value RBIAS from Equation with BIAS 100kW 26.9 choose 26.7
(81)
CALCULATING BOOST BP10V BYPASS CAPACITANCE
size bypass capacitor depends total gate charge MOSFET being used amount droop allowed bypass cap. BOOST capacitance Si7860DP, allowing 0.5-V droop BOOST from Equation BOOST (82) BP10V capacitance from Equation BP(10
(83)
this application, 0.1-µF capacitor used BOOST bypass capacitor 1-µF capacitor used BP10V bypass.
TPS40054-Q1, TPS40055-Q1, TPS40057-Q1
SLAS482A AUGUST 2005 REVISED NOVEMBER 2005
DESIGN EXAMPLE (continued) DESIGN EXAMPLE SUMMARY
Figure shows component selection 10-V 24-V 3.3-V dc-to-dc converter specified design example. input application, necessary Schottky diode from BP10 BOOST sufficient gate drive upper MOSFET. seen Figure BP10 output about with input upper MOSFET gate drive less than Schottky diode shown connected across synchronous rectifier MOSFET optional device that required layout causes excessive negative node voltage, greater than equal
RKFF 71.5 TPS4005xPWP 1N4150 Optional Hysteresis UVLO 3300 SYNC SGND COMP HDRV Si7860 BP10 Si7860 97.6 LDRV PGND 6.49 *optional RBIAS 26.7 ILIM BOOST
VOUT
UDG-03180
Figure DC-to-DC Converter Design Example
REFERENCES
Balogh, Laszlo, Design Application Guide High Speed MOSFET Gate Drive Circuits, Texas Instruments/Unitrode Corporation, Power Supply Design Seminar, SEM-1400 Topic PowerPAD Thermally Enhanced Package Texas Instruments, Semiconductor Group, Technical Brief (SLMA002)
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