SPRS282A DECEMBER 2005 REVISED JANUARY 2006 Digital Media System-

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

SPRS282A DECEMBER 2005 REVISED JANUARY 2006 Digital Media System-

Datasheet Thumbnail

Top Searches for this datasheet

TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Digital Media System-on-Chip (DMSoC)
Features
ARM926EJ-S (MPU) Core Support 32-Bit 16-Bit (Thumb® Mode) Instruction Sets Instruction Extensions Single Cycle ARM® Jazelle® Technology EmbeddedICE-RTLogic Real-Time Debug ARM9 Memory Architecture 16K-Byte Instruction Cache 8K-Byte Data Cache 16K-Byte 16K-Byte Emulation Trace Buffer(ETB11TM) With 4-KB Memory ARM9 Debug Endianness: Little Endian Video Processing Subsystem Resize Engine Provides: Resize Images From 1/4x Separate Horizontal Vertical Control Back Provides: Hardware On-Screen Display (OSD) DACs Combination Composite NTSC/PAL Video Luma/Chroma Separate Video (S-video) Component (YPbPr RGB) Video (Progressive) Digital Output 8-/16-Bit 24-Bit Resolution Video Windows External Memory Interfaces (EMIFs) 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8V I/O) Asynchronous16-Bit Wide EMIF (EMIFA) With 128M-Byte Address Reach Flash Memory Interfaces (8-/16-Bit-Wide Data) NAND (8-/16-Bit-Wide Data) Flash Card Interfaces Multimedia Card (MMC)/Secure Digital (SD) CompactFlash Controller With True Mode SmartMedia
High-Performance Digital Media 594-MHz C64x+Clock Rate 297-MHz ARM926EJ-SClock Rate Eight 32-Bit C64x+ Instructions/Cycle 4752 C64x+ MIPS Fully Software-Compatible With C64x ARM9Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+DSP Core Eight Highly Independent Functional Units ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, Quad 8-Bit Arithmetic Clock Cycle Multipliers Support Four 16-Bit Multiplies (32-Bit Results) Clock Cycle Eight 8-Bit Multiplies (16-Bit Results) Clock Cycle Load-Store Architecture With Non-Aligned Support 32-Bit General-Purpose Registers Instruction Packing Reduces Code Size Instructions Conditional Additional C64x+Enhancements Protected Mode Operation Exceptions Support Error Detection Program Redirection Hardware Support Modulo Loop Operation C64x+ Instruction Features Byte-Addressable (8-/16-/32-/64-Bit Data) 8-Bit Overflow Protection Bit-Field Extract, Set, Clear Normalization, Saturation, Bit-Counting Compact 16-Bit Instructions Additional Instructions Support Complex Multiplies C64x+ L1/L2 Memory Architecture 32K-Byte Program RAM/Cache (Direct Mapped) 80K-Byte Data RAM/Cache (2-Way Set-Associative) 64K-Byte Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this document. trademarks property their respective owners.
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
Copyright 2005-2006, Texas Instruments Incorporated
PRODUCT PREVIEW
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Enhanced Direct-Memory-Access (EDMA) Controller Independent Channels) 64-Bit General-Purpose Timers (Each Configurable 32-Bit Timers) 64-Bit Watch Timer Three UARTs (One with Flow Control) Serial Port Interface (SPI) with Chip-Selects Master/Slave Inter-Integrated Circuit (I2C BusTM) Audio Serial Port (ASP) AC97 Audio Codec Interface Standard Voice Codec Interface (AIC12) 10/100 Mb/s Ethernet (EMAC) IEEE 802.3 Compliant Media Independent Interface (MII) VLYNQInterface (FPGA Interface)
Port With Integrated High-/Full-Speed (480 Mbps) Client High-/Full-/Low-Speed Host (Mini-Host, Supporting External Device) Three Pulse Width Modulator (PWM) Outputs On-Chip Bootloader (RBL) Boot From NAND Flash UART ATA/ATAPI (ATA/ATAPI-5 Specification) Individual Power-Saving Modes ARM/DSP Flexible Clock Generators IEEE-1149.1 (JTAG) BoundaryScan-Compatible General-Purpose (GPIO) Pins (Multiplexed With Other Device Functions) 361-Pin Pb-Free Package (ZWT Suffix), 0.8-mm Ball Pitch 0.09-µm/6-Level Metal Process (CMOS) 3.3-V 1.8-V I/O, 1.2-V Internal Applications: Digital Media Networked Media Encode/Decode Video Imaging
PRODUCT PREVIEW
Digital Media System-on-Chip (DMSoC)
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Description
TMS320DM6443 (also referenced DM6443) leverages TI's Davinci technology meet networked media encode decode application processing needs next-generation embedded devices. DM6443 enables OEMs ODMs quickly bring market devices featuring robust operating systems support, rich user interfaces, high processing performance, long battery life through maximum flexibility fully integrated mixed processor solution. dual-core architecture DM6443 provides benefits both Reduced Instruction Computer (RISC) technologies, incorporating high-performance TMS320C64x+ core ARM926EJ-S core. ARM926EJ-S 32-bit RISC processor core that performs 32-bit 16-bit instructions processes 32-bit, 16-bit, 8-bit data. core uses pipelining that parts processor memory system operate continuously. core incorporates: coprocessor (CP15) protection module Data program Memory Management Units (MMUs) with table look-aside buffers. Separate 16K-byte instruction 8K-byte data caches. Both four-way associative with virtual index virtual (VIVT). TMS320C64x+DSPs highest-performance fixed-point generation TMS320C6000DSP platform. based enhanced version second-generation high-performance, advanced very-long-instruction-word (VLIW) architecture developed Texas Instruments (TI), making these cores excellent choice digital media applications. C64x code-compatible member C6000DSP platform. TMS320C64x+ enhancement C64x+ with added functionality expanded instruction set. reference C64x C64x also applies, unless otherwise noted, C64x+ C64x+ CPU, respectively. With performance 4752 million instructions second (MIPS) clock rate MHz, C64x+ core offers solutions high-performance programming challenges. core possesses operational flexibility high-speed controllers numerical capability array processors. C64x+ core processor general-purpose registers 32-bit word length eight highly independent functional units-two multipliers 32-bit result arithmetic logic units (ALUs). eight functional units include instructions accelerate performance video imaging applications. core produce four 16-bit multiply-accumulates (MACs) cycle total 2376 million MACs second (MMACS), eight 8-bit MACs cycle total 4752 MMACS. more details C64x+ DSP, TMS320C64x/C64x+ Instruction Reference Guide (literature number SPRU732). DM6443 also application-specific hardware logic, on-chip memory, additional on-chip peripherals similar other C6000 platform devices. DM6443 core uses two-level cache-based architecture. Level program cache (L1P) 256K-bit direct mapped cache Level data cache (L1D) 640K-bit 2-way set-associative cache. Level memory/cache (L2) consists 512K-bit memory space that shared between program data space. memory configured mapped memory, cache, combinations two. peripheral includes: configurable video port; 10/100 Mb/s Ethernet (EMAC) with Management Data Input/Output (MDIO) module; inter-integrated circuit (I2C) interface; audio serial port (ASP); 64-bit general-purpose timers each configurable independent 32-bit timers; 64-bit watchdog timer; 71-pins general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; UARTs with hardware handshaking support UART; pulse width modulator (PWM) peripherals; external memory interfaces: asynchronous external memory interface (EMIFA) slower memories/peripherals, higher speed synchronous memory interface DDR2.
Digital Media System-on-Chip (DMSoC)
PRODUCT PREVIEW
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
DM6443 includes Video Processing Sub-System (VPSS) that configurable Resizer Video Processing Back-End (VPBE) output used display. Resizer accepts image data separate horizontal vertical resizing from 1/4x increments 256/N, where between 1024. Video Processing Back-End (VPBE) comprised On-Screen Display Engine (OSD) Video Encoder (VENC). engine capable handling separate video windows separate windows. Other configurations include video windows, window, attribute window allowing levels alpha blending. VENC provides four analog DACs that MHz, providing means composite NTSC/PAL video, S-Video, and/or Component video output. VENC also provides bits digital output interface RGB888 devices. digital output capable 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal vertical syncs. Ethernet Media Access Controller (EMAC) provides efficient interface between DM644X network. DM6443 EMAC support both 10Base-T 100Base-TX, Mbits/second (Mbps) Mbps either half- full-duplex mode, with hardware flow control quality service (QOS) support. Management Data Input/Output (MDIO) module continuously polls MDIO addresses order enumerate devices system. Once candidate been selected ARM, MDIO module transparently monitors link state reading status register. Link change events stored MDIO module optionally interrupt ARM, allowing poll link status device without continuously performing costly MDIO accesses. I2C, SPI, USB2.0, VLYNQ ports allow DM6443 easily control peripheral devices and/or communicate with host processors. rich peripheral provides ability control external peripheral devices communicate with external processors. details each peripherals, related sections later this document associated peripheral reference guides. DM6443 complete development tools both DSP. These include compilers, assembly optimizer simplify programming scheduling, Windowsdebugger interface visibility into source code execution.
PRODUCT PREVIEW
Digital Media System-on-Chip (DMSoC)
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Functional Block Diagram
Figure shows functional block diagram DM6443.
JTAG Interface System Control Input Clock(s) PLLs/Clock Generator Power/Sleep Controller Multiplexing Subsystem ARM926EJ-S I-Cache D-Cache Subsystem C64x+ Data Video Processing Subsystem (VPSS) Front Back On-Screen Video Display Encoder (OSD) (VENC) BT.656, Y/C, NTSC/ PAL, S-Video, RGB, YPbPr
Resizer
Switched Central Resource (SCR)
Peripherals
Serial Interfaces System
EDMA
Audio Serial Port
UART
GeneralPurpose Timer
Watchdog Timer
Connectivity
Program/Data Storage
VLYNQ
EMAC With MDIO
DDR2 Ctlr (16b/32b)
Async EMIF/ NAND/ SmartMedia
ATA/ Compact Flash
MMC/
Figure 1-1. TMS320DM6443 Functional Block Diagram
Digital Media System-on-Chip (DMSoC)
PRODUCT PREVIEW
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Contents
Digital Media System-on-Chip (DMSoC) Features Description Functional Block Diagram Device Characteristics Device Compatibility Subsystem Subsystem Memory Summary Assignments 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 5.20 5.21 5.22 5.23 5.24 Parameter Information Recommended Clock Control Signal Transition Behavior Power Supplies Reset Oscillators Clock PLLs Interrupts General-Purpose Input/Output (GPIO). Enhanced Direct Memory Access (EDMA) Controller
Device Overview
Terminal Functions Device Support Device Configuration System Module Registers Power Considerations Clocks Considerations Bootmode Configurations Reset Configurations After Reset Emulation Control Debugging Considerations Configuration Examples Device Operating Conditions
MMC/SD Video Processing Sub-System (VPSS) Overview
External Memory Interface (EMIF) ATA/CF
PRODUCT PREVIEW
Universal Asynchronous Receiver/Transmitter (UART) Serial Port Interface (SPI). Inter-Integrated Circuit (I2C) Audio Serial Port (ASP). Ethernet Media Access Controller (EMAC). Management Data Input/Output (MDIO) Pulse Width Modulator (PWM) IEEE 1149.1 JTAG
Timer.
Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted) Recommended Operating Conditions Electrical Characteristics Over Recommended Ranges Supply Voltage Operating Case Temperature (Unless Otherwise Noted)
VLYNQ
Revision History Mechanical Packaging Orderable Information
Thermal Data Packaging Information
Peripheral Electrical Specifications.
Device Overview
Device Characteristics
Table provides overview TMS320DM6443 SoC. table shows significant features device, including capacity on-chip RAM, peripherals, internal peripheral frequency relative C64x+ DSP, package type with count.
Contents
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Table 2-1. Characteristics Processor
HARDWARE FEATURES DDR2 Memory Controller Asynchronous EMIF (EMIFA) (speed PLL1/6) Flash Cards (speed PLL1/6) EDMA (speed PLL1/3) Timers (speed PLL1/17 [Normal Mode]) (speed PLL1/22 [Turbo Mode]) Peripherals peripherals pins available same time (For more detail, Device Configuration section). UART (speed PLL1/17 [Normal Mode]) (speed PLL1/22 [Turbo Mode]) (speed PLL1/6) (speed PLL1/17 [Normal Mode]) (speed PLL1/22 [Turbo Mode]) Audio Serial Port [ASP] (speed PLL1/6) 10/100 Ethernet with Management Data Input/Output (speed PLL1/6) VLYNQ (speed PLL1/6) General-Purpose Input/Output Port (speed PLL1/6) (speed PLL1/17 [Normal Mode]) (speed PLL1/22 [Turbo Mode]) ATA/CF (speed PLL1/6) Configurable Video Port (speed PLL1/6) (speed PLL1/6) Size (Bytes) DM6443 DDR2 (16/32-bit width) Asynchronous (8/16-bit width) RAM, Flash (NOR,NAND) MMC/SD SmartMedia/xD independent channels QDMA channels 64-Bit General Purpose (each configurable separate 32-bit timers) 64-Bit Watch (one with flow control) (supports slave devices) (Master/Slave) outputs (ATA/ATAPI-5) Resizer Output (VPBE) High Speed Device High Speed Host 160KB RAM, 16KB [32KB Program (L1P)/Cache 32KB), 80KB Data (L1D)/Cache 32KB), 64KB Unified Mapped RAM/Cache (L2), [16KB I-cache, D-cache, 16KB RAM, 16KB ROM] 0x0B70 002F DM6443 -594 DM6443 -594 1.68 3.37 (-594) (Bypass), (-594) 357-Pin (ZWT) 0.09
On-Chip Memory
Organization
JTAG BSDL_ID Frequency (Maximum) Cycle Time (Minimum) Voltage Options Package Process Technology
Control Status Register (CSR.[31:16]) JTAGID register (address location: 0x01C4 0028) Core CLKIN frequency multiplier reference)
Speeds noted indicate peripheral operating speed, rather peripheral state machine clocking speed. Device Overview
PRODUCT PREVIEW
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Table 2-1. Characteristics Processor (continued)
HARDWARE FEATURES Product Status Product Preview (PP), Advance Information (AI), Production Data (PD) DM6443
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
Device Compatibility
ARM926EJ-S RISC compatible with other ARM9 MPUs from Holdings plc. C64x+ core code-compatible with C6000DSP platform supports features C64x family.
PRODUCT PREVIEW
Subsystem
Subsystem designed give ARM926EJ-S (ARM9) master control device. general, responsible configuration control device; including Subsystem, VPSS Subsystem, majority peripherals external memories. Subsystem includes following features: ARM926EJ-S RISC processor ARMv5TEJ (32/16-bit) instruction Little endian Co-Processor (CP15) 16KB Instruction cache Data cache Write Buffer 16KB Internal (32-bit wide access) 16KB Internal (ARM bootloader non-EMIFA boot options) Embedded Trace Module Embedded Trace Buffer (ETM/ETB) Interrupt controller Controller Power Sleep Controller (PSC) System Module
2.3.
ARM926EJ-S RISC
Subsystem integrates ARM926EJ-S processor. ARM926EJ-S processor member ARM9 family general-purpose microprocessors. This processor targeted multi-tasking applications where full memory management, high performance, size, power important. ARM926EJ-S processor supports 32-bit THUMB instruction sets, enabling user trade between high performance high code density. Specifically, ARM926EJ-S processor supports ARMv5TEJ instruction set, which includes features efficient execution Java byte codes, providing Java performance similar Just Time (JIT) Java interpreter, without associated code overhead. ARM926EJ-S processor supports debug architecture includes logic assist both hardware software debug. ARM926EJ-S processor Harvard architecture provides complete high performance subsystem, including: ARM926EJ integer core CP15 system control coprocessor
Device Overview
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Memory Management Unit (MMU) Separate instruction data Caches Write buffer Separate instruction data Tightly-Coupled Memories (TCMs) [internal RAM] interfaces Separate instruction data interfaces Embedded Trace Module Embedded Trace Buffer (ETM/ETB)
more complete details ARM9, refer ARM926EJ-S Technical Reference Manual, available http://www.arm.com
2.3.2
CP15
ARM926EJ-S system control coprocessor (CP15) used configure control instruction data caches, Tightly-Coupled Memories (TCMs), Memory Management Unit (MMU), other subsystem functions. CP15 registers programmed using instructions, when privileged mode such supervisor system mode.
2.3.3
ARM926EJ-S provides virtual memory features required operating systems such Linux, WindowCE, ultron, ThreadX, etc. single level page tables stored main memory used control address translation, permission checks memory region attributes both data instruction accesses. uses single unified Translation Lookaside Buffer (TLB) cache information held page tables. features are: Standard architecture mapping sizes, domains access protection scheme. Mapping sizes are: (sections) 64KB (large pages) (small pages) (tiny pages) Access permissions large pages small pages specified separately each quarter page (subpage permissions) Hardware page table walks Invalidate entire TLB, using CP15 register Invalidate entry, selected MVA, using CP15 register Lockdown entries, using CP15 register
2.3.4
Caches Write Buffer
size Instruction Cache 16KB, Data cache 8KB. Additionally, Caches have following features: Virtual index, virtual tag, addressed using Modified Virtual Address (MVA) Four-way associative, with cache line length eight words line (32-bytes line) with dirty bits Dcache Dcache supports write-through write-back copy back) cache operation, selected memory region using bits translation tables. Critical-word first cache refilling Cache lockdown registers enable control over which cache ways used allocation line fill, providing mechanism both lockdown, controlling cache corruption Dcache stores Physical Address TAG) corresponding each Dcache entry during cache line write-backs, addition Virtual Address stored RAM. This means that involved Dcache write-back operations, removing possibility misses related write-back address.
Device Overview
PRODUCT PREVIEW
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Cache maintenance operations provide efficient invalidation entire Dcache Icache, regions Dcache Icache, regions virtual memory.
write buffer used writes noncachable bufferable region, write-through region write misses write-back region. separate buffer incorporated Dcache holding write-back cache line evictions cleaning dirty cache lines. main write buffer 16-word data buffer four-address buffer. Dcache write-back eight data word entries single address entry.
2.3.5
Tightly Coupled Memory (TCM)
internal provided storing real-time performance-critical code/data Interrupt Vector table. internal enables non-EMIFA boot options, such NAND UART. memories interfaced ARM926EJ-S tightly coupled memory interface that provides separate instruction data connections. Since does allow instructions D-TCM data I-TCM bus, arbiter included that both data instructions stored internal RAM/ROM. arbiter also allows accesses RAM/ROM from extra-ARM sources (e.g., EDMA other masters). ARM926EJ-S built-in support direct accesses internal memory from non-ARM master. Because time-critical nature link internal memory, accesses from non-ARM devices treated transfers. Instruction Data accesses differentiated accessing different memory regions, with instruction region from 0x0000 through 0x7FFF data from 0x8000 through 0xFFFF. Placing instruction region 0x0000 necesssary allow Interrupt Vector table placed 0x0000, required architecture. internal 16-KB split into physical banks each, which allows simultaneous instruction data accesses accomplished code data separate banks. ARM926EJ-S built support direct accesses internal memory from nonARM device. Furthermore, because time critical nature link internal memory, accesses from non-ARM devices treated transfers.
PRODUCT PREVIEW
2.3.6 2.3.7 2.3.8
Advanced High-Performance (AHB)
Subsystem uses port ARM926EJ-S connect Config external memories. Arbiters employed arbitrate access separate D-AHB I-AHB Config external memories bus.
Embedded Trace Macrocell (ETM) Embedded Trace Buffer (ETB)
support real-time trace, ARM926EJ-S processor provides interface enable connection Embedded Trace Macrocell (ETM). ARM926ES-J Subsystem DM644X also includes Embedded Trace Buffer (ETB). Econsists parts: Trace Port provides real-time trace capability ARM9. Triggering facilities provide trigger resources, which include address data comparators, counter, sequencers. DM644X trace port pinned instead only connected Embedded Trace Buffer. buffer memory. enabled debug tools required read/interpret captured trace data.
Memory Mapping
memory shown Memory section this document. access memories shown following sections.
Device Overview
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
2.3.8.
Internal Memories
access following internal memories: 16KB Internal interface, logically separated into pages allow simulatenous access given cycle there separate acecsses code (I-TCM bus) data (D-TCM) different memory regions. 16KB Internal 2.3.8.2 External Memories access following External memories: DDR2 Synchronous DRAM Asynchronous EMIF Flash NAND Flash ATA/CF Flash card devices: MMC/SD SmartMedia 2.3.8.3 Memories access following memories:
2.3.9
ARM-DSP Integration
DM6443 integration features follows: visibility from ARM's memory map, Memory section details Boot Modes Device Configurations section details control boot reset Device Configurations section details control isolation powerdown powerup Device Configurations section Interrupts Interrupts section
2.3.10
Peripherals
ARM9 access peripherals DM6443 device.
2.3.1
Controller (PLLC)
Subsystem includes Controller. Controller contains registers configuring DM6443's internal PLLs (PLL1 PLL2). Controller provides following configuration control: Bypass Mode multiplier parameters divider parameters power down Oscillator power down PLLs briefly described this document Clocking section. more detailed information PLLs Controller register descriptions, Documentation Support section this document Subsystem Guide
Device Overview
PRODUCT PREVIEW
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
2.3.12
Power Sleep Controller (PSC)
Subsystem includes Power Sleep Controller (PSC). Through register settings accessible ARM9, provides levels power savings: peripheral/module clock gating power domain shut-off. Brief details given Power Supply section. more detailed information complete register descriptions PSC, Documentation Support section this document Subsystem Guide.
2.3.13
Interrupt Controller (AINTC)
Interrupt Controller (AINTC) accepts device interrupts maps them either ARM's (interrupt request) (fast interrupt request). Interrupt Controller briefly described this document Interrupts section. detailed information Interrupt Controller, Documentation Support section this document Subsystem Guide.
2.3.14
System Module
PRODUCT PREVIEW
Subsystem includes System module. System module consists registers configuring controlling variety system functions. details register descriptions System module, Device Configurations section Documentation Support section this document Subsystem Guide.
2.3.15
Power Management
DM6443 several means managing power consumption. There extensive clock gating, which reduces power used global device clocks individual peripheral clocks. power disabled through register settings. Voltage/Frequency scaling used allow user lower core power supply voltage frequency needs particular application lower. Clock management utilized reduce clock frequencies order reduce switching power. more details power management techniques, Device Configurations Peripheral sections this document Documentation Support section this document Subsystem Guide. DM6443 gives programmer full flexibility previously mentioned capabilities customize optimal power management strategy. Several typical power management scenarios described following sections. 2.3.15.1 Standby Power Mode This mode consumes lowest power, with minimum modules kept alive that required wake chip higher power mode. coprocessor subsystems powered. rest chip powered clocks suspended, except GPIO (interrupts), UARTs, slave mode), peripheral. PLLs operating bypass mode. 27-MHz clock only clock available system. DDR2 clock suspended DDR2 Memory Controller into self-refresh mode. 2.3.15.2 Low-Power Mode This mode sustain some basic control functions. coprocessor subsystems powered. rest chip powered, most clocks suspended, except ARM, GPIO, UARTs, SPI, I2C, PWMs, Timers. PLLs operating bypass mode. 27-MHz clock only clock available system. runs 13.5 MHz, handles peripherals direct access. DDR2 clock suspended DDR2 Memory Controller into self-refresh mode. will have access DDR2 caches either frozen inaccessible. 2.3.15.3 Active Power Mode entire chip powered. modules operate nominal clock frequency. Unused peripherals have their clocks suspended. Active peripherals have their clocks suspended when unneeded.
Device Overview
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Subsystem
Subsystem includes following features: C64X+ 32KB Program (L1P)/Cache 32KB) 80KB Data (L1D)/Cache 32KB) 64KB Unified Mapped RAM/Cache (L2) Little endian
2.4.
C64X+ Description
C64x+ Central Processing Unit (CPU) consists eight functional units, register files, data paths shown Figure 2-1. general-purpose register files each contain 32-bit registers total registers. general-purpose registers used data data address pointers. data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, 64-bit data. Values larger than bits, such 40-bit-long 64-bit-long values stored register pairs, with LSBs data placed even register remaining MSBs next upper register (which always odd-numbered register). eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, .S2) each capable executing instruction every clock cycle. functional units perform multiply operations. units perform general arithmetic, logical, branch functions. units primarily load data from memory register file store results from register file into memory. C64x+ extends performance C64x core through enhancements features. Each C64x+ unit perform following each clock cycle: multiply, multiply, multiplies, multiplies, multiplies with add/subtract capabilities, four multiplies, four multiplies with operations, four multiplies with add/subtract capabilites (including complex multiply). There also support Galois field mutiplication 8-bit 32-bit data. Many communications algorithms such FFTs modems require complex multiplication. complex multiply (CMPY) instruction takes 16-bit inputs produces 32-bit real 32-bit imaginary output. There also complex multiplies with rounding capability that produces 32-bit packed output that contain 16-bit real 16-bit imaginary values. multiply instructions provide extended precision necessary audio other high-precision algorithms variety signed unsigned 32-bit data types. (Arithmetic Logic Unit) incorporates ability parallel add/subtract operations pair common inputs. Versions this instruction exist work 32-bit data pairs 16-bit data performing dual 16-bit subtracts parallel. There also saturated forms these instructions. C64x+ core enhances unit several ways. C64x core, dual 16-bit MIN2 MAX2 comparisons were only available units. C64x+ core they also available unit which increases performance algorithms that searching sorting. Finally, increase data packing unpacking throughput, unit allows sustained high performance quad 8-bit/16-bit dual 16-bit instructions. Unpack instructions prepare 8-bit data parallel 16-bit operations. Pack instructions return parallel results output precision including saturation support. Other features include: SPLOOP small instruction buffer that aids creation software pipelining loops where multiple iterations loop executed parallel. SPLOOP buffer reduces code size associated with software pipelining. Futhermore, loops SPLOOP buffer fully interruptible. Compact Instructions native instruction size C6000 devices bits. Many common instructions such MPY, AND, ADD, expressed bits C64x+ compiler restrict code certain registers register file. This compression performed code generation tools.
Device Overview
PRODUCT PREVIEW
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Instruction Enhancement noted above, there instructions such 32-bit multiplications, complex multiplications, packing, sorting, manipulation, 32-bit Galois field multiplication. Exceptions Handling Intended programmer isolating bugs. C64x+ able detect respond exceptions, both from internally detected sources (such illegal op-codes) from system events (such watchdog time expiration). Privilege Defines user supervisor modes operation, allowing operating system give basic level protection sensitive resources. Local memory divided into multiple pages, each with read, write, execute permissions. Time-Stamp Counter Primarily targeted Real-Time Operating System (RTOS) robustness, free-running time-stamp counter implemented which sensitive system stalls.
more details C64x+ enhancements over C64x architecture, following documents: TMS320C64x/C64x+ Instruction Reference Guide (literature number SPRU732) TMS320C64x Technical Overview (literature number SPRU395)
PRODUCT PREVIEW
Device Overview
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
src2 even long
register file (A1, A5.A31)
Even register file (A0, A4.A30)
ST1b ST1a
long even src1 src2
Data path
LD1b LD1a
LD2a LD2b
src2 src1 dst2 dst1 src2
Data path
ST2a ST2b
src2
unit, dst2 MSB. unit, dst1 LSB. C64x unit, src2 bits; C64x+ unit, src2 bits. units, connects register files even connects even register files.
Figure 2-1. TMS320C64x+CPU (DSP Core) Data Paths
long even
even long
src1
src1 src2 Even register file (B0, B4.B30)
src2
src2
register file (B1, B5.B31)
Control Register
Device Overview
PRODUCT PREVIEW
dst2 dst1
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
2.4.1.
C64X+ Cache Registers
Table shows memory C64x+ cache Registers device. Table 2-2. C64x+ Cache Registers
ADDRESS RANGE 0x0184 0000 0x0184 0020 0x0184 0024 0x0184 0040 0x0184 0044 0x0184 0048 0x0184 0FFC 0x0184 1000 0x0184 1004 0x0184 1FFC 0x0184 2000 0x0184 2004 0x0184 2008 0x0184 200C 0x0184 2010 0x0184 3FFF 0x0184 4000 0x0184 4004 0x0184 4010 0x0184 4014 0x0184 4018 0x0184 401C 0x0184 4020 0x0184 4024 0x0184 4030 0x0184 4034 0x0184 4038 0x0184 4040 0x0184 4044 0x0184 4048 0x0184 404C 0x0184 4050 0x0184 4FFF 0x0184 5000 0x0184 5004 0x0184 5008 0x0184 500C 0x0184 5027 0x0184 5028 0x0184 502C 0x0184 5039 0x0184 5040 0x0184 5044 0x0184 5048 0x0184 8000 0x0184 8004 0x0184 8008 0x0184 8024 0x0184 8028 0x0184 802C 0x0184 8030 0x0184 803C 0x0184 8040 0x0184 8104 REGISTER ACRONYM L2CFG L1PCFG L1PCC L1DCFG L1DCC EDMAWEIGHT L2ALLOC0 L2ALLOC1 L2ALLOC2 L2ALLOC3 L2WBAR L2WWC L2WIBAR L2WIWC L2IBAR L2IWC L1PIBAR L1PIWC L1DWIBAR L1DWIWC L1DWBAR L1DWWC L1DIBAR L1DIWC L2WB L2WBINV L2INV L1PINV L1DWB L1DWBINV L1DINV MAR0 MAR1 MAR2 MAR9 MAR10 MAR11 MAR12 MAR15 MAR16 MAR65 DESCRIPTION Cache configuration register Size Cache configuration register Freeze Mode Cache configuration register Size Cache configuration register Freeze Mode Cache configuration register Reserved EDMA access control register Reserved allocation register allocation register allocation register allocation register Reserved writeback base address register writeback word count register writeback invalidate base address register writeback invalidate word count register invalidate base address register invalidate word count register invalidate base address register invalidate word count register writeback invalidate base address register writeback invalidate word count register Reserved Block Writeback Block Writeback invalidate base address register invalidate word count register Reserved writeback register writeback invalidate register Global Invalidate without writeback Reserved Global Invalidate Reserved Global Writeback Global Writeback with Invalidate Global Invalidate without writeback Reserved 0x0000 0000 0x01FF FFFF Memory Attribute Registers EMIFA 0x0200 0000 0x09FF FFFF Reserved 0x0A00 0000 0x0BFF FFFF Memory Attribute Registers VLYNQ 0x0C00 0000 0x0FFF FFFF Reserved 0x1000 0000 0x41FF FFFF
PRODUCT PREVIEW
Device Overview
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Table 2-2. C64x+ Cache Registers (continued)
ADDRESS RANGE 0x0184 8108 0x0184 813C 0x0184 8140 0x0184 8200 0x0184 823C 0x0184 8240 0x0184 83FC REGISTER ACRONYM MAR66 MAR79 MAR80 MAR127 MAR128 MAR143 MAR144 MAR255 DESCRIPTION Memory Attribute Registers EMIFA/VLYNQ Shadow 0x4200 0000 0x4FFF FFFF Reserved 0x5000 0000 0x7FFF FFFF Memory Attribute Registers DDR2 0x8000 0000 0x8FFF FFFF Reserved 0x9000 0000 0xFFFF FFFF
2.4.2
Memory Mapping
memory shown Section 2.5. Configuration control registers DDR2, EMIFA, Internal supported ARM. access memories shown following sections. access 16KB Internal D-TCM interface (i.e., data only).
2.4.2.2
External Memories
access following External memories: DDR2 Synchronous DRAM Asynchronous EMIF Flash 2.4.2.3 Internal Memories access following memories:
2.4.3
Peripherals
controllability following peripherals: EDMA Timers (Timer0 Timer1) that each configured 64-bit 32-bit timers
2.4.4
Interrupt Controller
Interrupt Controller accepts device interrupts appropriately maps them DSP's available interrupts. Interrupt Controller briefly described this document Interrupts section. more detailed Interrupt Controller, Documentation Support section this document C64x+ User's Guide.
Memory Summary
Table shows memory address ranges device. Table depicts expanded Configuration Space (0x0180 0000 through 0x0FFF FFFF). device multiple on-chip memories associated with processors various subsystems. help simplify software development unified memory used where possible maintain consistent view device resources across masters.
Device Overview
PRODUCT PREVIEW
2.4.2.
Internal Memories
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Table 2-3. Memory Summary
START ADDRESS 0x0000 0000 0x0000 2000 0x0000 4000 0x0000 8000 0x0000 A000 0x0000 C000 0x0001 0000 0x0010 0000 0x0020 0000 ADDRESS 0x0000 1FFF 0x0000 3FFF 0x0000 7FFF 0x0000 9FFF 0x0000 BFFF 0x0000 FFFF 0x000F FFFF 0x001F FFFF 0x007F FFFF 0x0080 FFFF 0x00DF FFFF 0x00E0 3FFF 0x00E0 7FFF 0x00E0 FFFF 0x00F0 3FFF 0x00F0 FFFF 0x00F1 7FFF 0x017F FFFF 0x01BB FFFF 0x01BC 0FFF 0x01BC 17FF 0x01BC 18FF 0x01BC FFFF 0x01BF FFFF 0x01FF FFFF 0x09FF FFFF 0x0BFF FFFF 0x0FFF FFFF 0x1000 7FFF 0x1000 9FFF 0x1000 BFFF 0x1000 FFFF 0x110F FFFF 0x111F FFFF 0x117F FFFF 0x1180 FFFF 0x11DF FFFF 0x11E0 3FFF 0x11E0 7FFF 0x11E0 FFFF 0x11F0 3FFF 0x11F0 FFFF 0x11F1 7FFF 0x1FFF FFFF SIZE (Bytes) 960K 6080K 976K 9120K 3840K 59136 192K 128M 17344K 6080K 976K 241M-32K RAM0 (Instruction) RAM1 (Instruction) (Instruction) RAM0 (Data) RAM1 (Data) (Data) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Memory Registers IceCrusher Reserved Reserved Peripherals EMIFA (Code Data) Reserved VLYNQ (Remote) Reserved Reserved Reserved Reserved Reserved Reserved Reserved RAM/Cache Reserved Reserved Reserved Cache Reserved RAM/Cache Reserved C64x+ Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RAM/Cache Reserved Reserved Reserved Cache Reserved Cache Reserved Space Space Space Space Space Space Peripherals EMIFA (Data) Reserved Reserved Reserved RAM0 RAM1 Reserved Reserved Reserved RAM/Cache Reserved Reserved Reserved Cache Reserved RAM/Cache Reserved EDMA/ PERIPHERAL Reserved Reserved Reserved RAM0 RAM1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Peripherals EMIFA (Data) Reserved VLYNQ (Remote) Reserved RAM0 RAM1 Reserved Reserved Reserved RAM/Cache Reserved Reserved Reserved Cache Reserved RAM/Cache Reserved VPSS Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
PRODUCT PREVIEW
0x0080 0000 0x0081 0000 0x00E0 0000 0x00E0 4000 0x00E0 8000 0x00E1 0000 0x00F0 4000 0x00F1 0000 0x00F1 8000 0x0180 0000 0x01BC 0000 0x01BC 1000 0x01BC 1800 0x01BC 1900 0x01BD 0000 0x01C0 0000 0x0200 0000 0x0A00 0000 0x0C00 0000 0x1000 0000 0x1000 8000 0x1000 A000 0x1000 C000 0x1001 0000 0x1110 0000 0x1120 0000 0x1180 0000 0x1181 0000 0x11E0 0000 0x11E0 4000 0x11E0 8000 0x11E1 0000 0x11F0 4000 0x11F1 0000 0x11F1 8000
Device Overview
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Memory Summary (continued)
START ADDRESS 0x2000 0000 0x2000 8000 0x4200 0000 0x5000 0000 0x8000 0000 0x9000 0000 ADDRESS 0x2000 7FFF 0x41FF FFFF 0x4FFF FFFF 0x7FFF FFFF 0x8FFF FFFF 0xFFFF FFFF SIZE (Bytes) 544M-32k 224M 768M 256M 1792M DDR2 Control Regs Reserved Reserved Reserved DDR2 Reserved C64x+ DDR2 Control Regs Reserved EMIFA/VLYNQ Shadow Reserved DDR2 Reserved EDMA/ PERIPHERAL DDR2 Control Regs Reserved EMIFA/VLYNQ Shadow Reserved DDR2 Reserved VPSS Reserved Reserved Reserved Reserved DDR2 Reserved
Table 2-4. Configuration Memory Summary
START ADDRESS 0x0180 0000 0x0181 0000 0x0181 1000 0x0181 2000 0x0182 0000 0x0183 0000 0x0184 0000 0x0185 0000 0x0188 0000 0x01BC 0000 0x01BC 0100 0x01BC 0400 0x01BC 0430 0x01BC 0500 0x01BD 0000 0x01C0 0000 0x01C1 0000 0x01C1 0400 0x01C1 8800 0x01C1 A000 0x01C2 0000 0x01C2 0400 0x01C2 0800 0x01C2 0C00 0x01C2 1000 0x01C2 1400 0x01C2 1800 0x01C2 1C00 0x01C2 2000 0x01C2 2400 0x01C2 2800 0x01C2 2C00 ADDRESS 0x0180 FFFF 0x0181 0FFF 0x0181 1FFF 0x0181 2FFF 0x0182 FFFF 0x0183 FFFF 0x0184 FFFF 0x0187 FFFF 0x01BB FFFF 0x01BC 00FF 0x01BC 01FF 0x01BC 042F 0x01BC 044F 0x01BC FFFF 0x01BF FFFF 0x01C0 FFFF 0x01C1 03FF 0x01C1 07FF 0x01C1 9FFF 0x01C1 FFFF 0x01C2 03FF 0x01C2 07FF 0x01C2 0BFF 0x01C2 0FFF 0x01C2 13FF 0x01C2 17FF 0x01C2 1BFF 0x01C2 1FFF 0x01C2 23FF 0x01C2 27FF 0x01C2 2BFF 0x01C3 FFFF SIZE (Bytes) 192K 3328K 64255 192K 117K ARM/EDMA/SEQUENCER Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved EDMA EDMA EDMA Reserved Reserved UART0 UART1 UART2 Reserved Timer0 Timer1 Timer2 (WatchDog) PWM0 PWM1 PWM2 Reserved C64x+ C64x+ Interrupt Controller C64x+ Powerdown Controller C64x+ Security C64x+ Revision C64x+ Reserved C64x+ Memory System Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved EDMA EDMA EDMA Reserved Reserved Reserved Reserved Reserved Reserved Reserved Timer0 Timer1 Reserved Reserved Reserved Reserved Reserved
Device Overview
PRODUCT PREVIEW
EMIFA shadow memory started 0x4200 0000 physically same memory location 0x0200 0000. Memory range 0x200 0000 through 0x09FF FFFF should only used C64x+ data accesses. Memory range 0x4200 0000 through 0x4FFF FFFF used C64x+ both code execution data accesses.
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Configuration Memory Summary (continued)
START ADDRESS 0x01C4 0000 0x01C4 0800 0x01C4 0C00 0x01C4 1000 0x01C4 2000 0x01C4 2030 0x01C4 2034 0x01C4 2400 0x01C4 8000 0x01C4 8400 0x01C6 0000 0x01C6 4000 0x01C6 6000 0x01C6 6800 0x01C6 7000 0x01C6 7800 0x01C6 8000 0x01C7 0000 0x01C7 4000 0x01C8 0000 0x01C8 1000 0x01C8 2000 0x01C8 4000 0x01C8 4800 0x01C8 5000 0x01CC 0000 0x01CE 0000 0x01D0 0000 0x01E0 0000 0x01E0 1000 0x01E0 2000 0x01E0 4000 0x01E1 0000 0x01E2 0000 0x01E4 0000 0x0200 0000 0x0400 0000 0x0600 0000 0x0800 0000 0x0A00 0000 0x0C00 0000 ADDRESS 0x01C4 07FF 0x01C4 0BFF 0x01C4 0FFF 0x01C4 1FFF 0x01C4 202F 0x01C4 2033 0x01C4 23FF 0x01C4 7FFF 0x01C4 83FF 0x01C5 FFFF 0x01C6 3FFF 0x01C6 5FFF 0x01C6 67FF 0x01C6 6FFF 0x01C6 77FF 0x01C6 7FFF 0x01C6 FFFF 0x01C7 3FFF 0x01C7 FFFF 0x01C8 0FFF 0x01C8 1FFF 0x01C8 3FFF 0x01C8 47FF 0x01C8 4FFF 0x01CB FFFF 0x01CD FFFF 0x01CF FFFF 0x01DF FFFF 0x01E0 0FFF 0x01E0 1FFF 0x01E0 3FFF 0x01E0 FFFF 0x01E1 FFFF 0x01E3 FFFF 0x01FF FFFF 0x03FF FFFF 0x05FF FFFF 0x07FF FFFF 0x09FF FFFF 0x0BFF FFFF 0x0FFF FFFF SIZE (Bytes) 236K 128K 128K 128K 1792K ARM/EDMA/SEQUENCER System Module Controller Controller Power Sleep Controller Reserved DDR2 Reserved Reserved Interrupt Controller Reserved Reserved USB2.0 Regs ATA/CF GPIO Reserved Reserved VPSS Regs Reserved EMAC Control Regs EMAC Control Module Regs EMAC Contol Module MDIO Control Regs Reserved Reserved Reserved Reserved Reserved EMIFA Control VLYNQ Control Regs Reserved MMC/SD Reserved Reserved EMIFA Data (CE0) EMIFA Data (CE1) EMIFA Data (CE2) EMIFA Data (CE3) Reserved VLYNQ (Remote) C64x+ System Module Reserved Reserved Power Sleep Controller Reserved DDR2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved EMIFA Data (CE0) EMIFA Data (CE1) EMIFA Data (CE2) EMIFA Data (CE3) Reserved Reserved
PRODUCT PREVIEW
Assignments
Extensive multiplexing used accommodate largest number peripheral functions smallest possible package. multiplexing controlled using combination hardware configuration device reset software programmable register settings.
Device Overview
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
2.6.
(Bottom View)
Figure through Figure show bottom view package assignments four quadrants
RSV3
DDR_D[4]
DDR_D[7]
DDR_D[9]
DDR_D[12]
DDR_D[14]
DDR_CLK0
DDR_CLK0
DDR_A[12]
DDR_A[11]
DDR_D[2]
DDR_D[3]
DDR_D[6]
DDR_D[8]
DDR_D[11]
DDR_D[13]
DDR_D[15]
DDR_CKE
DDR_BS[1]
DDR_A[8]
DDR_D[0]
DDR_D[1]
DDR_D[5]
DDR_DQS[0]
DDR_D[10]
DDR_DQS[1]
DDR_RAS
DDR_BS[0]
DDR_BS[2]
DDR_A[10]
EM_CS5/ GPIO8/ VLYNQ_ CLOCK
EM_CS4/ GPIO9/ VLYNQ_ SCRUN
EM_A[21]/ GPIO10/ VLYNQ_TXD0
DDR_ DQM[0]
DVDDR2
DDR_ DQM[1]
DDR_CAS
DDR_WE
DDR_CS
DDR_VDDDLL
EM_A[12]/ GPIO19
EM_A[16]/ EM_A[17]/ EM_A[20]/ EM_A[19]/ GPIO14/ GPIO11/ GPIO12/ GPIO15/ VLYNQ_TXD2 VLYNQ_RXD0 VLYNQ_TXD1 VLYNQ_RXD2
RSV7
DVDDR2
EM_A[10]/ GPIO2
EM_A[11]/ GPIO20
EM_A[18]/ EM_A[15]/ EM_A[14]/ GPIO13/ GPIO16/ GPIO17/ VLYNQ_TXD3 VLYNQ_RXD3 VLYNQ_RXD
DVDDR2
DVDDR2
DVDDR2
EM_A[6]/ GPIO25
EM_A[7]/ GPIO24
EM_A[8]/ GPIO23
EM_A[13]/ GPIO18
DVDD18
DVDDR2
DVDDR2
PLLVDD18
APLLREFV
EM_A[9]/ GPIO22
DVDD18
CVDD
CVDD
MXI/CLKIN
RSV6
RESET
DVDD18
CVDD
CVDD
CVDD
CLK_OUT0/ GPIO48
EM_A[3]/ GPIO28
EM_A[5]/ GPIO26
EM_A[4]/ GPIO27
DVDD18
CVDDDSP
CVDDDSP
CVDD
Figure 2-2. [Quadrant
Device Overview
PRODUCT PREVIEW
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
DDR_A[6]
DDR_A[5]
DDR_A[0]
DDR_D[16]
DDR_D[18]
DDR_D[21]
DDR_D[27]
DDR_D[29]
RSV4
DDR_A[7]
DDR_A[4]
DDR_A[2]
DDR_D[17]
DDR_D[19]
DDR_D[22]
DDR_D[24]
DDR_D[28]
DDR_D[30]
DDR_A[9]
DDR_A[3]
DDR_A[1]
DDR_DQS[2]
DDR_D[20]
DDR_DQS[3]
DDR_D[25]
DDR_D[26]
DDR_D[31]
PRODUCT PREVIEW
DDR_ VSSDLL
DDR_ZN
DDR_ZP
DDR_DQM[2]
DDR_VREF
DDR_DQM[3]
DDR_D[23]
VSSA_1P1V
DAC_IOUT_D
DVDDR2
DVDDR2
DVDDR2
DAC_RBIAS
DAC_VREF
VDDA_1P8V
DAC_IOUT_C
DVDDR2
DVDDR2
VDDA_1P1V
VSSA_1P8V
DAC_IOUT_B
DAC_IOUT_A
DVDDR2
DVDDR2
RSV12
UART_RTS2
UART_CTS2
UART_TXD2
UART_RXD2
CVDD
DVDD18
RSV15
RSV14
RSV13
RSV1
RSV9
CVDD
DVDD18
RSV19
RSV18
RSV17
RSV16
RSV10
CVDDDSP
CVDD
DVDD18
RSV23
RSV22
RSV2
RSV20
Figure 2-3. [Quadrant
Device Overview
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
CVDDDSP
CVDDDSP
DVDD18
USB_ID
USB_VBUS
USB_ VSSA3P3
USB_ VDDA3P3
CVDDDSP
CVDDDSP
DVDD18
USB_V SS1P8
USB_V DD1P8
USB_R
USB_DM
DVDD18
DVDD33
DVDD33
DVDD33
DVDD18
CVDD
M24VDD
M24VSS
M24XI
M24XO
GPIOV33_10/ RXD3
GPIOV33_7/ RXD0
GPIO
GPIO5/G
YOUT4/R4/ AEAW4
YOUT5/R5
YOUT6/R6
YOUT7/R7
CLK_OUT1/ TIM_IN/ GPIO49
GPIOV33_12/ RXDV
GPIOV33_4/
GPIO2/G0
GPIO38/R
YOUT0/G5/ AEAW0
YOUT1/G6/ AEAW
YOUT2/G7/ AEAW2
YOUT3/R3/ AEAW3
VCLK
GPIOV33_8/
GPIOV33_6/ TXD3
GPIO0/ LCD_OE
GPIO3/B0/ LCD_FIELD
PWM0/ GPIO45
COUT7/G4
HSYNC
VSYNC
VPBECLK
GPIOV33_9/ RXD2
GPIOV33_3/ TXD0
GPIOV33_0/ TXEN
GPIO4/R0
PWM1/R2/ GPIO46
COUT1/B4/ BTSEL
COUT3/B6/ DSP_BT
COUT5/G2
COUT6/G3
GPIOV33_5/ TXD2
GPIOV33_2/
GPIOV33_1/ TXCLK
GPIO6/B
PWM2/ B2/GPIO47
COUT0/B3/ BTSEL0
COUT2/B5/ EM_WIDTH
COUT4/B7
RSV2
BOLD text denotes DaVinci device function
Figure 2-4. [Quadrant
Device Overview
PRODUCT PREVIEW
USB_ VSSREF
USB_ VSSA1P2LD0
USB_ VDDA1P2LD0
USB_DP
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
EM_A[2]/ (CLE)
EM_A[1]/ (ALE)
EM_BA[0]/
EM_A[0]/ DA2/ GPIO53
GPIO50/ ATA_CS0
DVDD18
CVDDDSP
CVDDDSP
GPIO51/ ATA_CS
EM_BA[1]/ DA1/ GPIO52
DMACK/ UART_TXD
EM_OE/(RE)/ (IORD)/DIOR
EM_D14/ DD14
DVDD18
CVDDDSP
CVDDDSP
DMARQ/ UART_RXD
EM_WE/(WE)/ (IOWR)/DIOW
EM_R/W/ INTRQ
EM_D11/
EM_D10/ DD10
PRODUCT PREVIEW
DVDD18
DVDD18
EM_WAIT/ (RDY/BSY)/ IORDY
EM_D13/ DD13
EM_D8/
EM_D6/
EM_D2/
DVDD18
DVDD18
DVDD33
EM_D15/ DD15
EM_D9/
EM_D3/
EM_D4/
EM_D0/
DVDD18
SD_DATA
GPIOV33_15/ MDIO
EM_D12/ DD12
EM_D5/
EM_D1/
RSV5
UART_RXD0/ GPIO35
EMU0
TRST
SD_DATA0
SD_DATA2
GPIOV33_13/ RXER
EM_D7/
EM_CS2
GPIO7
SCL/ GPIO43
UART_TXD0/ GPIO36
FSR/ GPIO32
FSX/ GPIO3
SD_DATA3
GPIOV33_14/
EM_CS3
SPI_EN1/ HDDIR/ GPIO42
SPI_DI/ GPIO40
SDA/GPIO44
RTCK
GPIO33
CLKX/ GPIO29
SD_CMD
GPIOV33_16/ MDCLK
SPI_DO/ GPIO4
SPI_CLK/ GPIO39
SPI_EN0/ GPIO37
GPIO34
CLKR/ GPIO30
SD_CLK
GPIOV33_11/ RXCLK
Figure 2-5. [Quadrant
Device Overview
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
2.6.2
Signal Groups Description
DDR_D[31:0] Data DDR_CLK0 DDR_CLK0_# DDR_CKE DDR_CAS DDR_RAS DDR_WE DDR_DQS[3:0] DDR_REF DVDDR2 DDR_DQM[3] DDR_DQM[2] DDR_DQM[1] DDR_DQM[0] DDR_ZN Byte Enables DDR_ZP Bank Address DDR_VDDDLL DDR_VSSDLL DDR2 Memory Controller (32-bit) DDR_BA[2:0] (1.8
DDR_CS
Memory Space Select External Memory Control
DDR_A[12:0]
Address
Figure 2-6. DDR2 Memory Controller Signals
Device Overview
PRODUCT PREVIEW
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Terminal Functions
terminal functions tables (Table through Table 2-28) identify external signal names, associated (ball) numbers along with mechanical package designator, type, whether internal pullup pulldown resistors, functional description. more detailed information device configuration, peripheral selection, multiplexed/shared pin, debugging considerations, Device Configurations section this data sheet. Table 2-5. BOOT Terminal Functions
SIGNAL NAME TYPE OTHER BOOT COUT0/ BTSEL0 These pins multiplexed between boot mode VPBE. reset, boot mode inputs BTSEL0 BTSEL1 sampled determine boot configuration. below boot modes these inputs. Bootmode section more details. After reset, these video encoder outputs COUT0 COUT1, RGB666/888 Blue output data bits B3/B4. BTSEL1 COUT1/ BTSEL1 I/O/Z DVDD18 COUT2/ EM_WIDTH BTSEL0 Boot Mode Boot (NAND) [default] EMIFA Boot (NOR) Reserved Boot (UART) DESCRIPTION
PRODUCT PREVIEW
I/O/Z
DVDD18
I/O/Z
DVDD18
This multiplexed between EMIFA VPBE. reset, input state sampled EMIFA data width (EM_WIDTH). 8-bit wide EMIFA data bus, EM_WIDTH 16-bit wide EMIFA data bus, EM_WIDTH After reset, video encoder output COUT2 RGB666/888 Blue output data This multiplexed between boot VPBE. reset, input state sampled boot source DSP_BT. booted when DSP_BT=0. boots from EMIFA when DSP_BT=1. After reset, video encoder output COUT3 RGB666/888 Blue data output
COUT3/ DSP_BT YOUT0/ AEAW0 YOUT1/ AEAW1 YOUT2/ AEAW2 YOUT3/ AEAW3 YOUT4/ AEAW4
I/O/Z
DVDD18
I/O/Z
DVDD18 DVDD18 DVDD18 DVDD18 DVDD18
I/O/Z
I/O/Z
These pins multiplexed between EMIFA VPBE. reset, input states AEAW[4:0] sampled EMIFA address width. Peripheral Selection Device Reset section details. After reset, these video encoder outputs YOUT[0:4] RGB666/888 Green data outputs
I/O/Z
I/O/Z
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. pull signal opposite supply rail, resistor should used.) Specifies operating supply voltage each signal
Device Overview
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Table 2-6. Oscillator/PLL Terminal Functions
SIGNAL NAME MXI/ CLKIN MXVDD MXVSS M24XI M24XO M24VDD M24VSS PLLVDD18 APLLREFV TYPE OTHER OSCILLATOR, DVDD18 DVDD18
DESCRIPTION
Crystal input oscillator (system oscillator, typically MHz). internal oscillator bypassed, this external oscillator clock input. Crystal output oscillator 1.8V power supply oscillator Ground oscillator Crystal input oscillator USB) Crystal output oscillator 1.8V power supply oscillator Ground oscillator Volt power supply PLLs (system USB) Core voltage reference logic bandgap backup
DVDD18 DVDD18
Input, Output, High impedance, Supply voltage, Ground, Analog signal Specifies operating supply voltage each signal more information, Recommended Operating Conditions table
Table 2-7. Clock Generator Terminal Functions
SIGNAL NAME TYPE OTHER CLOCK GENERATOR CLK_OUT0/ GPIO48 I/O/Z DVDD18 This multiplexed between PLL1 clock generator GPIO. PLL1 clock generator, clock output CLK_OUT0. This configurable 13.5 clock outputs. GPIO, GPIO48 [default]. This multiplexed between clock generator, timer, GPIO. clock generator, clock output CLK_OUT1. This configurable clock outputs. Timer0, timer event capture input TIM_IN. GPIO, GPIO49 [default]. DESCRIPTION
CLK_OUT1/ TIM_IN/ GPIO49
I/O/Z
DVDD18
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. pull signal opposite supply rail, resistor should used.) Specifies operating supply voltage each signal
Table 2-8. RESET JTAG Terminal Functions
SIGNAL NAME TYPE OTHER RESET RESET DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 This active Global reset input. JTAG JTAG test-port mode select input JTAG test-port data output JTAG test-port data input JTAG test-port clock input DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. pull signal opposite supply rail, resistor should used.) Specifies operating supply voltage each signal Device Overview
PRODUCT PREVIEW
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Table 2-8. RESET JTAG Terminal Functions (continued)
SIGNAL NAME RTCK TRST EMU1 EMU0 TYPE I/O/Z I/O/Z OTHER DVDD18 DVDD18 DVDD18 DVDD18 DESCRIPTION JTAG test-port return clock output JTAG test-port reset. IEEE 1149.1 JTAG compatibility, IEEE 1149.1 JTAG compatibility statement portion this data sheet. Emulation Emulation
Table 2-9. EMIFA Terminal Functions
PRODUCT PREVIEW
SIGNAL NAME
TYPE
OTHER EMIFA BOOT CONFIGURATION
DESCRIPTION
COUT2/ EM_WIDTH
I/O/Z
DVDD18
This multiplexed between EMIFA VPBE. reset, input state sampled EMIFA data width (EM_WIDTH). 8-bit wide EMIFA data bus, EM_WIDTH 16-bit wide EMIFA data bus, EM_WIDTH After reset, video encoder output COUT2 RGB666/888 Blue output data This multiplexed between boot VPBE. reset, input state sampled boot source DSP_BT. booted when DSP_BT=0. boots from EMIFA when DSP_BT=1. After reset, video encoder output COUT3 RGB666/888 Blue data output
COUT3/ DSP_BT YOUT0/ AEAW0 YOUT1/ AEAW1 YOUT2/ AEAW2 YOUT3/ AEAW3 YOUT4/ AEAW4
I/O/Z
DVDD18
I/O/Z
DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 EMIFA FUNCTIONAL PINS: ASYNC
I/O/Z
I/O/Z
These pins multiplexed between EMIFA VPBE. reset, input states AEAW[4:0] sampled EMIFA address width. Peripheral Selection Device Reset section details. After reset, these video encoder outputs YOUT[0:4] RGB666/888 Green data outputs
I/O/Z
I/O/Z
EM_CS2 EM_CS3 EM_CS4/ GPIO9/ VLYNQ_SCRUN
I/O/Z I/O/Z
DVDD18 DVDD18 DVDD18
EMIFA, this Chip Select output EM_CS2 with asynchronous memories (i.e., flash) NAND flash. This chip select default boot boot modes. EMIFA, this Chip Select output EM_CS3 with asynchronous memories (i.e., flash) NAND flash. This multiplexed between EMIFA, GPIO, VLYNQ. EMIFA, Chip Select output EM_CS4 with asynchronous memories (i.e., flash) NAND flash. GPIO, GPIO9. VLYNQ, Serial Clock request VLYNQ_SCRUN. This multiplexed between EMIFA, GPIO, VLYNQ. EMIFA, Chip Select output EM_CS5 with asynchronous memories (i.e., flash) NAND flash. GPIO, GPIO GPIO8 VLYNQ, clock VLYNQ_CLOCK.
I/O/Z
EM_CS5/ GPIO8/ VLYNQ_CLOCK
I/O/Z
DVDD18
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. pull signal opposite supply rail, resistor should used.) Specifies operating supply voltage each signal Device Overview
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Table 2-9. EMIFA Terminal Functions (continued)
SIGNAL NAME EM_R/W/ INTRQ EM_WAIT/ (RDY/BSY)/ IORDY EM_OE/ (RE)/ (IORD)/ DIOR EM_WE (WE) (IOWR)/ DIOW TYPE OTHER DVDD18 DVDD18 DESCRIPTION This multiplexed between EMIFA ATA/CF. EMIFA, read/write output EM_R/W. ATA/CF, interrupt request input INTRQ. This multiplexed between EMIFA (NAND/SmartMedia/xD) ATA/CF. EMIFA, wait state extension input EM_WAIT. NAND/SmartMedia/xD, ready/busy input (RDY/BSY). ATA/CF, Ready input IORDY. This multiplexed between EMIFA (NAND/SmartMedia/xD) ATA/CF. EMIFA, output enable output EM_OE. NAND/SmartMedia/xD, read enable output (RE). read strobe output (IORD). ATA, read strobe output DIOR. This multiplexed between EMIFA (NAND/SmartMedia/xD) ATA/CF. NAND/SmartMedia/xD EMIFA, write enable output EM_WE. NAND/SmartMedia/xD, write enable output (WE). write strobe output (IOWR). ATA, write strobe output DIOW. This multiplexed between EMIFA ATA/CF. EMIFA, this Bank Address output (EM_BA[0]). When connected 8-bit asynchronous memory, this lowest order byte address. When connected 16-bit asynchronous memory, this same function EMIF address (EM_A[22]). ATA/CF, Device address output DA0. This multiplexed between EMIFA, ATA/CF, GPIO. EMIFA, this Bank Address output EM_BA[1]. When connected asynchronous memory this lowest order 16-bit word address. When connected 8-bit asynchronous memory, this address. ATA/CF, Device address output DA1. GPIO mode, GPIO52. This multiplexed between EMIFA, GPIO, VLYNQ. EMIFA, address output EM_A[21]. GPIO, GPIO10. VLYNQ, transmit VLYNQ_TXD0. This multiplexed between EMIFA, GPIO, VLYNQ. EMIFA, address output EM_A[20]. GPIO, GPIO11. VLYNQ, receive input VLYNQ_RXD0. This multiplexed between EMIFA, GPIO, VLYNQ. EMIFA, address output EM_A[19]. GPIO, GPIO12. VLYNQ, transmit output VLYNQ_TXD1. This multiplexed between EMIFA, GPIO, VLYNQ. EMIFA, address output EM_A[18]. GPIO, GPIO13. VLYNQ, receive input VLYNQ_RXD1. This multiplexed between EMIFA, GPIO, VLYNQ. EMIFA, address output EM_A[17]. GPIO, GPIO14. VLYNQ, transmit output VLYNQ_TXD2. This multiplexed between EMIFA, GPIO, VLYNQ. EMIFA, address output EM_A[16]. GPIO, GPIO15. VLYNQ, receive input VLYNQ_RXD2. This multiplexed between EMIFA, GPIO, VLYNQ. EMIFA, address output EM_A[15]. GPIO, GPIO16. VLYNQ, transmit output VLYNQ_TXD3. This multiplexed between EMIFA, GPIO, VLYNQ. EMIFA, address output EM_A[14]. GPIO, GPIO17. VLYNQ, receive input VLYNQ_RXD3. Device Overview
I/O/Z
I/O/Z
I/O/Z
DVDD18
I/O/Z
DVDD18
EM_BA[0]/
I/O/Z
DVDD18
EM_BA[1]/ DA1/ GPIO52
I/O/Z
DVDD18
EM_A[21]/ GPIO10/ VLYNQ_TXD0 EM_A[20]/ GPIO11/ VLYNQ_RXD0 EM_A[19]/ GPIO12/ VLYNQ_TXD1 EM_A[18]/ GPIO13/ VLYNQ_RXD1 EM_A[17]/ GPIO14/ VLYNQ_TXD2 EM_A[16]/ GPIO15/ VLYNQ_RXD2 EM_A[15]/ GPIO16/ VLYNQ_TXD3 EM_A[14]/ GPIO17/ VLYNQ_RXD3
I/O/Z
DVDD18
I/O/Z
DVDD18
I/O/Z
DVDD18
I/O/Z
DVDD18
I/O/Z
DVDD18
I/O/Z
DVDD18
I/O/Z
DVDD18
I/O/Z
DVDD18
PRODUCT PREVIEW
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Table 2-9. EMIFA Terminal Functions (continued)
SIGNAL NAME EM_A[13]/ GPIO18 EM_A[12]/ GPIO19 EM_A[11]/ GPIO20 EM_A[10]/ GPIO21 TYPE OTHER DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DESCRIPTION This multiplexed between EMIFA GPIO. EMIFA, address output EM_A[13]. GPIO, GPIO18. This multiplexed between EMIFA GPIO. EMIFA, address output EM_A[12]. GPIO, GPIO19. This multiplexed between EMIFA GPIO. EMIFA, address output EM_A[11]. GPIO, GPIO20. This multiplexed between EMIFA GPIO. EMIFA, address output EM_A[10]. GPIO, GPIO21. This multiplexed between EMIFA GPIO. EMIFA, address output EM_A[9]. GPIO, GPIO22. This multiplexed between EMIFA GPIO. EMIFA, address output EM_A[8]. GPIO, GPIO23. This multiplexed between EMIFA GPIO. EMIFA, address output EM_A[7]. GPIO, GPIO24. This multiplexed between EMIFA GPIO. EMIFA, address output EM_A[6]. GPIO, GPIO25. This multiplexed between EMIFA GPIO. EMIFA, address output EM_A[5]. GPIO, GPIO26. This multiplexed between EMIFA GPIO. EMIFA, address output EM_A[4]. GPIO, GPIO27. This multiplexed between EMIFA GPIO. EMIFA, address output EM_A[3]. GPIO, GPIO28. EMIFA, this EM_A[2] address line. NAND/SmartMedia/xD, this Command Latch Enable output (CLE). When used EMIFA, address output EM_A[1]. NAND/SmartMedia/xD, Address Latch Enable output (ALE). This multiplexed between EMIFA, ATA/CF, GPIO. EMIFA, this Address output EM_A[0], which least significant 32-bit word address. When connected 16-bit asynchronous memory, this address. 8-bit asynchronous memory, this address. ATA/CF, Device address output DA2. GPIO mode, GPIO53.
I/O/Z
I/O/Z
I/O/Z
I/O/Z
PRODUCT PREVIEW
EM_A[9]/ GPIO22 EM_A[8]/ GPIO23 EM_A[7]/ GPIO24 EM_A[6]/ GPIO25 EM_A[5]/ GPIO26 EM_A[4]/ GPIO27 EM_A[3]/ GPIO28 EM_A[2]/ (CLE) EM_A[1]/ (ALE) EM_A[0]/ DA2/ GPIO53
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z I/O/Z I/O/Z
I/O/Z
DVDD18
Device Overview
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Table 2-9. EMIFA Terminal Functions (continued)
SIGNAL NAME EM_D0/ EM_D1/ EM_D2/ EM_D3/ EM_D4/ EM_D5/ EM_D6/ EM_D7/ EM_D8/ EM_D9/ EM_D10/ DD10 EM_D11/ DD11 EM_D12/ DD12 EM_D13/ DD13 EM_D14/ DD14 EM_D15/ DD15 EM_A[1]/ (ALE) EM_A[2]/ (CLE) EM_WAIT/ (RDY/BSY)/ IORDY EM_OE/ (RE)/ (IORD)/ DIOR EM_WE (WE) (IOWR)/ DIOW EM_CS2 EM_CS3 TYPE I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z OTHER DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DESCRIPTION
DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 EMIFA FUNCTIONAL PINS: NAND SMARTMEDIA DVDD18 DVDD18 DVDD18 When used EMIFA, address output EM_A[1]. NAND/SmartMedia/xD, Address Latch Enable output (ALE). EMIFA, this EM_A[2] address line. NAND/SmartMedia/xD, this Command Latch Enable output (CLE). This multiplexed between EMIFA (NAND/SmartMedia/xD) ATA/CF. EMIFA, wait state extension input EM_WAIT. NAND/SmartMedia/xD, ready/busy input (RDY/BSY). ATA/CF, Ready input IORDY. This multiplexed between EMIFA (NAND/SmartMedia/xD) ATA/CF. EMIFA, output enable output EM_OE. NAND/SmartMedia/xD, read enable output (RE). read strobe output (IORD). ATA, read strobe output DIOR. This multiplexed between EMIFA (NAND/SmartMedia/xD) ATA/CF. EMIFA, write enable output EM_WE. NAND/SmartMedia/xD, write enable output (WE). write strobe output (IOWR). ATA, write strobe output DIOW. EMIFA, this Chip Select output EM_CS2 with asynchronous memories (i.e. flash) NAND flash. This chip select default boot boot modes. EMIFA, this Chip Select output EM_CS3 with asynchronous memories (i.e. flash) NAND flash. These pins multiplexed between EMIFA (NAND) ATA/CF. cases they used bi-directional data bus. EMIFA (NAND), these EM_D[15:0]. ATA/CF, these DD[15:0].
I/O/Z I/O/Z
I/O/Z
I/O/Z
DVDD18
I/O/Z
DVDD18
I/O/Z I/O/Z
DVDD18 DVDD18
Device Overview
PRODUCT PREVIEW
DVDD18
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Table 2-9. EMIFA Terminal Functions (continued)
SIGNAL NAME EM_CS4/ GPIO9/ VLYNQ_SCRUN TYPE OTHER DESCRIPTION This multiplexed between EMIFA, GPIO, VLYNQ. EMIFA, Chip Select output EM_CS4 with asynchronous memories (i.e., flash) NAND flash. GPIO, GPIO9. VLYNQ, Serial Clock request VLYNQ_SCRUN. This multiplexed between EMIFA, GPIO, VLYNQ. EMIFA, Chip Select output EM_CS5 with asynchronous memories (i.e., flash) NAND flash. GPIO, GPIO GPIO8 VLYNQ, clock VLYNQ_CLOCK.
I/O/Z
DVDD18
EM_CS5/ GPIO8/ VLYNQ_CLOCK EM_D0/
I/O/Z
DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18
I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z
PRODUCT PREVIEW
EM_D1/ EM_D2/ EM_D3/ EM_D4/ EM_D5/ EM_D6/ EM_D7/ EM_D8/ EM_D9/ EM_D10/ DD10 EM_D11/ DD11 EM_D12/ DD12 EM_D13/ DD13 EM_D14/ DD14 EM_D15/ DD15
These pins multiplexed between EMIFA (NAND) ATA/CF. cases they used bi-directional data bus. EMIFA (NAND), these EM_D[15:0]. ATA/CF, these DD[15:0].
Device Overview
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Table 2-10. DDR2 Memory Controller Terminal Functions
SIGNAL NAME DDR_CLK0 DDR_CLK0 DDR_CKE DDR_CS DDR_WE DDR_DQM[3] DDR_DQM[2] DDR_DQM[1] DDR_DQM[0] DDR_RAS DDR_CAS DDR_DQS[0] DDR_DQS[1] DDR_DQS[2] DDR_DQS[3] DDR_BS[0] DDR_BS[1] DDR_BS[2] DDR_A[12] DDR_A[11] DDR_A[10] DDR_A[9] DDR_A[8] DDR_A[7] DDR_A[6] DDR_A[5] DDR_A[4] DDR_A[3] DDR_A[2] DDR_A[1] DDR_A[0] I/O/Z DVDDR2 DDR2 address I/O/Z DVDDR2 Bank select outputs (BS[2:0]). required support DDR2 memories. TYPE OTHER DDR2 Memory Controller I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DDR2 Clock DDR2 Differential clock DDR2 Clock Enable DDR2 Active chip select DDR2 Active Write enable DDR2 Data mask outputs DQM3: upper byte data DDR_D[31:24] DQM2: DDR_D[23:16] DQM1: DDR_D[15:8] DQM0: lower byte DDR_D[7:0] DDR2 Access Signal output DDR2 Column Access Signal output Data strobe input/outputs each byte 32-bit data bus. They outputs DDR2 memory when writing inputs when reading. They used synchronize data transfers. DQS3 upper byte DDR_D[31:24] DQS2: DDR_D[23:16] DQS1: DDR_D[15:8] DQS0: bottom byte DDR_D[7:0] DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Specifies operating supply voltage each signal more information, Recommended Operating Conditions table
Device Overview
PRODUCT PREVIEW
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Table 2-10. DDR2 Memory Controller Terminal Functions (continued)
SIGNAL NAME DDR_D[31] DDR_D[30] DDR_D[29] DDR_D[28] DDR_D[27] DDR_D[26] DDR_D[25] DDR_D[24] DDR_D[23]
TYPE
OTHER
DESCRIPTION
PRODUCT PREVIEW
DDR_D[22] DDR_D[21] DDR_D[20] DDR_D[19] DDR_D[18] DDR_D[17] DDR_D[16] DDR_D[15] DDR_D[14] DDR_D[13] DDR_D[12] DDR_D[11] DDR_D[10] DDR_D[9] DDR_D[8] DDR_D[7] DDR_D[6] DDR_D[5] DDR_D[4] DDR_D[3] DDR_D[2] DDR_D[1] DDR_D[0] DDR_VREF DDR_VSSDLL DDR_VDDDLL DDR_ZN DDR_ZP
I/O/Z
DVDDR2
DDR2 data configured bits wide bits wide.
Reference voltage input SSTL_18 buffers. Ground DDR2 Power (1.8 Volts) DDR2 Impedance control DDR2 outputs. This must connected resistor DVDDR2. Impedance control DDR2 outputs. This must connected resistor VSS.
Device Overview
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Table 2-11. Terminal Functions
SIGNAL NAME SCL/ GPIO43 SDA/ GPIO44 TYPE OTHER I/O/Z I/O/Z DVDD18 DVDD18 This multiplexed between GPIO. I2C, clock output SCL. GPIO, GPIO43. This multiplexed between GPIO. I2C, bi-directional data signal SDA. GPIO, GPIO44. DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. pull signal opposite supply rail, resistor should used.) Specifies operating supply voltage each signal
SIGNAL NAME
TYPE
OTHER Audio Serial Port (ASP)
DESCRIPTION
CLKX/ GPIO29 CLKR/ GPIO30 FSX/ GPIO31 FSR/ GPIO32 GPIO33 GPIO34
I/O/Z
DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18
This multiplexed between GPIO. ASP, Transmit clock CLKX. GPIO, GPIO29. This multiplexed between GPIO. ASP, Receive clock CLKR. GPIO, GPIO30 This multiplexed between GPIO. ASP, Transmit frame synchronization FSX. GPIO, GPIO31. This multiplexed between GPIO. ASP, Receive frame synchronization FSR. GPIO, GPIO32. This multiplexed between GPIO. ASP, Data Transmit output GPIO, GPIO33. This multiplexed between GPIO. ASP, Data Receive input GPIO, GPIO34.
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. pull signal opposite supply rail, resistor should used.) Specifies operating supply voltage each signal
Table 2-13. Terminal Functions
SIGNAL NAME TYPE OTHER Serial Port Interface (SPI) SPI_EN0/ GPIO37 SPI_EN1/ HDDIR/ GPIO42 SPI_CLK/ GPIO39 I/O/Z DVDD18 DVDD18 DVDD18 This multiplexed between GPIO. When used SPI, slave device enable output SPI_EN0. GPIO, GPIO37. This multiplexed between SPI, ATA, GPIO. When used SPI, slave device enable output SPI_EN1. ATA, buffer direction control output HDDIR. GPIO, GPIO42. This multiplexed between GPIO. SPI, clock output SPI_CLK. GPIO, GPIO39. DESCRIPTION
I/O/Z
I/O/Z
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. pull signal opposite supply rail, resistor should used.) Specifies operating supply voltage each signal Device Overview
PRODUCT PREVIEW
Table 2-12. Audio Serial Port (ASP) Terminal Functions
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Table 2-13. Terminal Functions (continued)
SIGNAL NAME SPI_DI/ GPIO40 SPI_DO/ GPIO41 TYPE I/O/Z I/O/Z OTHER DVDD18 DVDD18 DESCRIPTION This multiplexed between GPIO. SPI, data input SPI_DI. GPIO, GPIO40. This multiplexed between GPIO. data output SPI_DO. GPIO, GPIO41.
Table 2-14. EMAC MDIO Terminal Functions
SIGNAL NAME TYPE OTHER EMAC DESCRIPTION
PRODUCT PREVIEW
GPIOV33_0/ TXEN GPIOV33_1/ TXCLK GPIOV33_2/ GPIOV33_6/ TXD3 GPIOV33_5/ TXD2 GPIOV33_4/ TXD1 GPIOV33_3/ TXD0 GPIOV33_11/ RXCLK GPIOV33_12/ RXDV GPIOV33_13/ RXER GPIOV33_14/ GPIOV33_10/ RXD3 GPIOV33_9/ RXD2 GPIOV33_8/
I/O/Z
DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33
This multiplexed between GPIO Ethernet MAC. GPIO mode, this 3.3V GPIO GPIOV33_0. Ethernet mode, Transmit Enable output TXEN. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_1. Ethernet mode, Transmit Clock output TXCLK. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_2. Ethernet mode, Collision Detect input COL. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_6. Ethernet mode, Transmit Data output TXD3. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_5. Ethernet mode, Transmit Data output TXD2. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_4. Ethernet mode, Transmit Data output TXD1. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_3. Ethernet mode, Transmit Data output TXD0. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_11. Ethernet mode, Receive Clock input RXCLK. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_12. Ethernet mode, Receive Data Valid input RXDV. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_13. Ethernet mode, Receive Error input RXER. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_14. Ethernet mode, Carrier Sense input CRS. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_10. Ethernet mode, Receive Data input RXD3. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_9. Ethernet mode, Receive Data input RXD2. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_8. Ethernet mode, Receive data input RXD1.
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. pull signal opposite supply rail, resistor should used.) Specifies operating supply voltage each signal Device Overview
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Table 2-14. EMAC MDIO Terminal Functions (continued)
SIGNAL NAME GPIOV33_7/ RXD0 TYPE OTHER DVDD33 DESCRIPTION This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_7. Ethernet mode, Receive Data input RXD0. MDIO GPIOV33_16/ MDCLK GPIOV33_15/ MDIO I/O/Z DVDD33 DVDD33 This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_16. Ethernet mode, Management Data Clock output MDCLK. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_15. Ethernet mode, Management Data MDIO.
I/O/Z
I/O/Z
Table 2-15. GPIOV33 Terminal Functions
SIGNAL NAME TYPE OTHER GPIOV33 GPIOV33_16/ MDCLK GPIOV33_15/ MDIO GPIOV33_14/ GPIOV33_13/ RXER GPIOV33_12/ RXDV GPIOV33_11/ RXCLK GPIOV33_10/ RXD3 GPIOV33_9/ RXD2 GPIOV33_8/ RXD1 GPIOV33_7/ RXD0 GPIOV33_6/ TXD3 GPIOV33_5/ TXD2 I/O/Z DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_16. Ethernet mode, Management Data Clock output MDCLK. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_15. Ethernet mode, Management Data MDIO. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_14. Ethernet mode, Carrier Sense input CRS. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_13. Ethernet mode, Receive Error input RXER. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_12. Ethernet mode, Receive Data Valid input RXDV. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_11. Ethernet mode, Receive Clock input RXCLK. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_10. Ethernet mode, Receive Data input RXD3. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_9. Ethernet mode, Receive Data input RXD2. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_8. Ethernet mode, Receive data input RXD1. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_7. Ethernet mode, Receive Data input RXD0. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_6. Ethernet mode, Transmit Data output TXD3. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_5. Ethernet mode, Transmit Data output TXD2. DESCRIPTION
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. pull signal opposite supply rail, resistor should used.) Specifies operating supply voltage each signal Device Overview
PRODUCT PREVIEW
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Table 2-15. GPIOV33 Terminal Functions (continued)
SIGNAL NAME GPIOV33_4/ TXD1 GPIOV33_3/ TXD0 GPIOV33_2/ GPIOV33_1/ TXCLK TYPE OTHER DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DESCRIPTION This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_4. Ethernet mode, Transmit Data output TXD1. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_3. Ethernet mode, Transmit Data output TXD0. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_2. Ethernet mode, Collision Detect input COL. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_1. Ethernet mode, Transmit Clock output TXCLK. This multiplexed between GPIO Ethernet MAC. GPIO mode, this 3.3V GPIO GPIOV33_0. Ethernet mode, Transmit Enable output TXEN.
I/O/Z
I/O/Z
I/O/Z
I/O/Z
PRODUCT PREVIEW
GPIOV33_0/ TXEN
I/O/Z
Table 2-16. Standalone GPIOV18 Terminal Functions
SIGNAL NAME TYPE OTHER Standalone GPIO18 GPIO7 GPIO1 I/O/Z I/O/Z DVDD18 DVDD18 This standalone functions GPIO7. This standalone functions GPIO1. DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. pull signal opposite supply rail, resistor should used.) Specifies operating supply voltage each signal
Table 2-17. Terminal Functions
SIGNAL NAME M24XI M24X0 M24VDD M24VSS PLLVDD18 USB_VBUS USB_ID USB_DP USB_DM USB_R1 USB_VSSREF USB_VDDA3P3 USB_VSSA3P3 TYPE OTHER
DESCRIPTION
DVDD18 DVDD18
Crystal input oscillator USB) Crystal output oscillator 1.8V power supply oscillator Ground oscillator Volt power supply PLLs (system USB) input that signifies that VBUS connected operating mode identification pin. Host mode operation, pull down this ground (VSS) external 1.5-k resistor. Device mode operation, pull this DVDD33 rail external 1.5-k resistor. bi-directional Data Differential signal pair [positive/negative]. Reference current output. This must connected resistor USB_VSSREF. Ground reference current. Analog power supply Analog ground
Input, Output, High impedance, Supply voltage, Ground, Analog signal Specifies operating supply voltage each signal more information, Recommended Operating Conditions table Device Overview
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Table 2-17. Terminal Functions (continued)
SIGNAL NAME USB_VDD1P8 USB_VSS1P8 USB_VDDA1P2LDO USB_VSSA1P2LDO TYPE OTHER
DESCRIPTION power supply Ground Core Power supply output phy. This must connected capacitor USB_VSSA1P2LDO. connect this other supply pins. Core Ground phy. This must connected capacitor USB_VDDA1P2LDO.
Table 2-18. VLYNQ Terminal Functions
SIGNAL NAME
VLYNQ EM_CS5/ GPIO8/ VLYNQ_CLOCK DVDD18 This multiplexed between EMIFA, GPIO, VLYNQ. EMIFA, Chip Select output EM_CS5 with asynchronous memories (i.e., flash) NAND flash. GPIO, GPIO GPIO8 VLYNQ, clock (VLYNQ_CLOCK). This multiplexed between EMIFA, GPIO, VLYNQ. EMIFA, Chip Select output EM_CS4 with asynchronous memories (i.e., flash) NAND flash. GPIO, GPIO9. VLYNQ, Serial Clock request (VLYNQ_SCRUN). This multiplexed between EMIFA, GPIO, VLYNQ. EMIFA, address output EM_A[15]. GPIO, GPIO16. VLYNQ, transmit output VLYNQ_TXD3. This multiplexed between EMIFA, GPIO, VLYNQ. EMIFA, address output EM_A[17]. GPIO, GPIO14. VLYNQ, transmit output VLYNQ_TXD2. This multiplexed between EMIFA, GPIO, VLYNQ. EMIFA, address output EM_A[19]. GPIO, GPIO12. VLYNQ, transmit output VLYNQ_TXD1. This multiplexed between EMIFA, GPIO, VLYNQ. EMIFA, address output EM_A[21]. GPIO, GPIO10. VLYNQ, transmit (VLYNQ_TXD0). This multiplexed between EMIFA, GPIO, VLYNQ. EMIFA, address output EM_A[14]. GPIO, GPIO17. VLYNQ, receive input VLYNQ_RXD3. This multiplexed between EMIFA, GPIO, VLYNQ. EMIFA, address output EM_A[16]. GPIO, GPIO15. VLYNQ, receive input VLYNQ_RXD2. This multiplexed between EMIFA, GPIO, VLYNQ. EMIFA, address output EM_A[18]. GPIO, GPIO13. VLYNQ, receive input VLYNQ_RXD1. This multiplexed between EMIFA, GPIO, VLYNQ. EMIFA, address output EM_A[20]. GPIO, GPIO11. VLYNQ, receive input VLYNQ_RXD0.
I/O/Z
EM_CS4/ GPIO9/ VLYNQ_SCRUN EM_A[15]/ GPIO16/ VLYNQ_TXD3 EM_A[17]/ GPIO14/ VLYNQ_TXD2 EM_A[19]/ GPIO12/ VLYNQ_TXD1 EM_A[21]/ GPIO10/ VLYNQ_TXD0 EM_A[14]/ GPIO17/ VLYNQ_RXD3 EM_A[16]/ GPIO15/ VLYNQ_RXD2 EM_A[18]/ GPIO13/ VLYNQ_RXD1 EM_A[20]/ GPIO11/ VLYNQ_RXD0
I/O/Z
DVDD18
I/O/Z
DVDD18
I/O/Z
DVDD18
I/O/Z
DVDD18
I/O/Z
DVDD18
I/O/Z
DVDD18
I/O/Z
DVDD18
I/O/Z
DVDD18
I/O/Z
DVDD18
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. pull signal opposite supply rail, resistor should used.) Specifies operating supply voltage each signal
Device Overview
PRODUCT PREVIEW
TYPE
OTHER
DESCRIPTION
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Table 2-19. VPBE Terminal Functions
SIGNAL NAME TYPE OTHER VIDEO (VPBE) HSYNC VSYNC VCLK VPBECLK I/O/Z I/O/Z I/O/Z I/O/Z DVDD18 DVDD18 DVDD18 DVDD18 VPBE Horizontal Synch Output VPBE Vertical Synch Output VPBE Clock Output VPBE Clock Input These pins multiplexed between boot mode VPBE. reset, boot mode inputs BTSEL0 BTSEL1 sampled determine boot configuration. below boot modes these inputs. Bootmode section more details. After reset, these video encoder outputs COUT0 COUT1, RGB666/888 Blue output data bits B3/B4. BTSEL1 COUT1/ BTSEL1 I/O/Z DVDD18 COUT2/ EM_WIDTH BTSEL0 Boot Mode Boot (NAND) [default] EMIFA Boot (NOR) Reserved Boot (UART) DESCRIPTION
PRODUCT PREVIEW
COUT0/ BTSEL0
I/O/Z
DVDD18
I/O/Z
DVDD18
This multiplexed between EMIFA VPBE. reset, input state sampled EMIFA data width (EM_WIDTH). 8-bit wide EMIFA data bus, EM_WIDTH [default]. 16-bit wide EMIFA data bus, EM_WIDTH After reset, video encoder output COUT2 RGB666/888 Blue output data This multiplexed between boot VPBE. reset, input state sampled boot source DSP_BT. booted when DSP_BT=0. boots from EMIFA when DSP_BT=1. After reset, video encoder output COUT3 RGB666/888 Blue data output Video encoder output COUT4 RGB666/888 Blue data output Video encoder output COUT5 RGB666/888 Green data output Video encoder output COUT6 RGB666/888 Green data output Video encoder output COUT7 RGB666/888 Green data output
COUT3/ DSP_BT COUT4/ COUT5/ COUT6/ COUT7/
I/O/Z
DVDD18
I/O/Z I/O/Z I/O/Z I/O/Z
DVDD18 DVDD18 DVDD18 DVDD18
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. pull signal opposite supply rail, resistor should used.) Specifies operating supply voltage each signal
Device Overview
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Table 2-19. VPBE Terminal Functions (continued)
SIGNAL NAME YOUT0/ AEAW0 YOUT1/ AEAW1 YOUT2/ AEAW2 YOUT3/ AEAW3 YOUT4/ AEAW4 YOUT5/ YOUT6/ YOUT7/ GPIO0/ LCD_OE GPIO2/ GPIO3/ LCD_FIELD GPIO4/ GPIO5/ GPIO6/ GPIO38/ PWM1/ GPIO46 PWM2/ GPIO47 TYPE OTHER DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 Video encoder output YOUT5 RGB666/888 data output Video encoder output YOUT6 RGB666/888 data output Video encoder output YOUT7 RGB666/888 data output This multiplexed between GPIO VPBE. GPIO mode, GPIO GPIO0. VPBE mode, output enable LCD_OE. This multiplexed between GPIO VPBE. GPIO mode, GPIO GPIO2. VPBE mode, RGB888 Green data output This multiplexed between GPIO, VPBE. GPIO mode, GPIO GPIO3. VPBE mode, RGB888 Blue data output interlaced output LCD_FIELD. This multiplexed between GPIO VPBE. GPIO mode, GPIO GPIO4. VPBE mode, RGB888 data output This multiplexed between GPIO VPBE. GPIO mode, GPIO GPIO5. VPBE mode, RGB888 Green data output This multiplexed between GPIO VPBE. GPIO mode, GPIO GPIO6. VPBE mode, RGB888 Blue data output This multiplexed between VPBE GPIO. When used GPIO, GPIO38. VPBE mode, RGB888 output data This multiplexed between PWM1, VPBE, GPIO. PWM1, output PWM1. VPBE mode, RGB888 output (R2). GPIO, GPIO46. This multiplexed between PWM2, VPBE, GPIO. PWM2, output PWM2. VPBE mode, RGB888 Blue output (B2). GPIO, GPIO47. DESCRIPTION
I/O/Z
I/O/Z
I/O/Z
These pins multiplexed between EMIFA VPBE. reset, input states AEAW[4:0] sampled EMIFA address width. Peripheral Selection Device Reset section details. After reset, these video encoder outputs YOUT[0:4] RGB666/888 Green data outputs
I/O/Z
I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
DVDD18
Device Overview
PRODUCT PREVIEW
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Table 2-20. [Part VPBE] Terminal Functions
SIGNAL NAME DAC_VREF DAC_IOUT_A DAC_IOUT_B DAC_IOUT_C DAC_IOUT_D VDDA_1P8V VSSA_1P8V VDDA_1P1V VSSA_1P1V DAC_RBIAS TYPE OTHER DAC[A:D]
DESCRIPTION
Reference voltage input (0.5 Output Output Output Output Analog power Analog ground 1.20 Analog core supply voltage (-594 device) Analog core ground External resistor connection current bias configuration. This must connected resistor VSSA_1P8V.
PRODUCT PREVIEW
Input, Output, High impedance, Supply voltage, Ground, Analog signal Specifies operating supply voltage each signal more information, Recommended Operating Conditions table
Table 2-21. UART0, UART1, UART2 Terminal Functions
SIGNAL NAME TYPE OTHER UART2 UART_RXD2 UART_TXD2 UART_CTS2 UART_RTS2 I/O/Z I/O/Z I/O/Z I/O/Z DVDD18 DVDD18 DVDD18 DVDD18 Receive data input UART_RXD2 Transmit data output UART_TXD2 Clear send input UART_CTS2 Ready send output UART_RTS2 UART1 DMACK/ UART_TXD1 DMARQ/ UART_RXD1 I/O/Z DVDD18 DVDD18 This multiplexed between ATA/CF UART1. ATA/CF, acknowledge output DMACK. UART1, transmit data output UART_TXD1. This multiplexed between ATA/CF UART1. ATA/CF, request DMARQ input. UART1, receive data input UART_RXD1. UART0 UART_RXD0/ GPIO35 UART_TXD0/ GPIO36 I/O/Z DVDD18 DVDD18 This multiplexed between UART0 GPIO. UART0, Receive Data input UART_RXD0. GPIO, GPIO35. This multiplexed between UART0 GPIO. UART0, Transmit Data output UART_TXD0. GPIO, GPIO36. DESCRIPTION
I/O/Z
I/O/Z
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. pull signal opposite supply rail, resistor should used.) Specifies operating supply voltage each signal
Device Overview
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Table 2-22. PWM0, PWM1, PWM2 Terminal Functions
SIGNAL NAME TYPE OTHER PWM2 PWM2/ GPIO47 I/O/Z DVDD18 This multiplexed between PWM2, VPBE, GPIO. PWM2, output PWM2. VPBE, RGB888 Blue output (B2). GPIO, GPIO47. PWM1 PWM1/ GPIO46 I/O/Z DVDD18 This multiplexed between PWM1, VPBE, GPIO. PWM1, output PWM1. VPBE, RGB888 output (R2). GPIO, GPIO46. This multiplexed between PWM0 GPIO. PWM0, output PWM0. GPIO, GPIO45. DESCRIPTION
PWM0/ GPIO45
I/O/Z
DVDD18
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. pull signal opposite supply rail, resistor should used.) Specifies operating supply voltage each signal
Table 2-23. ATA/CF Terminal Functions
SIGNAL NAME TYPE OTHER ATA/CF SPI_EN1/ HDDIR/ GPIO42 GPIO50/ ATA_CS0 GPIO51/ ATA_CS1 EM_R/W/ INTRQ EM_WAIT/ (RDY/BSY)/ IORDY EM_OE/ (RE)/ (IORD)/ DIOR EM_WE (WE) (IOWR)/ DIOW DMACK/ UART_TXD1 DMARQ/ UART_RXD1 I/O/Z DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 This multiplexed between SPI, ATA, GPIO. When used SPI, slave device enable output SPI_EN1. ATA, buffer direction control output HDDIR. GPIO, GPIO42. This multiplexed between GPIO ATA/CF. GPIO mode, GPIO50. mode, ATA/CF chip select output ATA_CS0. This multiplexed between GPIO ATA/CF. GPIO mode, GPIO51. mode, ATA/CF chip select output ATA_CS1. This multiplexed between EMIFA ATA/CF. EMIFA, EMIF read/write output EM_R/W. ATA/CF, interrupt request input INTRQ. This multiplexed between EMIFA (NAND/SmartMedia/xD) ATA/CF. EMIFA, wait state extension input EM_WAIT. NAND/SmartMedia/xD, ready/busy input (RDY/BSY). ATA/CF, Ready input IORDY. This multiplexed between EMIFA (NAND/SmartMedia/xD) ATA/CF. EMIFA, output enable output EM_OE. NAND/SmartMedia/xD, read enable output (RE). read strobe output (IORD). ATA, read strobe output DIOR. This multiplexed between EMIFA (NAND/SmartMedia/xD) ATA/CF. EMIFA, write enable output EM_WE. NAND/SmartMedia/xD, write enable output (WE). write strobe output (IOWR). ATA, write strobe output DIOW. This multiplexed between ATA/CF UART1. ATA/CF, acknowledge output DMACK. UART1, transmit data output UART_TXD1. This multiplexed between ATA/CF UART1. ATA/CF, request DMARQ input. UART1, receive data input UART_RXD1. DESCRIPTION
DVDD18
DVDD18
DVDD18 DVDD18
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. pull signal opposite supply rail, resistor should used.) Specifies operating supply voltage each signal Device Overview
PRODUCT PREVIEW
PWM0
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Table 2-23. ATA/CF Terminal Functions (continued)
SIGNAL NAME EM_D15/ DD15 EM_D14/ DD14 EM_D13/ DD13 EM_D12/ DD12 EM_D11/ DD11 EM_D10/ DD10 EM_D9/ EM_D8/ EM_D7/ EM_D6/ EM_D5/ EM_D4/ EM_D3/ EM_D2/ EM_D1/ EM_D0/ EM_A[0]/ DA2/ GPIO53 I/O/Z This multiplexed between EMIFA, ATA/CF, GPIO. EMIFA, this Address output EM_A[0], which least significant 32-bit word address. When connected 16-bit asynchronous memory, this address. 8-bit asynchronous memory, this address. ATA/CF, Device address output DA2. GPIO mode, GPIO53. This multiplexed between EMIFA, ATA/CF, GPIO. EMIFA, this Bank Address output EM_BA[1]. When connected asynchronous memory this lowest order 16-bit word address. When connected 8-bit asynchronous memory, this address. ATA/CF, Device address output DA1. GPIO mode, GPIO52. This multiplexed between EMIFA ATA/CF. EMIFA, this Bank Address output EM_BA[0]. When connected 8-bit asynchronous memory, this lowest order byte address. When connected 16-bit asynchronous memory, this same function EMIF address EM_A[22]. ATA/CF, Device address output DA0. These pins multiplexed between EMIFA (NAND) ATA/CF. cases they used bi-directional data bus. EMIFA (NAND), these EM_D[15:0]. ATA/CF, these DD[15:0]. TYPE OTHER DESCRIPTION
PRODUCT PREVIEW
DVDD18
I/O/Z
DVDD18
EM_BA[1]/ DA1/ GPIO52
I/O/Z
DVDD18
EM_BA[0]/
I/O/Z
DVDD18
Device Overview
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Table 2-24. MMC/SD Terminal Functions
SIGNAL NAME TYPE OTHER MMC/SD SD_CLK SD_CMD SD_DATA3 SD_DATA2 SD_DATA1 SD_DATA0 I/O/Z I/O/Z I/O/Z I/O/Z DVDD33 These pins nibble wide bi-directional data SD_DATA[3:0]. DVDD33 DVDD33 Data clock output SD_CLK Command output SD_CMD DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. pull signal opposite supply rail, resistor should used.) Specifies operating supply voltage each signal
Table 2-25. Timer Timer Timer Terminal Functions
SIGNAL NAME TYPE OTHER Timer Timer external pins. Timer Timer peripheral pins pinned external pins. Timer CLK_OUT1/ TIM_IN/ GPIO49 DVDD18 This multiplexed between clock generator, timer, GPIO. clock generator, clock output CLK_OUT1. This configurable clock outputs. Timer0, timer event capture input TIM_IN. GPIO, GPIO49. DESCRIPTION
I/O/Z
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. pull signal opposite supply rail, resistor should used.) Specifies operating supply voltage each signal
Table 2-26. Reserved Terminal Functions
SIGNAL NAME RSV1 RSV2 RSV3 RSV4 RSV5 RSV6 RSV7 RSV9 RSV10 RSV11 RSV12 RSV13 I/O/Z I/O/Z TYPE OTHER RESERVED Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. This must tied directly normal device operation. Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. This must tied directly normal device operation. Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. pull signal opposite supply rail, resistor should used.) Specifies operating supply voltage each signal Device Overview
PRODUCT PREVIEW
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Table 2-26. Reserved Terminal Functions (continued)
SIGNAL NAME RSV14 RSV15 RSV16 RSV17 RSV18 RSV19 RSV20 RSV21 RSV22 TYPE OTHER DESCRIPTION Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground)
PRODUCT PREVIEW
RSV23
Table 2-27. Supply Terminal Functions
SIGNAL NAME DVDD33 DVDD18 Input, Output, High impedance, Supply voltage, Ground, Analog signal supply voltage (see Power-Supply Decoupling section this data sheet) supply voltage (see Power-Supply Decoupling section this data sheet) TYPE OTHER SUPPLY VOLTAGE PINS DESCRIPTION
Device Overview
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Table 2-27. Supply Terminal Functions (continued)
SIGNAL NAME DVDDR2 CVDD CVDDDSP 1.20 DSPSS supply voltage (-594 devices) (see Power-Supply Decoupling section this data sheet) 1.20 core supply voltage (-594 device) (see Power-Supply Decoupling section this data sheet) DDR2 supply voltage (see Power-Supply Decoupling section this data sheet) TYPE OTHER DESCRIPTION
Device Overview
PRODUCT PREVIEW
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Table 2-28. Ground Terminal Functions
SIGNAL NAME Input, Output, High impedance, Supply voltage, Ground, Analog signal Ground pins TYPE OTHER GROUND PINS DESCRIPTION
PRODUCT PREVIEW
Device Overview
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Table 2-28. Ground Terminal Functions (continued)
SIGNAL NAME Ground pins TYPE OTHER DESCRIPTION
Device Overview
PRODUCT PREVIEW
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
2.8.
Device Support Development Support
offers extensive line development tools TMS320DM644x platform, including tools evaluate performance processors, generate code, develop algorithm implementations, fully integrate debug software hardware modules. tool's support documentation electronically available within Code Composer StudioIntergrated Development Environment (IDE). following products support development TMS320DM644x SoC-based applications: Software Development Tools: Code Composer StudioIntegrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP/BIOSTM), which provides basic run-time target software needed support application. Hardware Development Tools: Extended Development System (XDSTM) Emulator (supports TMS320DM644x multiprocessor system debug) (Evaluation Module) complete listing development-support tools TMS320DM644x platform, visit Texas Instruments site Worldwide http://www.ti.com uniform resource locator (URL). information pricing availability, contact nearest field sales office authorized distributor.
PRODUCT PREVIEW
Device Overview
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
2.8.2
Device Development-Support Tool Nomenclature
designate stages product development cycle, assigns prefixes part numbers devices support tools. Each commercial family member three prefixes: TMX, TMP, (e.g., TMX320DM6443ZWT). Texas Instruments recommends three possible prefix designators support tools: TMDX TMDS. These prefixes represent evolutionary stages product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Device development evolutionary flow: Experimental device that necessarily representative final device's electrical specifications. Final silicon that conforms device's electrical specifications completed quality reliability verification. Fully-qualified production device.
Support tool development evolutionary flow: TMDX TMDS Development-support product that completed Texas Instruments internal qualification testing. Fully qualified development-support product.
devices TMDX development-support tools shipped against following disclaimer: "Developmental product intended internal evaluation purposes." devices TMDS development-support tools have been characterized fully, quality reliability device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (TMX TMP) have greater failure rate than standard production devices. Texas Instruments recommends that these devices used production system because their expected end-use failure rate still undefined. Only qualified production devices used. device nomenclature also includes suffix with device family name. This suffix indicates package type (for example, ZWT), temperature range (for example, "Blank" commercial temperature range), device speed range megahertz (for example, "Blank" default [594-MHz DSP, 297-MHz ARM9]). Figure provides legend reading complete device name TMS320DM644x platform member.
Device Overview
PRODUCT PREVIEW
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
DM6443 PREFIX Experimental device Qualified device
DEVICE SPEED RANGE Blank 594-MHz DSP, 297-MHz ARM9 [Default]
DEVICE FAMILY TMS320t family
TEMPERATURE RANGE (DEFAULT: 85°C) Blank 85°C, commercial temperature
DEVICE(B) DM644x DSP: DM6443 DM6446
PACKAGE TYPE(A) 361-pin plastic BGA, with Pb-free soldered balls
SILICON REVISION Blank Initial Silicon Ball Grid Array actual device part numbers (P/Ns) ordering information, website (http://www.ti.com).
PRODUCT PREVIEW
Figure 2-7. Device Nomenclature
Device Overview
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
2.8.3
2.8.3.
Documentation Support
Related Documentation From Texas Instruments
following documents describe TMS320DM644x Digital Media System-on-Chip (DMSoC). Copies these documents available Internet www.ti.com. Tip: Enter literature number search provided www.ti.com. current documentation that describes DM644x DMSoC, related peripherals, other technical collateral, available C6000 product folder www.ti.com/c6000. SPRUE14 TMS320DM644x DMSoC Subsystem Reference Guide. Describes subsytem TMS320DM644x Digital Media System-on-Chip (DMSoC). subsystem designed give ARM926EJ-S (ARM9) master control device. general, responsible configuration control device; including subsystem, video processing subsystem, majority peripherals external memories. TMS320DM644x DMSoC Subsystem Reference Guide. Describes digital signal processor (DSP) subsystem TMS320DM644x Digital Media System-on-Chip (DMSoC). TMS320DM644x DMSoC Peripherals Overview Reference Guide. Provides overview briefly describes peripherals available TMS320DM644x Digital Media System-on-Chip (DMSoC). TMS320C64x TMS320C64x+ Migration Guide. Describes migrating from Texas Instruments TMS320C64x digital signal processor (DSP) TMS320C64x+ DSP. objective this document indicate differences between cores. Functionality devices that identical included. TMS320C64x/C64x+ Instruction Reference Guide. Describes architecture, pipeline, instruction set, interrupts TMS320C64x TMS320C64x+ digital signal processors (DSPs) TMS320C6000 family. C64x/C64x+ generation comprises fixed-point devices C6000 platform. C64x+ enhancement C64x with added functionality expanded instruction set. TMS320C64x+ Megamodule Reference Guide. Describes TMS320C64x+ digital signal processor (DSP) megamodule. Included discussion internal direct memory access (IDMA) controller, interrupt controller, power-down controller, memory protection, bandwidth management, memory cache. EDMA v3.0 (EDMA3) Migration Guide TMS320DM644x DMSoC. Describes migrating from Texas Instruments TMS320C64x digital signal processor (DSP) enhanced direct memory access (EDMA2) TMS320DM644x Digital Media System-on-Chip (DMSoC) EDMA3. This document summarizes differences between EDMA3 EDMA2 provides guidance migrating from EDMA2 EDMA3.
SPRUE15 SPRUE19
SPRAA84
SPRU732
SPRU87
SPRAAA6
Device Overview
PRODUCT PREVIEW
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Device Configuration
System Module Registers
system module includes status control registers required configuration device. Brief descriptions various registers shown Table 3-1. System Module registers required device configurations discussed following sections. Table 3-1. System Module Register Memory
ADDRESS RANGE REGISTER ACRONYM PINMUX0 PINMUX1 DSPBOOTADDR SUSPSRC INTGEN BOOTCFG DEVICE_ID USBPHY_CTL CHP_SHRTSW MSTPRI0 MSTPRI1 VPSS_CLKCTL VDD3P3V_PWDN DRRVTPER DESCRIPTION multiplexing control Section 3.6.4 details. multiplexing control Section 3.6.5 details. Boot address DSP. Section 3.4.1.2 details. Emulator Suspend Source. Section details. ARM/DSP Interrupt Status Control. ARM/DSP Communucations Interrupts section details. Device boot configuration. Section 3.4.1.1 details. Reserved Device number. JTAG section details. Reserved Reserved control. peripheral section details. Chip shorting switch control. Section 3.2.1 details. master priority control Section 3.6.1 details. master priority control Section 3.6.1 details. VPSS clock control. 3.3V powerdown control. Section 3.2.2 details. Enables access DDR2 Register Reserved
0x01C4 0000 0x01C4 0004 0x01C4 0008 0x01C4 000C 0x01C4 0010 0x01C4 0014 0x01C4 0018 0x01C4 0027 0x01C4 0028 0x01C4 002C 0x01C4 0030 0x01C4 0034 0x01C4 0038 0x01C4 003C 0x01C4 0040 0x01C4 0044 0x01C4 0048 0x01C4 004C 0x01C4 0050 0x01C4 006F
PRODUCT PREVIEW
Power Considerations
Global device power domains controlled Power Sleep Controller, except shown following sections.
3.2.
Power Configurations Reset
described DM6443 Power Clock Domains section, DM6443 power domains: Always DSP. There shorting switch between power domains that must opened when domain powered closed when domain powered CHP_SHRTSW register, shown Figure 3-1, controls shorting switch between device always-on power domains. This switch should enabled after powering-up domain. Setting DSPPWRON closes (enables) switch enables power domain. default switch value determined DSP_BT configuration input. self boot selected (DSP_BT=1), will powered-up DSPPWRON will value '1'. boot operation (DSP_BT=0), DSPPWRON will disable value must before domain power turned Note: Once power domain enabled (powered up), cannot disabled (powered down). Dynamic power down supported this device.
Device Configuration
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Figure 3-1. CHP_SHRTSW Register
RESERVED
R-0000 0000 0000 0000
RESERVED
R-0000 0000 0000 LEGEND: Read, Write, value reset, state latched reset rising
R/W-L
NAME DSPPWRON power domain enable. power domain power domain
DESCRIPTION
3.2.2
Power Configurations After Reset
VDD3P3V_PWDN register controls power 3.3V buffers MMC/SD GPIOV33. 3.3V I/Os separated into groups independent control shown Figure described Table 3-3. default, these pins disabled reset. Figure 3-2. VDD3P3V_PWDN Register
RESERVED
R-0000 0000 0000 0000
RESERVED
PWDN1 PWDN0
R-0000 0000 0000 LEGEND: Read, Write, value reset
R/W-
R/W-
Table 3-3. VDD3P3V_PWDN Register Description
NAME IOPWDN0 DESCRIPTION MMC/SD Powerdown controls SD_CLK, SD_CMD, SD_DATA[3:0] pins. buffers powered buffers powered down GIOV33 Powerdown controls GIOV33[16:0] pins. buffers powered buffers powered down
IOPWDN
Clocks Considerations
Global device local peripheral clocks controlled Power Sleep Controller, except shown following sections.
Device Configuration
PRODUCT PREVIEW
Table 3-2. CHP_SHRTSW Register Description
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
3.3.
Clock Configurations after Power-On/Hard Reset
described DM6443 Power Clock Domains section, DM6443 system includes separate power domains forty-one separate modules. "AlwaysOn" power domain always when chip "AlwaysOn" domain powered CVDD DM6443 chip. majority DM6443 modules within "AlwaysOn" power domain. Subsystem lies separate domain that always This domain referred "DSP" domain. power domain powered CVDDDSP device. Table shows state each module after chip Power-On/Hard Reset. default state "DSP" power domain module determined boot select (COUT3/B6/DSP_BT). selected self boot (COUT3/B6/DSP_BT reset, "DSP" domain will power default. Table 3-4. Module Configuration
DEFAULT STATES MODULE
PRODUCT PREVIEW
MODULE NAME VPSS EDMA
POWER DOMAIN
POWER DOMAIN STATE
MODULE STATE
LOCAL RESET STATE
Always Always
Disable BTSEL[1:0] Enable (NAND) BTSEL[1:0] Enable (NOR) BTSEL[1:0] Reserved BTSEL[1:0] Enable (UART) Disable Disable Disable Disable BTSEL[1:0] Enable (NAND) BTSEL[1:0] Enable (NOR) BTSEL[1:0] Reserved BTSEL[1:0] Enable (UART) Disable Disable Disable BTSEL[1:0] SyncRst (NAND) BTSEL[1:0] SyncRst (NOR) BTSEL[1:0] Reserved BTSEL[1:0] Enable (UART) Disable Disable Disable Disable Disable Disable Disable Enable Disable Enable Disable Enable Enable
USB2.0 ATA/CF VLNYQ DDR2 EMIF EMIFA
Always Always Always Always Always
MMC/SD UART0
Always Always Always Always
UART1 UART2 PWM0 PWM1 PWM2 GPIO TIMER0 TIMER1 TIMER2 EMAC/MDIO System Module
Always Always Always Always Always Always Always Always Always Always Always Always Always
Device Configuration
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Table 3-4. Module Configuration (continued)
DEFAULT STATES Switched Central Resource (SCR) Always Enable
COUT3_DSP_BT
COUT3_DSP_BT
3.3.1.
Power Domain Module States Defined Power Domain States
3.3.1.1.
3.3.1.1.2
Module States
module four states Disable, Enable, SwRstDisable, SyncReset. shown Table 3-5, four states correspond combinations module reset asserted de-asserted module clock off. Table 3-5. Module States
MODULE STATE Enable Disable SyncReset SwRstDisable MODULE RESET De-Asserted De-Asserted Asserted Asserted MODULE CLOCK
module states defined follows: Enable: module enable state module reset de-asserted clock Disable: module disable state module reset de-asserted clock off. This state typically used disabling module clock power savings. DM6443 designed full static CMOS, when stop module clock, modules state retained. When clock restarted, module resumes operating from point stopped. SyncRst: module SyncRst state module reset asserted clock After initial power-on, most modules default SyncRst state. SwRstDisable: module SwRstDisable state module reset asserted clock off. 3.3.1.2 Video Encoder Clocks Video Encoder Clocks within Video Processing SubSystem (VPSS) controlled VPSS_CLK_CTRL register shown Figure 3-3. Descriptions register fields given Table 3-6. Figure 3-3. VPSS_CLK_CTRL Register
RESERVED
R-0000 0000 0000 0000
RESERVED
CLKEN
CLKEN
VPSS_MUXSEL
R-0000 0000 LEGEND: Read, Write, value reset
R/W-0
R/W-0
R/W-0
R/W-00
Device Configuration
PRODUCT PREVIEW
power domain only states OFF, defined follows: Power power domain OFF: Power power domain off.
TMS320DM6443 Digital Media System-on-Chip
SPRS282A DECEMBER 2005 REVISED JANUARY 2006
Table 3-6. VPSS_CLK_CTRL Register Description
Name DACCLKEN Video clock control clock disabled clock enabled Video Encoder clock control Video Encoder clock disabled Video Encoder clock enabled Video Encoder clock selection VPSS_MUXSEL [1:0] VENC Clock MHz) MHz) VPBECLK input PCLK inverted PCLK Clock MHz) MHz) VPBECLK input Description
VENCLKEN
VPSS_MUXSEL
PRODUCT PREVIEW
Bootmode
device booted through multiple means: states captured reset, primary bootloaders within internal EMIFA, secondary user bootloaders from peripherals external memories. Boot modes, configurations, register configurations required booting device, described following

SPRS282A DECEMBER 2005 REVISED JANUARY 2006 Digital Media System-

Top Searches for this datasheet

Other recent searches