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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
Highest-Performance Floating-Point Digital
Signal Processor (DSP): TMS320C6713B Eight 32-Bit Instructions/Cycle 32/64-Bit Data Word 300-, 225-, 200-MHz (GDP ZDP), 225-, 200-, 167-MHz (PYP) Clock Rates 3.3-, 4.4-, 6-Instruction Cycle Times 2400/1800, 1800/1350, 1600/1200, 1336/1000 MIPS/MFLOPS Rich Peripheral Set, Optimized Audio Highly Optimized C/C++ Compiler Extended Temperature Devices Available Advanced Very Long Instruction Word (VLIW) TMS320C67x Core Eight Independent Functional Units: ALUs (Fixed-Point) ALUs (Floating-/Fixed-Point) Multipliers (Floating-/Fixed-Point) Load-Store Architecture With 32-Bit General-Purpose Registers Instruction Packing Reduces Code Size Instructions Conditional Instruction Features Native Instructions IEEE Single- Double-Precision Byte-Addressable (8-, 16-, 32-Bit Data) 8-Bit Overflow Protection Saturation; Bit-Field Extract, Set, Clear; Bit-Counting; Normalization L1/L2 Memory Architecture 4K-Byte Program Cache (Direct-Mapped) 4K-Byte Data Cache (2-Way) 256K-Byte Memory Total: 64K-Byte Unified Cache/Mapped RAM, 192K-Byte Additional Mapped Device Configuration Boot Mode: HPI, 16-, 32-Bit Boot Endianness: Little Endian, Endian 32-Bit External Memory Interface (EMIF) Glueless Interface SRAM, EPROM, Flash, SBSRAM, SDRAM 512M-Byte Total Addressable External Memory Space Enhanced Direct-Memory-Access (EDMA) Controller Independent Channels)
16-Bit Host-Port Interface (HPI) McASPs
Independent Clock Zones Each Eight Serial Data Pins Port: Individually Assignable Clock Zones Each Clock Zone Includes: Programmable Clock Generator Programmable Frame Sync Generator Streams From 2-32 Time Slots Support Slot Size: Bits Data Formatter Manipulation Wide Variety Similar Stream Formats Integrated Digital Audio Interface Transmitter (DIT) Supports: S/PDIF, IEC60958-1, AES-3, CP-430 Formats transmit pins Enhanced Channel Status/User Data Extensive Error Checking Recovery Inter-Integrated Circuit (I2C Bus) Multi-Master Slave Interfaces Multichannel Buffered Serial Ports: Serial-Peripheral-Interface (SPI) High-Speed Interface AC97 Interface 32-Bit General-Purpose Timers Dedicated GPIO Module With pins (External Interrupt Capable) Flexible Phase-Locked-Loop (PLL) Based Clock Generator Module IEEE-1149.1 (JTAG) Boundary-Scan-Compatible 208-Pin PowerPAD PQFP (PYP) 272-BGA Packages (GDP ZDP) 0.13-µm/6-Level Copper Metal Process CMOS Technology 3.3-V I/Os, 1.2-V Internal (GDP/ZDP/ PYP) 3.3-V I/Os, 1.4-V Internal (GDP/ZDP) [300 MHz]
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
TMS320C67x PowerPAD trademarks Texas Instruments. trademark Philips Electronics N.V. Corporation trademarks property their respective owners. IEEE Standard 1149.1-1990 Standard-Test-Access Port Boundary Scan Architecture. These values compatible with existing 1.26-V designs.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2005, Texas Instruments Incorporated
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
Table Contents
revision history 272-Ball package (bottom view) PowerPAD package (top view) description device characteristics functional block (DSP core) diagram (DSP core) description memory summary peripheral register descriptions signal groups description device configurations configuration examples debugging considerations terminal functions development support device support register description cache configuration (CCFG) register description interrupts interrupt selector external interrupt sources EDMA module EDMA selector controller multichannel audio serial port (McASP) peripherals general-purpose input/output (GPIO) power-down mode logic power-supply sequencing IEEE 1149.1 JTAG compatibility statement power-supply decoupling EMIF device speed EMIF endian mode correctness bootmode reset absolute maximum ratings over operating case temperature range recommended operating conditions electrical characteristics over recommended ranges supply voltage operating case temperature parameter measurement information signal transition levels timing parameters board routing analysis input output clocks asynchronous memory timing synchronous-burst memory timing synchronous DRAM timing HOLD/HOLDA timing BUSREQ timing reset timing external interrupt timing multichannel audio serial port (McASP) timing inter-integrated circuits (I2C) timing host-port interface timing multichannel buffered serial port timing timer timing general-purpose input/output (GPIO) port timing JTAG test-port timing mechanical data
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
REVISION HISTORY
TMS320C6713B device-specific documentation been split from TMS320C6713, TMS320C6713B Floating-Point Digital Signal Processors, literature number SPRS186K, into separate Data Sheet, literature number SPRS294. also highlights technical changes made SPRS294 generate SPRS294A; these changes marked "[Revision Revision History table below Scope: Updated information McASP, McBSP JTAG clarification. Changed Description (Revisions SPRS294 SPRS294A). Updated Nomenclature figure adding device-specific information package. Recommends designs that following pins configured such:
connected directly CVDD (core power) connected directly (ground)
PAGE(S) ADDITIONS/CHANGES/DELETIONS Terminal Assignments 272-Ball Packages Order Ball No.) table: Updated Signal Name Ball Updated Signal Name Ball PowerPAD package (top view): Updated drawing Device Configurations, Device Configurations Pins Device Reset (HD[4:3], HD8, HD12, CLKMODE0) section: Removed "CE1 width 32-bit" from Functional Description "00" HD[4:3](BOOTMODE) Configuration Table Peripheral Selection Matrix: Updated/changed MCBSP0DIS (DEVCFG bit) from "ACLKKO" "ACLKXO" Configuration Example McBSP McASP) figure: Updated from McBSP1DIS McBSP1DIS Terminal Functions, Resets Interrupts section: Updated IPU/IPD RESET Signal Name from "IPU" Terminal Functions table, Host Port Interface section: Removed "CE1 width 32-bit" from Description "00" Bootmode HD[4:3] Terminal Functions, Timer section: Updated Description TINP1/AHCLKX0 Signal Name Terminal Functions, Reserved Test section: Updated Description Signal Name, PYP, GDP/ZDP Updated Description Signal Name, PYP, GDP/ZDP Terminal Functions, Reserved Test section: Updated/changed Description Signal Name, "recommended") [Revision Updated/changed Description Signal Name, "recommended") [Revision Device Support, device development-support tool nomenclature section: Updated figure clarity Device Support, document support section: Updated paragraphs clarity
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
PAGE(S)
ADDITIONS/CHANGES/DELETIONS IEEE 1149.1 JTAG Compatibility Statement section: Updated/added paragraphs clarity Recommended Operating Conditions: Added VOS, Maximum voltage during overshoot associated footnote Added VUS, Maximum voltage during undershoot associated footnote Parameter Measurement Information, transient rise/fall time specifications section: Added Transient Specification Rise Time figure Added Transient Specification Fall Time figure MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING: timing requirements McASP section: Updated Parameter tc(ACKRX), from "33" "greater added associated footnote MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING: switching characteristics over recommended operating conditions McASP section: Updated Parameter tc(ACKRX), from "33" "greater added associated footnote MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING section: Updated McASP Input Output drawings MULTICHANNEL BUFFERED SERIAL PORT TIMING section: switching characteristics over recommended operating conditions McBSP section: Updated McBSP Timings figure Mechanical Data section: Added statement Packaging Information section
125,
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
272-Ball package (bottom view)
ED18 ARDY DVDD ECLKOUT AOE/ SDRAS/ SSOE ECLKIN CLKOUT2/ GP[2] EA14 EA16 EA18 DVDD EA20
CVDD
DVDD
ED17
DVDD
ARE/ SDCAS/ SSADS
DVDD
EA11
EA13
EA15
EA19
CVDD
ED20
ED19
CVDD
ED16
EA10
AWE/ SDWE/ SSWE
DVDD
EA12
DVDD
EA17
CVDD
DVDD
ED22
ED21
ED23
DVDD
CVDD
DVDD
CVDD
CVDD
DVDD
CVDD
CVDD
DVDD
EA21
ED24
ED25
DVDD
ED13
ED15
ED14
DVDD
ED27
ED26
CVDD
CVDD
DVDD
ED11
ED12
ED28
ED29
ED30
ED10
SCL0
SDA0
ED31
CLKR1/ AXR0[6]
DR1/ SDA1
FSR1/ AXR0[7]
DVDD
FSX1
DX1/ AXR0[5]
CLKX1/ AMUTE0 CLKS0/ AHCLKR0
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
DR0/ AXR0[0]
DVDD
FSR0/ AFSR0
HOLD
HOLDA
HRDY/ ACLKR1
HINT/ GP[1] HHWIL/ AFSR1
FSX0/ AFSX0 TOUT0/ AXR0[2]
DX0/ AXR0[1] TINP0/ AXR0[3]
CLKR0/ ACLKR0 CLKX0/ ACLKX0
DVDD
HCNTL0/ AXR1[3] HDS2/ AXR1[5] HAS/ ACLKX1
HCNTL1/ AXR1[1]
HR/W/ AXR1[0] HCS/ AXR1[2] HD0/ AXR1[4]
TOUT1/ AXR0[4]
TINP1/ AHCLKX0
DVDD
CVDD
CVDD
CLKS1/ SCL1
GP[7] (EXT_INT7)
HDS1/ AXR1[6]
DVDD
GP[6] (EXT_INT6)
EMU2
CVDD
CVDD
EMU0
CLKOUT3
CVDD
CVDD
CVDD
DVDD
HD2/ AFSX1
DVDD
HD1/ AXR1[7]
GP[5] GP[4]/ (EXT_INT5)/ (EXT_INT4)/ AMUTEIN0 AMUTEIN1 CVDD
CVDD
MODE0
PLLHV
CVDD
DVDD
EMU4
HD14/ GP[14] HD15/ GP[15]
HD12/ GP[12]
HD9/ GP[9] HD10/ GP[10]
HD6/ AHCLKR1 HD8/ GP[8]
CVDD
HD4/ GP[0]
HD3/ AMUTE1
DVDD
TRST
DVDD
EMU1
EMU3
EMU5
DVDD
HD5/ AHCLKX1
CVDD
CLKIN
CVDD
CVDD
CVDD
RESET
HD13/ GP[13]
HD11/ GP[11]
DVDD
HD7/ GP[3]
Shading denotes package functions that drop package.
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
Table Terminal Assignments 272-Ball Packages Order Ball No.)
BALL CLKIN CVDD CVDD CVDD [connect directly CVDD] RESET HD13/GP[13] HD11/GP[11] DVDD HD7/GP[3] CVDD DVDD TRST DVDD EMU1 EMU3 [connect directly VSS] EMU5 DVDD HD15/GP[15] HD10/GP[10] HD8/GP[8] HD5/AHCLKX1 CVDD SIGNAL NAME BALL SIGNAL NAME GP[5](EXT_INT5)/AMUTEIN0 GP[4](EXT_INT4)/AMUTEIN1 CVDD CLKMODE0 PLLHV CVDD DVDD EMU4 HD14/GP[14] HD12/GP[12] HD9/GP[9] HD6/AHCLKR1 CVDD HD4/GP[0] HD3/AMUTE1 DVDD GP[6](EXT_INT6) EMU2 CVDD CVDD EMU0 CLKOUT3 CVDD CVDD CVDD DVDD HD2/AFSX1 DVDD HD1/AXR1[7]
Shading denotes package functions that drop package.
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
Table Terminal Assignments 272-Ball Package Order Ball No.) (Continued)
BALL SIGNAL NAME CLKS1/SCL1 GP[7](EXT_INT7) HAS/ACLKX1 HDS1/AXR1[6] HD0/AXR1[4] TOUT1/AXR0[4] TINP1/AHCLKX0 DVDD CVDD CVDD HDS2/AXR1[5] HCS/AXR1[2] TOUT0/AXR0[2] TINP0/AXR0[3] CLKX0/ACLKX0 HCNTL0/AXR1[3] HCNTL1/AXR1[1] HR/W/AXR1[0] FSX0/AFSX0 DX0/AXR0[1] CLKR0/ACLKR0 DVDD HRDY/ACLKR1 HHWIL/AFSR1 DR0/AXR0[0] DVDD FSR0/AFSR0 BALL HOLD HOLDA BUSREQ HINT/GP[1] CVDD CLKS0/AHCLKR0 CVDD CVDD FSX1 DX1/AXR0[5] CLKX1/AMUTE0 CVDD CVDD CVDD CLKR1/AXR0[6] DR1/SDA1 FSR1/AXR0[7] DVDD SIGNAL NAME
Shading denotes package functions that drop package.
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
Table Terminal Assignments 272-Ball Package Order Ball No.) (Continued)
BALL SCL0 SDA0 ED31 ED28 ED29 ED30 ED10 DVDD ED27 ED26 CVDD CVDD DVDD ED11 ED12 ED24 ED25 DVDD ED13 ED15 ED14 ED22 ED21 ED23 DVDD CVDD DVDD SIGNAL NAME BALL CVDD CVDD DVDD CVDD CVDD DVDD EA21 ED20 ED19 CVDD ED16 EA10 ARE/SDCAS/SSADS AWE/SDWE/SSWE DVDD EA12 DVDD EA17 CVDD DVDD CVDD DVDD ED17 SIGNAL NAME
Shading denotes package functions that drop package.
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
Table Terminal Assignments 272-Ball Package Order Ball No.) (Continued)
BALL SIGNAL NAME DVDD AOE/SDRAS/SSOE DVDD EA11 EA13 EA15 EA19 CVDD ED18 BALL ARDY DVDD ECLKOUT ECLKIN CLKOUT2/GP[2] EA14 EA16 EA18 DVDD EA20 SIGNAL NAME
Shading denotes package functions that drop package.
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
PowerPAD package (top view)
208-PIN PowerPAD PLASTIC QUAD FLATPACK (PQFP) VIEW
HD4/GP[0] HD2/AFSX1 HD3/AMUTE1 /ACLKX1 HD1/AXR1[7] HDS1/AXR1[6] HDS2/AXR1[5] HD0/AXR1[4] HCNTL0/AXR1[3] HCS/AXR1[2] HCNTL1/AXR1[1] W/AXR1[0] HRDY/ACLKR1 HHWIL/AFSR1 HOLD HOLDA BUSREQ HINT/GP[1] ED10 ED12 ED11 ED14 ED15 ED13 EA21
CVDD HD5/AHCLKX1 HD8/GP[8] HD6/AHCLKR1 DVDD HD7/GP[3] HD9/GP[9] HD10/GP[10] HD11/GP[11] HD12/GP[12] CVDD CVDD HD13/GP[13] HD14/GP[14] HD15/GP[15] RESET
CVDD
DVDD
CLKOUT3 EMU1 EMU0 DVDD CVDD CVDD CVDD TRST CVDD PLLHV CLKIN CLKMODE0 DVDD CVDD
Exposed Thermal
8,30 6,79
8,30 6,79
CVDD EA20 EA19 EA17 DVDD CVDD EA18 EA15 EA12 EA16 EA13 EA14 CVDD DVDD EA11 DVDD AWE/SDWE/SSWE CLKOUT2/GP[2] CVDD ARE/SDCAS/SSADS ECLKIN ECLKOUT EA10 AOE/SDRAS/SSOE DVDD CVDD DVDD CVDD DVDD ARDY DVDD CVDD
NOTE: linear dimensions millimeters. This electrically thermally connected backside die. TMS320C6713B 208-Pin PowerPAD plastic quad flatpack, external thermal dimensions are: thermal externally flush with mold compound.
GP[4](EXT_INT4)/AMUTEIN1 GP[6](EXT_INT6) GP[5](EXT_INT5)/AMUTEIN0 GP[7](EXT_INT7) CLKS1/SCL1 TINP1/AHCLKX0 TOUT1/AXR0[4] CLKX0/ACLKX0 TINP0/AXR0[3] TOUT0/AXR0[2] CLKR0/ACLKR0 DX0/AXR0[1] FSX0/AFSX0 FSR0/AFSR0 DR0/AXR0[0] CLKS0/AHCLKR0 FSX1 DX1/AXR0[5] CLKX1/AMUTE0 CLKR1/AXR0[6] DR1/SDA1 FSR1/AXR0[7] SCL0 SDA0
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
description
TMS320C67xt DSPs (including TMS320C6713B device) compose floating-point generation TMS320C6000t platform. C6713B device based high-performance, advanced very-long-instruction-word (VLIW) architecture developed Texas Instruments (TI), making this excellent choice multichannel multifunction applications. Operating MHz, C6713B delivers 1350 million floating-point operations second (MFLOPS), 1800 million instructions second (MIPS), with dual fixed-/floating-point multipliers million multiply-accumulate operations second (MMACS). Operating MHz, C6713B delivers 1800 million floating-point operations second (MFLOPS), 2400 million instructions second (MIPS), with dual fixed-/floating-point multipliers million multiply-accumulate operations second (MMACS). C6713B uses two-level cache-based architecture powerful diverse peripherals. Level program cache (L1P) 4K-byte direct-mapped cache Level data cache (L1D) 4K-byte 2-way set-associative cache. Level memory/cache (L2) consists 256K-byte memory space that shared between program data space. bytes 256K bytes memory configured mapped memory, cache, combinations two. remaining 192K bytes serves mapped SRAM. C6713B rich peripheral that includes Multichannel Audio Serial Ports (McASPs), Multichannel Buffered Serial Ports (McBSPs), Inter-Integrated Circuit (I2C) buses, dedicated General-Purpose Input/Output (GPIO) module, general-purpose timers, host-port interface (HPI), glueless external memory interface (EMIF) capable interfacing SDRAM, SBSRAM, asynchronous peripherals. McASP interface modules each support transmit receive clock zone. Each McASP eight serial data pins which individually allocated zones. serial port supports time-division multiplexing each from time slots. C6713B sufficient bandwidth support serial data pins transmitting stereo signal. Serial data each zone transmitted received multiple serial data pins simultaneously formatted multitude variations Philips Inter-IC Sound (I2S) format. addition, McASP transmitter programmed output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with single containing full implementation user data channel status fields. McASP also provides extensive error-checking recovery features, such clock detection circuit each high-frequency master clock which verifies that master clock within programmed frequency range. ports TMS320C6713B allow easily control peripheral devices communicate with host processor. addition, standard multichannel buffered serial port (McBSP) used communicate with serial peripheral interface (SPI) mode peripheral devices. TMS320C6713B device bootmodes: from from external asynchronous ROM. more detailed information, bootmode section this data sheet. TMS320C67x generation supported eXpressDSPt industry benchmark development tools, including highly optimizing C/C++ Compiler, Code Composer Studiot Integrated Development Environment (IDE), JTAG-based emulation real-time debugging, DSP/BIOSt kernel.
TMS320C6000, eXpressDSP, Code Composer Studio, DSP/BIOS trademarks Texas Instruments. Throughout remainder this document, TMS320C6713B shall referred C6713B 13B.
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
device characteristics
Table provides overview C6713B DSP. table shows significant features device, including capacity on-chip RAM, peripherals, execution time, package type with count. more details C67x device part numbers part numbering, Figure Table Characteristics C6713B Processor
HARDWARE FEATURES Peripherals EMIF EDMA Channels) bit) McASPs I2Cs McBSPs Peripheral performance dependent chip-level configuration. 32-Bit Timers GPIO Module Size (Bytes) On-Chip Memory INTERNAL CLOCK SOURCE SYSCLK3 ECLKIN clock frequency SYSCLK2 AUXCLK, SYSCLK2 SYSCLK2 SYSCLK2 SYSCLK2 SYSCLK2 C6713B (FLOATING-POINT DSP) GDP/ZDP bit) 264K 4K-Byte (4KB) Program (L1P) Cache Data (L1D) Cache 64KB Unified Cache/Mapped 192KB Mapped 0x0203 300, 225, (GDP-300, ZDP-300) (GDP-225, ZDP-225) (GDPA-200, ZDPA-200) 1.20 (-300) 272-Ball (GDP) 272-Ball (ZDP) 0.13 208-Pin PowerPAD PQFP (PYP) 225, 200, (PYP-200) (PYP-225) (PYPA-167) (PYPA-200) bit)
peripheral pins available same time. (For more details, Device Configurations section.)
Organization
ID+CPU BSDL File Frequency
Control Status Register (CSR.[31:16]) C6713B BSDL file, contact your Field Sales Representative.
Cycle Time
Voltage
Core
Clock Generator Options
Prescaler Multiplier Postscaler
Packages Process Technology
Product Status Product Preview (PP) Advance Information (AI) Production Data (PD) AUXCLK McASP internal high-frequency clock source serial transfers. SYSCLK2 McASP system clock used clock check (high-frequency) circuit. This value compatible with existing 1.26-V designs. PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
C67x trademark Texas Instruments.
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
functional block (DSP core) diagram
Digital Signal Processor
EMIF Cache Direct Mapped Bytes Total
McASP1
Cache/ Memory Banks Bytes Total 4-Way)
C67x Instruction Fetch Instruction Dispatch Control Registers Control Logic Test In-Circuit Emulation Interrupt Control
McASP0
McBSP1
Instruction Decode Data Path Data Path Register File
Multiplexing
McBSP0
Register File
I2C1
Enhanced Controller channel) Memory 192K Bytes
I2C0
Timer
Cache 2-Way Associative Bytes
Timer
Clock Generator through Multiplier through Dividers
Power-Down Logic
GPIO
addition fixed-point instructions, these functional units execute floating-point instructions. EMIF interfaces -SDRAM -SBSRAM -SRAM, -ROM/Flash, -I/O devices McBSPs interface -SPI Control Port -High-Speed Codecs -AC97 Codecs -Serial EEPROM McASPs interface -I2S Multichannel ADC, DAC, Codec, -DIT: Multiple Outputs
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
(DSP core) description
TMS320C6713B floating-point digital signal processor based C67x CPU. fetches advanced very-long instruction words (VLIW) (256 bits wide) supply eight 32-bit instructions eight functional units during every clock cycle. VLIW architecture features controls which eight units have supplied with instructions they ready execute. first every 32-bit instruction determines next instruction belongs same execute packet previous instruction, whether should executed following clock part next execute packet. Fetch packets always bits wide; however, execute packets vary size. variable-length execute packets memory-saving feature, distinguishing C67x from other VLIW architectures. features sets functional units. Each contains four units register file. contains functional units .L1, .S1, .M1, .D1; other contains units .D2, .M2, .S2, .L2. register files each contain 32-bit registers total general-purpose registers. sets functional units, along with register files, compose sides (see functional block diagram Figure four functional units each side freely share registers belonging that side. Additionally, each side features single data connected registers other side, which sets functional units access data from register files opposite side. While register access functional units same side register file service units single clock cycle, register access using register file across supports read write cycle. C67x executes C62x instructions. addition C62x fixed-point instructions, eight functional units (.L1, .S1, .M1, .M2, .S2, .L2) also execute floating-point instructions. remaining functional units (.D1 .D2) also execute LDDW instruction which loads bits side total bits cycle. Another feature C67x load/store architecture, where instructions operate registers opposed data memory). sets data-addressing units (.D1 .D2) responsible data transfers between register files memory. data address driven units allows data addresses generated from register file used load store data from other register file. C67x supports variety indirect addressing modes using either linear- circular-addressing modes with 15-bit offsets. instructions conditional, most access registers. Some registers, however, singled support specific addressing hold condition conditional instructions condition automatically "true"). functional units dedicated multiplies. functional units perform general arithmetic, logical, branch functions with results available every clock cycle. processing flow begins when 256-bit-wide instruction fetch packet fetched from program memory. 32-bit instructions destined individual functional units "linked" together bits least significant (LSB) position instructions. instructions that "chained" together simultaneous execution eight total) compose execute packet. instruction breaks chain, effectively placing instructions that follow next execute packet. execute packet crosses fetch-packet boundary (256 bits wide), assembler places next fetch packet, while remainder current fetch packet padded with instructions. number execute packets within fetch packet vary from eight. Execute packets dispatched their respective functional units rate clock cycle next 256-bit fetch packet fetched until execute packets from current fetch packet have been dispatched. After decoding, instructions simultaneously drive active functional units maximum execution rate eight instructions every clock cycle. While most results stored 32-bit registers, they subsequently moved memory bytes half-words well. load store instructions byte-, half-word, word-addressable.
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
(DSP core) description (continued)
src1
src2
long long
Data Path
src2
src1 src2
src1 src2
src2 src1
src2
src1 src2
Data Path
src1 long long
src1
addition fixed-point instructions, these functional units execute floating-point instructions.
Figure TMS320C67x (DSP Core) Data Paths
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long long src2
long long src1
Register File (A0-A15) Register File (B0-B15) Control Register File
TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
memory summary
Table shows memory address ranges device. Table Memory Summary
MEMORY BLOCK DESCRIPTION Internal (L2) Internal RAM/Cache Reserved External Memory Interface (EMIF) Registers Registers Reserved Registers McBSP Registers McBSP Registers Timer Registers Timer Registers Interrupt Selector Registers Device Configuration Registers Reserved EDMA EDMA Registers Reserved GPIO Registers Reserved I2C0 Registers I2C1 Registers Reserved McASP0 Registers McASP1 Registers Reserved Registers Reserved Emulation Registers Reserved QDMA Registers Reserved Reserved McBSP0 Data Port McBSP1 Data Port Reserved McASP0 Data Port McASP1 Data Port Reserved EMIF EMIF EMIF EMIF Reserved BLOCK SIZE (BYTES) 192K 256K 256K 128K 128K 256K 256K 256K 256K 256K 256K 256K 768K 240K 160K 264K 256K 720M 256M 256M 256M 256M ADDRESS RANGE 0000 0000 0002 FFFF 0003 0000 0003 FFFF 0004 0000 017F FFFF 0180 0000 0183 FFFF 0184 0000 0185 FFFF 0186 0000 0187 FFFF 0188 0000 018B FFFF 018C 0000 018F FFFF 0190 0000 0193 FFFF 0194 0000 0197 FFFF 0198 0000 019B FFFF 019C 0000 019C 01FF 019C 0200 019C 0203 019C 0204 019F FFFF 01A0 0000 01A3 FFFF 01A4 0000 01AF FFFF 01B0 0000 01B0 3FFF 01B0 4000 01B3 FFFF 01B4 0000 01B4 3FFF 01B4 4000 01B4 7FFF 01B4 8000 01B4 BFFF 01B4 C000 01B4 FFFF 01B5 0000 01B5 3FFF 01B5 4000 01B7 BFFF 01B7 C000 01B7 DFFF 01B7 E000 01BB FFFF 01BC 0000 01BF FFFF 01C0 0000 01FF FFFF 0200 0000 0200 0033 0200 0034 02FF FFFF 0300 0000 2FFF FFFF 3000 0000 33FF FFFF 3400 0000 37FF FFFF 3800 0000 3BFF FFFF 3C00 0000 3C0F FFFF 3C10 0000 3C1F FFFF 3C20 0000 7FFF FFFF 8000 0000 8FFF FFFF 9000 0000 9FFF FFFF A000 0000 AFFF FFFF B000 0000 BFFF FFFF C000 0000 FFFF FFFF
number EMIF address pins (EA[21:2]) limits maximum addressable memory (SDRAM) 128MB space.
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
memory structure expanded Figure shows detail memory structure.
Mode 0x0000 0000 Memory Block Base Address
208K SRAM
192K SRAM
256K SRAM (All)
240K SRAM
224K SRAM
192K-Byte
0x0003 0000
4-Way Cache
3-Way Cache
2-Way Cache
1-Way Cache
Figure Memory Configuration
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16K-Byte 16K-Byte 16K-Byte 16K-Byte
0x0003 4000 0x0003 8000 0x0003 C000 0x0003 FFFF
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
peripheral register descriptions
Table through Table identify peripheral registers device their register names, acronyms, address address range. more detailed information register contents, names their descriptions, specific peripheral reference guide listed TMS320C6000 Peripherals Overview Reference Guide (literature number SPRU190). Table EMIF Registers
ADDRESS RANGE 0180 0000 0180 0004 0180 0008 0180 000C 0180 0010 0180 0014 0180 0018 0180 001C 0180 0020 0180 0024 0183 FFFF ACRONYM GBLCTL CECTL1 CECTL0 CECTL2 CECTL3 SDCTL SDTIM SDEXT EMIF global control EMIF space control EMIF space control Reserved EMIF space control EMIF space control EMIF SDRAM control EMIF SDRAM refresh control EMIF SDRAM extension Reserved REGISTER NAME
Table Cache Registers
ADDRESS RANGE 0184 0000 0184 4000 0184 4004 0184 4010 0184 4014 0184 4020 0184 4024 0184 4030 0184 4034 0184 5000 0184 5004 0184 8200 0184 8204 0184 8208 0184 820C 0184 8240 0184 8244 0184 8248 0184 824C 0184 8280 0184 8284 0184 8288 0184 828C 0184 82C0 0184 82C4 0184 82C8 0184 82CC 0184 82D0 0185 FFFF ACRONYM CCFG L2WBAR L2WWC L2WIBAR L2WIWC L1PIBAR L1PIWC L1DWIBAR L1DWIWC L2WB L2WBINV MAR0 MAR1 MAR2 MAR3 MAR4 MAR5 MAR6 MAR7 MAR8 MAR9 MAR10 MAR11 MAR12 MAR13 MAR14 MAR15 Cache configuration register writeback base address register writeback word count register writeback-invalidate base address register writeback-invalidate word count register invalidate base address register invalidate word count register writeback-invalidate base address register writeback-invalidate word count register writeback register writeback-invalidate register Controls range 8000 0000 80FF FFFF Controls range 8100 0000 81FF FFFF Controls range 8200 0000 82FF FFFF Controls range 8300 0000 83FF FFFF Controls range 9000 0000 90FF FFFF Controls range 9100 0000 91FF FFFF Controls range 9200 0000 92FF FFFF Controls range 9300 0000 93FF FFFF Controls range A000 0000 A0FF FFFF Controls range A100 0000 A1FF FFFF Controls range A200 0000 A2FF FFFF Controls range A300 0000 A3FF FFFF Controls range B000 0000 B0FF FFFF Controls range B100 0000 B1FF FFFF Controls range B200 0000 B2FF FFFF Controls range B300 0000 B3FF FFFF Reserved REGISTER NAME
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peripheral register descriptions (continued)
Table Interrupt Selector Registers
ADDRESS RANGE 019C 0000 019C 0004 019C 0008 019C 000C 019F FFFF ACRONYM MUXH MUXL EXTPOL REGISTER NAME Interrupt multiplexer high Interrupt multiplexer External interrupt polarity Reserved COMMENTS Selects which interrupts drive interrupts 10-15 (INT10-INT15) Selects which interrupts drive interrupts (INT04-INT09) Sets polarity external interrupts (EXT_INT4-EXT_INT7)
Table Device Registers
ADDRESS RANGE ACRONYM REGISTER DESCRIPTION Allows user control peripheral selection. This register also offers user control EMIF input clock source. more detailed information device configuration register, Device Configurations section this data sheet. Identifies which defines silicon revision CPU. This register also offers user control device operation. more detailed information Control Status Register, Register Description section this data sheet.
019C 0200
DEVCFG
Device Configuration
019C 0204 019F FFFF
Reserved
Control Status Register
Table EDMA Parameter
ADDRESS RANGE 01A0 0000 01A0 0017 01A0 0018 01A0 002F 01A0 0030 01A0 0047 01A0 0048 01A0 005F 01A0 0060 01A0 0077 01A0 0078 01A0 008F 01A0 0090 01A0 00A7 01A0 00A8 01A0 00BF 01A0 00C0 01A0 00D7 01A0 00D8 01A0 00EF 01A0 00F0 01A0 00107 01A0 0108 01A0 011F 01A0 0120 01A0 0137 01A0 0138 01A0 014F 01A0 0150 01A0 0167 01A0 0168 01A0 017F 01A0 0180 01A0 0197 01A0 0198 01A0 01AF 01A0 07E0 01A0 07F7 01A0 07F8 01A0 07FF ACRONYM REGISTER NAME Parameters Event words) Reload/Link Parameters other Event Parameters Event words) Reload/Link Parameters other Event Parameters Event words) Reload/Link Parameters other Event Parameters Event words) Reload/Link Parameters other Event Parameters Event words) Reload/Link Parameters other Event Parameters Event words) Reload/Link Parameters other Event Parameters Event words) Reload/Link Parameters other Event Parameters Event words) Reload/Link Parameters other Event Parameters Event words) Reload/Link Parameters other Event Parameters Event words) Reload/Link Parameters other Event Parameters Event words) Reload/Link Parameters other Event Parameters Event words) Reload/Link Parameters other Event Parameters Event words) Reload/Link Parameters other Event Parameters Event words) Reload/Link Parameters other Event Parameters Event words) Reload/Link Parameters other Event Parameters Event words) Reload/Link Parameters other Event Reload/link parameters Event 0-15 Reload/link parameters Event 0-15 Reload/link parameters Event 0-15
Scratch area words) device EDMA parameters total: Event/Reload parameters Reload-only parameters.
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peripheral register descriptions (continued)
more details EDMA parameter 6-word parameter entry structure, Figure
Word Word Word Word Word Word EDMA Channel Options Parameter (OPT) EDMA Channel Source Address (SRC) Array/Frame Count (FRMCNT) Array/Frame Index (FRMIDX) Element Count Reload (ELERLD) Element Count (ELECNT) Element Index (ELEIDX) Link Address (LINK) EDMA Channel Destination Address (DST)
EDMA Parameter
Figure EDMA Channel Parameter Entries Words) Each EDMA Event Table EDMA Registers
ADDRESS RANGE 01A0 0800 01A0 FEFC 01A0 FF00 01A0 FF04 01A0 FF08 01A0 FF0B 01A0 FF0C 01A0 FF1F 01A0 FFDC 01A0 FFE0 01A0 FFE4 01A0 FFE8 01A0 FFEC 01A0 FFF0 01A0 FFF4 01A0 FFF8 01A0 FFFC 01A1 0000 01A3 FFFF ACRONYM ESEL0 ESEL1 ESEL3 PQSR CIPR CIER CCER Reserved EDMA event selector EDMA event selector Reserved EDMA event selector Reserved Priority queue status register Channel interrupt pending register Channel interrupt enable register Channel chain enable register Event register Event enable register Event clear register Event register Reserved REGISTER NAME
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peripheral register descriptions (continued)
Table Quick (QDMA) Pseudo Registers
ADDRESS RANGE 0200 0000 0200 0004 0200 0008 0200 000C 0200 0010 0200 0014 0200 001C 0200 0020 0200 0024 0200 0028 0200 002C 0200 0030 ACRONYM QOPT QSRC QCNT QDST QIDX QSOPT QSSRC QSCNT QSDST QSIDX QDMA options parameter register QDMA source address register QDMA frame count register QDMA destination address register QDMA index register Reserved QDMA pseudo options register QDMA pseudo source address register QDMA pseudo frame count register QDMA pseudo destination address register REGISTER NAME
QDMA pseudo index register QDMA Pseudo registers write-accessible only
Table Controller Registers
ADDRESS RANGE 01B7 C000 01B7 C004 01B7 C0FF 01B7 C100 01B7 C104 01B7 C10F 01B7 C110 01B7 C114 01B7 C118 01B7 C11C 01B7 C120 01B7 C124 01B7 C128 01B7 DFFF ACRONYM PLLPID PLLCSR PLLM PLLDIV0 PLLDIV1 PLLDIV2 PLLDIV3 OSCDIV1 Reserved control/status register Reserved multiplier control register controller divider register controller divider register controller divider register controller divider register Oscillator divider register Reserved REGISTER NAME Peripheral identification register (PID) [0x00010801 Controller]
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peripheral register descriptions (continued)
Table McASP0 McASP1 Registers
ADDRESS RANGE McASP0 3C00 0000 3C00 FFFF McASP1 3C10 0000 3C10 FFFF ACRONYM REGISTER NAME McASPx receive buffer McASPx transmit buffer Peripheral Data Bus. (Used when RSEL XSEL bits [these bits located RFMT XFMT registers, respectively].) Peripheral Identification register [0x00100101 McASP0 McASP1] Power down emulation management register Reserved Reserved function register direction register data register data data register Read returns: PDIN Writes affect: PDSET data clear register Reserved Global control register Mute control register Digital Loop-back control register mode control register Reserved Alias GBLCTL containing only Receiver Reset bits, allows transmit reset independently from receive. Receiver format unit mask register Receive stream format register Receive frame sync control register Receive clock control register High-frequency receive clock control register Receive slot 0-31 register Receiver interrupt control register Status register Receiver Current receive slot register Receiver clock check control register Reserved Alias GBLCTL containing only Transmitter Reset bits, allows transmit reset independently from receive. Transmit format unit mask register Transmit stream format register Transmit frame sync control register Transmit clock control register High-frequency Transmit clock control register
RBUF/XBUFx
01B4 C000 01B4 C004 01B4 C008 01B4 C00C 01B4 C010 01B4 C014 01B4 C018 01B4 C01C 01B4 C020 01B4 C024 01B4 C040 01B4 C044 01B4 C048 01B4 C04C 01B4 C050 01B4 C054 01B4 C05C 01B4 C060 01B4 C064 01B4 C068 01B4 C06C 01B4 C070 01B4 C074 01B4 C078 01B4 C07C 01B4 C080 01B4 C084 01B4 C088 01B4 C08C 01B4 C09C 01B4 C0A0 01B4 C0A4 01B4 C0A8 01B4 C0AC 01B4 C0B0 01B4 C0B4
01B5 0000 01B5 0004 01B5 0008 01B5 000C 01B5 0010 01B5 0014 01B5 0018 01B5 001C 01B5 0020 01B5 0024 01B5 0040 01B5 0044 01B5 0048 01B5 004C 01B5 0050 01B5 0054 01B5 005C 01B5 0060 01B5 0064 01B5 0068 01B5 006C 01B5 0070 01B5 0074 01B5 0078 01B5 007C 01B5 0080 01B5 0084 01B5 0088 01B5 008C 01B5 009C 01B5 00A0 01B5 00A4 01B5 00A8 01B5 00AC 01B5 00B0 01B5 00B4
MCASPPIDx PWRDEMUx PFUNCx PDIRx PDOUTx PDIN/PDSETx PDCLRx GBLCTLx AMUTEx DLBCTLx DITCTLx RGBLCTLx RMASKx RFMTx AFSRCTLx ACLKRCTLx AHCLKRCTLx RTDMx RINTCTLx RSTATx RSLOTx RCLKCHKx XGBLCTLx XMASKx XFMTx AFSXCTLx ACLKXCTLx AHCLKXCTLx
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peripheral register descriptions (continued)
Table McASP0 McASP1 Registers (Continued)
ADDRESS RANGE McASP0 01B4 C0B8 01B4 C0BC 01B4 C0C0 01B4 C0C4 01B4 C0C8 01B4 C0D0 01B4 C0FC 01B4 C100 01B4 C104 01B4 C108 01B4 C10C 01B4 C110 01B4 C114 01B4 C118 01B4 C11C 01B4 C120 01B4 C124 01B4 C128 01B4 C12C 01B4 C130 01B4 C134 01B4 C138 01B4 C13C 01B4 C140 01B4 C144 01B4 C148 01B4 C14C 01B4 C150 01B4 C154 01B4 C158 01B4 C15C 01B4 C160 01B4 C17C 01B4 C180 01B4 C184 01B4 C188 01B4 C18C 01B4 C190 01B4 C194 01B4 C198 01B4 C19C 01B4 C1A0 01B4 C1FC McASP1 01B5 00B8 01B5 00BC 01B5 00C0 01B5 00C4 01B5 00C8 01B5 00CC 01B5 00FC 01B5 0100 01B5 0104 01B5 0108 01B5 010C 01B5 0110 01B5 0114 01B5 0118 01B5 011C 01B5 0120 01B5 0124 01B5 0128 01B5 012C 01B5 0130 01B5 0134 01B5 0138 01B5 013C 01B5 0140 01B5 0144 01B5 0148 01B5 014C 01B5 0150 01B5 0154 01B5 0158 01B5 015C 01B5 0160 01B5 017C 01B5 0180 01B5 0184 01B5 0188 01B5 018C 01B5 0190 01B5 0194 01B5 0198 01B5 019C 01B5 01A0 01B5 01FC ACRONYM XTDMx XINTCTLx XSTATx XSLOTx XCLKCHKx DITCSRA0x DITCSRA1x DITCSRA2x DITCSRA3x DITCSRA4x DITCSRA5x DITCSRB0x DITCSRB1x DITCSRB2x DITCSRB3x DITCSRB4x DITCSRB5x DITUDRA0x DITUDRA1x DITUDRA2x DITUDRA3x DITUDRA4x DITUDRA5x DITUDRB0x DITUDRB1x DITUDRB2x DITUDRB3x DITUDRB4x DITUDRB5x SRCTL0x SRCTL1x SRCTL2x SRCTL3x SRCTL4x SRCTL5x SRCTL6x SRCTL7x REGISTER NAME Transmit slot 0-31 register Transmit interrupt control register Status register Transmitter Current transmit slot Transmit clock check control register Reserved Left (even slot) channel status register file Left (even slot) channel status register file Left (even slot) channel status register file Left (even slot) channel status register file Left (even slot) channel status register file Left (even slot) channel status register file Right (odd slot) channel status register file Right (odd slot) channel status register file Right (odd slot) channel status register file Right (odd slot) channel status register file Right (odd slot) channel status register file Right (odd slot) channel status register file Left (even slot) user data register file Left (even slot) user data register file Left (even slot) user data register file Left (even slot) user data register file Left (even slot) user data register file Left (even slot) user data register file Right (odd slot) user data register file Right (odd slot) user data register file Right (odd slot) user data register file Right (odd slot) user data register file Right (odd slot) user data register file Right (odd slot) user data register file Reserved Serializer control register Serializer control register Serializer control register Serializer control register Serializer control register Serializer control register Serializer control register Serializer control register Reserved
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peripheral register descriptions (continued)
Table McASP0 McASP1 Registers (Continued)
ADDRESS RANGE McASP0 01B4 C200 01B4 C204 01B4 C208 01B4 C20C 01B4 C210 01B4 C214 01B4 C218 01B4 C21C 01B4 C220 01B4 C27C 01B4 C280 01B4 C284 01B4 C288 01B4 C28C 01B4 C290 01B4 C294 01B4 C298 01B4 C29C 01B4 C2A0 01B4 FFFF McASP1 01B5 0200 01B5 0204 01B5 0208 01B5 020C 01B5 0210 01B5 0214 01B5 0218 01B5 021C 01B5 C220 01B5 027C 01B5 0280 01B5 0284 01B5 0288 01B5 028C 01B5 0290 01B5 0294 01B5 0298 01B5 029C 01B5 02A0 01B5 3FFF ACRONYM XBUF0x XBUF1x XBUF2x XBUF3x XBUF4x XBUF5x XBUF6x XBUF7x RBUF0x RBUF1x RBUF2x RBUF3x RBUF4x RBUF5x RBUF6x RBUF7x REGISTER NAME Transmit Buffer Serializer through configuration Transmit Buffer Serializer through configuration Transmit Buffer Serializer through configuration Transmit Buffer Serializer through configuration Transmit Buffer Serializer through configuration Transmit Buffer Serializer through configuration Transmit Buffer Serializer through configuration Transmit Buffer Serializer through configuration Reserved Receive Buffer Serializer through configuration Receive Buffer Serializer through configuration Receive Buffer Serializer through configuration Receive Buffer Serializer through configuration Receive Buffer Serializer through configuration Receive Buffer Serializer through configuration Receive Buffer Serializer through configuration Receive Buffer Serializer through configuration Reserved
transmit buffers serializers accessible peripheral XSEL (XFMT register). receive buffers serializers accessible peripheral RSEL (RFMT register).
Table I2C0 I2C1 Registers
ADDRESS RANGE I2C0 01B4 0000 01B4 0004 01B4 0008 01B4 000C 01B4 0010 01B4 0014 01B4 0018 01B4 001C 01B4 0020 01B4 0024 01B4 0028 01B4 002C 01B4 0030 01B4 0034 01B4 0038 01B4 003C 01B4 3FFF I2C1 01B4 4000 01B4 4004 01B4 4008 01B4 400C 01B4 4010 01B4 4014 01B4 4018 01B4 401C 01B4 4020 01B4 4024 01B4 4028 01B4 402C 01B4 4030 01B4 4034 01B4 4038 01B4 403C 01B4 7FFF ACRONYM I2COARx I2CIERx I2CSTRx I2CCLKLx I2CCLKHx I2CCNTx I2CDRRx I2CSARx I2CDXRx I2CMDRx I2CISRCx I2CPSCx I2CPID10 I2CPID11 I2CPID20 I2CPID21 REGISTER DESCRIPTION I2Cx address register I2Cx interrupt enable register I2Cx interrupt status register I2Cx clock low-time divider register I2Cx clock high-time divider register I2Cx data count register I2Cx data receive register I2Cx slave address register I2Cx data transmit register I2Cx mode register I2Cx interrupt source register Reserved I2Cx prescaler register I2Cx Peripheral Identification register [0x0000 0103] I2Cx Peripheral Identification register [0x0000 0005] Reserved
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peripheral register descriptions (continued)
Table Registers
ADDRESS RANGE 0188 0000 0188 0004 018B FFFF ACRONYM HPID HPIA HPIC REGISTER NAME data register address register control register Reserved COMMENTS Host read/write access only Host read/write access only Both Host/CPU read/write access
Table Timer Timer Registers
ADDRESS RANGE TIMER 0194 0000 TIMER 0198 0000 ACRONYM REGISTER NAME COMMENTS Determines operating mode timer, monitors timer status, controls function TOUT pin. Contains number timer input clock cycles count. This number controls TSTAT signal frequency. Contains current value incrementing counter.
CTLx
Timer control register
0194 0004
0198 0004
PRDx
Timer period register
0194 0008 0194 000C 0197 FFFF
0198 0008 0198 000C 019B FFFF
CNTx
Timer counter register Reserved
Table McBSP0 McBSP1 Registers
ADDRESS RANGE McBSP0 018C 0000 3000 0000 33FF FFFF 018C 0004 3000 0000 33FF FFFF 018C 0008 018C 000C 018C 0010 018C 0014 018C 0018 018C 001C 018C 0020 018C 0024 018C 0028 018F FFFF McBSP1 0190 0000 3400 0000 37FF FFFF 0190 0004 3400 0000 37FF FFFF 0190 0008 0190 000C 0190 0010 0190 0014 0190 0018 0190 001C 0190 0020 0190 0024 0190 0028 0193 FFFF ACRONYM REGISTER DESCRIPTION McBSPx data receive register Configuration DRRx DRRx DXRx DXRx SPCRx RCRx XCRx SRGRx MCRx RCERx XCERx PCRx EDMA controller only read this register; they cannot write McBSPx data receive register Peripheral Data McBSPx data transmit register Configuration McBSPx data transmit register Peripheral Data McBSPx serial port control register McBSPx receive control register McBSPx transmit control register McBSPx sample rate generator register McBSPx multichannel control register McBSPx receive channel enable register McBSPx transmit channel enable register McBSPx control register Reserved
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peripheral register descriptions (continued)
Table GPIO Registers
ADDRESS RANGE 01B0 0000 01B0 0004 01B0 0008 01B0 000C 01B0 0010 01B0 0014 01B0 0018 01B0 001C 01B0 0020 01B0 0024 01B0 0028 01B0 3FFF ACRONYM GPEN GPDIR GPVAL GPDH GPHM GPDL GPLM GPGC GPPOL REGISTER NAME GPIO enable register GPIO direction register GPIO value register Reserved GPIO delta high register GPIO high mask register GPIO delta register GPIO mask register GPIO global control register GPIO interrupt polarity register Reserved
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signal groups description
CLKIN CLKOUT2/GP[2] CLKOUT3 CLKMODE0 PLLHV Clock/PLL Oscillator
TRST EMU0 EMU1 EMU2 EMU3 EMU4 EMU5
Reset Interrupts
RESET HD4/GP[0]
IEEE Standard 1149.1 (JTAG) Emulation
Control/Status
HD15/GP[15] HD14/GP[14] HD13/GP[13] HD12/GP[12] HD11/GP[11] HD10/GP[10] HD9/GP[9] HD8/GP[8] HD7/GP[3] HD6/AHCLKR1 HD5/AHCLKX1 HD4/GP[0] HD3/AMUTE1 HD2/AFSX1 HD1/AXR1[7] HD0/AXR1[4]
(Host-Port Interface) HAS/ACLKX1 HR/W/AXR1[0] HCS/AXR1[2] HDS1/AXR1[6] HDS2/AXR1[5] HRDY/ACLKR1 HINT/GP[1]
Control
Data
Register Select
HCNTL0/AXR1[3] HCNTL1/AXR1[1]
Half-Word Select
HHWIL/AFSR1
These external pins applicable packages only. GP[15:0] pins, through interrupt sharing, external interrupt capable GPINT0. more details, External Interrupt Sources section this data sheet. more details interrupt sharing, TMS320C6000 Interrupt Selector Reference Guide (literature number SPRU646). these pins external interrupt sources. more details, External Interrupt Sources section this data sheet. NOTE multiplexed pins, bolded text denotes active function that particular peripheral module.
Figure (DSP Core) Peripheral Signals
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
signal groups description (continued)
HD15/GP[15] HD14/GP[14] HD13/GP[13] HD12/GP[12] HD11/GP[11] HD10/GP[10] HD9/GP[9] HD8/GP[8]
GPIO
GP[7](EXT_INT7) GP[6](EXT_INT6) GP[5](EXT_INT5)/AMUTEIN0 GP[4](EXT_INT4)/AMUTEIN1 HD7/GP[3] CLKOUT2/GP[2] HINT/GP[1] HD4/GP[0]
General-Purpose Input/Output (GPIO) Port
TOUT1/AXR0[4] TINP1/AHCLKX0
Timer
Timer
TOUT0/AXR0[2] TINP0/AXR0[3]
Timers
CLKS1/SCL1 DR1/SDA1
I2C1 I2Cs
I2C0
SCL0 SDA0
GP[15:0] pins, through interrupt sharing, external interrupt capable GPINT0. GP[15:0] also external EDMA event source capable. more details, External Interrupt Sources External EDMA Event Sources sections this data sheet. NOTE multiplexed pins, bolded text denotes active function that particular peripheral module.
Figure Peripheral Signals
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signal groups description (continued)
ED[31:16] ED[15:0]
Data Memory Control
ECLKIN ECLKOUT ARE/SDCAS/SSADS AOE/SDRAS/SSOE AWE/SDWE/SSWE ARDY
EA[21:2]
Memory Space Select Arbitration HOLD HOLDA BUSREQ
Address
Byte Enables EMIF (External Memory Interface)
McBSP1
McBSP0
CLKX1/AMUTE0 FSX1 DX1/AXR0[5]
Transmit
Transmit
CLKX0/ACLKX0 FSX0/AFSX0 DX0/AXR0[1]
CLKR1/AXR0[6] FSR1/AXR0[7] DR1/SDA1
Receive
Receive
CLKR0/ACLKR0 FSR0/AFSR0 DR0/AXR0[0]
CLKS1/SCL1
Clock
Clock
CLKS0/AHCLKR0
McBSPs (Multichannel Buffered Serial Ports)
These external pins applicable packages only. NOTE multiplexed pins, bolded text denotes active function that particular peripheral module.
Figure Peripheral Signals (Continued)
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signal groups description (continued)
(Transmit/Receive Data Pins) FSR1/AXR0[7] CLKR1/AXR0[6] DX1/AXR0[5] TOUT1/AXR0[4] TINP0/AXR0[3] TOUT0/AXR0[2] DX0/AXR0[1] DR0/AXR0[0]
8-Serial Ports Flexible Partitioning
(Receive Clock) CLKR0/ACLKR0 CLKS0/AHCLKR0 (Receive Master Clock) Transmit Clock Check Circuit Receive Clock Generator Transmit Clock Generator
(Transmit Clock) CLKX0/ACLKX0 TINP1/AHCLKX0 (Transmit Master Clock)
Receive Clock Check Circuit
FSR0/AFSR0 (Receive Frame Sync Left/Right Clock)
Receive Frame Sync
Transmit Frame Sync
FSX0/AFSX0 (Transmit Frame Sync Left/Right Clock) CLKX1/AMUTE0 GP[5](EXT_INT5)/AMUTEIN0
Error Detect (see Note
Auto Mute Logic
McASP0 (Multichannel Audio Serial Port
NOTES: McASPs' Error Detect function detects underruns, overruns, early/late frame syncs, errors, external mute input. multiplexed pins, bolded text denotes active function that particular peripheral module. Bolded italicized text within parentheses denotes function pins audio system.
Figure Peripheral Signals (Continued)
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
signal groups description (continued)
(Transmit/Receive Data Pins) HD1/AXR1[7] HDS1/AXR1[6] HDS2/AXR1[5] HD0/AXR1[4] HCNTL0/AXR1[3] HCS/AXR1[2] HCNTL1/AXR1[1] HR/W/AXR1[0]
8-Serial Ports Flexible Partitioning
(Receive Clock) HRDY/ACLKR1 HD6/AHCLKR1 (Receive Master Clock) Transmit Clock Check Circuit Receive Clock Generator Transmit Clock Generator
(Transmit Clock) HAS/ACLKX1 HD5/AHCLKX1 (Transmit Master Clock)
Receive Clock Check Circuit
HHWIL/AFSR1 (Receive Frame Sync Left/Right Clock)
Receive Frame Sync
Transmit Frame Sync
HD2/AFSX1 (Transmit Frame Sync Left/Right Clock) HD3/AMUTE1 GP[4](EXT_INT4)/AMUTEIN1
Error Detect (see Note
Auto Mute Logic
McASP1 (Multichannel Audio Serial Port
NOTES: McASPs' Error Detect function detects underruns, overruns, early/late frame syncs, errors, external mute input. multiplexed pins, bolded text denotes active function that particular peripheral module. Bolded italicized text within parentheses denotes function pins audio system.
Figure Peripheral Signals (Continued)
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
DEVICE CONFIGURATIONS
C6713B device, bootmode certain device configurations/peripheral selections determined device reset, while other device configurations/peripheral selections software-configurable device configurations register (DEVCFG) [address location 0x019C0200] after device reset.
device configurations device reset
Table describes device configuration pins, which internal external pullup/pulldown resistors through data pins (HD[4:3], HD8, HD12), CLKMODE0 pin. These configuration pins must desired state until reset released. proper device operation, oppose [13, 11:9, pins with external pullups/pulldowns reset. more details these device configuration pins, Terminal Functions table Debugging Considerations section this data sheet.
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Table Device Configurations Pins Device Reset (HD[4:3], HD8, HD12, CLKMODE0)
CONFIGURATION GDP/ZDP FUNCTIONAL DESCRIPTION EMIF Endian mode correctness (EMIFBE) C6713BGDP C6713BZDP: EMIF data will always presented ED[7:0] side bus, regardless endianess mode (Little/Big Endian). Little Endian mode (HD8 =1), 8-bit 16-bit EMIF data will present ED[7:0] side bus. Endian mode (HD8 =0), 8-bit 16-bit EMIF data will present ED[31:24] side [default]. C6713BPYP, when Endian mode selected (LENDIAN proper device operation EMIFBE must externally pulled low. This functionality does affect systems using current default value HD12=1. more detailed information endian mode correctness, EMIF Endian Mode Correctness portion this data sheet. Device Endian mode (LEND) System operates Endian mode System operates Little Endian mode (default) Bootmode Configuration Pins (BOOTMODE) boot/Emulation boot width 8-bit, Asynchronous external boot with default timings (default mode) width 16-bit, Asynchronous external boot with default timings width 32-bit, Asynchronous external boot with default timings more detailed information these bootmode configurations, bootmode section this data sheet. Clock generator input clock source select Reserved. use. CLKIN square wave [default]
HD12
HD[4:3] (BOOTMODE)
156,
C19,
CLKMODE0
This must pulled correct level even after reset. other pins [15, 11:9, 7:5, 2:0]) have pullups/pulldowns (IPUs IPDs). proper device operation [13, 11:9, oppose these pins with external pullups/pulldowns reset; however, HD[15, pins opposed driven during reset. Internal pulldown, Internal pullup. oppose supply rail these IPD/IPU signal pins, external pullup pulldown resistors greater than respectively.]
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
DEVICE CONFIGURATIONS (CONTINUED) peripheral selection device reset
Some peripherals share same pins (internally muxed) mutually exclusive (i.e., HPI, general-purpose input/output pins GP[15:8, McASP1).
HPI, McASP1, GPIO peripherals
HPI_EN (HD14 pin) latched reset. This selects whether peripheral pins McASP1 peripheral pins GP[15:8, pins functionally enabled (see Table 19). Table HPI_EN (HD14 Pin) Peripheral Selection (HPI McASP1, Select GPIO Pins)
PERIPHERAL SELECTION HPI_EN (HD14 Pin) [173, C14] PERIPHERAL PINS SELECTED McASP1 GP[15:8,3,1,0] DESCRIPTION
HPI_EN pins disabled; McASP1 peripheral pins GP[15:8, 1,0] pins enabled. multiplexed HPI/McASP1 HPI/GPIO pins function McASP1 GPIO pins, respectively. GPIO pins, appropriate bits GPEN GPDIR registers need configured. HPI_EN pins enabled; McASP1 peripheral pins GP[15:8, 1,0] pins disabled [default]. multiplexed HPI/McASP1 HPI/GPIO pins function pins.
HPI_EN (HD[14]) cannot controlled software.
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
DEVICE CONFIGURATIONS (CONTINUED) peripheral selection/device configurations DEVCFG control register
device configuration register (DEVCFG) allows user control availability McBSP0, McBSP1, McASP0, I2C1, Timer peripherals. DEVCFG register also offers user control EMIF input clock source timer output pins. more detailed information DEVCFG register control bits, Table Table Table Device Configuration Register (DEVCFG) [Address location: 0x019C0200 0x019C02FF]
Reserved RW-0 Reserved RW-0 Legend: Read/Write; value after reset write non-zero values these locations. EKSRC R/W-0 TOUT1SEL R/W-0 TOUT0SEL R/W-0 MCBSP0DIS R/W-0 MCBSP1DIS R/W-0
Table Device Configuration (DEVCFG) Register Selection Descriptions
31:5 NAME Reserved DESCRIPTION Reserved. write non-zero values these locations. EMIF input clock source bit. Determines which clock signal used EMIF input clock. SYSCLK3 (from clock generator) EMIF input clock source (default) ECLKIN external EMIF input clock source Timer output (TOUT1) function select bit. Selects function TOUT1/AXR0[4] external independent rest peripheral selection bits DEVCFG register. functions Timer output (TOUT1) (default) functions McASP0 transmit/receive data (AXR0[4]). Timer module still active. Timer output (TOUT0) function select bit. Selects function TOUT0/AXR0[2] external independent rest peripheral selection bits DEVCFG register. functions Timer output (TOUT0) (default) functions McASP0 transmit/receive data (AXR0[2]). Timer module still active. Multichannel Buffered Serial Port (McBSP0) disable bit. Selects whether McBSP0 McASP0 multiplexed peripheral pins enabled disabled. McBSP0 peripheral pins enabled, McASP0 peripheral pins (AHCLKR0, ACLKR0, ACLKX0, AXR0[0], AXR0[1], AFSR0, AFSX0) disabled (default). McASP0 data pins available, McASP0 peripheral functional mode only.] McBSP0 peripheral pins disabled, McASP0 peripheral pins (AHCLKR0, ACLKR0, ACLKX0, AXR0[0], AXR0[1], AFSR0, AFSX0) enabled. Multichannel Buffered Serial Port (McBSP1) disable bit. Selects whether McBSP1 I2C1 McASP0 multiplexed peripheral pins enabled disabled. McBSP1 peripheral pins enabled, I2C1 peripheral pins (SCL1 SDA1) McASP0 peripheral pins (AXR0[7:5] AMUTE0) disabled (default) McBSP1 peripheral pins disabled, I2C1 peripheral pins (SCL1 SDA1) McASP0 peripheral pins (AXR0[7:5] AMUTE0) enabled.
EKSRC
TOUT1SEL
TOUT0SEL
MCBSP0DIS
MCBSP1DIS
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
DEVICE CONFIGURATIONS (CONTINUED) multiplexed pins
Multiplexed pins pins that shared more than peripheral internally multiplexed. Most these pins configured software device configuration register (DEVCFG), others (specifically, pins) configured external pullup/pulldown resistors only reset. muxed pins that configured software programmed switch functionalities time. muxed pins that configured external pullup/pulldown resistors mutually exclusive; only peripheral primary control function these pins after reset. Table summarizes peripheral pins affected HPI_EN (HD14 pin) DEVCFG register. Table identifies multiplexed pins device; shows default (primary) function default settings after reset; describes pins, registers, etc. necessary configure specific multiplexed functions.
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
DEVICE CONFIGURATIONS (CONTINUED)
Table Peripheral Selection Matrix
SELECTION BITS PERIPHERAL PINS AVAILABILITY GP[0:1], GP[3], GP[8:15] None Plus: GP[2] ctrl'd GP2EN GP[0:1], GP[3], GP[8:15]
HPI_EN (boot config pin)
AHCLKX1 AHCLKR1 ACLKX1 ACLKR1 AFSX1 AFSR1 AMUTE1 AXR1[0] AXR1[7]
None
None ACLKX0 ACLKR0 AFSX0 AFSR0 AHCLKR0 AXR0[0] AXR0[1] AMUTE0 AXR0[5] AXR0[6] AXR0[7] AMUTE0 AXR0[5] AXR0[6] AXR0[7] AXR0[2] AXR0[2] AXR0[4] AXR0[4]
MCBSP0DIS (DEVCFG bit)
None
MCBSP1DIS (DEVCFG bit)
None
None
TOUT0SEL (DEVCFG bit) TOUT1SEL (DEVCFG bit) HD12 (boot config pin)
TOUT0 TOUT0 TOUT1 TOUT1 ED[7:0]; ED[7:0] side [HD8 (Little)] ED[31:24] side [HD8 (Big)]
Gray blocks indicate that peripheral affected selection bit. McASP0 pins AXR0[3] AHCLKX0 shared with timer input pins TINP0 TINP1, respectively. Table more detailed information. more detailed information endianness correction, EMIF Endian Mode Correctness portion this data sheet.
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DEVICE CONFIGURATIONS (CONTINUED)
Table C6713B Device Multiplexed/Shared Pins
MULTIPLEXED PINS NAME GDP/ DEFAULT FUNCTION DEFAULT SETTING DESCRIPTION When CLKOUT2 enabled, CLK2EN EMIF global control register (GBLCTL) controls CLKOUT2 pin. CLK2EN CLKOUT2 held high CLK2EN CLKOUT2 enabled clock [default] these software-configurable GPIO pins, GPxEN bits Enable Register GPxDIR bits Direction Register must properly configured. GPxEN GP[x] enabled GPxDIR GP[x] input GPxDIR GP[x] output AMUTEIN0/1 function, GP[5]/GP[4] pins must configured input, INEN polarity through INPOL selected associated McASP AMUTE register. default, McBSP0 peripheral pins enabled upon reset (McASP0 pins disabled). enable McASP0 peripheral pins, MCBSP0DIS DEVCFG register must (disabling McBSP0 peripheral pins). default, McBSP1 peripheral pins enabled upon reset (I2C1 McASP0 pins disabled). enable I2C1 McASP0 peripheral pins, MCBSP1DIS DEVCFG register must (disabling McBSP1 peripheral pins).
CLKOUT2/GP[2]
CLKOUT2
GP2EN (GPEN register bit) GP[2] function disabled, CLKOUT2 enabled
GP[5](EXT_INT5)/AMUTEIN0 GP[4](EXT_INT4)/AMUTEIN1
GP[5](EXT_INT5) GP[4](EXT_INT4)
Function GPxDIR (input) GP5EN (disabled) GP4EN (disabled) [(GPEN register bits) GP[x] function disabled]
CLKS0/AHCLKR0 DR0/AXR0[0] DX0/AXR0[1] FSR0/AFSR0 FSX0/AFSX0 CLKR0/ACLKR0 CLKX0/ACLKX0 CLKS1/SCL1 DR1/SDA1 DX1/AXR0[5] FSR1/AXR0[7] CLKR1/AXR0[6] CLKX1/AMUTE0
McBSP1 function MCBSP1DIS (DEVCFG register bit) I2C1 McASP0 pins disabled, McBSP1 pins enabled McBSP0 function MCBSP0DIS (DEVCFG register bit) McASP0 pins disabled, McBSP0 pins enabled
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DEVICE CONFIGURATIONS (CONTINUED)
Table C6713B Device Multiplexed/Shared Pins (Continued)
MULTIPLEXED PINS NAME HINT/GP[1] HD15/GP[15] HD14/GP[14] HD13/GP[13] HD12/GP[12] HD11/GP[11] HD10/GP[10] HD9/GP[9] HD8/GP[8] HD7/GP[3] HD4/GP[0] HD1/AXR1[7] HD0/AXR1[4] HCNTL1/AXR1[1] HCNTL0/AXR1[3] HR/W/AXR1[0] HDS1/AXR1[6] HDS2/AXR1[5] HCS/AXR1[2] HD6/AHCLKR1 HD5/AHCLKX1 HD3/AMUTE1 HD2/AFSX1 HHWIL/AFSR1 HRDY/ACLKR1 HAS/ACLKX1 GDP/ Timer input function McASP0PDIR (input) [specifically AXR0[3] bit] default, Timer input enabled (and shared input until McASP0 peripheral forces output). McASP0PDIR input, output default, Timer output enabled. TOUT0SEL (DEVCFG register bit) [TOUT0 enabled McASP0 AXR0[2] disabled] enable McASP0 AXR0[2] pin, TOUT0SEL DEVCFG register must (disabling Timer peripheral output function). AXR2 McASP0PDIR register controls direction (input/output) AXR0[2] McASP0PDIR input, output function McASP1 pins eleven GPIO pins disabled. HPI_EN (HD14 pin) (HPI enabled) these software-configurable GPIO pins, GPxEN bits Enable Register GPxDIR bits Direction Register must properly configured. GPxEN GP[x] enabled GPxDIR GP[x] input GPxDIR GP[x] output McASP1 direction controlled PDIR[x] bits McASP1PDIR register. default, peripheral pins enabled reset. McASP1 peripheral pins eleven GPIO pins disabled. enable McASP1 peripheral pins eleven GPIO pins, external pulldown resistor must provided HD14 setting HPI_EN reset. DEFAULT FUNCTION DEFAULT SETTING DESCRIPTION
TINP0/AXR0[3]
TOUT0/AXR0[2]
Timer output function
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DEVICE CONFIGURATIONS (CONTINUED)
Table C6713B Device Multiplexed/Shared Pins (Continued)
MULTIPLEXED PINS NAME GDP/ DEFAULT FUNCTION DEFAULT SETTING DESCRIPTION default, Timer input McASP0 clock function enabled inputs. McASP0 clock function output: McASP0PDIR (specifically AHCLKX bit] default, Timer output enabled. TOUT1SEL (DEVCFG register bit) [TOUT1 enabled McASP0 AXR0[4] disabled] enable McASP0 AXR0[4] pin, TOUT1SEL DEVCFG register must (disabling Timer peripheral output function). AXR4 McASP0PDIR register controls direction (input/output) AXR0[4] McASP0PDIR input, output
TINP1/AHCLKX0
Timer input function
McASP0PDIR (input) [specifically AHCLKX bit]
TOUT1/AXR0[4]
Timer output function
configuration examples
Figure through Figure illustrate examples peripheral selections that configurable this device.
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued)
[31:16], ED[15:0] EA[21:2] CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY Clock, System, EMU, Reset CLKIN, CLKOUT3, CLKMODE0, PLLHV, TMS, TDO, TDI, TCK, TRST, EMU[5:3,1,0], RESET,
EMIF
GP[15:8, 3:1] GPIO EXT_INT GP[0], GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7)
I2C0
SCL0, SDA0
SCL1, SDA1
I2C1
McASP1
AFSX1, AFSR1, ACLKX1, ACLKR1, AHCLKR1, AHCLKX1, AMUTE1 AXR1[7:0] AXR0[7:0] {TINP0/AXR0[3]}
McBSP1
McASP0 AMUTE0, TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0, AFSR0, AFSX0
TIMER0 McBSP0 TIMER1
Shading denotes peripheral module available this configuration. DEVCFG Register Value: 0x0000 000F MCBSP0DIS MCBSP1DIS TOUT0SEL TOUT1SEL EKSRC HPI_EN(HD14) GP2EN (enabling GPEN.[2])
Figure Configuration Example McASP GPIO)
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued)
[31:16], ED[15:0] EA[21:2] EMIF Clock, System, EMU, Reset CLKIN, CLKOUT3, CLKMODE0, PLLHV, TMS, TDO, TDI, TCK, TRST, EMU[5:3,1,0], RESET,
CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY
GP[15:8, 3:1] GPIO EXT_INT GP[0], GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7)
I2C0
SCL0, SDA0
I2C1
McASP1
AFSX1, AFSR1, ACLKX1, ACLKR1, AHCLKR1, AHCLKX1, AMUTE1 AXR1[7:0]
AXR0[4:0] {TINP0/AXR0[3]} DR1, CLKS1, CLKR1, CLKX1, FSR1, DX1, FSX1 McBSP1 McASP0 TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0, AFSR0, AFSX0
TIMER0 McBSP0 TIMER1
Shading denotes peripheral module available this configuration. DEVCFG Register Value: 0x0000 000E MCBSP0DIS MCBSP1DIS TOUT0SEL TOUT1SEL EKSRC HPI_EN(HD14) GP2EN (enabling GPEN.[2])
Figure Configuration Example McBSP McASP GPIO)
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued)
[31:16], ED[15:0] EA[21:2] EMIF Clock, System, EMU, Reset CLKIN, CLKOUT3, CLKMODE0, PLLHV, TMS, TDO, TDI, TCK, TRST, EMU[5:3,1,0], RESET,
CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY
GP[15:8, 3:1] GPIO EXT_INT GP[0], GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7)
I2C0
SCL0, SDA0
SCL1, SDA1
I2C1
McASP1
AFSX1, AFSR1, ACLKX1, ACLKR1, AHCLKR1, AHCLKX1, AMUTE1 AXR1[7:0]
McBSP1
McASP0 (DIT Mode)
AXR0[7:2] {TINP0/AXR0[3]}
AMUTE0, TINP1/AHCLKX0 TIMER0 DR0, CLKS0, CLKR0, CLKX0, FSR0, DX0, FSX0 McBSP0 TIMER1
Shading denotes peripheral module available this configuration. DEVCFG Register Value: 0x0000 000D MCBSP0DIS MCBSP1DIS TOUT0SEL TOUT1SEL EKSRC HPI_EN(HD14) GP2EN (enabling GPEN.[2])
Figure Configuration Example McBSP McASP McASP (DIT) GPIO]
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued)
[31:16], ED[15:0] EA[21:2] EMIF Clock, System, EMU, Reset CLKIN, CLKOUT3, CLKMODE0, PLLHV, TMS, TDO, TDI, TCK, TRST, EMU[5:3,1,0], RESET,
CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY
GP[15:8, 3:1] GPIO EXT_INT GP[0], GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7)
I2C0
SCL0, SDA0
I2C1
McASP1
AFSX1, AFSR1, ACLKX1, ACLKR1, AHCLKR1, AHCLKX1, AMUTE1 AXR1[7:0]
McASP0 (DIT Mode) AXR0[4:2] {TINP0/AXR0[3]}
DR1, CLKS1, CLKR1, CLKX1, FSR1, DX1, FSX1
McBSP1
TINP1/AHCLKX0
TIMER0 DR0, CLKS0, CLKR0, CLKX0, FSR0, DX0, FSX0 McBSP0 TIMER1
TOUT0/AXR0[2]
TOUT1/AXR0[4]
Shading denotes peripheral module available this configuration. DEVCFG Register Value: 0x0000 000C MCBSP0DIS MCBSP1DIS TOUT0SEL TOUT1SEL EKSRC HPI_EN(HD14) GP2EN (enabling GPEN.[2])
Figure Configuration Example McBSP McASP McASP (DIT) GPIO Timers]
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued)
[31:16], ED[15:0] EA[21:2] CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY EMIF Clock, System, EMU, Reset CLKIN, CLKOUT3, CLKMODE0, PLLHV, TMS, TDO, TDI, TCK, TRST, EMU[5:3,1,0], RESET, CLKOUT2
GPIO EXT_INT
GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7)
HD[15:0] HINT, HHWIL, HRDY, HR/W, HCNTRL1, HCNTRL0, HCS, HDS2, HDS1, SCL1, SDA1 I2C1 McASP1 I2C0 SCL0, SDA0
AXR0[7:0], {TINP0/AXR0[3]} McBSP1 McASP0 AMUTE0, TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0, AFSR0, AFSX0
TIMER0 McBSP0 TIMER1
Shading denotes peripheral module available this configuration. DEVCFG Register Value: 0x0000 000F MCBSP0DIS MCBSP1DIS TOUT0SEL TOUT1SEL EKSRC HPI_EN(HD14) GP2EN (enabling GPEN.[2])
Figure Configuration Example McASP)
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued)
[31:16], ED[15:0] EA[21:2] CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY EMIF Clock, System, EMU, Reset CLKIN, CLKOUT3, CLKMODE0, PLLHV, TMS, TDO, TDI, TCK, TRST, EMU[5:3,1,0], RESET, CLKOUT2
GPIO EXT_INT
GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7)
HD[15:0] HINT, HHWIL, HRDY, HR/W, HCNTRL1, HCNTRL0, HCS, HDS2, HDS1, I2C1 McASP1 I2C0 SCL0, SDA0
AXR0[4:0] {TINP0/AXR0[3]} DR1, CLKS1, CLKR1, CLKX1, FSR1, DX1, FSX1 McBSP1 McASP0 TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0, AFSR0, AFSX0
TIMER0 McBSP0 TIMER1
Shading denotes peripheral module available this configuration. DEVCFG Register Value: 0x0000 000E MCBSP0DIS MCBSP1DIS TOUT0SEL TOUT1SEL EKSRC HPI_EN(HD14) GP2EN (enabling GPEN.[2])
Figure Configuration Example McBSP McASP)
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
DEVICE CONFIGURATIONS (CONTINUED) debugging considerations
recommended that external connections provided peripheral selection/device configuration pins, including HD[14, CLKMODE0. Although internal pullup resistors exist these pins, providing external connectivity adds convenience user debugging flexibility switching operating modes. Internal pullup/pulldown resistors also exist non-configuration pins data HD[15, 11:9, 7:5, 2:0]. proper device operation HD[13, 11:9, oppose internal pullup/pulldown resistors these non-configuration pins with external pullup/pulldown resistors. external controller provides signals these HD[13, 11:9, non-configuration pins, these signals must driven default state pins reset, driven all. list routed out, 3-stated, not-driven pins recommended external pullup/pulldown resistors, internal pullup/pulldown resistors device pins, etc., Terminal Functions table. However, HD[15, non-configuration pins opposed driven during reset.
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
TERMINAL FUNCTIONS
terminal functions table identifies external signal names, associated (ball) numbers along with mechanical package designator, type O/Z, I/O/Z), whether internal pullup/pulldown resistors functional description. more detailed information device configuration, peripheral selection, multiplexed/shared pins, debugging considerations, Device Configurations section this data sheet. Terminal Functions
SIGNAL NAME GDP/ TYPE IPD/ CLOCK/PLL CONFIGURATION CLKIN CLKOUT2/GP[2] CLKOUT3 Clock Input Clock output half device speed (O/Z) [default] (SYSCLK2 internal signal from clock generator) this programmed GP[2] (I/O/Z) Clock output programmable OSCDIV1 register controller. Clock generator input clock source select Reserved, use. CLKIN square wave [default] proper device operation, this must either left unconnected externally pulled with resistor. Analog power (3.3 (PLL Filter) JTAG EMULATION EMU5 EMU4 EMU3 EMU2 I/O/Z I/O/Z I/O/Z I/O/Z JTAG test-port mode select JTAG test-port data JTAG test-port data JTAG test-port clock JTAG test-port reset. IEEE 1149.1 JTAG compatibility, IEEE 1149.1 JTAG Compatibility Statement section this data sheet. Emulation Reserved future use, leave unconnected. Emulation Reserved future use, leave unconnected. Emulation Reserved future use, leave unconnected. Emulation Reserved future use, leave unconnected. Emulation [1:0] pins Select device functional mode operation EMU[1:0] Operation Boundary Scan/Functional Mode (see Note) Reserved Reserved Emulation/Functional Mode [default] (see IEEE 1149.1 JTAG Compatibility Statement section this data sheet) placed Functional mode when EMU[1:0] pins configured either Boundary Scan Emulation. Note: When EMU[1:0] pins configured Boundary Scan mode, internal pulldown (IPD) TRST signal must opposed order operate Functional mode. Boundary Scan mode drive EMU[1:0] RESET pins low. Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. oppose supply rail these IPD/IPU signal pins, external pullup pulldown resistors greater than respectively.] ensure proper logic level during reset when these pins both routed 3-stated driven, recommended include external pullup/pulldown resistor sustain IPU/IPD, respectively. DESCRIPTION
CLKMODE0
PLLHV
EMU1 EMU0
I/O/Z
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
Terminal Functions (Continued)
SIGNAL NAME GDP/ TYPE IPD/ RESETS INTERRUPTS RESET Device reset. When using Boundary Scan mode, drive EMU[1:0] RESET pins low. this device, this does have IPU. Nonmaskable interrupt Edge-driven (rising edge) noise trigger interrupt; therefore, used, recommended that grounded versus relying IPD. General-purpose input/output pins (I/O/Z) which also function external interrupts Edge-driven Polarity independently selected External Interrupt Polarity Register bits (EXTPOL.[3:0]), addition GPIO registers. GP[4] GP[5] pins also function AMUTEIN1 McASP1 mute input AMUTEIN0 McASP0 mute input, respectively, enabled INEN associated McASP AMUTE register. HOST-PORT INTERFACE (HPI) HINT/GP[1] HCNTL1/AXR1[1] HCNTL0/AXR1[3] Host interrupt (from host) [default] this programmed GP[1] (I/O/Z). Host control selects between control, address, data registers [default] McASP1 data (I/O/Z). Host control selects between control, address, data registers [default] McASP1 data (I/O/Z). Host half-word select first second half-word (not necessarily high order) [default] McASP1 receive frame sync left/right clock (LRCLK) (I/O/Z). DESCRIPTION
GP[7](EXT_INT7) GP[6](EXT_INT6) GP[5](EXT_INT5)/ AMUTEIN0 GP[4](EXT_INT4)/ AMUTEIN1
I/O/Z
HHWIL/AFSR1
HR/W/AXR1[0] Host read write select [default] McASP1 data (I/O/Z). Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. oppose supply rail these IPD/IPU signal pins, external pullup pulldown resistors greater than respectively.]
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
Terminal Functions (Continued)
SIGNAL NAME GDP/ TYPE IPD/ DESCRIPTION
HOST-PORT INTERFACE (HPI) (CONTINUED) Host-port data pins (I/O/Z) [default] general-purpose input/output pins (I/O/Z) Used transfer data, address, control Also controls initialization modes reset pullup/pulldown resistors Device Endian Mode (HD8) Endian Little Endian C6713BGDP C6713BZDP: Endian Mode Correctness EMIFBE (HD12) EMIF data will always presented ED[7:0] side bus, regardless endianess mode (Little/Big Endian). Little Endian mode (HD8 =1), 8-bit 16-bit EMIF data will present ED[7:0] side bus. Endian mode (HD8 =0), 8-bit 16-bit EMIF data will present ED[31:24] side [default]. C6713BPYP, when Endian mode selected (LENDIAN proper device operation EMIFBE must externally pulled low. HD11/GP[11] I/O/Z This functionality does affect systems using current default value HD12=1. more detailed information endian mode correctness, EMIF Endian Mode Correctness portion this data sheet. Bootmode (HD[4:3]) boot/Emulation boot width 8-bit, Asynchronous external boot with default timings (default mode) width 16-bit, Asynchronous external boot with default timings width 32-bit, Asynchronous external boot with default timings HPI_EN (HD14) disabled, McASP1 enabled enabled, McASP1 disabled (default)
HD15/GP[15]
HD10/GP[10]
HD9/GP[9]
Other pins [13, 11:9, 7:5, 2:0] have pullups/pulldowns (IPUs/IPDs). proper device operation HD[13, 11:9, oppose these pins with external IPUs/IPDs reset; however, HD[15, pins opHD7/GP[3] posed driven reset. more details, Device Configurations section this data sheet. Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. oppose supply rail these IPD/IPU signal pins, external pullup pulldown resistors greater than respectively.] ensure proper logic level during reset when these pins both routed 3-stated driven, recommended include external pullup/pulldown resistor sustain IPU/IPD, respectively.
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Terminal Functions (Continued)
SIGNAL NAME GDP/ TYPE IPD/ DESCRIPTION
HOST-PORT INTERFACE (HPI) (CONTINUED) HD6/AHCLKR1 HD5/AHCLKX1 HD2/AFSX1 HD1/AXR1[7] HD0/AXR1[4] HAS/ACLKX1 HCS/AXR1[2] HDS1/AXR1[6] HDS2/AXR1[5] HRDY/ACLKR1 HOLDA HOLD I/O/Z I/O/Z I/O/Z I/O/Z Byte-enable control Decoded from lowest bits internal address Byte-write enables most types memory directly connected SDRAM read write mask signal (SDQM) Memory space enables Enabled bits through word address Only asserted during external data access Host-port data (I/O/Z) default] McASP1 receive high-frequency master clock (I/O/Z). Host-port data (I/O/Z) default] McASP1 transmit high-frequency master clock (I/O/Z). Host-port data (I/O/Z) default] this programmed GP[0] (I/O/Z). Host-port data (I/O/Z) default] McASP1 mute output (O/Z). Host-port data (I/O/Z) default] McASP1 transmit frame sync left/right clock (LRCLK) (I/O/Z). Host-port data (I/O/Z) default] McASP1 data (I/O/Z). Host-port data (I/O/Z) default] McASP1 data (I/O/Z). Host address strobe [default] McASP1 transmit clock (I/O/Z). Host chip select [default] McASP1 data (I/O/Z). Host data strobe [default] McASP1 data (I/O/Z). Host data strobe [default] McASP1 data (I/O/Z) Host ready (from host) [default] McASP1 receive clock (I/O/Z).
EMIF COMMON SIGNALS TYPES
EMIF Hold-request-acknowledge host Hold request from host
BUSREQ request output Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. oppose supply rail these IPD/IPU signal pins, external pullup pulldown resistors greater than respectively.] ensure proper logic level during reset when these pins both routed 3-stated driven, recommended include external pullup/pulldown resistor sustain IPU/IPD, respectively. maintain signal integrity EMIF signals, serial termination resistors should inserted into EMIF output signal lines.
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Terminal Functions (Continued)
SIGNAL NAME GDP/ TYPE IPD/ DESCRIPTION
EMIF ASYNCHRONOUS/SYNCHRONOUS MEMORY ECLKIN External EMIF input clock source EMIF output clock depends EKSRC (DEVCFG.[4]) EKEN (GBLCTL.[5]). EKSRC ECLKOUT based internal SYSCLK3 signal from clock generator (default). EKSRC ECLKOUT based external EMIF input clock source (ECLKIN) EKEN EKEN ARE/SDCAS/ SSADS AOE/SDRAS/ SSOE AWE/SDWE/ SSWE ARDY EA21 EA20 EA19 EA18 EA17 EA16 EA15 EA14 EA13 EA12 EA11 EA10 EMIF external address Note: EMIF address numbering C6713BPYP device starts with maintain signal name compatibility with other C671x devices (e.g., C6711, C6713BGDP C6713BZDP) [see 32-bit EMIF addressing scheme TMS320C6000 External Memory Interface (EMIF) Reference Guide (literature number SPRU266)]. ECLKOUT held ECLKOUT enabled clock (default)
ECLKOUT
Asynchronous memory read enable/SDRAM column-address strobe/SBSRAM address strobe Asynchronous memory output enable/SDRAM row-address strobe/SBSRAM output enable Asynchronous memory write enable/SDRAM write enable/SBSRAM write enable Asynchronous memory ready input EMIF
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. oppose supply rail these IPD/IPU signal pins, external pullup pulldown resistors greater than respectively.] maintain signal integrity EMIF signals, serial termination resistors should inserted into EMIF output signal lines.
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Terminal Functions (Continued)
SIGNAL NAME GDP/ TYPE IPD/ EMIF ED31 ED30 ED29 ED28 ED27 ED26 ED25 ED24 ED23 ED22 ED21 ED20 ED19 ED18 ED17 ED16 ED15 ED14 ED13 ED12 ED11 ED10 I/O/Z External data pins (ED[31:16] pins applicable packages only) DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. oppose supply rail these IPD/IPU signal pins, external pullup pulldown resistors greater than respectively.] maintain signal integrity EMIF signals, serial termination resistors should inserted into EMIF output signal lines.
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Terminal Functions (Continued)
SIGNAL TYPE IPD/ DESCRIPTION
MULTICHANNEL AUDIO SERIAL PORT (McASP1) GP[4](EXT_INT4)/ AMUTEIN1 HD3/AMUTE1 HRDY/ACLKR1 HD6/AHCLKR1 HAS/ACLKX1 HD5/AHCLKX1 I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z General-purpose input/output external interrupt (I/O/Z) [default] McASP1 mute input (I/O/Z). Host-port data (I/O/Z) default] McASP1 mute output (O/Z). Host ready (from host) [default] McASP1 receive clock (I/O/Z). Host-port data (I/O/Z) default] McASP1 receive high-frequency master clock (I/O/Z). Host address strobe [default] McASP transmit clock (I/O/Z). Host-port data (I/O/Z) default] McASP1 transmit high-frequency master clock (I/O/Z). Host half-word select first second half-word (not necessarily high order) [default] McASP1 receive frame sync left/right clock (LRCLK) (I/O/Z). Host-port data (I/O/Z) default] McASP1 transmit frame sync left/ right clock (LRCLK) (I/O/Z). Host-port data (I/O/Z) default] McASP1 TX/RX data (I/O/Z). Host data strobe [default] McASP1 TX/RX data (I/O/Z). Host data strobe [default] McASP1 TX/RX data (I/O/Z). Host-port data (I/O/Z) default] McASP1 TX/RX data (I/O/Z). Host control selects between control, address, data registers [default] McASP1 TX/RX data (I/O/Z). Host chip select [default] McASP1 TX/RX data (I/O/Z). Host control selects between control, address, data registers [default] McASP1 TX/RX data (I/O/Z). Host read write select [default] McASP1 TX/RX data (I/O/Z). General-purpose input/output external interrupt (I/O/Z) [default] McASP0 mute input (I/O/Z). McBSP1 transmit clock (I/O/Z) [default] McASP0 mute output (O/Z). McBSP0 receive clock (I/O/Z) [default] McASP0 receive clock (I/O/Z). Timer input McASP0 transmit high-frequency master clock (I/O/Z). This defaults Timer input McASP transmit high-frequency master clock input (I). McBSP0 transmit clock (I/O/Z) [default] McASP0 transmit clock (I/O/Z). McBSP0 external clock source opposed internal) [default] McASP0 receive high-frequency master clock (I/O/Z). McBSP0 receive frame sync (I/O/Z) [default] McASP0 receive frame sync left/right clock (LRCLK) (I/O/Z). McBSP0 transmit frame sync (I/O/Z) [default] McASP0 transmit frame sync left/right clock (LRCLK) (I/O/Z). McBSP1 receive frame sync (I/O/Z) [default] McASP0 TX/RX data (I/O/Z).
HHWIL/AFSR1
I/O/Z
HD2/AFSX1 HD1/AXR1[7] HDS1/AXR1[6] HDS2/AXR1[5] HD0/AXR1[4] HCNTL0/AXR1[3] HCS/AXR1[2] HCNTL1/AXR1[1] HR/W/AXR1[0] GP[5](EXT_INT5)/ AMUTEIN0 CLKX1/AMUTE0 CLKR0/ACLKR0 TINP1/AHCLKX0 CLKX0/ACLKX0 CLKS0/AHCLKR0 FSR0/AFSR0 FSX0/AFSX0 FSR1/AXR0[7]
I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z
MULTICHANNEL AUDIO SERIAL PORT (McASP0) I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. oppose supply rail these IPD/IPU signal pins, external pullup pulldown resistors greater than respectively.]
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Terminal Functions (Continued)
SIGNAL NAME GDP/ TYPE IPD/ DESCRIPTION
MULTICHANNEL AUDIO SERIAL PORT (McASP0) (CONTINUED) CLKR1/AXR0[6] DX1/AXR0[5] TOUT1/AXR0[4] TINP0/AXR0[3] TOUT0/AXR0[2] DX0/AXR0[1] DR0/AXR0[0] TOUT1/AXR0[4] TINP1/AHCLKX0 I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z McBSP1 receive clock (I/O/Z) [default] McASP0 TX/RX data (I/O/Z). McBSP1 transmit data (O/Z) [default] McASP0 TX/RX data (I/O/Z). Timer output [default] McASP0 TX/RX data (I/O/Z). Timer input [default] McASP0 TX/RX data (I/O/Z). Timer output [default] McASP0 TX/RX data (I/O/Z). McBSP0 transmit data (O/Z) [default] McASP0 TX/RX data (I/O/Z). McBSP0 receive data [default] McASP0 TX/RX data (I/O/Z). TIMER Timer output [default] McASP0 TX/RX data (I/O/Z). Timer input McASP0 transmit high-frequency master clock (I/O/Z). This defaults Timer input McASP transmit high-frequency master clock input (I). TIMER0 TOUT0/AXR0[2] TINP0/AXR0[3] Timer output [default] McASP0 TX/RX data (I/O/Z). Timer input [default] McASP0 TX/RX data (I/O/Z). McBSP1 external clock source opposed internal) [default] I2C1 clock (I/O/Z). This does have internal pullup pulldown. When this used McBSP pin, this should either driven externally times pulled with 10-k resistor valid logic level. Because common some 3-state their outputs times, 10-k pullup resistor desirable even when external device driving pin. McBSP1 receive clock (I/O/Z) [default] McASP0 TX/RX data (I/O/Z). McBSP1 transmit clock (I/O/Z) [default] McASP0 mute output (O/Z). McBSP1 receive data [default] I2C1 data (I/O/Z). This does have internal pullup pulldown. When this used McBSP pin, this should either driven externally times pulled with 10-k resistor valid logic level. Because common some 3-state their outputs times, 10-k pullup resistor desirable even when external device driving pin. McBSP1 transmit data (O/Z) [default] McASP0 TX/RX data (I/O/Z). McBSP1 receive frame sync (I/O/Z) [default] McASP0 TX/RX data (I/O/Z).
MULTICHANNEL BUFFERED SERIAL PORT (McBSP1)
CLKS1/SCL1
CLKR1/AXR0[6] CLKX1/AMUTE0
I/O/Z I/O/Z
DR1/SDA1
DX1/AXR0[5] FSR1/AXR0[7]
I/O/Z
FSX1 I/O/Z McBSP1 transmit frame sync Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. oppose supply rail these IPD/IPU signal pins, external pullup pulldown resistors greater than respectively.]
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Terminal Functions (Continued)
SIGNAL NAME GDP/ TYPE IPD/ DESCRIPTION
MULTICHANNEL BUFFERED SERIAL PORT (McBSP0) CLKS0/AHCLKR0 CLKR0/ACLKR0 CLKX0/ACLKX0 DR0/AXR0[0] DX0/AXR0[1] FSR0/AFSR0 FSX0/AFSX0 I/O/Z I/O/Z I/O/Z I/O/Z McBSP0 external clock source opposed internal) [default] McASP0 receive high-frequency master clock (I/O/Z). McBSP0 receive clock (I/O/Z) [default] McASP0 receive clock (I/O/Z). McBSP0 transmit clock (I/O/Z) [default] McASP0 transmit clock (I/O/Z). McBSP0 receive data [default] McASP0 TX/RX data (I/O/Z). McBSP0 transmit data (O/Z) [default] McASP0 TX/RX data (I/O/Z). McBSP0 receive frame sync (I/O/Z) [default] McASP0 receive frame sync left/right clock (LRCLK) (I/O/Z). McBSP0 transmit frame sync (I/O/Z) [default] McASP0 transmit frame sync left/right clock (LRCLK) (I/O/Z).
INTER-INTEGRATED CIRCUIT (I2C1) McBSP1 external clock source opposed internal) [default] I2C1 clock (I/O/Z). This must externally pulled When this used pin, value pullup resistor dependent number devices connected bus. more details, Philips Specification Revision (January 2000). McBSP1 receive data [default] I2C1 data (I/O/Z). This must externally pulled When this used pin, value pullup resistor dependent number devices connected bus. more details, Philips Specification Revision (January 2000).
CLKS1/SCL1
I/O/Z
DR1/SDA1
I/O/Z
INTER-INTEGRATED CIRCUIT (I2C0) I2C0 clock. This must externally pulled value pullup resistor this dependent number devices connected bus. more details, Philips Specification Revision (January 2000). I2C0 data. This must externally pulled value pullup resistor this dependent number devices connected bus. more details, Philips Specification Revision (January 2000).
SCL0
I/O/Z
SDA0
I/O/Z
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. oppose supply rail these IPD/IPU signal pins, external pullup pulldown resistors greater than respectively.]
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Terminal Functions (Continued)
SIGNAL NAME GDP/ TYPE IPD/ DESCRIPTION
GENERAL-PURPOSE INPUT/OUTPUT (GPIO) HD15/GP[15] HD14/GP[14] HD13/GP[13] HD12/GP[12] HD11/GP[11] HD10/GP[10] HD9/GP[9] HD8/GP[8] GP[7](EXT_INT7) GP[6](EXT_INT6) GP[5](EXT_INT5)/ AMUTEIN0 GP[4](EXT_INT4)/ AMUTEIN1 HD7/GP[3] CLKOUT2/GP[2] HINT/GP[1] HD4/GP[0] I/O/Z I/O/Z GPxEN GP[x] enabled. GPxDIR GP[x] input. GPxDIR GP[x] output. functionality description Host-port data pins boot configuration pins, Host-Port Interface (HPI) portion this table. General-purpose input/output pins (I/O/Z) which also function external interrupts Edge-driven Polarity independently selected External Interrupt Polarity Register bits (EXTPOL.[3:0]) GP[4] GP[5] pins also function AMUTEIN1 McASP1 mute input AMUTEIN0 McASP0 mute input, respectively, enabled INEN associated McASP AMUTE register. I/O/Z I/O/Z I/O/Z Host-port data (I/O/Z) [default] general-purpose input/output (I/O/Z) Clock output half device speed (O/Z) [default] this programmed GP[2] pin. Host interrupt (from host) [default] this programmed GP[1] (I/O/Z). Host-port data (I/O/Z) default] this programmed GP[0] (I/O/Z). Host-port data pins (I/O/Z) [default] general-purpose input/output pins (I/O/Z) some function boot configuration pins reset. Used transfer data, address, control Also controls initialization modes reset pullup/pulldown resistors general-purpose input/output (GP[x]) functions, these pins software-configurable through registers. "GPxEN" bits Enable register GPxDIR bits Direction register must properly configured:
RESERVED TEST Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. This does have IPU. proper device operation, must externally pulled down with 10-k resistor. Reserved. [For designs, recommended that this connected directly CVDD (core power). designs, this left unconnected.
Reserved. [For designs, recommended that this connected directly (ground). designs, this left unconnected. Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. oppose supply rail these IPD/IPU signal pins, external pullup pulldown resistors greater than respectively.]
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Terminal Functions (Continued)
SIGNAL NAME GDP/ TYPE SUPPLY VOLTAGE PINS DVDD 3.3-V supply voltage (see power-supply decoupling portion this data sheet) DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal
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Terminal Functions (Continued)
SIGNAL NAME GDP/ TYPE DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) DVDD CVDD Note: This value compatible with existing 1.26-V designs. 1.2-V supply voltage [PYP package] 1.20-V supply voltage [GDP packages] (See Note) 1.4-V supply voltage [GDP packages C6711D-300 only] (see power-supply decoupling portion this data sheet) 3.3-V supply voltage (see power-supply decoupling portion this data sheet)
Input, Output, High impedance, Supply voltage, Ground, Analog signal
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Terminal Functions (Continued)
SIGNAL NAME GDP/ TYPE DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) CVDD GROUND PINS Ground pins Note: This value compatible with existing 1.26-V designs. 1.2-V supply voltage [PYP package] 1.20-V supply voltage [GDP packages] (See Note) 1.4-V supply voltage [GDP packages C6711D-300 only] (see power-supply decoupling portion this data sheet)
Input, Output, High impedance, Supply voltage, Ground, Analog signal
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Terminal Functions (Continued)
SIGNAL NAME GDP/ TYPE GROUND PINS (CONTINUED) Ground pins# center thermal balls (J9-J12, K9-K12, L9-L12, M9-M12) [shaded] tied ground both electrical grounds thermal relief (thermal dissipation). DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Shaded numbers denote center thermal balls.
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Terminal Functions (Continued)
SIGNAL NAME GDP/ TYPE GROUND PINS (CONTINUED) Ground pins DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
Terminal Functions (Continued)
SIGNAL NAME GDP/ TYPE GROUND PINS (CONTINUED) Ground pins DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal
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development support
offers extensive line development tools TMS320C6000 platform, including tools evaluate performance processors, generate code, develop algorithm implementations, fully integrate debug software hardware modules. following products support development C6000 DSP-based applications: Software Development Tools: Code Composer Studio Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP/BIOS), which provides basic run-time target software needed support application. Hardware Development Tools: Extended Development System (XDS) Emulator (supports C6000 multiprocessor system debug) (Evaluation Module) complete listing development-support tools TMS320C6000 platform, visit Texas Instruments site Worldwide http://www.ti.com uniform resource locator (URL). information pricing availability, contact nearest field sales office authorized distributor. offers extensive line development tools TMS320C6000 platform, including tools evaluate performance processors, generate code, develop algorithm implementations, fully integrate debug software hardware modules.
C6000 trademarks Texas Instruments.
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device support
device development-support tool nomenclature designate stages product development cycle, assigns prefixes part numbers devices support tools. Each commercial family member three prefixes: TMX, TMP, TMS. (e.g., TMS320C6713BGDP300). Texas Instruments recommends three possible prefix designators support tools: TMDX TMDS. These prefixes represent evolutionary stages product development from engineering prototypes (TMX TMDX) through fully qualified production devices/tools (TMS TMDS). Device development evolutionary flow: Experimental device that necessarily representative final device's electrical specifications. Final silicon that conforms device's electrical specifications completed quality reliability verification. Fully qualified production device.
Support tool development evolutionary flow: TMDX Development-support product that completed Texas Instruments internal qualification testing. Fully qualified development-support product.
TMDS
devices TMDX development-support tools shipped with following disclaimer: "Developmental product intended internal evaluation purposes." devices TMDS development-support tools have been characterized fully, quality reliability device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (TMX TMP) have greater failure rate than standard production devices. Texas Instruments recommends that these devices used production system because their expected end-use failure rate still undefined. Only qualified production devices used. device nomenclature also includes suffix with device family name. This suffix indicates package type (for example, GDP), temperature range (for example, blank default commercial temperature range), device speed range megahertz (for example, -225 MHz). package, like package, 272-ball plastic only with Pb-free balls. device part numbers further ordering information TMS320C6713B PYP, package types, website (http://www.ti.com) contact your sales representative.
TMS320 trademark Texas Instruments.
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
device development-support tool nomenclature (continued)
6713B
DEVICE SPEED RANGE PREFIX Experimental device Prototype device Qualified device MIL-PRF-38535, High (non-38535)
TEMPERATURE RANGE (DEFAULT: 90°C) Blank 90°C, commercial temperature -40°C 105°C, extended temperature
DEVICE FAMILY TMS320 family
PACKAGE 272-pin plastic 208-pin PowerPADt plastic 272-pin plastic BGA, with Pb-free soldered balls
TECHNOLOGY CMOS
DEVICE C6713B Ball Grid Array Quad Flatpack mechanical package designator represents version with Pb-Free soldered balls. package devices supported same speed grades package devices (available upon request). actual device part numbers (P/Ns) ordering information, Mechanical Data section this document website (www.ti.com).
Figure TMS320C6000 Device Nomenclature (Including TMS320C6713B Device)
MicroStar PowerPAD trademarks Texas Instruments.
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
documentation support Extensive documentation supports TMS320 family generations devices from product announcement through applications development. types documentation available include: data sheets, such this document, with design specifications; complete user's reference guides devices tools; technical briefs; development-support tools; on-line help; hardware software applications. following brief, descriptive list support documentation specific C6000 devices: TMS320C6000 Instruction Reference Guide (literature number SPRU189) describes C6000 (DSP core) architecture, instruction set, pipeline, associated interrupts. TMS320C6000 Peripherals Overview Reference Guide [hereafter referred C6000 Overview] (literature number SPRU190) provides overview briefly describes functionality peripherals available C6000 platform devices. This document also includes table listing peripherals available C6000 devices along with literature numbers hyperlinks associated peripheral documents. These C6713B peripherals similar peripherals TMS320C6711 TMS320C64x devices; therefore, TMS320C6711 (C6711 C67x) peripheral information, some cases, where indicated, TMS320C6711 (C6711 C671x) peripheral information some cases, where indicated, C64x information C6000 Overview (literature number SPRU190). TMS320DA6000 Multichannel Audio Serial Port (McASP) Reference Guide (literature number SPRU041) describes functionality McASP peripherals available C6713B device. TMS320C6000 Software-Programmable Phase-Locked Loop (PLL) Controller Reference Guide (literature number SPRU233) describes functionality peripheral available C6713B device. TMS320C6000 Inter-Integrated Circuit (I2C) Module Reference Guide (literature number SPRU175) describes functionality peripherals available C6713B device. PowerPAD Thermally Enhanced Package Technical Brief (literature number SLMA002) focuses specifics integrating PowerPAD package into printed circuit board design make optimum thermal efficiencies designed into PowerPAD package. TMS320C6000 Technical Brief (literature number SPRU197) gives introduction C62x/C67x devices, associated development tools, third-party support. Migrating from TMS320C6211(B)/C6711(B) TMS320C6713 application report (literature number SPRA851) indicates differences describes issues interest related migration from Texas Instruments TMS320C6211(B)/C6711(B), package, TMS320C6713, packages. TMS320C6713, TMS320C6713B Digital Signal Processors Silicon Errata (literature number SPRZ191) describes known exceptions functional specifications particular silicon revisions TMS320C6713B device. TMS320C6711D, C6712D, C6713B Power Consumption Summary application report (literature number SPRA889A2 later) discusses power consumption user applications with TMS320C6713B, TMS320C6712D, TMS320C6711D devices. Using IBIS Models Timing Analysis application report (literature number SPRA839) describes properly IBIS models attain accurate timing analysis given system. tools support documentation electronically available within Code Composer Studio Integrated Development Environment (IDE). complete listing C6000 latest documentation, visit Texas Instruments site Worldwide http://www.ti.com uniform resource locator (URL). Worldwide application report Begin Development Today With TMS320C6713 Floating-Point (literature number SPRA809), which describes more detail similarities/differences between C6713 C6711 C6000 devices.
C62x trademark Texas Instruments.
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
register description
control status register (CSR) contains Revision (bits 16-31) well status device power-down modes [PWRD field (bits 15-10)], program data cache control modes, endian (EN, global interrupt enable (GIE, previous (PGIE, Figure Table identify fields register. more detailed information fields register, TMS320C6000 Peripherals Overview Reference Guide (literature number SPRU190) TMS320C6000 Instruction Reference Guide (literature number SPRU189).
REVISION R-0x03
R-0x02
PWRD
R/W-0
R/C-0
R/W-0
R/W-0
PGIE R/W-0
R/W-0
Legend: Readable instruction, Readable/Writeable instruction; Read/write; value after reset, undefined value after
reset, Clearable instruction
Figure Control Status Register (CPU CSR)
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
register description (continued)
Table Register Field Description
31:24 23:16 NAME REVISION DESCRIPTION Read only. Identifies which used defines silicon revision CPU. REVISION (31:16) combined value 0x0203 Control power-down modes. values always read zero. 000000 001001 010001 011010 011100 Others power-down (default) PD1, wake-up enabled interrupt PD1, wake-up enabled enabled interrupt PD2, wake-up device reset PD3, wake-up device reset Reserved
15:10
PWRD
Saturate bit. when unit performs saturate. This cleared only instruction only functional unit. functional unit priority over clear instruction) they occur same cycle. saturate full cycle (one delay slot) after saturate occurs. This will modified conditional instruction whose condition false. Endian bit. This read-only. Depicts device endian mode. Endian mode. Little Endian mode [default]. Program Cache control mode. L1D, Level Program Cache 000/010 Cache Enabled Cache accessed updated reads. other values reserved. Data Cache control mode. L1D, Level Data Cache 000/010 Cache Enabled 2-Way Cache other values reserved Previous (global interrupt enable); saves Global Interrupt Enable (GIE) when interrupt taken. Allows proper nesting interrupts.
PGIE Previous value (default) Previous value Global interrupt enable bit. Enables disables interrupts except reset interrupt (nonmaskable interrupt).
Disables interrupts (except reset interrupt NMI) [default] Enables interrupts (except reset interrupt NMI)
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
cache configuration (CCFG) register description
C6713B device includes enhancement cache configuration (CCFG) register. (CCFG.31) allows programmer select priority accesses memory originating from transfer crossbar (TC) over accesses originating from memory system. important class accesses EDMA transfers, which move data from memory. While EDMA normally issue accessing memory high rates memory system, there pathological cases where certain behavior could block EDMA from accessing memory long enough cause missed deadline when transferring data peripheral such McASP McBSP. This avoided setting because EDMA will assume higher priority than memory system when accessing memory. more detailed information P-bit function silicon advisories concerning EDMA memory accesses blocked, TMS320C6713, TMS320C6713B Digital Signal Processors Silicon Errata (literature number SPRZ191).
Reserved 0000
L2MODE R/W-000
R/W-0
Reserved
Legend: Readable; Readable/Writeable; value after reset; undefined value after reset This device includes bit.
Figure Cache Configuration Register (CCFG) Table CCFG Register Field Description
30:10 NAME Reserved DESCRIPTION requestor priority bit. requests higher priority than requests requests higher priority than requests Reserved. Read-only, writes have effect. Invalidate bit. Normal operation lines invalidated Invalidate bit. Normal operation lines invalidated Reserved. Read-only, writes have effect. operation mode bits (L2MODE). 000b 001b 010b 011b 111b others Cache disabled (All SRAM mode) [256K SRAM] 1-way Cache (16K Cache) [240K SRAM] 2-way Cache (32K Cache) [224K SRAM] 3-way Cache (48K Cache) [208K SRAM] 4-way Cache (64K Cache) [192K SRAM] Reserved
Reserved
L2MODE
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
interrupts interrupt selector
C67x core supports prioritized interrupts, which listed Table highest priority interrupt INT_00 (dedicated RESET) while lowest priority INT_15. first four interrupts non-maskable fixed. remaining interrupts (4-15) maskable default interrupt source listed Table However, their interrupt source reprogrammed sources listed Table (Interrupt Selector). Table lists selector value corresponding each alternate interrupt sources. selector choice interrupts 4-15 made programming corresponding fields (listed Table MUXH (address 0x019C0000) MUXL (address 0x019C0004) registers.
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TMS320C6713B FLOATING POINT DIGITAL SIGNAL PROCESSOR
Table Interrupts
INTERRUPT NUMBER INT_00 INT_01 INT_02 INT_03 INT_04 INT_05 INT_06 INT_07 INT_08 INT_09 INT_10 INT_11 INT_12 INT_13 INT_14 INT_15 INTERRUPT SELECTOR CONTROL REGISTER MUXL[4:0] MUXL[9:5] MUXL[14:10] MUXL[20:16] MUXL[25:21] MUXL[30:26] MUXH[4:0] MUXH[9:5] MUXH[14:10] MUXH[20:16] MUXH[25:21] MUXH[30:26] DEFAULT SELECTOR VALUE (BINARY) 00100 00101 00110 00111 01000 01001 00011 01010 01011 00000 00001 00010 DEFAULT INTERRUPT EVENT RESET Reserved Reserved GPINT4 GPINT5 GPINT6 GPINT7 EDMAINT EMUDTDMA SDINT EMURTDXRX EMURTDXTX DSPINT TINT0 TINT1
Table Interrupt Selector
INTERRUPT SELECTOR VALUE (BINARY) 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 INTERRUPT EVENT DSPINT TINT0 TINT1 SDINT GPINT4 GPINT5 GPINT6 GPINT7 EDMAINT EMUDTDMA EMURTDXRX EMURTDXTX XINT0 RINT0 XINT1 RINT1 GPINT0 Reserved Reserved Reserved Reserved Reserved I2CINT0 I2CINT1 Reserved Reserved Reserved Reserved AXINT0 ARINT0 AXINT1 ARINT1 MODULE
Timer Timer EMIF GPIO GPIO GPIO GPIO EDMA Emulation Emulation Emulation McBSP0 McBSP0 McBSP1 McBSP1 GPIO I2C0 I2C1 McASP0 McASP0 McASP1 McASP1
Interrupt Events GPINT4, GPINT5, GPINT6, GPINT7 outputs from GPIO module (GP). They originate from device pins GP[4](EXT_
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