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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
Low-Price/High-Performance Floating-Point
Digital Signal Processor (DSP): TMS320C6712D Eight 32-Bit Instructions/Cycle 150-MHz Clock Rate 6.7-ns Instruction Cycle Time MFLOPS Advanced Very Long Instruction Word (VLIW) C67x Core Eight Highly Independent Functional Units: Four ALUs (Floating- Fixed-Point) ALUs (Fixed-Point) Multipliers (Floating- Fixed-Point) Load-Store Architecture With 32-Bit General-Purpose Registers Instruction Packing Reduces Code Size Instructions Conditional Instruction Features Hardware Support IEEE Single-Precision Double-Precision Instructions Byte-Addressable (8-, 16-, 32-Bit Data) 8-Bit Overflow Protection Saturation Bit-Field Extract, Set, Clear Bit-Counting Normalization L1/L2 Memory Architecture 32K-Bit (4K-Byte) Program Cache (Direct Mapped) 32K-Bit (4K-Byte) Data Cache (2-Way Set-Associative) 512K-Bit (64K-Byte) Unified Mapped RAM/Cache (Flexible Data/Program Allocation) Device Configuration Boot Mode: 16-Bit Boot Little Endian, Endian Enhanced Direct-Memory-Access (EDMA) Controller Independent Channels)
16-Bit External Memory Interface (EMIF)
Glueless Interface Asynchronous Memories: SRAM EPROM Glueless Interface Synchronous Memories: SDRAM SBSRAM 256M-Byte Total Addressable External Memory Space Multichannel Buffered Serial Ports (McBSPs) Direct Interface T1/E1, MVIP, SCSA Framers ST-Bus-Switching Compatible Channels Each AC97-Compatible Serial-Peripheral-Interface (SPI) Compatible (Motorola) 32-Bit General-Purpose Timers Flexible Software-Configurable PLL-Based Clock Generator Module Dedicated General-Purpose Input/Output (GPIO) Module With Pins IEEE-1149.1 (JTAG) Boundary-Scan-Compatible 272-Pin Ball Grid Array (BGA) Package (GDP Suffix) CMOS Technology 0.13-µm/6-Level Copper Metal Process 3.3-V I/Os, 1.20-V Internal
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
TMS320C67x C67x trademarks Texas Instruments. Motorola trademark Motorola, Inc. Other trademarks property their respective owners. IEEE Standard 1149.1-1990 Standard-Test-Access Port Boundary Scan Architecture. These values compatible with existing 1.26V designs.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2005, Texas Instruments Incorporated
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
Table Contents
revision history package (bottom view) description device characteristics device compatibility functional block (DSP core) diagram (DSP core) description memory summary peripheral register descriptions signal groups description device configurations terminal functions development support device support register description cache configuration (CCFG) register description interrupt sources interrupt selector EDMA module EDMA selector controller general-purpose input/output (GPIO) power-down mode logic power-supply sequencing power-supply decoupling IEEE 1149.1 JTAG compatibility statement EMIF device speed EMIF endian mode correctness bootmode reset absolute maximum ratings over operating case temperature range recommended operating conditions electrical characteristics over recommended ranges supply voltage operating case temperature
parameter measurement information signal transition levels timing parameters board routing analysis input output clocks asynchronous memory timing synchronous-burst memory timing synchronous DRAM timing HOLD/HOLDA timing BUSREQ timing reset timing external interrupt timing multichannel buffered serial port timing timer timing general-purpose input/output (GPIO) port timing JTAG test-port timing mechanical data
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
REVISION HISTORY
TMS320C6712D device-specific documentation been split from TMS320C6712, TMS320C6712C, TMS320C6712D Floating-Point Digital Signal Processors, literature number SPRS148L, into separate Data Sheet, literature number SPRS293. also highlights technical changes made SPRS293 generate SPRS293A; these changes marked "[Revision Revision History table below Scope: Updated information McBSP JTAG clarification. Changed Description (Revisions SPRS293 SPRS293A). Updated Nomenclature figure adding device-specific information package. Recommends designs that following pins configured such:
connected directly CVDD (core power) connected directly (ground)
PAGE(S) ADDITIONS/CHANGES/DELETIONS Device Configurations, device configurations device reset section: Added Note Terminal Functions, Bootmode section: Added Note Terminal Functions, Little/Big Endian Format section: Added Note Terminal Functions, Resets Interrupts section: Updated IPU/IPD RESET Signal Name from "IPU" Terminal Functions, Reserved Test section: Changed "IPU" Changed "IPU" Updated Type from Terminal Functions, Reserved Test section: Updated Description Signal Name, GDP/ZDP Updated Description Signal Name, GDP/ZDP Terminal Functions, Reserved Test section: Updated/changed Description Signal Name, "recommended") [Revision Updated/changed Description Signal Name, "recommended") [Revision Device Support, device development-support tool nomenclature: Updated figure clarity Device Support, document support section: Updated paragraphs clarity IEEE 1149.1 JTAG Compatibility Statement section: Updated/added paragraphs clarity Recommended Operating Conditions: Added VOS, Maximum voltage during overshoot associated footnote Added VUS, Maximum voltage during undershoot associated footnote Parameter Measurement Information: transient rise/fall time specifications section: Added Transient Specification Rise Time figure Added Transient Specification Fall Time figure
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
PAGE(S) RESET TIMING section: Added Note
ADDITIONS/CHANGES/DELETIONS
MULTICHANNEL BUFFERED SERIAL PORT TIMING: switching characteristics over recommended operating conditions McBSP section: Updated McBSP Timings figure clarification
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
package (bottom view)
272-PIN BALL GRID ARRAY (BGA) PACKAGE BOTTOM VIEW
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
description
TMS320C67x (including TMS320C6712, TMS320C6712C, TMS320C6712D devices) members floating-point family TMS320C6000 platform. C6712, C6712C, C6712D devices based high-performance, advanced very-long-instruction-word (VLIW) architecture developed Texas Instruments (TI), making these DSPs excellent choice multichannel multifunction applications. With performance million floating-point operations second (MFLOPS) clock rate MHz, C6712D device lowest-cost C6000 platform. C6712D possesses operational flexibility high-speed controllers numerical capability array processors. This processor general-purpose registers 32-bit word length eight highly independent functional units. eight functional units provide four floating-/fixed-point ALUs, fixed-point ALUs, floating-/fixed-point multipliers. C6712D produce MACs cycle total MMACS. C6712D uses two-level cache-based architecture powerful diverse peripherals. Level program cache (L1P) 32-Kbit direct mapped cache Level data cache (L1D) 32-Kbit 2-way set-associative cache. Level memory/cache (L2) consists 512-Kbit memory space that shared between program data space. memory configured mapped memory, cache, combinations two. peripheral includes multichannel buffered serial ports (McBSPs), general-purpose timers, glueless 16-bit external memory interface (EMIF) capable interfacing SDRAM, SBSRAM, asynchronous peripherals. C6712D device also includes dedicated general-purpose input/output (GPIO) peripheral module. C6712D also application-specific hardware logic, on-chip memory, additional on-chip peripherals. C6712D complete development tools which includes: compiler, assembly optimizer simplify programming scheduling, Windows debugger interface visibility into source code execution.
TMS320C6000 C6000 trademarks Texas Instruments. Windows registered trademark Microsoft Corporation. Throughout remainder this document, TMS320C6712D shall referred individual full device part number abbreviated C6712D 12D.
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
device characteristics
Table provides overview DSP. table shows significant features device, including capacity on-chip RAM, peripherals, execution time, package type with count. more details C6000 device part numbers part numbering, Figure Table Characteristics C6712D Processor
HARDWARE FEATURES EMIF EDMA Peripherals McBSPs 32-Bit Timers GPIO Module Size (Bytes) INTERNAL CLOCK SOURCE ECLKIN SYSCLK3 ECLKIN clock frequency CPU/2 clock frequency SYSCLK2 CPU/4 clock frequency SYSCLK2 SYSCLK2 4K-Byte (4KB) Program (L1P) Cache Data (L1D) Cache 64KB Unified Mapped RAM/Cache (L2) 0x0203 1.20 272-Pin (GDP ZDP) 0.13 C6712D (FLOATING-POINT DSP)
On-Chip Memory
Organization
Frequency Cycle Time Voltage Options Clock Generator Options
Control Status Register (CSR.[31:16]) Core CLKIN frequency multiplier Prescaler Multiplier Postscaler
Package Process Technology Product Status Product Preview (PP) Advance Information (AI) Production Data (PD)
This value compatible with existing 1.26V designs. PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
device compatibility
TMS320C6712 C6211/C6711 devices pin-compatible; thus, making system designs easier providing faster time market. following list summarizes device characteristic differences among C6211, C6211B, C6711, C6711B, C6711C, C6711D, C6712, C6712C, C6712D devices:
C6211 C6211B devices have fixed-point TMS320C62x core (CPU), while C6711,
C6711B, C6711C, C6711D, C6712, C6712C, C6712D devices have floating-point C67x CPU.
C6211, C6211B, C6711, C6711B, C6711C, C6711D devices have 32-bit EMIF, while C6712,
C6712C, C6712D devices have 16-bit EMIF.
C6211, C6211B, C6711, C6711B, C6711C, C6711D devices feature HPI, while C6712,
C6712C, C6712D devices not.
C6712, C6712C, C6712D devices have dedicated device configuration pins, BOOTMODE,
LENDIAN, EMIFBE (12D only) that specify boot-load operation device endianness, respectively, during reset. C6211/C6211B C6711/C6711B/C6711C/C6711D devices, these configuration pins integrated with pins.
C6211/C6211B device runs -167 -150 clock speeds (with C6211BGFNA extended
temperature device that also runs -150 MHz), while C6711/C6711B device runs -150 -100 (with C6711BGFNA extended temperature device that also runs -100 MHz) C6711C/C6711D device runs -200 clock speed (with C6711CGDPA extended temperature device that also runs -167 MHz). C6712 device runs -100 clock speed C6712C/C6712D device runs -150 clock speed.
C6211/C6211B, C6711-100, C6711B C6712 devices have core voltage C6711-150
device core voltage C6711C/C6711D C6712C/C6712D devices operate with core voltage 1.20
There several enhancements features that only available C6711C/C6711D
C6712C/C6712D devices, such CLKOUT3 signal, software-programmable Controller, GPIO peripheral module. C6711D C6712D devices also have additional enhancements such EMIF Endian mode correctness EMIFBE requestor priority ["P" bit] cache configuration (CCFG) register. C6712D supports Endian mode.
C6712/C6712C/C6712D lowest-cost entry TMS320C6000 platform.
more detailed discussion similarities/differences among C6211, C6711, C6712 devices, Begin Development Today with TMS320C6211 DSP, Begin Development with TMS320C6711 DSP, Begin Development With TMS320C6712 application reports (literature number SPRA474, SPRA522, SPRA693, respectively). more detailed discussion migration C6211, C6211B, C6711, C6711B device TMS320C6711C device, Migrating from TMS320C6211(B)/6711(B) TMS320C6711C application report (literature number SPRA837). more detailed discussion migration C6712 device TMS320C6712C device, Migrating from TMS320C6712 TMS320C6712C application report (literature number SPRA852).
TMS320C62x C67x trademarks Texas Instruments. This value compatible with existing 1.26V designs.
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
functional block (DSP core) diagram
SDRAM SBSRAM SRAM ROM/FLASH Devices Timer C67x (DSP Core) Timer Enhanced Controller channel) Memory Banks Bytes Total Instruction Fetch Instruction Dispatch Instruction Decode Data Path Register File Data Path Register File Control Registers Control Logic Test In-Circuit Emulation Interrupt Control
Digital Signal Processor
External Memory Interface (EMIF) Cache Direct Mapped Bytes Total
Framing Chips: H.100, MVIP, SCSA, AC97 Devices, Devices, Codecs
Multichannel Buffered Serial Port (McBSP1)
Multichannel Buffered Serial Port (McBSP0)
Interrupt Selector Power-Down Logic
Cache 2-Way Associative Bytes Total
GPIO
Boot Configuration
addition fixed-point instructions, these functional units execute floating-point instructions. device software-configurable (with through multiplier through divider) Controller.
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
(DSP core) description
fetches advanced very-long instruction words (VLIW) (256 bits wide) supply eight 32-bit instructions eight functional units during every clock cycle. VLIW architecture features controls which eight units have supplied with instructions they ready execute. first every 32-bit instruction determines next instruction belongs same execute packet previous instruction, whether should executed following clock part next execute packet. Fetch packets always bits wide; however, execute packets vary size. variable-length execute packets memory-saving feature, distinguishing C67x from other VLIW architectures. features sets functional units. Each contains four units register file. contains functional units .L1, .S1, .M1, .D1; other contains units .D2, .M2, .S2, .L2. register files each contain 32-bit registers total general-purpose registers. sets functional units, along with register files, compose sides [see functional block (DSP Core) diagram Figure four functional units each side freely share registers belonging that side. Additionally, each side features single data connected registers other side, which sets functional units access data from register files opposite side. While register access functional units same side register file service units single clock cycle, register access using register file across supports read write cycle. C67x executes C62x instructions. addition C62x fixed-point instructions, eight functional units (.L1, .M1, .D1, .D2, .M2, .L2) also execute floating-point instructions. remaining functional units (.S1 .S2) also execute LDDW instruction which loads bits side total bits cycle. Another feature C67x load/store architecture, where instructions operate registers opposed data memory). sets data-addressing units (.D1 .D2) responsible data transfers between register files memory. data address driven units allows data addresses generated from register file used load store data from other register file. C67x supports variety indirect addressing modes using either linear- circular-addressing modes with 15-bit offsets. instructions conditional, most access registers. Some registers, however, singled support specific addressing hold condition conditional instructions condition automatically "true"). functional units dedicated multiplies. functional units perform general arithmetic, logical, branch functions with results available every clock cycle. processing flow begins when 256-bit-wide instruction fetch packet fetched from program memory. 32-bit instructions destined individual functional units "linked" together bits least significant (LSB) position instructions. instructions that "chained" together simultaneous execution eight total) compose execute packet. instruction breaks chain, effectively placing instructions that follow next execute packet. execute packet crosses fetch-packet boundary (256 bits wide), assembler places next fetch packet, while remainder current fetch packet padded with instructions. number execute packets within fetch packet vary from eight. Execute packets dispatched their respective functional units rate clock cycle next 256-bit fetch packet fetched until execute packets from current fetch packet have been dispatched. After decoding, instructions simultaneously drive active functional units maximum execution rate eight instructions every clock cycle. While most results stored 32-bit registers, they subsequently moved memory bytes half-words well. load store instructions byte-, half-word, word-addressable.
C62x trademark Texas Instruments.
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
(DSP core) description (continued)
src1
src2
long long
Data Path
src2
src1 src2
src1 src2
src2 src1
src2
src1 src2
Data Path
src1 long long
src1
addition fixed-point instructions, these functional units execute floating-point instructions.
Figure TMS320C67x (DSP Core) Data Paths
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long long src2
long long src1
Register File (A0-A15) Register File (B0-B15) Control Register File
TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
memory summary
Table shows memory address ranges device. Internal memory always located address used both program data memory. configuration registers common peripherals located same address ranges. external memory address ranges device begin address location 0x8000 0000. Table Memory Summary
MEMORY BLOCK DESCRIPTION Internal (L2) Reserved External Memory Interface (EMIF) Registers Registers Reserved McBSP Registers McBSP Registers Timer Registers Timer Registers Interrupt Selector Registers Device Configuration Registers Reserved EDMA EDMA Registers Reserved GPIO Registers Reserved Controller Registers Reserved QDMA Registers Reserved McBSP Data/Peripheral Data McBSP Data/Peripheral Data Reserved Reserved EMIF EMIF EMIF EMIF Reserved BLOCK SIZE (BYTES) 256K 256K 256K 256K 256K 256K 256K 256K 256K 768K 480K 520K 736M 256M 256M 256M 256M ADDRESS RANGE 0000 0000 0000 FFFF 0001 0000 017F FFFF 0180 0000 0183 FFFF 0184 0000 0187 FFFF 0188 0000 018B FFFF 018C 0000 018F FFFF 0190 0000 0193 FFFF 0194 0000 0197 FFFF 0198 0000 019B FFFF 019C 0000 019C 01FF 019C 0200 019C 0203 019C 0204 019F FFFF 01A0 0000 01A3 FFFF 01A4 0000 01AF FFFF 01B0 0000 01B0 3FFF 01B0 4000 01B7 BFFF 01B7 C000 01B7 DFFF 01B7 E000 01FF FFFF 0200 0000 0200 0033 0200 0034 2FFF FFFF 3000 0000 33FF FFFF 3400 0000 37FF FFFF 3800 0000 3BFF FFFF 3C00 0000 7FFF FFFF 8000 0000 8FFF FFFF 9000 0000 9FFF FFFF A000 0000 AFFF FFFF B000 0000 BFFF FFFF
C000 0000 FFFF FFFF number EMIF address pins (EA[21:2]) limits maximum addressable memory (SDRAM) 128MB space. 256MB addressable memory, additional general-purpose output external logic required.
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
peripheral register descriptions
Table through Table identify peripheral registers device their register names, acronyms, address address range. more detailed information register contents, names, their descriptions, specific peripheral reference guide listed TMS320C6000 Peripherals Overview Reference Guide (literature number SPRU190). Table EMIF Registers
ADDRESS RANGE 0180 0000 0180 0004 0180 0008 0180 000C 0180 0010 0180 0014 0180 0018 0180 001C 0180 0020 0180 0024 0183 FFFF ACRONYM GBLCTL CECTL1 CECTL0 CECTL2 CECTL3 SDCTL SDTIM SDEXT EMIF global control EMIF space control EMIF space control Reserved EMIF space control EMIF space control EMIF SDRAM control EMIF SDRAM refresh control EMIF SDRAM extension Reserved REGISTER NAME
Table Cache Registers
ADDRESS RANGE 0184 0000 0184 4000 0184 4004 0184 4010 0184 4014 0184 4020 0184 4024 0184 4030 0184 4034 0184 5000 0184 5004 0184 8200 0184 8204 0184 8208 0184 820C 0184 8240 0184 8244 0184 8248 0184 824C 0184 8280 0184 8284 0184 8288 0184 828C 0184 82C0 0184 82C4 0184 82C8 0184 82CC 0184 82D0 0187 FFFF ACRONYM CCFG L2WBAR L2WWC L2WIBAR L2WIWC L1PIBAR L1PIWC L1DWIBAR L1DWIWC L2WB L2WBINV MAR0 MAR1 MAR2 MAR3 MAR4 MAR5 MAR6 MAR7 MAR8 MAR9 MAR10 MAR11 MAR12 MAR13 MAR14 MAR15 Cache configuration register writeback base address register writeback word count register writeback-invalidate base address register writeback-invalidate word count register invalidate base address register invalidate word count register writeback-invalidate base address register writeback-invalidate word count register writeback register writeback-invalidate register Controls range 8000 0000 80FF FFFF Controls range 8100 0000 81FF FFFF Controls range 8200 0000 82FF FFFF Controls range 8300 0000 83FF FFFF Controls range 9000 0000 90FF FFFF Controls range 9100 0000 91FF FFFF Controls range 9200 0000 92FF FFFF Controls range 9300 0000 93FF FFFF Controls range A000 0000 A0FF FFFF Controls range A100 0000 A1FF FFFF Controls range A200 0000 A2FF FFFF Controls range A300 0000 A3FF FFFF Controls range B000 0000 B0FF FFFF Controls range B100 0000 B1FF FFFF Controls range B200 0000 B2FF FFFF Controls range B300 0000 B3FF FFFF Reserved REGISTER NAME
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
peripheral register descriptions (continued)
Table Interrupt Selector Registers
ADDRESS RANGE 019C 0000 019C 0004 019C 0008 019C 000C 019F FFFF ACRONYM MUXH MUXL EXTPOL REGISTER NAME Interrupt multiplexer high Interrupt multiplexer External interrupt polarity Reserved COMMENTS Selects which interrupts drive interrupts 10-15 (INT10-INT15) Selects which interrupts drive interrupts (INT04-INT09) Sets polarity external interrupts (EXT_INT4-EXT_INT7)
Table Device Registers
ADDRESS RANGE 019C 0200 019C 0204 019F FFFF ACRONYM DEVCFG Device Configuration Reserved Identifies which defines silicon revision CPU. This register also offers user control device operation. more detailed information Control Status Register, Register Description section this data sheet. REGISTER DESCRIPTION This register allows user control EMIF input clock source. more detailed information device configuration register, Device Configurations section this data sheet.
Control Status Register
Table EDMA Parameter
ADDRESS RANGE 01A0 0000 01A0 0017 01A0 0018 01A0 002F 01A0 0030 01A0 0047 01A0 0048 01A0 005F 01A0 0060 01A0 0077 01A0 0078 01A0 008F 01A0 0090 01A0 00A7 01A0 00A8 01A0 00BF 01A0 00C0 01A0 00D7 01A0 00D8 01A0 00EF 01A0 00F0 01A0 00107 01A0 0108 01A0 011F 01A0 0120 01A0 0137 01A0 0138 01A0 014F 01A0 0150 01A0 0167 01A0 0168 01A0 017F 01A0 0180 01A0 0197 01A0 0198 01A0 01AF 01A0 07E0 01A0 07F7 01A0 07F8 01A0 07FF ACRONYM REGISTER NAME Parameters Event words) Reload/Link Parameters other Event Parameters Event words) Reload/Link Parameters other Event Parameters Event words) Reload/Link Parameters other Event Parameters Event words) Reload/Link Parameters other Event Parameters Event words) Reload/Link Parameters other Event Parameters Event words) Reload/Link Parameters other Event Parameters Event words) Reload/Link Parameters other Event Parameters Event words) Reload/Link Parameters other Event Parameters Event words) Reload/Link Parameters other Event Parameters Event words) Reload/Link Parameters other Event Parameters Event words) Reload/Link Parameters other Event Parameters Event words) Reload/Link Parameters other Event Parameters Event words) Reload/Link Parameters other Event Parameters Event words) Reload/Link Parameters other Event Parameters Event words) Reload/Link Parameters other Event Parameters Event words) Reload/Link Parameters other Event Reload/link parameters Event 0-15 Reload/link parameters Event 0-15 Reload/link parameters Event 0-15
Scratch area words) device EDMA parameters total: Event/Reload parameters Reload-only parameters.
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
peripheral register descriptions (continued)
more details EDMA parameter 6-word parameter entry structure, Figure
Word Word Word Word Word Word EDMA Channel Options Parameter (OPT) EDMA Channel Source Address (SRC) Array/Frame Count (FRMCNT) Array/Frame Index (FRMIDX) Element Count Reload (ELERLD) Element Count (ELECNT) Element Index (ELEIDX) Link Address (LINK) EDMA Channel Destination Address (DST)
EDMA Parameter
Figure EDMA Channel Parameter Entries Words) Each EDMA Event Table EDMA Registers
ADDRESS RANGE 01A0 0800 01A0 FEFC 01A0 FF00 01A0 FF04 01A0 FF08 01A0 FF0B 01A0 FF0C 01A0 FF1F 01A0 FFDC 01A0 FFE0 01A0 FFE4 01A0 FFE8 01A0 FFEC 01A0 FFF0 01A0 FFF4 01A0 FFF8 01A0 FFFC 01A1 0000 01A3 FFFF ACRONYM ESEL0 ESEL1 ESEL3 PQSR CIPR CIER CCER Reserved EDMA event selector EDMA event selector Reserved EDMA event selector Reserved Priority queue status register Channel interrupt pending register Channel interrupt enable register Channel chain enable register Event register Event enable register Event clear register Event register Reserved REGISTER NAME
Table Quick (QDMA) Pseudo Registers
ADDRESS RANGE 0200 0000 0200 0004 0200 0008 0200 000C 0200 0010 0200 0014 0200 001C 0200 0020 0200 0024 0200 0028 0200 002C 0200 0030 ACRONYM QOPT QSRC QCNT QDST QIDX QSOPT QSSRC QSCNT QSDST QSIDX QDMA options parameter register QDMA source address register QDMA frame count register QDMA destination address register QDMA index register Reserved QDMA pseudo options register QDMA pseudo source address register QDMA pseudo frame count register QDMA pseudo destination address register REGISTER NAME
QDMA pseudo index register QDMA Pseudo registers write-accessible only
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
peripheral register descriptions (continued)
Table Controller Registers
ADDRESS RANGE 01B7 C000 01B7 C004 01B7 C0FF 01B7 C100 01B7 C104 01B7 C10F 01B7 C110 01B7 C114 01B7 C118 01B7 C11C 01B7 C120 01B7 C124 01B7 C128 01B7 DFFF ACRONYM PLLPID PLLCSR PLLM PLLDIV0 PLLDIV1 PLLDIV2 PLLDIV3 OSCDIV1 Reserved control/status register Reserved multiplier control register controller divider register controller divider register controller divider register controller divider register Oscillator divider register Reserved REGISTER NAME Peripheral identification register (PID) [0x00010801 Controller]
Table GPIO Registers
ADDRESS RANGE 01B0 0000 01B0 0004 01B0 0008 01B0 000C 01B0 0010 01B0 0014 01B0 0018 01B0 001C 01B0 0020 01B0 0024 01B0 0028 01B0 3FFF ACRONYM GPEN GPDIR GPVAL GPDH GPHM GPDL GPLM GPGC GPPOL REGISTER NAME GPIO enable register GPIO direction register GPIO value register Reserved GPIO delta high register GPIO high mask register GPIO delta register GPIO mask register GPIO global control register GPIO interrupt polarity register Reserved
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
peripheral register descriptions (continued)
Table Timer Timer Registers
ADDRESS RANGE TIMER 0194 0000 TIMER 0198 0000 ACRONYM REGISTER NAME COMMENTS Determines operating mode timer, monitors timer status, controls function TOUT pin. Contains number timer input clock cycles count. This number controls TSTAT signal frequency. Contains current value incrementing counter.
CTLx
Timer control register
0194 0004
0198 0004
PRDx
Timer period register
0194 0008 0194 000C 0197 FFFF
0198 0008 0198 000C 019B FFFF
CNTx
Timer counter register Reserved
Table McBSP0 McBSP1 Registers
ADDRESS RANGE McBSP0 018C 0000 3000 0000 33FF FFFF 018C 0004 3000 0000 33FF FFFF 018C 0008 018C 000C 018C 0010 018C 0014 018C 0018 018C 001C 018C 0020 018C 0024 018C 0028 018F FFFF McBSP1 0190 0000 3400 0000 37FF FFFF 0190 0004 3400 0000 37FF FFFF 0190 0008 0190 000C 0190 0010 0190 0014 0190 0018 0190 001C 0190 0020 0190 0024 0190 0028 0193 FFFF ACRONYM REGISTER DESCRIPTION McBSPx data receive register Configuration DRRx DRRx DXRx DXRx SPCRx RCRx XCRx SRGRx MCRx RCERx XCERx PCRx EDMA controller only read this register; they cannot write McBSPx data receive register Peripheral Data McBSPx data transmit register Configuration McBSPx data transmit register Peripheral Data McBSPx serial port control register McBSPx receive control register McBSPx transmit control register McBSPx sample rate generator register McBSPx multichannel control register McBSPx receive channel enable register McBSPx transmit channel enable register McBSPx control register Reserved
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
signal groups description
CLKIN CLKOUT3 CLKOUT2 CLKMODE0 PLLHV BIG/LITTLE ENDIAN LENDIAN Clock/PLL Reset Interrupts RESET EXT_INT7 EXT_INT6 EXT_INT5 EXT_INT4
TRST EMU0 EMU1 EMU2 EMU3 EMU4 EMU5
IEEE Standard 1149.1 (JTAG) Emulation Reserved
BOOTMODE Control/Status
BOOTMODE1 BOOTMODE0
ED[15:0] EA[21:2] Data Memory Control Memory Space Select ECLKIN ECLKOUT ARE/SDCAS/SSADS AOE/SDRAS/SSOE AWE/SDWE/SSWE ARDY
Address Arbitration
HOLD HOLDA BUSREQ
Byte Enables EMIF (16-bit) (External Memory Interface)
CLKOUT2 multiplexed with GP[2] pin. Default function CLKOUT2. this GPIO, GP2EN GPEN register GP2DIR GPDIR register must properly configured. external interrupts (EXT_INT[7-4]) through general-purpose input/output (GPIO) module. When used interrupt inputs, GP[7-4] pins must configured inputs (via GPDIR register) enabled (via GPEN register) addition enabling interrupts interrupt enable register (IER). This functions Endian mode correctness used when Endian mode selected (LENDIAN
Figure (DSP Core) Peripheral Signals
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
signal groups description (continued)
TOUT1 TINP1
Timer
Timer
TOUT0 TINP0
Timers
McBSP1
McBSP0
CLKX1 FSX1
Transmit
Transmit
CLKX0 FSX0
CLKR1 FSR1
Receive
Receive
CLKR0 FSR0
CLKS1
Clock
Clock
CLKS0
McBSPs (Multichannel Buffered Serial Ports)
GPIO
GP[7](EXT_INT7) GP[6](EXT_INT6) GP[5](EXT_INT5) GP[4](EXT_INT4) CLKOUT2/GP[2]
General-Purpose Input/Output (GPIO) Port proper device operation, these pins must externally pulled with 10-k resistor.
Figure Peripheral Signals
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DEVICE CONFIGURATIONS
device, bootmode certain device configurations/peripheral selections determined device reset. Other device configurations (e.g., EMIF input clock source) software-configurable device configurations register (DEVCFG) [address location 0x019C0200] after device reset.
device configurations device reset
Table describes device configuration pins, which internal external pullup/pulldown resistors through LENDIAN, EMIFBE, BOOTMODE[1:0], CLKMODE0 pins. These configuration pins must desired state until reset released. more details these device configuration pins, Terminal Functions table this data sheet. Note: configuration must routed from device, internal pullup/pulldown (IPU/IPD) resistor should relied upon; recommends external pullup/pulldown resistor.
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Table Device Configurations Pins Device Reset (LENDIAN, EMIFBE, BOOTMODE[1:0], CLKMODE0)
CONFIGURATION GDP/ZDP FUNCTIONAL DESCRIPTION EMIF Endian mode correctness (EMIFBE) When Endian mode selected (LENDIAN proper device operation EMIFBE must externally pulled low. This functionality does affect systems using current default value pin=1. more detailed information Endian mode correctness, EMIF Endian Mode Correctness portion this data sheet. Device Endian mode (LEND) System operates Endian mode. EMIFBE must pulled low. System operates Little Endian mode (default) Bootmode Configuration Pins (BOOTMODE) Emulation boot width 8-bit, Asynchronous external boot with default timings (default mode) width 16-bit, Asynchronous external boot with default timings Reserved, more detailed information these bootmode configurations, bootmode section this data sheet. Clock generator input clock source select Reserved. use. CLKIN square wave [default] proper device operation, this must either left unconnected externally pulled with resistor.
EMIFBE
LENDIAN
BOOTMODE[1:0]
C19,
CLKMODE0
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DEVICE CONFIGURATIONS (CONTINUED) DEVCFG register description
device configuration register (DEVCFG) allows user control EMIF input clock source. more detailed information DEVCFG register control bits, Table Table Table Device Configuration Register (DEVCFG) [Address location: 0x019C0200 0x019C02FF]
Reserved RW-0 Reserved RW-0 Legend: Read/Write; value after reset write non-zero values these locations. EKSRC R/W-0 Reserved R/W-0
Table Device Configuration (DEVCFG) Register Selection Descriptions
31:5 NAME Reserved DESCRIPTION Reserved. write non-zero values these locations. EMIF input clock source bit. Determines which clock signal used EMIF input clock. SYSCLK3 (from clock generator) EMIF input clock source (default) ECLKIN external EMIF input clock source Reserved. write non-zero values these locations.
EKSRC
Reserved
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TERMINAL FUNCTIONS
terminal functions table identifies external signal names, associated (ball) numbers along with mechanical package designator, type O/Z, I/O/Z), whether internal pullup/pulldown resistors functional description. more detailed information device configuration, Device Configurations section this data sheet.
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Terminal Functions
SIGNAL NAME GDP/ TYPE IPD/ CLOCK/PLL CLKIN Clock Input CLKOUT2 multiplexed with GP[2] pin. Clock output half device speed (O/Z) [default] (SYSCLK2 internal signal from clock generator) this programmed GP[2] (I/O/Z). CLKOUT2 When CLKOUT2 enabled, CLK2EN EMIF global control register (GBLCTL) controls CLKOUT2 (All devices). CLK2EN CLKOUT2 disabled CLK2EN CLKOUT2 enabled clock [default] Clock output programmable OSCDIV1 register controller Clock generator input clock source select Reserved. use. CLKIN square wave [default] proper device operation, this must either left unconnected externally pulled with resistor. Analog power (3.3 JTAG EMULATION EMU5 EMU4 EMU3 I/O/Z I/O/Z I/O/Z JTAG test-port mode select JTAG test-port data JTAG test-port data JTAG test-port clock JTAG test-port reset. IEEE 1149.1 JTAG compatibility, IEEE 1149.1 JTAG Compatibility Statement section this data sheet. Emulation Reserved future use, leave unconnected. Emulation Reserved future use, leave unconnected. Emulation Reserved future use, leave unconnected. DESCRIPTION
CLKOUT3
CLKMODE0
PLLHV
EMU2 I/O/Z Emulation Reserved future use, leave unconnected. Input, Output, High impedance, Supply voltage, Ground, Analog signal (PLL Filter) Internal pulldown, Internal pullup. oppose supply rail these IPD/IPU signal pins, external pullup pulldown resistors greater than respectively.] ensure proper logic level during reset when these pins both routed 3-stated driven, recommended that external 10-k pullup/pulldown resistor included sustain IPU/IPD, respectively.
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Terminal Functions (Continued)
SIGNAL NAME GDP/ TYPE IPD/ DESCRIPTION
JTAG EMULATION (CONTINUED) Emulation [1:0] pins. Select device functional mode operation EMU[1:0] Operation Boundary Scan/Functional Mode (see Note) Reserved Reserved Emulation/Functional Mode [default] (see IEEE 1149.1 JTAG Compatibility Statement section this data sheet) placed Functional mode when EMU[1:0] pins configured either Boundary Scan Emulation. Note: When EMU[1:0] pins configured Boundary Scan mode, internal pulldown (IPD) TRST signal must opposed order operate Functional mode. Boundary Scan mode drive EMU[1:0] RESET pins low. BOOTMODE Note: configuration must routed from device, internal pullup/pulldown (IPU/IPD) resistor should relied upon; recommends external pullup/pulldown resistor. Bootmode[1:0] Emulation boot width 8-bit, asynchronous external boot with default timings (default mode) width 16-bit, asynchronous external boot with default timings Reserved, LITTLE/BIG ENDIAN FORMAT Note: configuration must routed from device, internal pullup/pulldown (IPU/IPD) resistor should relied upon; recommends external pullup/pulldown resistor. Device Endian mode System operates Endian mode. EMIFBE must pulled low. System operates Little Endian mode. EMIF Endian mode correctness (EMIFBE) When Endian mode selected (LENDIAN proper device operation EMIFBE must externally pulled low. more detailed information Endian mode correctness, EMIF Endian Mode Correctness portion this data sheet. Input, Output, High impedance, Supply voltage, Ground, Analog signal (PLL Filter) Internal pulldown, Internal pullup. oppose supply rail these IPD/IPU signal pins, external pullup pulldown resistors greater than respectively.]
EMU1 EMU0
I/O/Z
BOOTMODE1 BOOTMODE0
LENDIAN
EMIFBE
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Terminal Functions (Continued)
SIGNAL NAME GDP/ TYPE IPD/ RESETS INTERRUPTS RESET Device reset. When using Boundary Scan mode device, drive EMU[1:0] RESET pins low. This does have IPU. Nonmaskable interrupt Edge-driven (rising edge) noise trigger interrupt; therefore, used, recommended that grounded versus relying IPD. General-purpose input/output pins (I/O/Z) which also function external interrupts (default) Edge-driven Polarity independently selected External Interrupt Polarity Register bits (EXTPOL.[3:0]), addition GPIO registers. DESCRIPTION
EXT_INT7 EXT_INT6 EXT_INT5 EXT_INT4
EMIF CONTROL SIGNALS COMMON TYPES MEMORY# Memory space enables Enabled bits through word address Only asserted during external data access Byte-enable control Decoded from lowest bits internal address Byte-write enables most types memory directly connected SDRAM read write mask signal (SDQM) EMIF ARBITRATION# Hold-request-acknowledge host Hold request from host
HOLDA HOLD BUSREQ ECLKIN
request output EMIF ASYNCHRONOUS/SYNCHRONOUS DRAM/SYNCHRONOUS BURST SRAM MEMORY CONTROL# EMIF input clock EMIF output clock depends EKSRC (DEVCFG.[4]) EKEN (GBLCTL.[5]) EKSRC ECLKOUT based internal SYSCLK3 signal from clock generator (default). EKSRC ECLKOUT based external EMIF input clock source (ECLKIN) EKEN EKEN ECLKOUT held ECLKOUT enabled clock (default)
ECLKOUT
Input, Output, High impedance, Supply voltage, Ground, Analog signal (PLL Filter) Internal pulldown, Internal pullup. oppose supply rail these IPD/IPU signal pins, external pullup pulldown resistors greater than respectively.] maintain signal integrity EMIF signals, serial termination resistors should inserted into EMIF output signal lines.
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Terminal Functions (Continued)
SIGNAL NAME GDP/ TYPE IPD/ DESCRIPTION
EMIF ASYNCHRONOUS/SYNCHRONOUS DRAM/SYNCHRONOUS BURST SRAM MEMORY CONTROL (CONTINUED)# ARE/SDCAS/ SSADS AOE/SDRAS/ SSOE AWE/SDWE/ SSWE ARDY EA21 EA20 EA19 EA18 EA17 EA16 EA15 EA14 EA13 EA12 EA11 EA10 ED15 ED14 ED13 ED12 ED11 EMIF DATA# I/O/Z External data EMIF external address Note: EMIF address numbering device start with maintain signal name compatibility with other C671x devices (e.g., C6711, C6713) [see 16-bit EMIF addressing scheme TMS320C6000 External Memory Interface (EMIF) Reference Guide (literature number SPRU266)]. Asynchronous memory read enable/SDRAM column-address strobe/SBSRAM address strobe Asynchronous memory output enable/SDRAM row-address strobe/SBSRAM output enable Asynchronous memory write enable/SDRAM write enable/SBSRAM write enable Asynchronous memory ready input EMIF ADDRESS#
ED10 Input, Output, High impedance, Supply voltage, Ground, Analog signal (PLL Filter) Internal pulldown, Internal pullup. oppose supply rail these IPD/IPU signal pins, external pullup pulldown resistors greater than respectively.] maintain signal integrity EMIF signals, serial termination resistors should inserted into EMIF output signal lines.
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Terminal Functions (Continued)
SIGNAL NAME GDP/ TYPE IPD/ EMIF DATA (CONTINUED)# TOUT1 TINP1 TOUT0 TINP0 TIMER1 Timer general-purpose output Timer general-purpose input TIMER0 Timer general-purpose output Timer general-purpose input External clock source opposed internal) this device, this does have internal pulldown (IPD). proper device operation, CLKS1 should either driven externally times pulled with 10-k resistor valid logic level. Because common some 3-state their outputs times, 10-k pullup resistor desirable even when external device driving pin. Receive clock Transmit clock Receive data this device, this does have internal pullup (IPU). proper device operation, should either driven externally times pulled with 10-k resistor valid logic level. Because common some 3-state their outputs times, 10-k pullup resistor desirable even when external device driving pin. Transmit data Receive frame sync I/O/Z External data I/O/Z External data DESCRIPTION
MULTICHANNEL BUFFERED SERIAL PORT (McBSP1)
CLKS1
CLKR1 CLKX1
I/O/Z I/O/Z
FSR1
I/O/Z
FSX1 I/O/Z Transmit frame sync Input, Output, High impedance, Supply voltage, Ground, Analog signal (PLL Filter) Internal pulldown, Internal pullup. oppose supply rail these IPD/IPU signal pins, external pullup pulldown resistors greater than respectively.] maintain signal integrity EMIF signals, serial termination resistors should inserted into EMIF output signal lines.
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Terminal Functions (Continued)
SIGNAL NAME GDP/ TYPE IPD/ DESCRIPTION
MULTICHANNEL BUFFERED SERIAL PORT (McBSP0) CLKS0 CLKR0 CLKX0 FSR0 FSX0 I/O/Z I/O/Z I/O/Z I/O/Z External clock source opposed internal) Receive clock Transmit clock Receive data Transmit data Receive frame sync Transmit frame sync Clock output half device speed CLKOUT2/GP[2] I/O/Z this device, CLKOUT2 multiplexed with GP[2] pin. Clock output half device speed (O/Z) [default] (SYSCLK2 internal signal from clock generator) this programmed GP[2] (I/O/Z). External interrupts Edge-driven Polarity independently selected External Interrupt Polarity Register bits (EXTPOL.[3:0]) I/O/Z GP[5](EXT_INT5) GP[4](EXT_INT4) General-purpose input/output pins (I/O/Z) which also function external interrupts Edge-driven Polarity independently selected External Interrupt Polarity Register bits (EXTPOL.[3:0]), addition GPIO registers. RESERVED TEST Reserved (leave unconnected, connect power ground) proper device operation, must externally pulled down with 10-k resistor.
GENERAL-PURPOSE INPUT/OUTPUT (GPIO) MODULE
GP[7](EXT_INT7) GP[6](EXT_INT6)
Input, Output, High impedance, Supply voltage, Ground, Analog signal (PLL Filter) Internal pulldown, Internal pullup. oppose supply rail these IPD/IPU signal pins, external pullup pulldown resistors greater than respectively.]
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Terminal Functions (Continued)
SIGNAL NAME GDP/ TYPE IPD/ DESCRIPTION
Reserved (leave unconnected, connect power ground) Reserved. proper device operation, this must externally pulled with 10-k resistor. Reserved. proper device operation, this must externally pulled with 10-k resistor. Reserved (leave unconnected, connect power ground) Reserved (leave unconnected, connect power ground) Reserved. [For designs, recommended that this connected directly CVDD (core power). designs, this left unconnected. Reserved [For designs, recommended that this connected directly (ground). designs, this left unconnected. ADDITIONAL RESERVED TEST
Input, Output, High impedance, Supply voltage, Ground, Analog signal (PLL Filter) Reserved (leave unconnected, connect power ground)
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Terminal Functions (Continued)
SIGNAL NAME GDP/ TYPE IPD/ DESCRIPTION
ADDITIONAL RESERVED TEST Input, Output, High impedance, Supply voltage, Ground, Analog signal (PLL Filter) Reserved (leave unconnected, connect power ground)
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Terminal Functions (Continued)
SIGNAL NAME GDP/ TYPE DESCRIPTION
SUPPLY VOLTAGE PINS DVDD CVDD Note: This value compatible with existing 1.26-V designs. Input, Output, High impedance, Supply voltage, Ground, Analog signal (PLL Filter) 1.20-V supply voltage [See Note] (see power-supply decoupling portion this data sheet) 3.3-V supply voltage (see power-supply decoupling portion this data sheet)
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Terminal Functions (Continued)
SIGNAL NAME GDP/ TYPE DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED) CVDD GROUND PINS Input, Output, High impedance, Supply voltage, Ground, Analog signal (PLL Filter) Ground pins Note: This value compatible with existing 1.26-V designs. 1.20-V supply voltage [See Note] (see power-supply decoupling portion this data sheet)
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Terminal Functions (Continued)
SIGNAL NAME GDP/ Input, Output, High impedance, Supply voltage, Ground, Analog signal (PLL Filter) Shaded numbers denote center thermal balls packages. Ground pins|| center thermal balls (J9-J12, K9-K12, L9-L12, M9-M12) [shaded] tied ground both electrical grounds thermal relief (thermal dissipation). TYPE DESCRIPTION
GROUND PINS (CONTINUED)
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Terminal Functions (Continued)
SIGNAL NAME Input, Output, High impedance, Supply voltage, Ground, Analog signal (PLL Filter) Ground pins TYPE DESCRIPTION
GROUND PINS (CONTINUED)
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development support
offers extensive line development tools TMS320C6000 platform, including tools evaluate performance processors, generate code, develop algorithm implementations, fully integrate debug software hardware modules. following products support development C6000 DSP-based applications: Software Development Tools: Code Composer Studio Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP/BIOS), which provides basic run-time target software needed support application. Hardware Development Tools: Extended Development System (XDS) Emulator (supports C6000 multiprocessor system debug) (Evaluation Module) complete listing development-support tools TMS320C6000 platform, visit Texas Instruments site Worldwide http://www.ti.com uniform resource locator (URL). information pricing availability, contact nearest field sales office authorized distributor.
Code Composer Studio, DSP/BIOS, trademarks Texas Instruments.
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
device support
device development-support tool nomenclature designate stages product development cycle, assigns prefixes part numbers devices support tools. Each commercial family member three prefixes: TMX, TMP, TMS. (e.g., TMS320C6712DGDP150). Texas Instruments recommends three possible prefix designators support tools: TMDX TMDS. These prefixes represent evolutionary stages product development from engineering prototypes (TMX TMDX) through fully qualified production devices/tools (TMS TMDS). Device development evolutionary flow: Experimental device that necessarily representative final device's electrical specifications. Final silicon that conforms device's electrical specifications completed quality reliability verification. Fully qualified production device.
Support tool development evolutionary flow: TMDX Development-support product that completed Texas Instruments internal qualification testing. Fully qualified development-support product.
TMDS
devices TMDX development-support tools shipped with following disclaimer: "Developmental product intended internal evaluation purposes." devices TMDS development-support tools have been characterized fully, quality reliability device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (TMX TMP) have greater failure rate than standard production devices. Texas Instruments recommends that these devices used production system because their expected end-use failure rate still undefined. Only qualified production devices used. device nomenclature also includes suffix with device family name. This suffix indicates package type (for example, GDP), temperature range (for example, blank default commercial temperature range extended temperature range), device speed range megahertz (for example, -150 MHz). package, like package, 272-ball plastic only with Pb-free balls. device part numbers further ordering information TMS320C6712D package types, website (http://www.ti.com) contact your sales representative.
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
device development-support tool nomenclature (continued)
6712D
PREFIX
Experimental device Prototype device Qualified device MIL-PRF-38535, High (non-38535)
DEVICE SPEED RANGE
DEVICE FAMILY TMS320 family
TEMPERATURE RANGE (DEFAULT: 90°C) Blank 90°C, commercial temperature -40°C 105°C, extended temperature PACKAGE 272-pin plastic 272-pin plastic BGA, with Pb-free soldered balls
TECHNOLOGY CMOS DEVICE C6712D
Ball Grid Array Quad Flatpack mechanical package designator represents version with Pb-Free soldered balls. package devices supported same speed grades package devices (available upon request). actual device part numbers (P/Ns) ordering information, Mechanical Data section this document website (www.ti.com).
Figure TMS320C6000 Platform Device Nomenclature (Including TMS320C6712D Device)
MicroStar PowerPAD trademarks Texas Instruments.
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
documentation support Extensive documentation supports TMS320 family generations devices from product announcement through applications development. types documentation available include: data sheets, such this document, with design specifications; complete user's reference guides devices tools; technical briefs; development-support tools; on-line help; hardware software applications. following brief, descriptive list support documentation specific C6000 devices: TMS320C6000 Instruction Reference Guide (literature number SPRU189) describes C6000 core (CPU) architecture, instruction set, pipeline, associated interrupts. TMS320C6000 Peripherals Overview Reference Guide [hereafter referred C6000 Overview] (literature number SPRU190) provides overview briefly describes functionality peripherals available C6000 platform devices. This document also includes table listing peripherals available C6000 devices along with literature numbers hyperlinks associated peripheral documents. These C6712D peripherals, except PLL, similar peripherals TMS320C6712 TMS320C64x devices; therefore, TMS320C6712 (C6711 C67x) peripheral information, some cases, where indicated, TMS320C6712 (C6712 TMS320C67x C671x C67x) peripheral information, some cases, where indicated, C64x information TMS320C6000 Peripherals Overview Reference Guide (literature number SPRU190). TMS320C6000 Technical Brief (literature number SPRU197) gives introduction C62x/C67x devices, associated development tools, third-party support. TMS320C6000 Software-Programmable Phase-Locked Loop (PLL) Controller Reference Guide (literature number SPRU233) describes functionality peripheral available C6712C/12D device. Migrating from TMS320C6211(B)/6711(B) TMS320C6711C application report (literature number SPRA837) describes differences issues interest related migration from Texas Instruments TMS320C6211, TMS320C6211B, TMS320C6711, TMS320C6711B devices, packages, TMS320C6711C device, package. Migrating from TMS320C6712 TMS320C6712C application report (literature number SPRA852) describes differences issues interest related migration from Texas Instruments TMS320C6712 device, package, TMS320C6712C device, package. TMS320C6712, TMS320C6712C, TMS320C6712D Digital Signal Processors Silicon Errata (C6712 Silicon Revisions 1.0, 1.2, 1.3, C6712C Silicon Revision 1.1, C6712D Silicon Revision 2.0) [literature number SPRZ182C later] categorizes describes known exceptions functional specifications usage notes TMS320C6712, TMS320C6712C, TMS320C6712D devices. TMS320C6711D, C6712D, C6713B Power Consumption Summary application report (literature number SPRA889A later) discusses power consumption user applications with TMS320C6713B, TMS320C6712D, TMS320C6711D devices. tools support documentation electronically available within Code Composer Studio Integrated Development Environment (IDE). complete listing C6000 latest documentation, visit Texas Instruments site Worldwide http://www.ti.com uniform resource locator (URL). Worldwide application report Begin Development with TMS320C6712 (literature number SPRA693), which describes more detail compatibility similarities/differences between C6711 C6712 devices.
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
register description
control status register (CSR) contains Revision (bits 16-31) well status device power-down modes [PWRD field (bits 15-10)], program data cache control modes, endian (EN, global interrupt enable (GIE, previous (PGIE, Figure Table identify fields register. more detailed information fields register, TMS320C6000 Peripherals Overview Reference Guide (literature number SPRU190) TMS320C6000 Instruction Reference Guide (literature number SPRU189).
REVISION R-0x03
R-0x02
PWRD
R/W-0
R/C-0
R/W-0
R/W-0
PGIE R/W-0
R/W-0
Legend: Readable instruction, Readable/Writeable instruction; Read/write; value after reset, undefined value after
reset, Clearable instruction
Figure Control Status Register (CPU CSR)
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
register description (continued)
Table Register Field Description
31:24 23:16 NAME REVISION DESCRIPTION Read only. Identifies which used defines silicon revision CPU. REVISION (31:16) combined value 0x0203 Control power-down modes. values always read zero. 000000 001001 010001 011010 011100 Others power-down (default) PD1, wake-up enabled interrupt PD1, wake-up enabled enabled interrupt PD2, wake-up device reset PD3, wake-up device reset Reserved
15:10
PWRD
Saturate bit. when unit performs saturate. This cleared only instruction only functional unit. functional unit priority over clear instruction) they occur same cycle. saturate full cycle (one delay slot) after saturate occurs. This will modified conditional instruction whose condition false. Endian bit. This read-only. Depicts device endian mode. Endian mode. Little Endian mode [default]. Program Cache control mode. L1D, Level Program Cache 000/010 Cache Enabled Cache accessed updated reads. other values reserved. Data Cache control mode. L1D, Level Data Cache 000/010 Cache Enabled 2-Way Cache other values reserved Previous (global interrupt enable); saves Global Interrupt Enable (GIE) when interrupt taken. Allows proper nesting interrupts.
PGIE Previous value (default) Previous value Global interrupt enable bit. Enables disables interrupts except reset interrupt (nonmaskable interrupt).
Disables interrupts (except reset interrupt NMI) [default] Enables interrupts (except reset interrupt NMI)
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
cache configuration (CCFG) register description
device includes enhancement cache configuration (CCFG) register. (CCFG.31) allows programmer select priority accesses memory originating from transfer crossbar (TC) over accesses originating from memory system. important class accesses EDMA transfers, which move data from memory. While EDMA normally issue accessing memory high rates memory system, there pathological cases where certain behavior could block EDMA from accessing memory long enough cause missed deadline when transferring data peripheral such McASP McBSP. This avoided setting because EDMA will assume higher priority than memory system when accessing memory. more detailed information P-bit function silicon advisories concerning EDMA memory accesses blocked, TMS320C6712, TMS320C6712C, TMS320C6712D Digital Signal Processors Silicon Errata (literature number SPRZ182C later).
Reserved 0000
L2MODE R/W-000
R/W-0
Reserved
Legend: Readable; Readable/Writeable; value after reset; undefined value after reset This device includes bit.
Figure Cache Configuration Register (CCFG) Table CCFG Register Field Description
30:10 NAME Reserved DESCRIPTION requestor priority bit. requests higher priority than requests requests higher priority than requests Reserved. Read-only, writes have effect. Invalidate bit. Normal operation lines invalidated Invalidate bit. Normal operation lines invalidated Reserved. Read-only, writes have effect. operation mode bits (L2MODE). 000b 001b 010b 011b 111b others Cache disabled (All SRAM mode) [64K SRAM] 1-way Cache (16K Cache) [48K SRAM] 2-way Cache (32K Cache) [32K SRAM] 3-way Cache (48K Cache) [16K SRAM] 4-way Cache (64K Cache) SRAM] Reserved
Reserved
L2MODE
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
interrupt sources interrupt selector
C67x core supports prioritized interrupts, which listed Table highest priority interrupt INT_00 (dedicated RESET) while lowest priority INT_15. first four interrupts non-maskable fixed. remaining interrupts (4-15) maskable default interrupt source listed Table However, their interrupt source reprogrammed sources listed Table (Interrupt Selector). Table lists selector value corresponding each alternate interrupt sources. selector choice interrupts 4-15 made programming corresponding fields (listed Table MUXH (address 0x019C0000) MUXL (address 0x019C0004) registers. Table Interrupts
INTERRUPT NUMBER INT_00 INT_01 INT_02 INT_03 INT_04 INT_05 INT_06 INT_07 INT_08 INT_09 INT_10 INT_11 INT_12 INT_13 INT_14 INT_15 INTERRUPT SELECTOR CONTROL REGISTER MUXL[4:0] MUXL[9:5] MUXL[14:10] MUXL[20:16] MUXL[25:21] MUXL[30:26] MUXH[4:0] MUXH[9:5] MUXH[14:10] MUXH[20:16] MUXH[25:21] MUXH[30:26] DEFAULT SELECTOR VALUE (BINARY) 00100 00101 00110 00111 01000 01001 00011 01010 01011 00000 00001 00010 DEFAULT INTERRUPT EVENT RESET Reserved Reserved GPINT4 GPINT5 GPINT6 GPINT7 EDMAINT EMUDTDMA SDINT EMURTDXRX EMURTDXTX DSPINT TINT0 TINT1
Table Interrupt Selector
INTERRUPT SELECTOR VALUE (BINARY) 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 INTERRUPT EVENT TINT0 TINT1 SDINT GPINT4 GPINT5 GPINT6 GPINT7 EDMAINT EMUDTDMA EMURTDXRX EMURTDXTX XINT0 RINT0 XINT1 RINT1 GPINT0 MODULE
Timer Timer EMIF GPIO GPIO GPIO GPIO EDMA Emulation Emulation Emulation McBSP0 McBSP0 McBSP1 McBSP1 GPIO
Interrupt Events GPINT4, GPINT5, GPINT6, GPINT7 outputs from GPIO module (GP). They originate from device pins GP[4](EXT_INT4), GP[5](EXT_INT5), GP[6](EXT_INT6), GP[7](EXT_INT7). These pins used edge-sensitive EXT_INTx with polarity controlled External Interrupt Polarity Register (EXTPOL.[3:0]). corresponding pins must first enabled GPIO module setting corresponding enable bits Enable Register (GPEN.[7:4]), configuring them inputs Direction Register (GPDIR.[7:4]). These interrupts controlled through GPIO module addition simple EXTPOL.[3:0] bits. more information interrupt control GPIO module, TMS320C6000 General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU584).
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
EDMA module EDMA selector
C67x EDMA this device also supports EDMA channels. Four sixteen channels (channels 8-11) reserved EDMA chaining, leaving EDMA channels available service peripheral devices. this device, user, through EDMA selector registers, control EDMA channels servicing peripheral devices. EDMA selector registers located addresses 0x01A0FF00 (ESEL0), 0x01A0FF04 (ESEL1), 0x01A0FF0C (ESEL3). These EDMA selector registers control mapping EDMA events EDMA channels. Each EDMA event assigned EDMA selector code (see Table 22). loading each EVTSELx register field with EDMA selector code, users desired EDMA event specified EDMA channel. Table lists default EDMA selector value each EDMA channel. Table Table EDMA Event Selector registers their associated descriptions.
Table EDMA Channels
EDMA CHANNEL EDMA SELECTOR CONTROL REGISTER ESEL0[5:0] ESEL0[13:8] ESEL0[21:16] ESEL0[29:24] ESEL1[5:0] ESEL1[13:8] ESEL1[21:16] ESEL1[29:24] DEFAULT SELECTOR VALUE (BINARY) 000000 000001 000010 000011 000100 000101 000110 000111 DEFAULT EDMA EVENT
Table EDMA Selector
EDMA SELECTOR CODE (BINARY) 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000-111111 XEVT0 REVT0 XEVT1 REVT1 Reserved GPINT2 Reserved McBSP0 McBSP0 McBSP1 McBSP1 TINT0 TINT1 SDINT GPINT4 GPINT5 GPINT6 GPINT7 Reserved Reserved GPIO EDMA EVENT Reserved TIMER0 TIMER1 EMIF GPIO GPIO GPIO GPIO MODULE
TINT0 TINT1 SDINT GPINT4 GPINT5 GPINT6 GPINT7 TCC8 (Chaining) TCC9 (Chaining) TCC10 (Chaining) TCC11 (Chaining) XEVT0 REVT0 XEVT1 REVT1
ESEL3[5:0] ESEL3[13:8] ESEL3[21:16] ESEL3[29:24]
001000 001001 001010 001011
GPINT[4-7] interrupt events sourced from GPIO module external interrupt capable GP[4-7] pins.
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
EDMA module EDMA selector (continued)
Table EDMA Event Selector Registers (ESEL0, ESEL1, ESEL3) ESEL0 Register (0x01A0 FF00)
Reserved
EVTSEL3 R/W-00 0011b
Reserved
EVTSEL2 R/W-00 0010b
EVTSEL0
Reserved
EVTSEL1 R/W-00 0001b
Reserved
R/W-00 0000b
Legend: Read only, Read/Write; value after reset
ESEL1 Register (0x01A0 FF04)
Reserved
EVTSEL7 R/W-00 0111b
Reserved Reserved
EVTSEL6 R/W-00 0110b
EVTSEL4
Reserved
EVTSEL5 R/W-00 0101b
R/W-00 0100b
Legend: Read only, Read/Write; value after reset
ESEL3 Register (0x01A0 FF0C)
Reserved
EVTSEL15 R/W-00 1111b
Reserved
EVTSEL14 R/W-00 1110b
Reserved
EVTSEL13 R/W-00 1101b
Reserved
EVTSEL12 R/W-00 1100b
Legend: Read only, Read/Write; value after reset
Table EDMA Event Selection Registers (ESEL0, ESEL1, ESEL3) Description
31:30 23:22 15:14 NAME DESCRIPTION
Reserved
Reserved. Read-only, writes have effect.
EDMA event selection bits channel Allows mapping EDMA events EDMA channels. 29:24 21:16 13:8 EVTSEL0 through EVTSEL15 bits correspond channels respectively. These EVTSELx fields user-selectable. configuring EVTSELx fields EDMA selector value desired EDMA sync event number (see Table 22), users EDMA event EDMA channel. example, EVTSEL15 programmed 0001b (the EDMA selector code TINT0), then channel triggered Timer0 TINT0 events.
EVTSELx
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
controller
TMS320C6712D includes flexible controller peripheral consisting prescaler (D0) four dividers (OSCDIV1, D3). controller able generate different clocks different parts system (i.e., core, Peripheral Data Bus, External Memory Interface, McASP, other peripherals). Figure illustrates PLL, controller, clock generator logic.
+3.3 filter
PLLHV
CLKMODE0 CLKIN PLLREF
DIVIDER
PLLOUT
PLLEN (PLL_CSR.[0])
DIVIDER
Reserved
D1EN (PLLDIV1.[15]) D0EN (PLLDIV0.[15])
OSCDIV1
DIVIDER
SYSCLK1 (DSP Core)
CLKOUT3 System
D2EN (PLLDIV2.[15])
DIVIDER
SYSCLK2 (Peripherals)
OD1EN (OSCDIV1.[15]) D3EN (PLLDIV3.[15]) ECLKIN (EMIF Clock Input)
SYSCLK3
EKSRC (DEVCFG.[4])
C6712D
EMIF ECLKOUT
Dividers must never disabled. Never write D1EN D2EN bits PLLDIV1 PLLDIV2 registers. NOTES: Place external components (C1, Filter) close C67x device possible. best performance, recommends that external components single side board without jumpers, switches, components other than ones shown. reduced jitter, maximize spacing between switching signals external components (C1, Filter). 3.3-V supply filter must from same 3.3-V power plane supplying voltage, DVDD. filter manufacturer part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U.
Figure Clock Generator Logic
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
controller (continued)
Reset Time amount wait time needed when resetting (writing PLLRST=1), order properly reset, before bringing reset (writing PLLRST Reset Time value, Table Lock Time amount time from when PLLRST with PLLEN (PLL reset, still bypassed) when PLLEN safely changed (switching from bypass path), Table Figure Under some operating conditions, maximum Lock Time vary from specified typical value. Lock Time values, Table Table Lock Reset Times
Lock Time Reset Time 187.5 UNIT
Table shows device's CLKOUT signals, they derived what register control bits, default settings. more details PLL, Clock Generator Logic diagram (Figure Table CLKOUT Signals, Default Settings, Control
CLOCK OUTPUT SIGNAL NAME CLKOUT2 CLKOUT3 DEFAULT SETTING (ENABLED DISABLED) (ENABLED) (ENABLED) CONTROL BIT(s) (Register) D2EN (PLLDIV2.[15]) CK2EN (EMIF GBLCTL.[3]) OD1EN (OSCDIV1.[15]) DESCRIPTION SYSCLK2 selected [default] Derived from CLKIN SYSCLK3 selected [default]. ECLKOUT (ENABLED); derived from SYSCLK3 EKSRC (DEVCFG.[4]) EKEN (EMIF GBLCTL.[5]) select ECLKIN source: EKSRC (DEVCFG.[4]) EKEN (EMIF GBLCTL.[5])
This input clock directly available internal high-frequency clock source that divided down programmable divider OSCDIV1 (/1, /32) output CLKOUT3 other system. Figure shows that input clock source divided down divider PLLDIV0 (/1, /32) then multiplied factor x25. Either input clock (PLLEN output (PLLEN then serves high-frequency reference clock rest system. core clock, peripheral clock, EMIF clock divided down from this high-frequency clock (each with unique divider) example, with 40-MHz input, output configured MHz, core operated (/2) while EMIF configured operate rate (/5). Note that there specific minimum maximum reference clock (PLLREF) output clock (PLLOUT) block labeled Figure well core, peripheral bus, EMIF. clock generator must configured exceed these constraints (certain combinations external clock input, internal dividers, multiply ratios might supported). Table clocks input output frequency ranges.
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
controller (continued)
Table Clock Frequency Ranges
150and CLOCK SIGNAL PLLREF (PLLEN PLLOUT SYSCLK1 SYSCLK3 (EKSRC Device Speed (DSP Core) UNIT
SYSCLK2 rate must exactly half SYSCLK1. Also electrical specification (timing requirements switching characteristics parameters) Input Output Clocks section this data sheet.
EMIF itself clocked external reference clock ECLKIN generated on-chip SYSCLK3. SYSCLK3 derived from divider PLLOUT (see Figure Clock Generator Logic). EMIF clock selection programmable EKSRC DEVCFG register. settings multiplier each dividers clock generation block reconfigured software time. either input changes CLKMODE0, CLKIN, multiplier changed, then software must enter bypass first stay bypass until enough time lock (see electrical specifications). programming procedure, TMS320C6000 Software-Programmable Phase-Locked Loop (PLL) Controller Reference Guide (literature number SPRU233). SYSCLK2 internal clock source peripheral control. SYSCLK2 (Divider must programmed half SYSCLK1 rate. example, configured divide-by-2 mode (/2), then must programmed divide-by-4 mode (/4). SYSCLK2 also tied directly CLKOUT2 (see Figure During programming transition Divider Divider (resulting SYSCLK1 SYSCLK2 output clocks, Figure order programming PLLDIV1 PLLDIV2 registers must observed ensure that SYSCLK2 always runs half SYSCLK1 rate slower. example, divider ratios changed from (respectively) (respectively) then, PLLDIV2 register must programmed before PLLDIV1 register. transition ratios become /10; then /10. divider ratios changed from then, PLLDIV1 register must programmed before PLLDIV2 register. transition ratios, this case, become then final SYSCLK2 rate must exactly half SYSCLK1 rate. Note that Divider Divider must always enabled (i.e., D1EN D2EN bits PLLDIV1 PLLDIV2 registers). detailed information clock generator (PLL Controller registers) their associated software descriptions, Table through Table
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
controller (continued)
PLLCSR Register (0x01B7 C100)
Reserved STABLE Reserved PLLRST RW-1 Reserved R/W-0 PLLPWRDN R/W-0b PLLEN RW-0
Reserved
Legend: Read only, Read/Write; value after reset
Table Control/Status Register (PLLCSR)
31:7 NAME Reserved STABLE Reserved PLLRST Reserved PLLPWRDN DESCRIPTION Reserved. Read-only, writes have effect. Clock Input Stable. This indicates clock input stabilized. Clock input stable. Clock counter finished counting (default). Clock input stable. Reserved. Read-only, writes have effect. Asserts RESET Reset Released. Reset Asserted (default). Reserved. user must write this bit. Select Power Down Operational (default). Placed Power-Down State. Mode Enable Bypass Mode (default). disabled. Divider bypassed. SYSCLK1/SYSCLK2/SYSCLK3 divided down directly from input reference clock. Enabled. Divider bypassed. SYSCLK1/SYSCLK2/SYSCLK3 divided down from output.
PLLEN
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
controller (continued)
PLLM Register (0x01B7 C110)
Reserved Reserved Legend: Read only, Read/Write; value after reset PLLM R/W-0 0111
Table Multiplier Control Register (PLLM)
31:5 NAME Reserved multiply mode [default 0111)]. 00000 Reserved 10000 00001 Reserved 10001 00010 Reserved 10010 00011 Reserved 10011 00100 10100 00101 10101 00110 10110 00111 10111 01000 11000 01001 11001 01010 11010 01011 11011 01100 11100 01101 11101 01110 11110 01111 11111 DESCRIPTION Reserved. Read-only, writes have effect. Reserved Reserved Reserved Reserved Reserved Reserved
PLLM
PLLM select values 00000 through 00011 11010 through 11111 supported.
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
controller (continued)
PLLDIV0, PLLDIV1, PLLDIV2, PLLDIV3 Registers (0x01B7 C114, 0x01B7 C118, 0x01B7 C11C, 0x01B7 C120, respectively)
Reserved Reserved PLLDIVx R/W-x xxxx
DxEN
R/W-1
Legend: Read only, Read/Write; value after reset Default values PLLDIV0, PLLDIV1, PLLDIV2, PLLDIV3 bits 0000), 0000), 0001), 0001), respectively.
CAUTION: should never disabled. should only disabled ECLKIN used.
Table Wrapper Divider Registers (Prescaler Divider Post-Scaler Dividers
31:16 NAME Reserved DESCRIPTION Reserved. Read-only, writes have effect. Divider Enable (where denotes through Divider Disabled. clock output. Divider Enabled (default). These divider-enable bits device-specific must enable. 14:5 Reserved Reserved. Read-only, writes have effect. Divider Ratio [Default values PLLDIV0, PLLDIV1, PLLDIV2, PLLDIV3 bits respectively]. 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
DxEN
PLLDIVx
Note that SYSCLK2 must half rate SYSCLK1. Therefore, divider ratio must times slower than example, then must
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
controller (continued)
OSCDIV1 Register (0x01B7 C124)
Reserved Reserved OSCDIV1 R/W-0 0111
OD1EN
R/W-1
Legend: Read only, Read/Write; value after reset
OSCDIV1 register controls oscillator divider CLKOUT3. CLKOUT3 signal does through path. Table Oscillator Divider Register (OSCDIV1)
31:16 14:5 NAME Reserved OD1EN Reserved DESCRIPTION Reserved. Read-only, writes have effect. Oscillator Divider Enable. Oscillator Divider Disabled. Oscillator Divider Enabled (default). Reserved. Read-only, writes have effect. Oscillator Divider Ratio [default 0111)]. 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
OSCDIV1
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
general-purpose input/output (GPIO)
GP[7:4, software-configurable GPIO pins, GPxEN bits Enable (GPEN) Register GPxDIR bits Direction (GPDIR) Register must properly configured. GPxEN GPxDIR GPxDIR GP[x] enabled GP[x] input GP[x] output
where represents through GPIO pins Figure shows GPIO enable bits GPEN register device. pins general-purpose input/output functions, corresponding GPxEN must (enabled). Default values device-specific, refer Figure default configuration.
Reserved R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0
Reserved R/W-0
Legend: Readable/Writeable; value after reset, undefined value after reset
Figure GPIO Enable Register (GPEN) [Hex Address: 01B0 0000] Figure shows GPIO direction bits GPDIR register. This register determines given GPIO input output providing corresponding GPxEN enabled (set "1") GPEN register. default, GPIO pins configured input pins.
Reserved R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Reserved R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Legend: Readable/Writeable; value after reset, undefined value after reset
Figure GPIO Direction Register (GPDIR) [Hex Address: 01B0 0004] more detailed information general-purpose inputs/outputs (GPIOs), TMS320C6000 General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU584).
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
power-down mode logic
Figure shows power-down mode logic.
CLKOUT2
Internal Clock Tree Clock Distribution Dividers
Clock
PowerDown Logic
PWRD Internal Peripherals
TMS320C6712D CLKIN RESET
External input clocks, with exception CLKOUT3 CLKIN, gated power-down mode logic.
Figure Power-Down Mode Logic triggering, wake-up, effects power-down modes their wake-up methods programmed setting PWRD field (bits 15-10) control status register (CSR). PWRD field shown Figure described Table When writing CSR, bits PWRD field should same time. Logic should used when "writing" reserved (bit PWRD field. discussed detail TMS320C6000 Instruction Reference Guide (literature number SPRU189).
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
Reserved R/W-0
Enable Non-Enabled Interrupt Wake R/W-0
Enabled Interrupt Wake R/W-0
R/W-0
R/W-0
R/W-0
Legend: R/W-x Read/write reset value NOTE: shadowed bits part power-down logic discussion therefore covered here. information these other fields register, TMS320C6000 Instruction Reference Guide (literature number SPRU189).
Figure PWRD Field Register delay nine clock cycles occur after instruction that sets PWRD bits before mode takes effect. best practice, NOPs should padded after PWRD bits account this delay. mode terminated non-enabled interrupt, program execution returns instruction where took effect. mode terminated enabled interrupt, interrupt service routine will executed first, then program execution returns instruction where took effect. case with enabled, interrupt, NMIE interrupt enable register (IER) must also order interrupt service routine execute; otherwise, execution returns instruction where took effect upon mode termination enabled interrupt. modes only aborted device reset. Table summarizes power-down modes.
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
Table Characteristics Power-Down Modes
PRWD FIELD (BITS 15-10) 000000 001001 010001 POWER-DOWN MODE power-down WAKE-UP METHOD Wake enabled interrupt Wake enabled non-enabled interrupt EFFECT CHIP'S OPERATION halted (except interrupt logic) Power-down mode blocks internal clock inputs boundary CPU, preventing most CPU's logic from switching. During PD1, EDMA transactions proceed between peripherals internal memory. Output clock from halted, stopping internal clock structure from switching resulting entire chip being halted. register internal contents preserved. functional "freeze" last state when clock turned off. Input clock stops generating clocks. register internal contents preserved. functional "freeze" last state when clock turned off. Following reset, needs time re-lock, just does following power-up. Wake-up from takes longer than wake-up from because needs re-locked, just does following power-up.
011010
Wake device reset
011100
Wake device reset
others Reserved When entering PD3, functional remains previous state. However, peripherals which asynchronous nature peripherals with external clock source, output signals transition response stimulus inputs. Under these conditions, peripherals will operate according specifications.
device includes programmable which allows software control bypass PLLEN PLLCSR register. With this enhanced functionality comes some additional considerations when entering power-down modes. power-down modes (PD2 PD3) function disabling stop clocks device. However, bypassed (PLLEN device will still receive clocks from external clock input (CLKIN). Therefore, bypassing makes power-down modes ineffective. Make sure that enabled writing PLLEN (PLLCSR.0) before writing either (CSR.11) (CSR.10) enter power-down mode.
power-supply sequencing
DSPs require specific power sequencing between core supply supply. However, systems should designed ensure that neither supply powered extended periods time second) other supply below proper operating voltage. system-level design considerations System-level design considerations, such contention, require supply sequencing implemented. core supply should powered prior (and powered down after), buffers. This ensure that buffers receive valid inputs from core before output buffers powered thus, preventing contention with other chips board. power-supply design considerations dual-power supply with simultaneous sequencing used eliminate delay between core power Schottky diode also used core rail rail (see Figure 13).
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
Supply DVDD Schottky Diode Core Supply C6000 CVDD
Figure Schottky Diode Diagram Core supply voltage regulators should located close array) minimize inductance resistance power delivery path. Additionally, when designing high-performance applications utilizing C6000 platform DSPs, board should include separate power planes core, I/O, ground, bypassed with high-quality low-ESL/ESR capacitors.
power-supply decoupling
order properly decouple supply planes from system noise, place many capacitors (caps) possible close DSP. Assuming 0603 caps, user should able total caps core supply supply. These caps need close more than 1.25 maximum distance) effective. Physically smaller caps better, such 0402, size needs evaluated from yield/manufacturing point-of-view. Parasitic inductance limits effectiveness decoupling capacitors, therefore physically smaller capacitors should used while maintaining largest available capacitance value. with selection component, verification capacitor availability over product's production lifetime needs considered.
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
IEEE 1149.1 JTAG compatibility statement
requires that both TRST RESET resets asserted upon power properly initialized. While RESET initializes core, TRST initializes DSP's emulation logic. Both resets required proper operation. Note: TRST synchronous must clocked TCLK; otherwise, BSCAN respond expected after TRST asserted. While both TRST RESET need asserted upon power only RESET needs released boot properly. TRST asserted indefinitely normal operation, keeping JTAG port interface DSP's emulation logic reset state. TRST only needs released when necessary JTAG controller debug exercise DSP's boundary scan functionality. TMS320C6712D includes internal pulldown (IPD) TRST ensure that TRST will always asserted upon power DSP's internal emulation logic will always properly initialized when this routed out. JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers drive TRST high expect external pullup resistor TRST. When using this type JTAG controller, assert TRST initialize after powerup externally drive TRST high before attempting emulation boundary scan operations. Following release RESET, low-to-high transition TRST must "seen" latch state EMU1 EMU0. EMU[1:0] pins configure device either Boundary Scan mode Emulation mode. more detailed information, terminal functions section this data sheet. Note: DESIGN-WARNING section BSDL file contains information constraints regarding proper device operation while Boundary Scan Mode. more detailed information JTAG emulation, TMS320C6000 Designing JTAG Emulation Reference Guide (literature number SPRU641).
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
EMIF device speed
maximum EMIF speed device MHz. recommends utilizing buffer information specification (IBIS) analyze timings determine maximum EMIF speed achievable given board layout. properly IBIS models attain accurate timing analysis given system, Using IBIS Models Timing Analysis application report (literature number SPRA839). ease design evaluation, Table contains IBIS simulation results showing maximum EMIF-SDRAM interface speeds given example boards (TYPE) SDRAM speed grades. Timing analysis should performed verify that timings specified board layout. Other configurations also possible, again, timing analysis must done verify proper timings. maintain signal integrity, serial termination resistors should inserted into EMIF output signal lines (see Terminal Functions table EMIF output signals). Table Example Boards Maximum EMIF Speed
BOARD CONFIGURATION TYPE EMIF INTERFACE COMPONENTS BOARD TRACE SDRAM SPEED GRADE 32-bit SDRAM (-7) 1-Load Short Traces bank 32-Bit SDRAM 3-inch traces with proper termination resistors; Trace impedance 32-bit SDRAM (-6) 32-bit SDRAM (-55) 32-bit SDRAM (-5) 16-bit SDRAM (-8E) 2-Loads Short Traces bank 16-Bit SDRAMs inches from EMIF each load, with proper termination resistors; Trace impedance 16-bit SDRAM (-75) 16-bit SDRAM (-7E) 16-bit SDRAM (-6A) 16-bit SDRAM (-6) 16-bit SDRAM (-8E) bank 32-Bit SDRAMs bank buffer inches from EMIF each load, with proper termination resistors; Trace impedance 16-bit SDRAM (-75) 16-bit SDRAM (-7E) 16-bit SDRAM (-6A) 16-bit SDRAM (-6) 32-bit SDRAM (-7) 3-Loads Long Traces bank 32-Bit SDRAM bank 32-Bit SBSRAM bank buffer 32-bit SDRAM (-6) inches from EMIF; Trace impedance 32-bit SDRAM (-55) 32-bit SDRAM (-5) MAXIMUM ACHIEVABLE EMIF-SDRAM INTERFACE SPEED short traces, SDRAM data output hold time these SDRAM speed grades cannot meet EMIF input hold time requirement (see NOTE short traces, EMIF cannot meet SDRAM input hold requirement (see NOTE short traces, EMIF cannot meet SDRAM input hold requirement (see NOTE SDRAM data output hold time cannot meet EMIF input hold requirement (see NOTE
3-Loads Short Traces
NOTE Results based IBIS simulations given example boards (TYPE). Timing analysis should performed determine timing requirements particular system.
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
EMIF endian mode correctness
device Endian mode (LENDIAN) selects endian mode operation (little endian endian) device. Little endian default setting. When Endian mode selected (LENDIAN EMIF Endian mode correctness (EMIFBE) must pulled low. Figure shows mapping 16-bit 8-bit data device with EMIF endianness correction.
EMIF DATA LINES (PINS) WHERE DATA PRESENT ED[15:8] (BE1) 16-Bit Device Endianness Mode 8-Bit Device Endianness Mode ED[7:0] (BE0)
Figure 16/8-Bit EMIF Endian Mode Correctness Mapping] This feature does affect systems operating Little Endian mode, providing default value used.
bootmode
C67x device resets using active-low signal RESET internal reset signal. While RESET low, internal reset also asserted device held reset initialized prescribed reset state. Refer reset timing reset timing characteristics states device pins during reset. release internal reset signal (see Reset Phase discussion Reset Timing section this data sheet) starts processor running with prescribed device configuration boot mode. C6712D types boot mode:
Emulation boot
Emulation boot mode, necessary load valid code into internal memory. emulation driver will release from "stalled" state, which point will vector address Prior beginning execution, emulator sets breakpoint address This prevents execution invalid code halting prior executing first instruction. Emulation boot good tool debug phase development.
EMIF boot (using default timings)
Upon release internal reset, 1K-Byte code located beginning copied address EDMA using default timings, while internally "stalled". data should stored endian format that system using. boot process also lets choose width ROM. this case, EMIF automatically assembles consecutive 8-bit bytes 16-bit half-words form 32-bit instruction words copied. transfer automatically done EDMA single-frame block transfer from address After completion block transfer, released from "stalled" state starts running from address
reset
hardware reset (RESET) required place into known good state power-up. RESET signal asserted (pulled low) prior ramping core voltages after core voltages have reached their proper operating conditions. best practice, reset should held during power-up. Prior deasserting RESET (low-to-high transition), core voltages should their proper operating conditions CLKIN should also running correct frequency.
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
absolute maximum ratings over operating case temperature range (unless otherwise noted)
Supply voltage range, CVDD (see Note Supply voltage range, DVDD (see Note -0.3 Input voltage ranges: -0.3 DVDD Output voltage ranges: -0.3 DVDD Operating case temperature range, 90_C Storage temperature range, Tstg -65_C 150_C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTE voltage values with respect VSS.
recommended operating conditions
CVDD DVDD Supply voltage, Core Supply voltage, Supply ground signals except CLKS1, DR1, RESET High-level input voltage Low-level input voltage CLKS1, DR1, RESET signals except CLKS1, DR1, RESET CLKS1, DR1, RESET signals except ECLKOUT, CLKOUT2, CLKS1, ECLKOUT CLKOUT2 signals except ECLKOUT, CLKOUT2, CLKS1, ECLKOUT CLKOUT2 CLKS1 Maximum voltage during overshoot (See Figure Maximum voltage during undershoot (See Figure 3.13 0.3*DVDD -0.7# 1.32 3.47 UNIT
High-level output
Low-level output
Operating case temperature this device, core supply should powered prior (and powered down after), supply. Systems should designed ensure that neither supply powered extended period time other supply below proper operating voltage. These values compatible with existing 1.26V designs. Refers steady state) currents only, actual switching currents higher. more details, device-specific IBIS models. absolute maximum ratings should exceeded more than cycle period.
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
electrical characteristics over recommended ranges supply voltage operating case temperature (unless otherwise noted)
PARAMETER High-level output voltage Low-level output voltage signals except CLKS1 signals except CLKS1 CLKS1 signals except CLKS1 CLKS1 Off-state output current Core supply current supply current Input capacitance C6712D signals except CLKS1 CLKS1 CVDD 1.26 clock DVDD EMIF speed DVDD DVDD TEST CONDITIONS DVDD MIN, ±170 ±170 UNIT
DVDD MIN,
Input current
IDD2V IDD3V
Output capacitance C6712D test conditions shown MIN, MAX, NOM, appropriate value specified recommended operating conditions table. more details CPU, peripheral, activity, TMS320C62x/C67x Power Consumption Summary application report (literature number SPRA486). device, these currents were measured with average activity (50% high/50% power) 25°C case temperature 100-MHz EMIF. This model represents device performing high-DSP-activity operations time, remainder performing low-DSP-activity operations. high/low-DSP-activity models defined follows: High-DSP-Activity Model: CPU: instructions/cycle with LDDW instructions Data Memory: bits/cycle LDDW instructions; Program Memory: bits/cycle; L2/EMIF EDMA: writes, reads to/from SDRAM (50% bit-switching)] McBSP: channels rate Timers: timers maximum rate Low-DSP-Activity Model: CPU: instructions/cycle with instruction Data Memory: bits/cycle; Program Memory: bits cycles; L2/EMIF EDMA: None] McBSP: channels rate Timers: timers maximum rate actual current draw highly application-dependent. more details core activity, refer TMS320C6711D/12D/13B Power Consumption Summary application report (literature number SPRA889A).
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
PARAMETER MEASUREMENT INFORMATION
Tester Electronics
Data Sheet Timing Reference Point
Transmission Line (see note)
Output Under Test Device (see note)
1.85
NOTE: data sheet provides timing device pin. output timing analysis, tester electronics transmission line effects must taken into account. transmission line with delay longer used produce desired transmission line effect. transmission line intended load only. necessary subtract transmission line delay longer) from data sheet timings. Input requirements this data sheet tested with input slew rate Volts nanosecond V/ns) device pin.
Figure Test Load Circuit Timing Measurements
signal transition levels
input output timing parameters referenced both logic levels.
Vref
Figure Input Output Voltage Reference Levels Timing Measurements rise fall transition timing parameters referenced input clocks, output clocks.
Vref MIN)
Vref MAX)
Figure Rise Fall Transition Time Voltage Reference Levels
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PARAMETER MEASUREMENT INFORMATION (CONTINUED) transient rise/fall time specifications
Figure Figure show transient specifications Rise Fall Time. device-specific information these values, refer Recommended Operating Conditions section this Data Sheet.
(max)
(max) Minimum Risetime Waveform Valid Region Ground (min)
Figure Transient Specification Rise Time
peripheral cycle time. tc(max)
(max) (max) Ground
Figure Transient Specification Fall Time
peripheral cycle time.
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timing parameters board routing analysis
timing parameter values specified this data sheet include delays board routings. good board design practice, such delays must always taken into account. Timing values adjusted increasing/decreasing such delays. recommends utilizing available buffer information specification (IBIS) models analyze timing characteristics correctly. properly IBIS models attain accurate timing analysis given system, Using IBIS Models Timing Analysis application report (literature number SPRA839). needed, external logic hardware such buffers used compensate timing differences. inputs, timing most impacted round-trip propagation delay from external device from external device DSP. This round-trip delay tends negatively impact input setup time margin, also tends improve input hold time margins (see Table Figure 20). Figure represents general transfer between external device. figure also represents board route delays they perceived external device.
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
PARAMETER MEASUREMENT INFORMATION (CONTINUED)
Table Board-Level Timings Example (see Figure
DESCRIPTION Clock route delay Minimum hold time Minimum setup time External device hold time requirement External device setup time requirement Control signal route delay External device hold time External device access time hold time requirement setup time requirement Data route delay
ECLKOUT (Output from DSP) ECLKOUT (Input External Device) Control Signals (Output from DSP) Control Signals (Input External Device) Data Signals (Output from External Device) Data Signals (Input DSP) Control signals include data Writes. Data signals generated during Reads from external device.
Figure Board-Level Input/Output Timings
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
INPUT OUTPUT CLOCKS timing requirements (see Figure
-150 MODE (PLLEN tc(CLKIN) tw(CLKINH) tw(CLKINL) tt(CLKIN) Cycle time, CLKIN Pulse duration, CLKIN high Pulse duration, CLKIN Transition time, CLKIN 0.4C 0.4C 83.3 BYPASS MODE (PLLEN 0.4C 0.4C UNIT
reference points rise fall transitions measured MIN. CLKIN cycle time example, when CLKIN frequency MHz, Controller section this data sheet.
CLKIN
Figure CLKIN Timings
switching characteristics over recommended operating conditions (see Figure
-150 tc(CKO2) tw(CKO2H) tw(CKO2L) tt(CKO2) PARAMETER Cycle time, CLKOUT2 Pulse duration, CLKOUT2 high Pulse duration, CLKOUT2 (C2/2) (C2/2) (C2/2) (C2/2) UNIT
Transition time, CLKOUT2 reference points rise fall transitions measured MIN. CLKOUT2 period CLKOUT2 period determined controller output SYSCLK2 period, which must period divide-by-2. CLKOUT2
Figure CLKOUT2 Timings
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
INPUT OUTPUT CLOCKS (CONTINUED) switching characteristics over recommended operating conditions CLKOUT3 (see Figure
-150 tc(CKO3) tw(CKO3H) tw(CKO3L) tt(CKO3) PARAMETER Cycle time, CLKOUT3 Pulse duration, CLKOUT3 high Pulse duration, CLKOUT3 Transition time, CLKOUT3 (C3/2) (C3/2) (C3/2) (C3/2) UNIT
td(CLKINH-CKO3V) Delay time, CLKIN high CLKOUT3 valid reference points rise fall transitions measured MIN. CLKOUT3 period CLKOUT3 period divide-down clock, configurable OSCDIV1 register. more details, controller. CLKIN CLKOUT3 NOTE this example, CLKOUT3 frequency CLKIN divide-by-2.
Figure CLKOUT3 Timings
timing requirements (see Figure
-150 tc(EKI) tw(EKIH) tw(EKIL) tt(EKI) Cycle time, ECLKIN Pulse duration, ECLKIN high Pulse duration, ECLKIN Transition time, ECLKIN UNIT
reference points rise fall transitions measured MIN. ECLKIN
Figure ECLKIN Timings
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
INPUT OUTPUT CLOCKS (CONTINUED) switching characteristics over recommended operating conditions (see Figure
-150 tc(EKO) tw(EKOH) tw(EKOL) tt(EKO) td(EKIH-EKOH) td(EKIL-EKOL) PARAMETER Cycle time, ECLKOUT Pulse duration, ECLKOUT high Pulse duration, ECLKOUT Transition time, ECLKOUT Delay time, ECLKIN high ECLKOUT high UNIT
Delay time, ECLKIN ECLKOUT reference points rise fall transitions measured MIN. ECLKIN period high period ECLKIN period ECLKIN
ECLKIN ECLKOUT
Figure ECLKOUT Timings
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
ASYNCHRONOUS MEMORY TIMING timing requirements asynchronous memory cycles (see Figure 26-Figure
-150 tsu(EDV-AREH) th(AREH-EDV) tsu(ARDY-EKOH) th(EKOH-ARDY) Setup time, valid before high Hold time, valid after high Setup time, ARDY valid before ECLKOUT high Hold time, ARDY valid after ECLKOUT high UNIT
ensure data setup time, simply program strobe width wide enough. ARDY internally synchronized. ARDY signal recognized cycle which setup hold time met. ARDY asynchronous input, pulse width ARDY signal should wide enough (e.g., pulse width ensure setup hold time met. Read setup, Read strobe, Read hold, Write setup, Write strobe, Write hold. These parameters programmed EMIF space control registers.
switching characteristics over recommended operating conditions asynchronous memory (see Figure 26-Figure
-150 tosu(SELV-AREL) toh(AREH-SELIV) td(EKOH-AREV) tosu(SELV-AWEL) toh(AWEH-SELIV) td(EKOH-AWEV) tosu(EDV-AWEL) PARAMETER Output setup time, select signals valid Output hold time, high select signals invalid Delay time, ECLKOUT high valid Output setup time, select signals valid Output hold time, high select signals invalid Delay time, ECLKOUT high valid Output setup time, valid RS*E RH*E WS*E WH*E (WS-1)*E UNIT
Read setup, Read strobe, Read hold, Write setup, Write strobe, Write hold. These parameters programmed EMIF space control registers. ECLKOUT period Select signals include: CE[3:0], BE[1:0], EA[21:2], AOE.
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup ECLKOUT CE[3:0] BE[1:0] EA[21:2] Address ED[15:0] AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE ARDY AOE/SDRAS/SSOE, ARE/SDCAS/SSADS, AWE/SDWE/SSWE operate (identified under select signals), ARE, AWE, respectively, during asynchronous memory accesses. Read Data Strobe Ready Hold
Figure Asynchronous Memory Read Timing
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup ECLKOUT BE[3:0] EA[21:2] ED[31:0] AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE ARDY AOE/SDRAS/SSOE, ARE/SDCAS/SSADS, AWE/SDWE/SSWE operate (identified under select signals), ARE, AWE, respectively, during asynchronous memory accesses. Write Data Address Strobe Ready Hold
Figure Asynchronous Memory Write Timing
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
SYNCHRONOUS-BURST MEMORY TIMING timing requirements synchronous-burst SRAM cycles (see Figure
-150 tsu(EDV-EKOH) th(EKOH-EDV) Setup time, read valid before ECLKOUT high Hold time, read valid after ECLKOUT high UNIT
SBSRAM interface takes advantage internal burst counter SBSRAM. Accesses default incrementing 4-word bursts, random bursts decrementing bursts done interrupting bursts progress. burst types sustain continuous data flow.
switching characteristics over recommended operating conditions synchronous-burst SRAM cycles (see Figure Figure
-150 td(EKOH-CEV) td(EKOH-BEV) td(EKOH-BEIV) td(EKOH-EAV) td(EKOH-EAIV) td(EKOH-ADSV) td(EKOH-OEV) td(EKOH-EDV) td(EKOH-EDIV) td(EKOH-WEV) PARAMETER Delay time, ECLKOUT high valid Delay time, ECLKOUT high valid Delay time, ECLKOUT high invalid Delay time, ECLKOUT high valid Delay time, ECLKOUT high invalid Delay time, ECLKOUT high ARE/SDCAS/SSADS valid Delay time, ECLKOUT high AOE/SDRAS/SSOE valid Delay time, ECLKOUT high valid Delay time, ECLKOUT high invalid Delay time, ECLKOUT high AWE/SDWE/SSWE valid UNIT
SBSRAM interface takes advantage internal burst counter SBSRAM. Accesses default incrementing 4-word bursts, random bursts decrementing bursts done interrupting bursts progress. burst types sustain continuous data flow. ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, AWE/SDWE/SSWE operate SSADS, SSOE, SSWE, respectively, during SBSRAM accesses.
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
ECLKOUT CE[3:0] BE[1:0] EA[21:2] ED[15:0] ARE/SDCAS/SSADS AOE/SDRAS/SSOE AWE/SDWE/SSWE ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, AWE/SDWE/SSWE operate SSADS, SSOE, SSWE, respectively, during SBSRAM accesses.
Figure SBSRAM Read Timing
ECLKOUT CE[3:0] EA[21:2] ARE/SDCAS/SSADS AOE/SDRAS/SSOE AWE/SDWE/SSWE
BE[1:0]
ED[15:0]
ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, AWE/SDWE/SSWE operate SSADS, SSOE, SSWE, respectively, during SBSRAM accesses.
Figure SBSRAM Write Timing
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
SYNCHRONOUS DRAM TIMING timing requirements synchronous DRAM cycles (see Figure
-150 tsu(EDV-EKOH) th(EKOH-EDV) Setup time, read valid before ECLKOUT high UNIT
Hold time, read valid after ECLKOUT high SDRAM interface takes advantage internal burst counter SDRAM. Accesses default incrementing 4-word bursts, random bursts decrementing bursts done interrupting bursts progress. burst types sustain continuous data flow.
switching characteristics over recommended operating conditions synchronous DRAM cycles (see Figure 30-Figure
-150 td(EKOH-CEV) td(EKOH-BEV) td(EKOH-BEIV) td(EKOH-EAV) td(EKOH-EAIV) td(EKOH-CASV) td(EKOH-EDV) td(EKOH-EDIV) td(EKOH-WEV) td(EKOH-RAS) PARAMETER Delay time, ECLKOUT high valid Delay time, ECLKOUT high valid Delay time, ECLKOUT high invalid Delay time, ECLKOUT high valid Delay time, ECLKOUT high invalid Delay time, ECLKOUT high ARE/SDCAS/SSADS valid Delay time, ECLKOUT high valid Delay time, ECLKOUT high invalid Delay time, ECLKOUT high AWE/SDWE/SSWE valid UNIT
Delay time, ECLKOUT high AOE/SDRAS/SSOE valid SDRAM interface takes advantage internal burst counter SDRAM. Accesses default incrementing 4-word bursts, random bursts decrementing bursts done interrupting bursts progress. burst types sustain continuous data flow. ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE operate SDCAS, SDWE, SDRAS, respectively, during SDRAM accesses.
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
SYNCHRONOUS DRAM TIMING (CONTINUED)
READ ECLKOUT CE[3:0] BE[1:0] Bank Column EA12 ED[15:0] AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE operate SDCAS, SDWE, SDRAS, respectively, during SDRAM accesses.
EA[21:13] EA[11:2]
Figure SDRAM Read Command (CAS Latency
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
SYNCHRONOUS DRAM TIMING (CONTINUED)
WRITE ECLKOUT CE[3:0] BE[1:0] EA[21:13] EA[11:2] EA12 ED[15:0] AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE operate SDCAS, SDWE, SDRAS, respectively, during SDRAM accesses. Column Bank
Figure SDRAM Write Command
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
SYNCHRONOUS DRAM TIMING (CONTINUED)
ACTV ECLKOUT CE[3:0] BE[1:0] Bank Activate Address Address
EA[21:13] EA[11:2]
EA12 ED[15:0]
AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE
ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE operate SDCAS, SDWE, SDRAS, respectively, during SDRAM accesses.
Figure SDRAM ACTV Command
DCAB ECLKOUT CE[3:0] BE[1:0] EA[21:13, 11:2] EA12 ED[15:0] AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE operate SDCAS, SDWE, SDRAS, respectively, during SDRAM accesses.
Figure SDRAM DCAB Command
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
SYNCHRONOUS DRAM TIMING (CONTINUED)
DEAC ECLKOUT CE[3:0] BE[1:0] EA[21:13] EA[11:2] EA12 ED[15:0] AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE operate SDCAS, SDWE, SDRAS, respectively, during SDRAM accesses. Bank
Figure SDRAM DEAC Command
REFR ECLKOUT CE[3:0] BE[1:0] EA[21:2] EA12 ED[15:0] AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE operate SDCAS, SDWE, SDRAS, respectively, during SDRAM accesses.
Figure SDRAM REFR Command
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
SYNCHRONOUS DRAM TIMING (CONTINUED)
ECLKOUT CE[3:0] BE[1:0] value
EA[21:2] ED[15:0]
AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE
ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE operate SDCAS, SDWE, SDRAS, respectively, during SDRAM accesses.
Figure SDRAM Command
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TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR
HOLD/HOLDA TIMING timing requirements HOLD/HOLDA cycles (see Figure
-150 th(HOLDAL-HOLDL) ECLKIN period Hold time, HOLD after HOLDA UNIT
switching characteristics over recommended operating conditions HOLD/HOLDA cycles (see Figure
-150 td(HOLDL-EMHZ) td(EMHZ-HOLDAL) td(HOLDH-EMLZ) td(EMLZ-HOLDAH) PARAMETER Delay time, HOLD EMIF high impedance Delay time, EMIF high impedance HOLDA Delay time, HOLD high EMIF impedance Delay time, EMIF impedance HOLDA high UNIT
ECLKIN period EMIF consists CE[3:0], BE[1:0], ED[15:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, AWE/SDWE/SSWE. pending EMIF transactions allowed complete before HOLDA asserted. transactions occurring, then minimum delay time achieved. Also, hold indefinitely delayed setting NOHOLD Owns External Requestor Owns HOLD HOLDA EMIF C6712D C6712D Owns
EMIF consists CE[3:0], BE[1:0], ED[15:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, AWE/SDWE/SSWE.
Figure HOLD/HOLDA Timing
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B
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