8192 Search Bins with Acquisition Accelerator Accuracy 2.5m (Stand-Alo

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8192 Search Bins with Acquisition Accelerator Accuracy 2.5m (Stand-Alo

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16-channel Correlator
8192 Search Bins with Acquisition Accelerator Accuracy 2.5m (Stand-Alone, off) Time First Fix: (Cold Start) Acquisition Sensitivity: -140 Tracking Sensitivity: -150 Utilizes ARM7TDMI® ARM® Thumb® Processor Core High-performance 32-bit RISC Architecture High-density 16-bit Instruction Embedded (In-circuit Emulation) Kbytes Internal Kbytes Internal with u-blox Firmware Fully programmable External Interface (EBI) Maximum External Address Space Mbytes Chip Selects Software Programmable 8/16-bit External Data Channel Peripheral Data Controller (PDC) 8-level Priority, Individually Maskable, Vectored Interrupt Controller External Interrupts User-programmable Lines USARTs Dedicated Peripheral Data Controller (PDC) Channels USART Master/Slave Interface Dedicated Peripheral Data Controller (PDC) Channels 8-bit 16-bit Programmable Data Length External Slave Chip Selects Programmable Watchdog Timer Power Management Controller (PMC) Peripherals Deactivated Individually Clock Manager (CLM) Geared Master Clock Reduce Power Consumption Sleep State with Disabled Master Clock Real Time Clock (RTC) 2.3V 3.6V 1.8V Supply Voltage Includes Power Supervisor Battery Backup Memory Package (TFBGA)
Baseband Processor ATR0620 Summary Preliminary
Electrostatic sensitive device. Observe precautions handling.
Rev. 4574FS-GPS-01/06
Note: This summary document. complete document available under NDA. more information, please contact your local Atmel sales office.
Description
baseband processor ATR0620 includes 16-channel Correlator based ARM7TDMI® processor core. This processor high performance 32-bit RISC architecture very power consumption. addition, large number internally banked registers result very fast exception handling, making device ideal real-time control applications. ATR0620 direct connection off-chip memory, including Flash, through External Interface (EBI). ATR0620 includes full firmware, licensed from u-blox which performs basic operation, including tracking, acquisition, navigation position data output. normal (Position/Velocity/Time) applications, there need off-chip Flash memory ROM. customer-specific applications, Software Development available. ATR0620 manufactured using Atmel high density CMOS technology. combining ARM7TDMI microcontroller core with on-chip SRAM, 16-channel Correlator wide range peripheral functions monolithic chip, ATR0620 provides highly-flexible cost-effective solution applications.
ATR0620 [Preliminary]
4574FS-GPS-01/06
ATR0620 [Preliminary]
Figure 1-1. Block Diagram
SRAM
XT_IN XT_OUT
Correlators
Power Management Controller
Accelerator
NSHDN NSLEEP
RF_ON
SIGLO SIGHI
Generator
Clock Manager (CLM)
CLK23
P20/TIMEPULSE P29/GPSMODE12 P27/GPSMODE11 P26/GPSMODE10 P25/GPSMODE9 P24/GPSMODE8 P23/GPSMODE7 P19/GPSMODE6 P17/GPSMODE5 P14/GPSMODE4 P13/GPSMODE3 P12/GPSMODE2 P9/GPSMODE1 P1/GPSMODE0 PIO2 PIO2 Controller
Special Function
USART2
P21/TXD2 P22/RXD2
PIO2
Advanced Interrupt Controller
USART1
P18/TXD1 P31/RXD1
P11/EXTINT2
Watchdog
EM_A19 EM_A1 EM_DA15 EM_DA0
Interface Off-Chip Memory (EBI)
PDC2
P16/NWD_OVF P30/BOOT_MODE0 P28/EM_A20 P10/EM_A0/NLB P8/STATUSLED P7/NUB/NWR1 P6/NOE/NRD P5/NWE/NWR0 P4/nCS0 P3/nCS1 P2/BOOT_MODE1
USART0
P15/TXD0 P0/RXD0
TOUT1
ARM7TDMI
Embedded
Power Supply Manager
DBG_EN TEST_MODE NTRST
JTAG
SRAM 128K
288K
VBAT18_O VBAT VBAT18_I LDOBAT_IN LDO_OUT LDO_IN LDO_EN
NRESET
Reset Controller
4574FS-GPS-01/06
Architectural Overview
Description
ATR0620 architecture consists main buses, Advanced System (ASB) Advanced Peripheral (APB). designed maximum performance. interfaces processor with on-chip 32-bit memories external memories devices means External Interface (EBI). designed accesses on-chip peripherals optimized power consumption. AMBAbridge provides interface between APB. on-chip Peripheral Data Controller (PDC2) transfers data between on-chip USARTs/SPI on-chip off-chip memories without processor intervention. Most importantly, PDC2 removes processor interrupt handling overhead significantly reduces number clock cycles required data transfer. transfer contiguous bytes without reprogramming starting address. result, performance microcontroller increased power consumption reduced. ATR0620 peripherals designed easily programmable with minimum number instructions. Each peripheral 16-Kbyte address space allocated upper Mbytes 4-Gbyte address space. (Except interrupt controller, which 4-Kbyte address space.) peripheral base address lowest address memory space. peripheral register composed control, mode, data, status, interrupt registers. maximize efficiency manipulation, frequently-written registers mapped into three memory locations. first address used individual register bits, second resets bits, third address reads value stored register. reset writing corresponding position appropriate address. Writing effect. Individual bits thus modified without having costly read-modifywrite complex bit-manipulation instructions. external signals on-chip peripherals under control Parallel (PIO2) Controller. PIO2 Controller programmed insert input filter each generate interrupt signal change. After reset, user must carefully program PIO2 Controller order define which peripheral signals connected with off-chip logic. ARM7TDMI® processor operates little-endian mode ATR0620 Baseband. processor's internal architecture Thumb instruction sets described ARM7TDMI datasheet. memory on-chip peripherals described detail ATR0620 full datasheet. electrical mechanical characteristics also documented ATR0620 full datasheet. standard In-circuit Emulator (ICE) debug interface supported JTAG/ICE port ATR0620. features firmware, refer software documentation available from u-blox Switzerland.
ATR0620 [Preliminary]
4574FS-GPS-01/06
ATR0620 [Preliminary]
Configuration
Pinout
Pinout TFBGA100 (Top View)
Figure 3-1.
Table 3-1.
Serial Number Notes:
ATR0620
ATR0620 Pinout
Bank TFBGA100 Name EM_DA0 EM_DA1 EM_DA2 EM_DA3 EM_DA4 EM_DA5 EM_DA6 EM_DA7 EM_DA8 EM_DA9 EM_DA10 EM_DA11 EM_DA12 EM_DA13 EM_DA14 EM_DA15 TXD0 RXD0 GPSMODE4 TXD1 RXD1 GPSMODE5 RXD1 SCK1 SCK1 RXD0 SCK0 SCK0 TXD1 NUB/NWR1 TXD0 Firmware Label Bank
switched Output High reset, internal pull-down resistor GND, internal pull-up resistor VDD18
4574FS-GPS-01/06
Table 3-1.
Serial Number Notes:
ATR0620 Pinout (Continued)
Bank TFBGA100 Name SIGHI SIGLO XT_IN XT_OUT NSLEEP CLK23 (PU(1)) (PD(1)) (PD(1)) (PD(1)) (PD(1)) NTRST (PD(1)) TEST_MODE (PD(1)) DBG_EN (PD(1)) RF_ON NRESET (PU(1)) NSHDN EM_A1 EM_A2 EM_A3 EM_A4 EM_A5 EM_A6 EM_A7 EM_A8 EM_A9 EM_A10 EM_A11 EM_A12 EM_A13 EM_A14 EM_A15 EM_A16 EM_A17 EM_A18 EM_A19 VDD18 VDD18 BOOT_MODE0 BOOT_MODE1 NWD_OVF TIMEPULSE Firmware Label Bank
switched Output High reset, internal pull-down resistor GND, internal pull-up resistor VDD18
ATR0620 [Preliminary]
4574FS-GPS-01/06
ATR0620 [Preliminary]
Table 3-1.
Serial Number Notes:
ATR0620 Pinout (Continued)
Bank TFBGA100 Name VDD18 VDD18 VBAT LDO_EN LDO_OUT (OH(1)) (OH(1)) LDO_IN (OH(1)) LDOBAT_IN VBAT18_O VBAT18_I TOUT1 TXD2 RXD2 TIMEPULSE GPSMODE11 EM_A20 GPSMODE12 GPSMODE2 GPSMODE3 EXTINT1 RXD2 SCK2 SCK2 NPCS1 NPCS2 NPCS3 NCS2 NCS3 EM_A20 TXD2 EM_A22 EM_A23 TIMEPULSE
Bank
Firmware Label
GPSMODE8 GPSMODE9 GPSMODE7 GPSMODE10 GPSMODE1
MOSI MISO EXTINT0
MOSI MISO NPCS0 EM_A0/NLB MCLK_OUT
NCS1 NCS0 NWE/NWR0 NOE/NRD NUB/NWR1 EM_A0/NLB EM_A21 STATUSLED NWD_OVF GPSMODE6 GPSMODE0 SIGHI2 SIGLO2 EXTINT2
NCS1 NCS0 NWE/NWR0 NOE/NRD NUB/NWR1 EM_A0/NLB AGCOUT0
AGCOUT0
MCLK_OUT EM_A21 NWD_OVF EM_A20
AGCOUT1
switched Output High reset, internal pull-down resistor GND, internal pull-up resistor VDD18
4574FS-GPS-01/06
Signal Description
ATR0620 Signal Description
Name EM_A0 EM_A23 NCS0 NCS1 NCS2 NCS3 NWR0 NWR1 BOOT_MODE0 BOOT_MODE1 TXD0 TXD2 Function Address Chip Select Chip Select Lower Byte Write Signal Upper Byte Write Signal Read Signal Write Enable Output Enable Upper Byte Select (16-bit SRAM) Lower Byte Select (16-bit SRAM) Boot Mode Input Boot Mode Input Transmit Data Output Receive Data Input External Synchronous Serial Clock Type Output Output Output Output Output Output Output Output Output Output Input Input Output Input Input Output Output Sleep Output Shutdown Output Oscillator Input Oscillator Output Clock Master Slave Master Slave Slave Select Slave Select Watchdog Timer Overflow Programmable Port Output Output Input Output Output Output Active Level Comment High/Low/ Edge Output High RESET state PIO-controlled after reset Output High RESET state Output High RESET state Output High RESET state Output High RESET state Output High RESET state Output High RESET state Output High RESET state PIO-controlled after reset, internal pull-up resistor PIO-controlled after reset, internal pull-down resistor PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset Interface ATR0600 PIO-controlled after reset Interface ATR0600 Interface ATR0600 Connect EN_LDO18 oscillator oscillator PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset valid after reset
Table 3-2.
Module
EM_DA0 EM_DA15 Data
USART
RXD0 RXD2 SCK0 SCK2
EXTINT0 EXTINT2 External Interrupt Request AGCOUT0 AGCOUT1 RF_ON NSLEEP NSHDN XT_IN XT_OUT MOSI Automatic Gain Control
MISO NSS/NPCS0 NPCS1 NPCS3
NWD_OVF
ATR0620 [Preliminary]
4574FS-GPS-01/06
ATR0620 [Preliminary]
Table 3-2.
Module
ATR0620 Signal Description (Continued)
Name GPSMODE0 GPSMODE12 SIGHI SIGLO SIGHI2 SIGLO2 TIMEPULSE NTRST DBG_EN Function Mode Digital Digital Digital Digital Synchronized Time Pulse Test Mode Select Test Data Test Data Test Clock Test Reset Input Debug Enable Clock Input Master Clock Output Reset Input Type Input Input Input Input Input Output Input Input Output Input Input Input Input Output Power Power Power Power Power Enable Test Mode Select Test Output Power Power Input Input Output Active Level Comment Internal pull-down resistor; Production test, connect Production test, connect Backup power 1.8V 2.3V 3.6V 1.95V 3.6V 1.8V backup voltage 2.3V 3.6V 1.8V core voltage, max. Internal pull-down resistor Internal pull-down resistor Internal pull-down resistor Interface ATR0600, Schmitt trigger input PIO-controlled after reset Open drain with internal pull-up resistor Core voltage PIO-controlled after reset Interface ATR0600 Interface ATR0600 PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset Internal pull-down resistor Internal pull-down resistor
JTAG/ICE
CLOCK
CLK23 MCLK_OUT
RESET
NRESET VDD18
POWER
VBAT18_I LDOBAT_IN
LDOBAT
VBAT VBAT18_O LDO_IN
LDO18
LDO_OUT LDO_EN
TEST
TEST_MODE TOUT1
4574FS-GPS-01/06
Setting GPSMODE0 GPSMODE12
start-up configuration ROM-based system without external non-volatile memory defined status GPSMODE pins after system reset. Alternatively, system configured through message commands passed through serial interface after start-up. Flash memory available, configuration stored Flash memory.
Table 3-3.
GPSMODE0 GPSMODE1 GPSMODE2 GPSMODE3 GPSMODE4 GPSMODE5 GPSMODE6 GPSMODE7 GPSMODE8 GPSMODE9 GPSMODE10 GPSMODE11 GPSMODE12
GPSMODE Functions
Function Enable configuration with GPSMODE pins FixNow (not used GPSMODE configuration) sensitivity settings Active antenna supervisor enable Serial configuration Navigation rate settings Active antenna supervisor input (not used GPSMODE configuration) Navigation rate settings Serial configuration
Table 3-4.
Enable Configuration with GPSMODE Pins
Ignore GPSMODE pins. default settings indicated below used. settings specified with GPSMODE[2
GPSMODE0 Description
Table 3-5.
GPSMODE1
Description This reserved FixNow functionality.
Table 3-6.
GPSMODE3
Sensitivity Settings
GPSMODE2 Description Auto mode Fast mode Normal mode (Default) High sensitivity
ATR0620 [Preliminary]
4574FS-GPS-01/06
ATR0620 [Preliminary]
Table 3-7.
Active Antenna Supervisor
Description Disable active antenna supervisor function (Default) Enable active antenna supervisor function
GPSMODE4
active antenna supervisor enabled, pins associated with USART0, that P0/RXD0 P15/TXD0 plus P25/MISO, initialized general purpose I/Os used follows:
Table 3-8.
P0/RXD0
Usage Active Antenna Supervisor
Usage AASCD_N AADET_N AAPON Meaning Active antenna short circuit detection input (Low Antenna short circuit detected) Active antenna detection input (Low Active antenna present) Active antenna power output (High Supply power active antenna)
P25/MISO/GPSMODE9 P15/TXD0
P15/TXD0 output which used switch antenna power supply. Input P0/RXD0 will indicate antenna short circuit, that zero voltage antenna, firmware. Input P25/MISO indicates that current sunk into antenna. case short circuit, both will active (low). Refer u-blox active antenna supervisor application note detailed functional description. antenna supervisor functionality software will configured follows this functionality enabled GPSMODE4 pin: Enable control signal Enable short circuit detection (power down short detected) Enable open circuit detection Table 3-9.
Active Antenna Supervisor AADET_N input
Description This reserved antenna supervisor function AADET_N active antenna supervisor disabled, RXD0 TXD0 will initialized serial port pins.
GPSMODE9
4574FS-GPS-01/06
Table 3-10.
Serial Configuration
USART0 (Output Protocol/ Baud Rate (kBaud)) -/19.2 -/9.6 -/4.8 -/Auto -/19.2 -/4.8 -/9.6 -/19.2 USART1 (Output Protocol/ Baud Rate (kBaud)) UBX/57.6 UBX/38.4 UBX/19.2 -/Auto NMEA/19.2 NMEA/4.8 NMEA/9.6 UBX/115.2 USART2 (Output Protocol/ Baud Rate (kBaud)) NMEA/19.2 NMEA/9.6 NMEA/4.8 -/Auto UBX/57.6 UBX/19.2 UBX/38.4 NMEA/19.2
GPSMODE
Messages High High Debug
Information Messages (UBX INF)
Information Messages (NMEA TXT)
User, Notice, Warning, Error User, Notice, Warning, Error User, Notice, Warning, Error User, Notice, Warning, Error User, Notice, Warning, Error User, Notice, Warning, Error None None User, Notice, Warning, Error User, Notice, Warning, Error User, Notice, Warning, Error User, Notice, Warning, Error User, Notice, Warning, Error User, Notice, Warning, Error User, Notice, Warning, Error
three USART ports accept input messages three supported protocols (NMEA, RTCM, UBX) configured baud rate. Input messages three protocols arbitrarily mixed. Auto Mode, output message sent default, input messages accepted supported baud rate. Response query input commands will given using same protocol baud rate used query command. Using respective configuration commands, periodic output messages enabled. Refer u-blox documentation further information this feature.
Table 3-11.
Serial Default Setting GPSMODE Configuration Deselected (GPSMODE0
USART1 NMEA 57.6 UBX, NMEA, RTCM NMEA GGA, RMC, GSA, User, Notice, Warning, Error USART2 57.6 UBX, NMEA, RTCM NAV: SOL, SVINFO User, Notice, Warning, Error
USART0 Serial Configuration RTCM Baud Rate (kBaud) Input Protocol Output Protocol Messages 57.6 UBX, NMEA, RTCM
Information Messages (UBX NMEA TXT)
three USART ports accept input messages three supported protocols (NMEA, RTCM UBX) configured baud rate. Input messages three protocols arbitrarily mixed. Response query input message will always same protocol query input message.
ATR0620 [Preliminary]
4574FS-GPS-01/06
ATR0620 [Preliminary]
Table 3-12.
NMEA Port Port
Following Message Settings Used Table Above
Standard GGA, SOL, SVINFO
Supported Messages Setting "Low"
Supported Messages Setting "Medium" NMEA Port Port Standard GGA, RMC, GSA, GSV, GLL, VTG, SOL, SVINFO, POSECEF, POSLLH, STATUS, DOP, VELECEF, VELNED, TIMEGPS, TIMEUTC, CLOCK
Supported Messages Setting "High" NMEA Port Standard Proprietary GGA, RMC, GSA, GSV, GLL, VTG, ZDA, GRS, PUBX00, PUBX03, PUBX04 SOL, SVINFO, POSECEF, POSLLH, STATUS, DOP, VELECEF, VELNED, TIMEGPS, TIMEUTC, CLOCK SCHD,
Port
Supported Messages Setting "Debug" (Additional Undocumented Message Part Output Data) NMEA Port Standard Proprietary Port GGA, RMC, GSA, GSV, GLL, VTG, ZDA, GRS, PUBX00, PUBX03, PUBX04 SOL, SVINFO, POSECEF, POSLLH, STATUS, DOP, VELECEF, VELNED, TIMEGPS, TIMEUTC, CLOCK SCHD,
Table 3-13.
GPSMODE11
Navigation Rate Settings
GPSMODE10 GPSMODE8 GPSMODE7 navigation rate 0.5Hz navigation rate navigation rate navigation rate Navigation Rate navigation rate (default) navigation rate navigation rate navigation rate
4574FS-GPS-01/06
External Connections Working System
Example External Connection
SIGH SIGL Table 3-14 Table 3-14 Table 3-14 Table 3-14 Table 3-14 Table 3-14 Table 3-14 (see Power Supply) SIGHI SIGLO CLK23 RF_ON NSLEEP NRESET EM_DA0 EM_A1 NTRST TEST_MODE DBG_EN NSHDN LDO_EN LDO_OUT VDD18 LDO_IN LDOBAT_IN VBAT18_O VBAT18_I VBAT
Figure 3-2.
ATR0600
ATR0620
TOUT1 XT_IN XT_OUT
STATUS TIMEPULSE Optional USART Optional USART Optional USART
32.368 (see RTC)
(see Power Supply)
connected
ATR0620 [Preliminary]
4574FS-GPS-01/06
ATR0620 [Preliminary]
Table 3-14.
Name P0/RXD0
Recommended Connection
Recommended External Circuit Pull-up resistor VDD18 connect VDD18 unused. Pull-down resistor also possible used GPIO input user application. Never leave open. Pull-up resistor VDD18 pull-down resistor used input user application; connect VDD18 unused used GPSMODE only. GPSMODE definitions "Setting GPSMODE0 GPSMODE12" page left open configured output user application. this left open, GPSMODE configuration feature must completely disabled user application. Internal pull-down resistor; should left open. Output default firmware: leave open; only needs pull-up resistor VDD18 pull-down resistor used GPIO input user application. Output default firmware: leave open; only needs pull-up resistor VDD18 pull-down resistor used GPIO input user application. Output default firmware: leave open; only needs pull-up resistor VDD18 pull-down resistor used GPIO input user application. Output default firmware: leave open; only needs pull-up resistor VDD18 pull-down resistor used GPIO input user application. Output default firmware: leave open; only needs pull-up resistor VDD18 pull-down resistor used GPIO input user application. Output default firmware: leave open; only needs pull-up resistor VDD18 pull-down resistor used GPIO input user application. Pull-up resistor VDD18 pull-down resistor connect VDD18 unused. Never leave open. Output default firmware: leave open; only needs pull-up resistor VDD18 pull-down resistor used GPIO input user application. Pull-up resistor VDD18 pull-down resistor (this used address line EM_A21 standard firmware, connect VDD18 directly). Never leave open. Pull-up resistor VDD18 pull-down resistor used input user application; connect VDD18 unused used GPSMODE only. GPSMODE definitions "Setting GPSMODE0 GPSMODE12" page left open used GPSMODE configured output user application. Pull-up resistor VDD18 pull-down resistor used input user application; connect VDD18 unused used GPSMODE only. GPSMODE definitions "Setting GPSMODE0 GPSMODE12" page Never leave open. Pull-up resistor VDD18 pull-down resistor used input user application; connect VDD18 unused used GPSMODE only. GPSMODE definitions "Setting GPSMODE0 GPSMODE12" page left open used GPSMODE configured output user application. Output default firmware: leave open; only needs pull-up resistor VDD18 pull-down resistor used GPIO input user application. Output default firmware: leave open; only needs pull-up resistor VDD18 pull-down resistor used GPIO input user application. Pull-up resistor VDD18 pull-down resistor used input user application; connect VDD18 unused used GPSMODE only. GPSMODE definitions "Setting GPSMODE0 GPSMODE12" page left open used GPSMODE configured output user application.
P1/GPSMODE0
P2/BOOT_MODE1 P3/NCS1 P4/NCS0 P5/NWE/NWR0 P6/NOE/NRD P7/NUB/NWR1 P8/STATUS P9/EXTINT0/GPSMODE1 P10/EMA0/NLB P11/EXTINT2/EM_A21
P12/NCS2/GPSMODE2
P13/EXTINT1/ GPSMODE3/NCS3
P14/SCK0/GPSMODE4
P15/TXD0 P16/NWD_OVF
P17/SCK1/GPSMODE5
P18/TXD1 Note:
Output default firmware: leave open; only needs pull-up resistor VDD18 pull-down resistor used GPIO input user application. "Never leave open" means: This needs defined level, even VDD18 supplied system backup mode.
4574FS-GPS-01/06
Table 3-14.
Name
Recommended Connection (Continued)
Recommended External Circuit Pull-up resistor VDD18 pull-down resistor used input user application; connect VDD18 unused used GPSMODE only. GPSMODE definitions "Setting GPSMODE0 GPSMODE12" page left open used GPSMODE configured output user application. Output default firmware: leave open; only needs pull-up resistor VDD18 pull-down resistor used GPIO input user application. Output default firmware: leave open; only needs pull-up resistor VDD18 pull-down resistor used GPIO input user application. Pull-up resistor VDD18 connect VDD18 unused. Pull-down resistor also possible used GPIO input user application. Never leave open. Pull-up resistor VDD18 pull-down resistor used input user application; connect VDD18 unused used GPSMODE only. GPSMODE definitions "Setting GPSMODE0 GPSMODE12" page left open used GPSMODE configured output user application. Pull-up resistor VDD18 pull-down resistor used input user application; connect VDD18 unused used GPSMODE only. GPSMODE definitions "Setting GPSMODE0 GPSMODE12" page left open used GPSMODE configured output user application. Pull-up resistor VDD18 pull-down resistor used input user application; connect VDD18 unused used GPSMODE only. GPSMODE definitions "Setting GPSMODE0 GPSMODE12" page left open used GPSMODE configured output user application. Pull-up resistor VDD18 pull-down resistor used input user application; connect VDD18 unused used GPSMODE only. GPSMODE definitions "Setting GPSMODE0 GPSMODE12" page pull-up resistor VDD18 used. Never leave open. Pull-up resistor VDD18 pull-down resistor used input user application; connect VDD18 unused used GPSMODE only. GPSMODE definitions "Setting GPSMODE0 GPSMODE12" page left open used GPSMODE configured output user application. Output default firmware: leave open; only needs pull-up resistor VDD18 pull-down resistor used GPIO input user application. Pull-up resistor VDD18 pull-down resistor used input user application; connect VDD18 unused used GPSMODE only. GPSMODE definitions "Setting GPSMODE0 GPSMODE12" page left open used GPSMODE configured output user application. Internal pull-up resistor; should left open. Pull-up resistor VDD18 connect VDD18 unused. Pull-down resistor also possible used GPIO input user application. Never leave open.
P19/SIGLO2/GPSMODE6
P20/SCK2/TIMEPULSE P21/TXD2 P22/RXD2
P23/SCK/GPSMODE7
P24/MOSI/GPSMODE8
P25/MISO/GPSMODE9
P26/NSS/NPCS0/ GPSMODE10
P27/NPCS1/GPSMODE11
P28/EM_A20/NPCS2
P29/NPCS3/GPSMODE12
P30/BOOT_MODE0 P31/RXD1
EM_DA0 EM_DA15 Note:
external memory used, connect GND. These pins need defined level (pull-up resistor VDD18 pull-down resistor GND) external memory connected external accesses occur. "Never leave open" means: This needs defined level, even VDD18 supplied system backup mode.
ATR0620 [Preliminary]
4574FS-GPS-01/06
ATR0620 [Preliminary]
Power Supply
baseband supplied with distinct supply voltages: VDD18, nominal 1.8V supply voltage core VBAT18_I supply backup SRAM baseband contains built-in low-dropout voltage regulator LDO18. This regulator used host system does provide core voltage VDD18 1.8V (nominal). such case, LDO18 will provide 1.8V supply voltage from input voltage between 2.3V 3.6V. will also allow supplying external components such Flash memory with 1.8V. LDO_EN input used shut down VDD18 system standby mode. host system does, however, supply 1.8V core voltage directly, this voltage connected VDD18 supply pins baseband LDO_EN must connected GND. LDO_IN connected GND. LDO_OUT must connected. second built-in low-dropout voltage regulator LDOBAT provides supply voltage backup SRAM from input voltage VBAT between 1.95V 3.6V. backup battery only discharged (supplied LDOBAT_IN) shut down. Only after VDD18 have been supplied ATR0620 section backup battery switch will initialized properly. only VBAT applied first, current consumption backup SRAM undetermined. Figure 4-1. External Wiring Example Using Internal LDOs Backup Power Supply
ATR0620 internal VDD18 2.3V 3.6V LDO_IN NSHDN (X7R) LDO_EN LDO_OUT LDO18 LDO_IN LDO_EN LDO_OUT
LDOBAT (X7R) 1.95V 3.6V LDOBAT_IN VBAT VBAT18_O (X7R) SMDUAL VBAT18_I VBAT18 outsm VBAT VBAT18 outsmbak RTC/BBR
Signals: VDD18 1.8V regulated LDO_IN Input LDO18 (not LDOBAT input!) VBAT unregulated backup battery voltage VBAT18_O 1.8V regulated backup voltage output VBAT18_I 1.8V backup voltage input outsmbak internal signal switch, LDOBAT_IN 1.8V outsm brownout flag, VBAT18 1.2V reset VBAT18 1.2V
vbat18
4574FS-GPS-01/06
Figure 4-2.
External Wiring Example Using 1.8V from Host System Backup Power Supply
ATR0620 internal 1.65V 1.95V (X7R) VDD18 LDO18 LDO_IN LDO_EN LDO_OUT LDO_IN LDO_EN LDO_OUT
LDOBAT 2.7V 3.3V LDOBAT_IN VBAT VBAT18_O VBAT VBAT18 outsmbak RTC/BBR
1.95V 3.6V
SMDUAL VBAT18_I (X7R) VBAT18 outsm
Signals: VDD18 1.8V regulated (from host system) LDOBAT_IN 2.7- 3.3V supply voltage) VBAT unregulated backup battery voltage VBAT18_O 1.8V regulated backup voltage output VBAT18_I 1.8V backup voltage input outsmbak internal signal switch, LDOBAT_IN 1.8V outsm brownout flag, VBAT18 1.2V reset VBAT18 1.2V
vbat18
Oscillator
Figure 5-1. Crystal Connection
ATR0620 internal
XT_IN Crystal Oscillator 32.768 XT_OUT
32.768 clock
max.
max.
ATR0620 [Preliminary]
4574FS-GPS-01/06
ATR0620 [Preliminary]
Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Parameters Operating Free Temperature Range Storage Temperature Supply Voltage Supply Voltage Supply Voltage Supply Voltage Supply Voltage VDD18 VBAT18_I LDO_IN LDOBAT_IN VBAT Min. -0.3 -0.3 -0.3 -0.3 -0.3 Max. +150 +1.95 +1.95 +3.6 +3.6 +3.6 Unit
Note:
P31, EM_DA0 EM_DA16, SIGHI, SIGLO, CLK23, XT_IN, -0.3 Input Voltage XTOUT, TMS, TCK, TDI, NTRST, LDO_EN, TEST_MODE, DBG_EN, LDO_EN, NRESET Minimum/maximum limits +25°C ambient temperature, unless otherwise specified
+1.95
Electrical Characteristics Characteristics
Parameters Supply Voltage Output Voltage Low-level Input Voltage High-level Input Voltage Low-level Output Voltage High-level Output Voltage Low-level Output Current High-level Output Current VDD18 1.65V 1.95V VDD18 1.65V 1.95V VDD18 1.65V VDD18 1.65V VDD18 1.8V, 0.4V VDD18 1.8V, 1.3V Test Conditions VBAT18_I, VDD18 Symbol VDD18 ILEAK VDD18 Min. 1.65 -0.3 VDD18 Typ. Max. 1.95 VDD18 VDD18 VDD18 Unit
VDD18 1.95V, VBAT18_I Input-leakage Current 1.95 (Standard Inputs I/Os) VIL=0V, -40°C 85°C Input-leakage Current (Inputs I/Os with Pull-up) Input-leakage Current (Inputs I/Os with Pull-down) VDD18 1.95V, VBAT18_I 1.95 -40°C 85°C VDD18 1.95V, VBAT18_I 1.95 =0V, -40°C 85°C
ILEAK
-250
-100
ILEAK
-6.6
+6.6
Notes:
VDD18 1.95V, VBAT18_I Input-leakage Current 1.95 (Standard Inputs I/Os) 1.95V, -40°C 85°C
ILEAK
Min./Max. limits +25°C ambient temperature, unless otherwise specified.
4574FS-GPS-01/06
Electrical Characteristics Characteristics (Continued)
Parameters Input-leakage Current (Inputs I/Os with Pull-up) Input-leakage Current (Inputs I/Os with Pull-down) Input Capacitance Input Pull-up Resistor Input Pull-down Resistor -40°C 85°C -40°C 85°C Test Conditions VDD18 1.95V, VBAT18_I 1.95 1.95V, -40°C 85°C VDD18 1.95V, VBAT18_I 1.95 1.95V, -40°C 85°C Symbol ILEAK Min. Typ. Max. Unit
Notes:
ILEAK ICAP
0.65 0.95
0.80 1.20
Verified Schmitt Trigger Threshold characterization. Schmitt Trigger Threshold Verified characterization.
Min./Max. limits +25°C ambient temperature, unless otherwise specified.
Power Consumption
Table 8-1.
Mode Reset Sleep Shutdown
Core Power Consumption
Conditions 23.104 1.8V, CLK23 backup SRAM only Satellite acquisition Normal tracking channels with fix/s; each additional active tracking channel adds channels disabled Typ. 0.15(1) 0.025(1) Unit
Normal
Note:
Specified value only
Table 8-2.
Mode
Core Power Consumption Peripheral
Max.
Unit
USART default configuration USARTs use) default configuration used) Note: Preliminary results
0.3(1)
ATR0620 [Preliminary]
4574FS-GPS-01/06
ATR0620 [Preliminary]
Sensitivity
Table 9-1.
Test Model Human Body Model (HBM) Machine Model (MM) Charge Device Model (CDM) Field Induced Charge Device Model (FCDM)
Sensitivity
Max. 1000 Unit
LDO18
LDO18 built-in low-dropout voltage regulator which used host system does provide core voltage VDD18.
Table 10-1.
Parameter
Electrical Characteristics LDO18
Conditions Min. 1.65 After startup, load Standby Mode During startup, load Load change: Supply change: 2.3V (100V/ms), load Load change: Supply change: 3.6V (100V/ms), load Typ. Max. 1.95 Unit
Supply voltage LDO_IN Output voltage (LDO_OUT) Output current (LDO_OUT) Current consumption Current consumption Current consumption Voltage drop (Load) Voltage drop (Supply LDO_IN) Voltage surge (Load) Voltage surge (LDO_IN)
4574FS-GPS-01/06
LDOBAT
LDOBAT built-in low-dropout voltage regulator which provides supply voltage backup SRAM. LDOBAT voltage regulator switches battery mode LDOBAT_IN falls below 1.8V.
Table 11-1.
Parameter
Electrical Characteristics LDOBAT
Conditions Min. 1.95 1.65 After startup, load After startup, load During startup, load Load change: Supply change: 2.3V (100V/ms), load Supply change: 1.95V (100V/ms), load Load change: Supply change: 3.6V (100V/ms), load Supply change: 1.95 3.6V (100V/ms), load Main power (VDD) falls below 1.8V, VBAT 1.95V 10.3 Typ. Max. 1.95 Unit
Supply voltage Supply voltage VBAT Output voltage (VBAT18_O) Output current (VPAT18_O) Current consumption Current consumption Current consumption Voltage drop (Load) Voltage drop (supply VDD) Voltage drop (supply VBAT) Voltage surge (Load) Voltage surge (supply VDD) Voltage surge (supply VBAT) Switch time
ATR0620 [Preliminary]
4574FS-GPS-01/06
ATR0620 [Preliminary]
Ordering Information
Extended Type Number ATR0620R-7FQ ATR0620R-7FQY Package TFBGA100 TFBGA100 Remarks 0.80 pitch, 0.80 pitch, Pb-free
Package TFBGA100
Package: R-TFBGA 100_C R-TFBGA 100_F Dimensions 0.08 0.15 Corner View Bottom View Corner 0.35 0.45 (100x)
9±0.05
technical drawings according specifications
0.15 (4x) 9±0.05 0.53 ref. (0.21)
0.12
0.25 0.35
Seating plane
Drawing-No.: 6.580-5004.01-4 Issue: 27.10.05
4574FS-GPS-01/06
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4574FS-GPS-01/06

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