Expandable LAN-Subsystem Memory Mbytes 32-Bit Host Address Subsys
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TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
Expandable LAN-Subsystem Memory Mbytes 32-Bit Host Address
Subsystem Attached System MHz)
Transmit TI380C30 Receive Memory Network
Figure Network-Commprocessor Applications Diagram
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. Token-Ring Network trademarks International Business Machines Corp. PacketBlaster trademark Texas Instruments Incorporated.
ADVANCE INFORMATION concerns products sampling preproduction phase development. Characteristic data other specifications subject change without notice.
Copyright 1995, Texas Instruments Incorporated
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Single-Chip Token-Ring Solution IBMToken-Ring Network Compatible Compatible With IEEE Std. 802.5:1992 Token-Ring Access-Method Physical-Layer Specifications Compatible With TI380FPA PacketBlasterGlueless Memory Interface Digital Phase-Locked Loop Precise Control Bandwidths Improved Jitter Tolerance Minimizes Accumulated Phase Slope Phantom Drive Physical Insertion Onto Ring Differential Line Receiver With Level-Dependent Frequency Equalization Low-Impedance Differential Line Driver Ease Transmit-Filter Design On-Chip Watchdog Timer Internal Crystal Oscillator Reference-Clock Generation
80x8x 68xxx-Type Memory Organization Dual-Port Direct Transfers Host Supports 16-Bit Pseudo-DMA Operation 176-Pin Thin Quad Flat Package (PGF Suffix) CMOS Technology Operating Temperature Range 70°C Token-Ring Features 4-Mbps Data Rates Supports 18-KByte Frame Size Mbps Only) Supports Universal Local Addressing Early Token-Release Option Mbps Only) Built-In Real-Time Error Detection Automatic Frame-Buffer Management 33-MHz System-Bus Clock Slow-Clock Low-Power Mode
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
assignments
PACKAGE VIEW
MBIAEN MRESET MBCLK2 MBCLK1 OSCOUT NSELOUT1 WRAP DRVR+ DRVR WFLT PXTAL RCVR RCLK SSC1 RATER NABL PWRDN SSL1 SSA1 RCV+ DDA1 RCV- DDL1 XMT- XMT+ PHOUTB PHOUTA SSL1 DDL1
MREF MACS MROMEN OSC32 OSCIN TCLK TRST VSSC SYNCIN VDDL MDDIR MAX0 MAX2 MCAS MRAS VSSC VSSL MBEN MADH7 MADH6 MADH5 MADH4 MADH3 MADH2 MADH1 MADH0 MAXPH MBRQ MBGR MAXPL MADL7 MADL6 MADL5 MADL4 MADL3
VSSO VDDA2 ATEST VSSA2 IREF VSSA3 REDY VDDA3 FRAQ NSRT VSSL XMATCH XFAIL TEST0 TEST1 TEST2 TEST3 TEST4 TEST5 SADH0 SADH1 SADH2 SADH3 SADH4 SADH5 VSSC SADH6 SADH7 SUDS SRDY SDTACK SOWN SDBEN SBHE SRNW SHRQ SBRQ SADL0 SADL1 SADL2
MADL2 MADL1 MADL0 EXTINT3 EXTINT2 EXTINT1 EXTINT0 CLKDIV NSELOUT0 PRTYEN BTSTRP SIACK SRESET SRS1 SRS0 SRSX SBRLS SBBSY SHALT SRS2 SBERR SINTR SIRQ SHLDA SBGR SDDIR SRAS SLDS SXAL SALE SBCLK SADL7 SADL6 SADL5 SADL4 SADL3
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TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
description
TI380C30 single-chip token-ring solution, combining both commprocessor physical-layer interface onto single device. TI380C30 supports both Mbps operation, conforms 8802-5/ IEEE 802.5 1992 standards, been verified completely Token-Ring Network compatible. TI380C30 provides high degree integration combines functions TI380C25 TI380C60 onto single chip. With this chip, only local memory minimal additional components such PAL® devices crystal oscillators need added complete LAN-subsystem design. TI380C30 provides 32-bit system-memory address reach with high-speed bus-master interface that supports rapid communications with host system. addition, TI380C30 supports direct low-cost 16-bit pseudo-DMA interface that requires only chip select work directly 80x8x 8-bit slave interface. Selectable 80x8x 68xxx-type host-system memory organization design flexibility. TI380C30 supports addressing Mbytes local memory. This expanded memory capacity improve LAN-subsystem performance minimizing frequency host LAN-subsystem communications allowing larger blocks information transferred time. support large local memory important applications that require large data transfers (such graphics data-base transfers) heavily loaded networks where extra memory provide data buffers store data until processed host. proprietary used TI380C30 allows protocol software downloaded into stored local-memory space. moving protocols [such logical link control (LLC)] LAN-subsystem, overall system performance increased. This accomplished offloading processing from host-system TI380C30, which also reduce LAN-subsystem-to-host communications. other protocol software developed, greater differentiation products with enhanced system performance possible. TI380C30 includes hardware counters that provide real-time error detection automatic frame-buffer management. These counters control system-bus retries burst size, track host- LAN-subsystem-buffer status. Previously, these counters needed maintained software. integrating them into hardware, software overhead removed LAN-subsystem performance improved. TI380C30 implements TI-patented enhanced-address-copy-option (EACO) interface. This interface supports external address-checking devices, such TMS380SRA source-routing accelerator. TI380C30 128-word external space memory support external address-checker devices other hardware extensions TMS380 architecture. physical-layer interface, Manchester-encoded data stream received phase aligned using on-chip dual-digital phase-locked loop (PLL). Both recovered clock data passed protocol-handling circuits TI380C30 serial-to-parallel conversion data processing. transmit, TI380C30 buffers output from protocol-handling circuit drives media suitable isolation waveform-shaping components. TI380C30 uses CMOS technology reduce power consumption PCMCIA-compatible levels. Power-management features incorporated support Green compatibility. addition PLL, other functions required interface IEEE-802.5 token ring provided. These functions include phantom drive control relays within trunk-coupling unit wire-fault detection circuits; internal-wrap function self-test watchdog timer provide fail-safe deinsertion from ring event station, microcode commprocessor failure. major blocks TI380C30 include communications processor (CP), system interface (SIF), memory interface (MIF), protocol handler (PH), clock generator (CG), adapter-support function (ASF), physical-layer interface (PHY), shown functional block diagram.
PAL® registered trademark Advanced Micro Devices Inc. Other companies also manufacture programmable array logic devices.
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TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
functional block diagram
SADH0 SADH7 SADL0 SADL7 SBRLS SINTR/ SIRQ SDDIR SDBEN SALE SXAL SOWN SIACK SBCLK SRD/ SUDS SWR/ SLDS SRDY/SDTACK SI/M SHLDA/ SBGR SBHE/ SRNW SRAS/ SHALT SRESET SRS0 SRS1 SRS2/ SBERR SRSX SHRQ/ SBRQ SBBSY BTSTRP PRTYEN NSELOUT0 NSELOUT1 System Interface (SIF) Memory Interface (MIF) MADH0 MADH7 MADL0 MADL7 MRAS MCAS MAXPH MAXPL MDDIR MAX0 MAX2 MRESET MROMEN MBEN MBRQ MBGR MACS MBIAEN MREF OSCIN OSCOUT MBCLK1 MBCLK2 SYNCIN CLKDIV EXTINT0 EXTINT3 TEST0 TEST5 XMATCH XFAIL FRAQ NSRT WRAP DRVR+ DRVR XMT+ XMT- RDV+ RCV- PWRDN NABL RATER
Control Control Control
DRAM Refresh Local-Bus Arbitrator Local-Bus Control Local Parity-Check Generator
ADVANCE INFORMATION
Clock Generator (CG)
AdapterSupport Function (ASF) Communications Processor Interrupts Test Function
Token-Ring Protocol Handler (PH) RCLK REDY WFLT RCVR PXTAL OCS32 TCLK TRST ATEST PHOUTA PHOUTB Signals provided test monitoring purposes.
Physical-Layer-Interface Test Port
Physical-Layer Interface Analog Signal
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TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
Functions
NAME ATEST I/O/E Analog test. Should left unconnected. Bootstrap. value BTSTRP loaded into BOOT SIFACL register reset (i.e., when SRESET asserted ARESET SIFACL register set) form default value. BTSTRP indicates whether chapters memory ROM. these chapters RAM, TI380C30 denied access local-memory until CPHALT SIFACL register cleared. Chapters local memory RAM-based (see Note Chapters local memory ROM-based. Clock divider select (see Note CLKDIV 64-MHz OSCIN 4-MHz local 32-MHz OSCIN 4-MHz local 48-MHz OSCIN 6-MHz local Differential-driver data outputs (reserved) Equalization gain points. Connections allow frequency tuning equalization circuit. DESCRIPTION
BTSTRP
DRVR+ DRVR EXTINT0 EXTINT1 EXTINT2 EXTINT3 FRAQ
Reserved; must pulled high (see Note
Frequency-acquisition control. Clock recovery initialized. Normal operation Internal reference. IREF allows internal bias current analog circuitry external resistor. Reserved; must tied (see Note Local-memory address, data, status high byte. first quarter local-memory cycle, these lines carry address bits second quarter, they carry status bits; third fourth quarters, they carry data bits most significant MADH0 least significant MADH7. Memory Cycle Status
IREF MACS MADH0 MADH1 MADH2 MADH3 MADH4 MADH5 MADH6 MADH7
Signal
AX4,
MADL0 Local-memory address, data, status byte. first quarter local-memory MADL1 cycle, these lines carry address bits A14; second quarter, they carry address bits MADL2 third fourth quarters, they carry data bits most significant MADL3 MADL0 least significant MADL7. MADL4 Memory Cycle MADL5 MADL6 Signal AX4, MADL7 input, output, provides external-component connection internal circuitry tuning NOTES: internal pullup device maintain high-voltage level when left unconnected etch). TI380FPA TMS380SRA currently supported only with 4-MHz local either CLKDIV state. Expansion support 6-MHz local under development. Each must individually tied with pullup resistor. should connected ground.
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TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
Functions (Continued)
NAME I/O/E DESCRIPTION Memory-address latch. strobe signal sampling address start memory cycle; used SRAMs EPROMs. full 20-bit word address valid MAX0, MAXPH, MAX2, MAXPL, MADH0 MADH7, MADL0 MADL7. Three 8-bit transparent latches used retain 20-bit static address throughout cycle. Rising edge signal latching Falling edge Allows above address signals latched Local-memory extended-address bit. MAX0 drives row-address time column-address data-valid times cycles. MAX0 latched MRAS. Driving eases interfacing burn-in address (BIA) ROM. MAX0 Memory Cycle
Signal
MAX2
Local-memory extended-address bit. MAX2 drives row-address time, which latched MRAS, column-address data-valid times cycles. Driving eases interfacing ROM. Memory Cycle Signal Local-memory extended address parity high byte. first quarter memory cycle, MAXPH carries extended-address AX1; second quarter memory cycle, MAXPH carries extended-address AX0; last half memory cycle, MAXPH carries parity high data byte. Memory Cycle Signal Parity Parity Local-memory extended address parity byte. first quarter memory cycle, MAXPL carries extended-address AX3; second quarter memory cycle, MAXPL carries extended-address AX2; last half memory cycle, MAXPL carries parity data byte. Memory Cycle Signal Parity Parity Local-bus clock local-bus clock MBCLK1 MBCLK2 referenced local-bus transfers. MBCLK2 lags MBCLK1 quarter cycle. MBCLK1 MBCLK2 operate according
ADVANCE INFORMATION
MAXPH
MAXPL
MBCLK1 MBCLK2
MBCLK [1:2]
OSCIN
CLKDIV
MBEN
Buffer enable. MBEN enables bidirectional buffer outputs MADH, MAXPH, MAXPL, MADL buses during data phase. MBEN used conjunction with MDDIR, which selects buffer-output direction. Buffer output disabled Buffer output enabled
MBGR
Reserved; must left unconnected Burned-in address enable. MBIAEN output signal used provide output enable containing adapter's BIA.
MBIAEN
MBIAEN driven high write accesses addresses between 00.0000 00.000F, accesses (read/write) other address. MBIAEN driven read from addresses between 00.0000 00.000F.
input, output, provides external-component connection internal circuitry tuning
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TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
Functions (Continued)
NAME MBRQ I/O/E DESCRIPTION Reserved; must pulled high (see Note Column-address strobe DRAMs. column address valid 3/16 memory cycle following row-address portion cycle. MCAS driven every memory cycle while column address valid MADL0 MADL7, MAXPH, MAXPL, except when following conditions occurs: MCAS
When address accessed 00.0000 00.000F) When address accessed EPROM memory (i.e., when BOOT SIFACL register zero access made between 00.0010 00.FFFF 1F.0000 1F.FFFF) When cycle refresh cycle, which case MCAS driven start cycle before MRAS (for DRAMs that have CAS-before-RAS refresh). DRAMs that support CAS-before-RAS refresh, necessary disable MCAS with MREF during refresh cycle.
Data direction. MDDIR used direction control bidirectional drivers. MDDIR becomes valid before MBEN becomes active. MDDIR
Memory-output enable. enables outputs DRAM memory during read cycle. high EPROM read cycles. Disable DRAM outputs Enable DRAM outputs Row-address strobe DRAMs. address lasts first 5/16 memory cycle. MRAS driven every memory cycle while address valid MADL0 MADL7, MAXPH, MAXPL both cycles. MRAS also driven during refresh cycles when refresh address valid MADL0 MADL7. DRAM refresh cycle progress. MREF indicates that DRAM refresh cycle occurring. also used disabling MCAS DRAMs that CAS-before-RAS refresh. MREF DRAM refresh cycle process DRAM refresh cycle Memory-bus reset. MRESET reset signal generated when either ARESET SIFACL register SRESET asserted. MRESET used resetting external local-bus glue logic. MRESET External logic reset External logic reset enable. During first 5/16 memory cycle, MROMEN used provide chip select ROMs when BOOT SIFACL zero (i.e., when code resident ROM, RAM). MROMEN latched MAL. MROMEN goes read from addresses 00.0010 00.FFFF 1F.0000 1F.FFFF when BOOT SIFACL register zero. MROMEN stays high writes these addresses, accesses other addresses, accesses address when BOOT During final three quarters memory cycle, MROMEN outputs address signal interfacing ROM. This means MBIAEN, MAX0, ROMEN, MAX2 form glueless interface ROM. disabled enabled Local-memory write. used specify write cycle local-memory bus. data MADH0 MADH7 MADL0 MADL7 buses valid while low. DRAMs latch data falling edge while SRAMs latch data rising edge local-memory write cycle Local-memory write cycle input, output, provides external-component connection internal circuitry tuning NOTE Each must individually tied with pullup resistor.
MRAS
MROMEN
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TI380C30 memory-bus write TI380C30 memory-bus read
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
Functions (Continued)
NAME NABL I/O/E DESCRIPTION Output-enable control. NABL used physical-layer circuitry (see Note These pins should left unconnected. Nonmaskable interrupt request. must left unconnected. Network selection outputs. NSELOUT0 NSELOUT1 controlled host through corresponding bits SIFACL register. value NSELOUT0 NSELOUT1 changed only while TI380C30 reset. NSELOUT0 NSELOUT1 DESCRIPTION 16-Mbps token ring 4-Mbps token ring
NSELOUT0 NSELOUT1
NSRT
Insert control. NSRT enables phantom-driver outputs (PHOUTA PHOUTB) through watchdog timer insertion onto token ring. Static high Inactive, phantom current removed (due watchdog timer) Static Inactive, phantom current removed (due watchdog timer) Falling edge Active, current output PHOUTA PHOUTB Oscillator output OSC32 provides 32-MHz clock output used drive OSCIN other load. External oscillator input. OSCIN provides clock frequency TI380C30 4-MHz 6-MHz internal (see Notes CLKDIV OSCIN 4-MHz local 4-MHz local 6-MHz local Oscillator output CLKDIV OSCOUT OSCIN OSCIN
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OSC32
OSCIN
OSCOUT
OSCIN MHz, OSCOUT MHz; OSCIN MHz, OSCOUT MHz) OSCIN MHz, OSCOUT MHz)
PHOUTA PHOUTB
Phantom-driver outputs PHOUTA PHOUTB cause insertion onto token ring. PHOUTA PHOUTB should connected center transmit transformer secondary winding phantom-drive generation. Parity enable. value PRTYEN loaded into SIFACL register reset (i.e., when SRESET asserted ARESET SIFACL register set) form default value. PRTYEN enables parity checking local memory. Local-memory data checked parity (see Note Local-memory data checked parity. Power-down control (see Note Normal operation TI380C30 physical-layer circuitry placed into power-down state. outputs physical layer driven high-impedance state. Reference-clock output. PXTAL synthesized from 8-MHz crystal oscillator used XT2. Mbps 32-MHz clock, Mbps 8-MHz clock.
PRTYEN
PWRDN
PXTAL
input, output, provides external-component connection internal circuitry tuning NOTES: internal pullup device maintain high-voltage level when left unconnected etch). Each must individually tied with pullup resistor. expanded input voltage specification. maximum TI380C30 devices connected oscillator. should tied with 4.7-k pullup resistor.
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TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
Functions (Continued)
NAME RATER I/O/E DESCRIPTION RATER indicates that there transitions RCV+ RCV- input pair (DRVR DRVR WRAP asserted low) that transition rate consistent with ring speed selected pin. Recovered clock. RCLK clock recovered from token-ring received data. 16-Mbps operation, 32-MHz clock. 4-Mbps operation, 8-MHz clock. Receiver. RCV+ RCV- differential inputs that receive token-ring data isolation transformers. Recovered data. RCVR contains data recovered from token ring. ready. REDY normally asserted (active) low. cleared following assertion FRAQ reasserted after data recovery been reinitialized. Received data valid Received data valid Reserved. Should left unconnected. System address/data high byte (see Note 1).These lines make most significant byte each address word (32-bit address bus) data word (16-bit data bus). most significant SADH0, least significant SADH7. Address multiplexing: Bits bits Data multiplexing: Bits
RCLK RCV+ RCV- RCVR
REDY
SADH0 SADH1 SADH2 SADH3 SADH4 SADH5 SADH6 SADH7 SADL0 SADL1 SADL2 SADL3 SADL4 SADL5 SADL6 SADL7
System address/data byte (see Note These lines make least significant byte each address word (32-bit address bus) data word (16-bit data bus). most significant SADL0, least significant SADL7. Address multiplexing: Bits bits Data multiplexing Bits
SALE
System address-latch enable. SALE enable pulse used externally latch LSBs address from SADH0 SADH7 SADL0 SADL7 buses start cycle. Systems that implement address parity also externally latch parity bits (SPH SPL) latched address. System busy. TI380C30 samples value SBBSY during arbitration (see Note sample values:
SBBSY
busy. TI380C30 become master grant condition met. Busy. TI380C30 cannot become master.
SBCLK
System clock. TI380C30 requires external clock synchronize timings transfers. Valid frequencies MHz. SBHE used system byte high enable. SBHE 3-state output driven during DMA; input other times. Intel Mode System byte high enabled (see Note System byte high enabled SRNW used system read write. SRNW serves control signal indicate read write cycle. Read cycle (see Note Write cycle
SBHE SRNW
Motorola Mode
input, output, provides external-component connection internal circuitry tuning Typical ordering Inteland Motorola processor buses NOTE internal pullup device maintain high-voltage level when left unconnected etch). Intel trademark Intel Corporation.
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TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
Functions (Continued)
NAME I/O/E DESCRIPTION System-bus release. SBRLS indicates TI380C30 that higher-priority device requires system bus. value SBRLS ignored when TI380C30 performing DMA. SBRLS internally synchronized SBCLK. SBRLS TI380C30 hold onto system (see Note TI380C30 should release system upon completion current cycle. transfer complete, rearbitrates system bus. System-chip select. activates system interface TI380C30 read write. selected (see Note Selected System data-bus enable. SDBEN signals external data buffers begin driving data. SDBEN activated during both DMA. SDBEN Keep external data buffers high-impedance state Cause external data buffers begin driving data
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System data direction. SDDIR provides external data buffers signal indicating direction which data moving. During writes reads, SDDIR (data direction into TI380C30). During reads writes, SDDIR high (data direction from TI380C30). When system interface involved operation, SDDIR high default. SDDIR SDDIR DATA DIRECTION output input read write write read
Intel Mode Motorola Mode
SHLDA used system-hold acknowledge. SHLDA indicates that system DMA-hold request been acknowledged. SHLDA internally synchronized SBCLK (see Note Hold request acknowledged Hold request acknowledged SBGR used system grant. SBGR active-low grant, defined standard 68xxx interface, internally synchronized SBCLK (see Note System granted System granted SHRQ used system-hold request. SHRQ used request control system preparation transfer. SHRQ internally synchronized SBCLK.
SHLDA SBGR
Intel Mode Motorola Mode System requested System requested SBRQ used system-bus request. SBRQ used request control system preparation transfer. SBRQ internally synchronized SBCLK. System requested System requested
SHRQ SBRQ
System-interrupt acknowledge. SIACK from host processor acknowledge interrupt request from TI380C30. SIACK System interrupt acknowledged (see Note System interrupt acknowledged: TI380C30 places interrupt vector onto system bus.
input, output, provides external-component connection internal circuitry tuning NOTE internal pullup device maintain high-voltage level when left unconnected etch).
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TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
Functions (Continued)
NAME I/O/E DESCRIPTION System-Intel Motorola mode select. value specifies system-interface mode. Intel-compatible-interface mode selected. Intel interface 8-bit 16-bit mode (see SHALT description Note Motorola-compatible-interface mode selected. Motorola-interface mode always bits. SINTR used system-interrupt request. TI380C30 activates SINTR signal interrupt request host processor. Intel Mode Motorola Mode Interrupt request TI380C30 interrupt request SIRQ used system-interrupt request. TI380C30 activates SIRQ signal interrupt request host processor. interrupt request Interrupt request TI380C30
SINTR SIRQ
SOWN
TI380C30 does have control system bus. TI380C30 control system bus. System parity high. optional odd-parity each address data byte transmitted over SADH0 SADH7 (see Note System parity low. optional odd-parity each address data byte transmitted over SADL0 SADL7 (see Note SRAS used system memory-address strobe (see Note SRAS used latch SRSX SRS2 register input signals. minimum-chip system, SRAS tied SALE output system bus. latching capability defeated since internal latch these inputs remains transparent long SRAS remains high. This permits SRAS pulled high signals SCS, SRSX SRS2, SBHE applied independently SALE strobe from system bus. During DMA, SRAS remains input. Falling edge Transparent mode Holds latched values SCS, SRSX SRS2, SBHE Latches SCS, SRSX SRS2, SBHE
Intel Mode
SRAS
Motorola Mode
used sytem-memory address strobe (see Note active-low address strobe that input during (although ignored address strobe) output during DMA. Address valid. Address valid transfer operation progress.
input, output, provides external-component connection internal circuitry tuning NOTES: internal pullup device maintain high-voltage level when left unconnected etch). should tied with 4.7-k pullup resistor.
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System owned. SOWN indicates external devices that TI380C30 control system bus. SOWN drives enable signal bus-transceiver chips that drive address bus-control signals.
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
Functions (Continued)
NAME I/O/E DESCRIPTION used system-read strobe (see Note active-low strobe indicating that read cycle performed system bus. input during output during DMA. Intel Mode Read cycle occurring. DMA, host provides data system bus. DIO, provides data system bus. SUDS used upper-data strobe (see Note SUDS active-low upper-data strobe. SUDS input during output during DMA. valid data SADH0 SADH7 lines Valid data SADH0 SADH7 lines SRDY used system ready (see Note SRDY indicates master that data transfer complete. SRDY asynchronous during pseudo-DMA cycles, internally synchronized SBCLK. During cycles, SRDY must asserted before falling edge SBCLK state order prevent wait state. SRDY output when TI380C30 selected DIO; otherwise, input. System ready. Data transfer complete; system ready. SDTACK used system data-transfer acknowledge (see Note purpose SDTACK indicate master that data transfer complete. SDTACK internally synchronized SBCLK. During cycles, SDTACK must asserted before falling edge SBCLK state order prevent wait state. SDTACK output when TI380C30 selected DIO; otherwise, input. System ready. Data transfer complete; system ready. System reset. SRESET activated place TI380C30 into known initial state. Hardware reset puts most TI380C30 outputs into high-impedance state places blocks into reset state. Intel-mode bus-width selection (S8) latched rising edge SRESET. SRESET system reset System reset Rising edge Latch width operations (for Intel-mode applications) SRSX SRS0 SRS2 used system-register select. These inputs select word byte transferred during system access. most significant SRSX least significant SRS2 (see Note Register selected SRSX SRSX SRS0 SRS1 SRS2 SBERR SRS2 SBERR
SUDS
Motorola Mode
Intel Mode
ADVANCE INFORMATION
SRDY SDTACK
Motorola Mode
Intel Mode
SRS0
SRS1
Motorola Mode
SRSX, SRS0 SRS1 used system-register select. These inputs select word byte transferred during system access. most significant SRSX least significant SRS1 (see Note SRSX SRS1
Register selected
SRS0
SBERR used error. SBERR corresponds bus-error signal 68xxx microprocessor. internally synchronized SBCLK. SBERR driven during cycle indicate TI380C30 that cycle must terminated (see Section 3.4.5.3 TMS380 Second-Generation Token-Ring User's Guide (SPWU005) more information). input, output, provides external-component connection internal circuitry tuning NOTES: internal pullup device maintain high-voltage level when left unconnected etch). should tied with 4.7-k pullup resistor.
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TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
Functions (Continued)
NAME I/O/E DESCRIPTION used system-write strobe (see Note active-low write strobe that input during output during DMA. Intel Mode Motorola Mode Write cycle occurring. DMA, data driven from host bus. DIO, rising edge, data latched written selected register. SLDS used lower-data strobe (see Note SLDS input during output during DMA. valid data SADL0 SADL7 lines Valid data SADL0 SADL7 lines
SLDS
SXAL
System extended-address latch. SXAL provides enable pulse used externally latch most significant bits 32-bit system address during DMA. SXAL activated prior first cycle each block transfer, thereafter necessary (whenever increment address counter causes carry lower bits). Systems that implement parity addresses SXAL externally latch parity bits (available SPH) address extension. Reserved. SYNCIN must left unconnected (see Note Speed switch. specifies token-ring data rate physical layer. 4-Mbps data rate 16-Mbps data rate used system /16-bit select. selects width used communications through system interface. rising edge SRESET, TI380C30 latches width; otherwise, value dynamically selects width. Selects 8-bit mode (see Note Selects 16-bit mode SHALT used system halt error retry. SHALT asserted along with error (SBERR), adapter retries last cycle. This rerun operation defined 68xxx specification. BERETRY counter decremented SBERR when SHALT asserted (see Section 3.4.5.3 TMS380 Second-Generation Token-Ring User's Guide (SPWU005) more information).
SYNCIN
Intel Mode
SHALT
Motorola Mode
TCLK
Test ports used during production test device. Should left unconnected.
Network select inputs. TEST0 TEST2 used select network speed type used TI380C30. These inputs should changed only during adapter reset. Connect TEST2 VDDL. TEST0 TEST1 TEST2 TEST0 TEST1 TEST2 DESCRIPTION 16-Mbps token ring 4-Mbps token ring Reserved
TEST3 TEST4 TEST5 TRST
Test inputs. TEST3 TEST5 should left unconnected (see Note Module-in-place test mode achieved tying TEST3 TEST4 ground. this mode, TI380C30 outputs high-impedance state. Internal pullups TI380C30 inputs disabled (except TEST3 TEST5). Test-port reset. TRST should tied ground normal operation TI380C30. Reserved Test ports forced idle state
input, output, provides external-component connection internal circuitry tuning NOTES: internal pullup device maintain high-voltage level when left unconnected etch). should tied with 4.7-k pullup resistor.
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TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
Functions (Continued)
NAME 136, I/O/E DESCRIPTION
Positive-supply voltage commprocessor output buffers. pins must attached common-system power-supply plane.
VDDA1 VDDA2 VDDA3 VDDD VDDL VDDL1 VDDO VDDP VDDX
Positive-supply voltage receiver circuits Positive-supply voltage data recovery Positive-supply voltage current-bias generator Positive-supply voltage physical layer output buffers Positive-supply voltage commprocessor digital logic. VDDL pins must attached common-system power-supply plane. Positive-supply voltage physical layer digital logic. VDDL pins must attached common-system power-supply plane. Positive-supply voltage XTAL oscillator Positive-supply voltage phantom drive Positive-supply voltage transmit output
ADVANCE INFORMATION
Ground connections commprocessor output buffers. pins must attached system ground plane.
VSSA1 VSSA2 VSSA3 VSSC VSSC1 VSSD VSSL
Ground reference receiver circuits Ground reference data recovery Ground reference current-bias generator Ground reference commprocessor output buffers (clean ground). VSSC pins must attached common-system ground plane. Ground reference physical layer output buffers Ground reference physical layer output buffers
Ground reference digital logic. VSSL pins must attached common-system ground plane.
VSSL1 VSSO VSSP VSSX
Ground reference internal logic Ground reference XTAL oscillator Ground reference phantom drive Ground reference transmit output Phantom-wire fault. WFLT provides indication presence short open circuit PHOUTA PHOUTB. fault Open short. fault condition present phantom-drive lines.
WFLT
input, output, provides external-component connection internal circuitry tuning
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TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
Functions (Continued)
NAME I/O/E DESCRIPTION Internal wrap mode control. WRAP indicates TI380C30 placed physical layer loopback-wrap mode adapter self test. Normal ring operation Physical-layer wrap mode selected External fail-to-match signal. enhanced address copy option (EACO) device uses XFAIL indicate TI380C30 that should copy frame ARI/FCI bits token-ring frame external address match.The ARI/FCI bits token-ring frame internal address-matched frame. EACO device used, XFAIL must left unconnected. XFAIL ignored when mode enabled [see table XMATCH description section (see Note 1)]. address match external address checker External address-checker-armed state External match signal. EACO device uses XMATCH indicate TI380C30 copy frame ARI/FCI bits token-ring frame. EACO device used, XMATCH must left unconnected. XMATCH ignored when mode enabled (see Note Address match recognized external address checker External address-checker-armed state XMATCH XMATCH Hi-Z XMT+ XMT- XFAIL Hi-Z FUNCTION Armed (processing frame data) externally match frame (XFAIL takes precedence) Copy frame externally match frame (XFAIL takes precedence) Reset state (adapter initialized)
WRAP
XFAIL
Transmit differential outputs XMT+ XMT- provide low-impedance differential source line drive filtering transformer isolation.
XTAL connection. 8-MHz crystal network connected here provide reference clock TI380C30. Alternatively, 8-MHz clock source connected XT1. input, output, provides external-component connection internal circuitry tuning NOTE internal pullup device maintain high-voltage level when left unconnected etch).
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architecture
major blocks TI380C30 include communications processor (CP), system interface (SIF), memory interface (MIF), protocol handler (PH), clock generator (CG), adapter-support function (ASF), physical-layer interface. functionality each block described following sections. communications processor (CP) performs control monitoring other functional blocks TI380C30. control monitoring protocols specified software (downloaded ROM-based) local memory. Available protocols include:
Media access control (MAC) software Logical link control (LLC) software Copy frames (CAF) software
proprietary 16-bit central processing unit (CPU) with data cache single prefetch pipe pipelining instructions. These features enhance TI380C30 maximum performance capability about million instructions second (MIPS) with average about MIPS.
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system interface (SIF) performs interfacing subsystem host system. This interface require additional logic depending application. system interface transfer information data using these three methods:
Direct memory access (DMA) Direct input output (DIO) Pseudo-direct memory access (PDMA)
PDMA) used transfer data from host memory from local memory. main uses loading software local memory initializing TI380C30. also allows command status interrupts occur from TI380C30. system interface hardware selected either modes using mode selected determines memory organizations control signals used. These modes are:
Intel mode (80x8x families): 16-, 32-bit devices Motorola mode (68xxx microprocessor family): 32-bit devices
system interface supports host-system memory addressing bits (32-bit reach into host system memory). This allows greater flexibility using accessing host-system memory. System designers allowed customize system interface their particular
Programmable burst transfers cycle-steal operations Optional parity protection
These features implemented hardware reduce system overhead, facilitate automatic rearbitration after burst, repeat cycle when errors occur (parity bus). retries also supported. system-interface hardware also includes features enhance integrity TI380C30 operation data. These features include following:
Always internally maintain odd-byte parity regardless parity being disabled Monitor presence clock failure Provide switchable speeds 2MHz 33MHz
every cycle, system interface compares system clocks reference clock. clocks become invalid, TI380C30 enters slow-clock mode which prevents latch-up TI380C30. SBCLK invalid, cycle terminated immediately; otherwise, cycle completed TI380C30 placed slow-clock mode.
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system interface (SIF) (continued) When TI380C30 enters slow-clock mode, clock that failed replaced slow free-running clock, device placed into low-power reset state. When failed clock(s) return valid operation, TI380C30 must reinitialized. with 16-MHz clock, continuous transfer rate Mbps MBps) obtained. with 25-MHz clock, continuous transfer rate Mbps MBps) obtained. with 33-MHz clock, continuous transfer rate Mbps 16MBps) obtained. 8-bit 16-bit pseudo-DMA, following data rates obtained:
LOCAL SPEED 8-BIT PDMA Mbps Mbps 16-BIT PDMA Mbps Mbps
Since main purpose downloading initialization, transfer rate significant issue.
performs memory management allow TI380C30 address Mbytes local memory. Hardware allows TI380C30 directly connected DRAMs without additional circuitry. This glueless-DRAM connection includes DRAM refresh controller. also handles internal arbitration between these blocks. When required, arbitrates external bus. responsible memory mapping task. memory DRAMs, EPROMs, burned-in addresses (BIA), external devices appropriately addressed when required system interface, protocol handler when required transfer. memory interface capable 64-Mbps continuous transfer rate when using 4-MHz local (64-MHz device crystal) 96-Mbps continuous transfer rate when using 6-MHz local bus. protocol handler (PH) performs hardware-based real-time protocol functions token-ring LAN. Network type determined TEST0 TEST2. Token-ring network determined software either Mbps Mbps. These speeds fixed software hardware. converts parallel-transmit data serial-network data appropriate coding converts received serial data parallel data. data-management state machines direct transmission/ reception data from local memory through MIF. buffer-management state machines automatically oversee this process, directly sending receiving linked lists frames without intervention. contains many state machines that provide following features:
Transmit receive frames Capture tokens Provide token-priority controls Manage TI380C30 buffer memory Provide frame-address recognition (group, specific, functional, multicast) Provide internal parity protection Control verify physical-layer circuitry-interface signals
Integrity transmitted received data assured cyclic-redundancy checks (CRC), detection network-data violations, parity internal data paths. data paths registers optionally parity protected assure functional integrity.
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memory interface (MIF)
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
adapter-support function (ASF) performs support functions contained other blocks. features are:
TI380C30 base timer Identification, management, service internal external interrupts Test-pin mode control, including unit-in-place mode board testing Checks illegal states, such illegal opcodes parity
clock generator (CG) performs generation internal clocks required other functional blocks, including local memory-bus clocks (MBCLK1, MBCLK2). also generates reference timer used sample input clocks (SBCLK, OSCIN, RCLK, PXTALIN). transition detected within period reference timer input clock signal, places TI380C30 into slow-clock mode. frequency reference timer range kHz.
physical-layer interface (PHY)
major blocks TI380C30 include receiver equalizer, clock recovery PLL, wrap function, phantom drive with wire-fault detector, watchdog timer. Figure block diagram illustrating these major blocks, functionality each block described following sections.
External Equalizer XTAL Receiver Data Receiver Clock Recovery PXTAL RCVR RCLK OSC32 FRAQ REDY DRVR+ DRVR- XMT+ Transmit XMT- WFLT PHOUTA Phantom Drive PHOUTB Error Rate Watchdog Timer Test Port RATER NSRT (internal)
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WRAP
ATEST
FRAQ
NABL
RCV+ RCV-
PWRDN
Bias
IREF
TLCK
TRST
Figure Functional Block Diagram
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receiver Figure shows arrangement line-receiver equalizer circuit. differential-input pair, RCV+ RCV-, designed connected floating winding isolation transformer. Each equipped with bias circuit center operating point differential input approximately differential-input pair consists pair MOSFETs, each with identical current source source terminal that supply nominal current signal levels, gain this pair inversely proportional impedance connected between their sources frequency-equalization network connected between provide equalization media-signal distortion. internal-wrap mode provided self test device. When selected taking WRAP low, normal input path disabled multiplexer path enabled from DRVR+ DRVR- input pair. Receiver gain, thresholds, equalization unchanged internal-wrap mode.
LOAD
LOAD
RCV+ Bias Network RCV- WRAP
DATA External Equalizer
DATA
WRAP IEQB From DRVR+ DRVR- IEQB
Figure Line Receiver Equalizer receiver-clock recovery clock data recovery TI380C30 performed advanced, digitally controlled phase-locked loop. contrast TMS38054, TI380C30 digitally controlled loop parameters internally programmed digital constants. This results precise control loop parameters requires external loop-filter components. TI380C30 implements intelligent algorithm determine optimum phase position data sampling extracted-clock synthesis. resulting action TI380C30 modeled cascaded PLLs shown Figure
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receiver-clock recovery (continued)
PLL1
PLL2 RCLK
Data RCVR
f3dB
f3dB
NOTE f3dB bandwidth
Figure Dual Arrangement
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PLL1 represents algorithm recover data from incoming stream detected receiver. relatively high bandwidth provide good jitter tolerance. Data embedded-clock-phase information digital values PLL2 that generates extracted clock (RCLK) commprocessor. recovered data sent commprocessor RCVR signal synchronously with RCLK. addition sampling RCVR signal, commprocessor uses RCLK retransmit data most cases. lower bandwidth PLL2 greatly reduces rate accumulation data-correlated phase jitter token-ring network provides very good accumulated-phase-slope (APS) characteristics. addition RCLK, token-ring reference clock (PXTAL) fixed-frequency 32-MHz clock (OSC32) also synthesized from 8-MHz crystal reference. line driver wrap function line-drive function TI380C30 performed XMT+ XMT-. Unlike TMS38054, these pins low-impedance outputs require external-series resistance provide line termination. These pins provide buffering differential signal from DRVR+/ DRVR- with action control skew asymmetry, with retiming transmit path. wrap function designed provide signal path system self-test diagnostics. When drives WRAP low, receiver inputs ignored transmit signal receiver input circuitry multiplexer. internal wrap mode, WRAP checked observing signal amplitude equalization pins, Equalization active this signal level, although signal does exhibit high-frequency attenuation effects which equalization intended compensate. During wrap mode, both XMT+ XMT- driven state prevent current flowing isolation transformer. phantom driver wire-fault detection phantom-drive circuit under control NSRT generates voltage both phantom-drive outputs, PHOUTA PHOUTB. order maintain phantom drive, NSRT toggled TI380C30 least once every watchdog timer included TI380C30 remove phantom drive NSRT does have required transitions. watchdog timer normally allowed expire because being reinitialized least every there problem TI380C30 microcode resulting failure toggle NSRT, timer expires maximum this happens, phantom drive deasserted remains until next falling edge NSRT. watchdog timer requires external-timing components. When phantom drive deasserted, phantom-drive lines actively pulled low, reaching level less within
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phantom driver wire-fault detection (continued) voltage from PHOUTA PHOUTB superimposed transmit-signal pair trunk-coupling unit (TCU) request that station inserted into ring. This achieved connecting transmit-signal pair center secondary winding transmit-isolation transformer. Since PHOUTA PHOUTB connected media side isolation transformer, they require extensive protection against line surges. capacitor connected between phantom lines provide path transmit signal, while PHOUTA PHOUTB independently drive voltage each transmit lines allowing independent wire-fault detection each. phantom voltage detected TCU, causing external wrap path from transmitter outputs back receiver inputs broken ring broken. signal connection established from ring receiver inputs from transmitter outputs ring. return current from dc-phantom voltage transmit pair returned station receive pair. This provides some measure wire-fault detection receive lines. phantom-drive outputs current limited prevent damage short circuited. They detect either abnormally high abnormally load current either output corresponding short open circuit ring wiring. Either type fault results wire-fault indicator output (WFLT) driven low. logic state WFLT high when phantom drive active. frequency acquisition REDY Unlike predecessors, TMS3805x family, data-recovery TI380C30 physical layer does require constant frequency monitoring; neither necessary recenter frequency FRAQ control line. When commprocessor asserts FRAQ, initiates reset clock-recovery PLL. REDY signal deasserted duration this action reasserted when complete maximum later). This low-going transition REDY required commprocessor following setting FRAQ high indicate that frequency error that could have detected been corrected. power-down control TI380C30 physical-layer interface disabled PWRDN signal. PWRDN taken low, outputs physical-layer interface high-impedance state internal logic powered down, bringing power consumption very level. Upon removing PWRDN, device resets initializes itself. This process could take care should taken ensure that system does require stable clocks during this period.
user-accessible hardware registers TI380C30-internal pointers
tables following pages show access internal data pointers address registers host interface. SIFACL register, which directly controls device operation, described detail. adapter-internal pointers table defined only after TI380C30 initialization until OPEN command issued. These pointers defined TI380C30 software (microcode), this table describes release software.
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Adapter-Internal Pointers Token Ring
ADDRESS 00.FFF8 00.FFFA 01.0A00 01.0A02 01.0A04 DESCRIPTION Pointer software microcode level chapter Pointer starting location copyright notices. Copyright notices separated character terminated character chapter Pointer burned-in address chapter Pointer software level chapter Pointer TI380C30 addresses chapter Pointer node address Pointer group address Pointer functional address Pointer TI380C30 parameters chapter Pointer physical-drop number Pointer upstream neighbor address Pointer upstream physical-drop number Pointer last ring-poll address Pointer reserved Pointer transmit access priority Pointer source class authorization Pointer last attention code Pointer source address last received frame Pointer last beacon type Pointer last major vector Pointer ring status Pointer soft-error timer value Pointer ring-interface error counter Pointer local ring number Pointer monitor error code Pointer last beacon-transmit type Pointer last beacon-receive type Pointer last MAC-frame correlator Pointer last beaconing-station Pointer reserved Pointer last beaconing-station physical-drop number Pointer buffer special buffer used software transmit adapter-generated frames) chapter Pointer counters chapter Pointer MAX_SAPs Pointer open SAPs Pointer MAX_STATIONs Pointer open stations Pointer available stations Pointer reserved Pointer 16-Mbps word flag. zero, adapter Mbps. nonzero, adapter Mbps.
01.0A06
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01.0A08 01.0A0A
01.0A0C 01.0A0E
Pointer total TI380C30 found bytes allocation test chapter This table describes pointers release TI380C30 software. This address valid only microcode release
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User-Access Hardware Registers
80x8x 16-BIT MODE: SHALT WORD TRANSFERS SBHE SRS2 SIFDAT SIFDAT SIFADR SIFCMD SIFACL SIFADR SIFADX DMALEN NORMAL MODE SBHE SRS2 SBHE SRS2 SIFDAT SIFDAT SIFADR SIFSTS SIFACL SIFADR SIFADX DMALEN PSEUDO-DMA MODE ACTIVE SBHE SRS2 SBHE SRS2 SDMADAT DMALEN SDMAADR SDMAADX SIFACL SIFADR SIFADX DMALEN SBHE SRS2 SDMADAT DMALEN SDMAADR SDMAADX SIFACL SIFADR SIFADX DMALEN
BYTE TRANSFERS SRSX SRS0 SRS1
SBHE SRS2 defined 80x8x 8-BIT MODE: SHALT SRSX SRS0 SRS1 SRS2 NORMAL MODE SBHE SIFDAT SIFDAT SIFDAT SIFDAT SIFADR SIFADR SIFSTS SIFCMD SIFACL SIFACL SIFADR SIFADR SIFADX SIFADX DMALEN DMALEN PSEUDO-DMA MODE ACTIVE SBHE SDMADAT SDMADAT DMALEN DMALEN SDMAADR SDMAADR SDMAADX SDMAADX SIFACL SIFACL SIFADR SIFADR SIFADX SIFADX DMALEN DMALEN
68xxx MODE: WORD TRANSFERS SUDS SLDS SIFDAT SIFDAT SIFADR SIFCMD SIFACL SIFADR SIFADX DMALEN NORMAL MODE SUDS SLDS SUDS SLDS SIFDAT SIFDAT SIFADR SIFSTS SIFACL SIFADR SIFADX DMALEN PSEUDO-DMA MODE ACTIVE SUDS SLDS SUDS SLDS SDMADAT DMALEN SDMAADR SDMAADX SIFACL SIFADR SIFADX DMALEN SUDS SLDS SDMADAT DMALEN SDMAADR SDMAADX SIFACL SIFADR SIFADX DMALEN
BYTE TRANSFERS SRSX SRS0 SRS1
68xxx mode always bit.
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adapter-control register (SIFACL)
SIFACL register allows host processor control some extent reconfigure TI380C30 under software control. SIFACL Register
SWHLDA
SWDDIR
SWHRQ
PSDMAEN
ARESET
CPHALT
BOOT
SINTEN
NSEL OUT0
NSEL OUT1
Legend:
Read Write Write during ARESET only only Value after reset Value BTSTRP Value PRTYEN Indeterminate
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Bits
Value TEST0 TEST2 pins These bits read only reflect value corresponding device pins. This allows host determine speed configuration. network speed type software configurable, these bits used determine which configurations supported network hardware.
TEST0 TEST1 TEST2 Description 16-Mbps token ring 4-Mbps token ring Reserved
Reserved. Read data indeterminate. SWHLDA Software-Hold Acknowledge Allows function SHLDA SBGR emulated from software control pseudo-DMA mode.
PSDMAEN SWHLDA SWHRQ RESULT SWHLDA value SIFACL register cannot one. pseudo-DMA request pending Indicates pseudo-DMA request interrupt Pseudo-DMA process progress
value SHLDA SBGR ignored.
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adapter-control register (SIFACL) (continued)
SWDDIR Current SDDIR-Signal Value Contains current value pseudo-DMA direction. This enables host easily determine direction transfers, which allows system controlled system software. Pseudo from host system TI380C30 Pseudo from TI380C30 host system SWHRQ Current SHRQ-Signal Value Contains current value SHRQ SBRQ when Intel mode inverse value SHRQ/ SBRQ Motorola mode. This enables host easily determine pseudo-DMA transfer requested. INTEL MODE System requested System requested PSDMAEN Pseudo-System-DMA Enable Enables pseudo-DMA operation Normal bus-master operation possible. Pseudo-DMA operation selected. Operation dependent values SWHLDA SWHRQ bits SIFACL register. ARESET Adapter Reset hardware reset TI380C30. This same effect SRESET except that interface SIFACL register maintained. This clock failure detected (OSCIN, PXTALIN, RCLK, SBCLK valid). TI380C30 operates normally. TI380C30 held reset condition. CPHALT Communications-Processor Halt Controls TI380C30 processor access internal TI380C30 buses. This prevents TI380C30 from executing instructions before microcode downloaded. TI380C30 processor access internal TI380C30 buses. TI380C30 processor cannot access internal-adapter buses. BOOT Bootstrap Code Indicates whether memory chapters local-memory space ROM/ PROM/ EPROM. This controls operation MCAS MROMEN. ROM/ PROM/ EPROM memory chapters memory chapters MOTOROLA MODE System requested System requested
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adapter-control register (SIFACL) (continued)
Local-Bus Priority Controls priority levels devices local bus. external devices (such TI380FPA) used with TI380C30. external device (such TI380FPA) used with TI380C30. This allows external master operate necessary priority local bus. system uses TMS380SRA only, must system uses both TMS380SRA TI380FPA, must SINTEN System-Interrupt Enable Allows host processor enable disable system-interrupt requests from TI380C30. system-interrupt request from TI380C30 SINTR SIRQ. following equation shows SINTR SIRQ driven. table details results states. SINTR/ SIRQ (PSDMAEN SWHRQ !SWHLDA) (SINTEN SYSTEM_INTERRUPT)
PSDMAEN SWHRQ SWHLDA SINTEN SYSTEM INTERRUPT (SIFSTS REGISTER) Pseudo active. TI380C30 generated system interrupt pseudo DMA. pseudo-DMA interrupt TI380C30 generates system interrupt. TI380C30 does generate system interrupt. TI380C30 cannot generate system interrupt.
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RESULT
value SHLDA SBGR ignored.
Parity Enable Determines whether data transfers within TI380C30 checked parity. Data transfers checked parity. Data transfers checked correct parity. NSELOUT0, NSELOUT0 Network-Selection Outputs Values control NSELOUT0 NSELOUT1. These bits modified only while ARESET set. These bits used software configure TI380C30: NSELOUT0 should connected TEST0 (TEST1 should left unconnected TEST2 should tied high). NSELOUT0 NSELOUT1 used select network speed shown table below:
NSELOUT0 NSELOUT1 SELECTION Reserved 16-Mbps token ring Reserved 4-Mbps token ring
power these bits corresponding 16-Mbps token ring (NSELOUT1 NSELOUT0
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SIFACL control pseudo-DMA operation
Pseudo operation software controlled using five bits SIFACL register. logic model SIFACL-register control pseudo-DMA operation shown Figure
Internal Signals
Motorola Mode
Host Interface SINTR SIRQ
SYSTEM_INTERRUPT (SIFSTS register)
Request
SHRQ SBRQ
Grant
DMADIR SWHLDA SWDDIR SWHRQ PSDMAEN SINTEN
SDDIR
SIFACL Register
Figure Pseudo-DMA Logic Related SIFACL Bits
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SHLDA SBGR
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, (see Note Input voltage range (see Note Output voltage range Power dissipation 1.25 Operating free-air temperature range, 70°C Maximum case temperature, 95°C Storage temperature range, Tstg 65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTE Voltage values with respect VSS, pins should routed minimize inductance system ground.
recommended operating conditions
Supply voltage TTL-level signal High-level input voltage Low-level input voltage, TTL-level signal (see Note High-level output current High-level output current (see Note Operating free-air temperature outputs outputs OSCIN RCLK, PXTAL, RCVR 4.75 5.25 UNIT
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NOTES: algebraic convention, where more negative (less positive) limit designated minimum, used logic-voltage levels only. Output current sufficient drive five low-power Schottky loads advanced low-power Schottky loads (worst case).
electrical characteristics over recommended ranges supply voltage operating free-air temperature (unless otherwise noted)
PARAMETER High-level output voltage, TTL-level signal (see Note Low-level output voltage, TTL-level signal High impedance output current High-impedance Input current, input input output Supply current Input capacitance, input Normal mode Power-down mode TEST CONDITIONS MIN, MIN, MAX, MAX, Others UNIT
MHz,
Output capacitance, output input output MHz, Others conditions shown MAX, appropriate value specified under recommended operating conditions. NOTE following signals require external pullup resistor: SRAS SAS, SRDY SDTACK, SUDS, SLDS, EXTINT0 EXTINT3, MBRQ.
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electrical characteristics over recommended ranges supply voltage operating free-air temperature (unless otherwise noted) (continued)
receiver input (RCV+ RCV-)
PARAMETER Vr(CM) Vf(CM) Receiver-input bias voltage Rising-input threshold voltage Falling-input threshold voltage Asymmetry threshold voltage, Rising-input common-mode rejection (@VSB (@VSB Falling-input common-mode rejection (@VSB (@VSB Note VICM VSB, Rtst Notes Figure VICM VSB, Rtst Notes Figure VICM VSB, Rtst Notes Figure Notes Figure Notes Figure Both inputs VSB, Note Figure Input under test Other input Notes Figure Rtst Input under test Other input Note IEQB Equalizer bias current RCV+ RCV- RCV- RCV+ Figure TEST CONDITIONS UNIT
II(RCVR)
Receiver input current
VEQW Equalizer wrap voltage WRAP low, Figure NOTES: self-bias voltage input pair RCV+ RCV-. defined (VSB+ +VSB (where VSB+ self-bias voltage RCV+; self-bias voltage RCV-). self-bias voltage both pins approximately VICM common-mode voltage applied RCV+ RCV-.
phantom driver (PHOUTA PHOUTB)
PARAMETER IOZH IOZL High-level High level output voltage Short-circuit output current Low-level output current Off-state output current with high-level voltage applied Off-state output current with low-level voltage applied TEST CONDITIONS UNIT
wire fault WFLT (see Notes
PARAMETER Phantom load resistance detected short circuit Phantom load resistance detected open circuit 0.15 UNIT
Phantom load resistance dectected normal NOTES: wire-fault circuit recognizes fault condition phantom-drive load resistance ground greater than load resistance less than RLS. resistance range specified recognized wire fault. fault condition either PHOUTA PHOUTB results WFLT signal being asserted (low). Resistor (RLS, RLO, RLN) connected from output under test ground, other output loaded with ground.
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electrical characteristics over recommended ranges supply voltage operating free-air temperature (unless otherwise noted) (continued)
characteristics
PARAMETER VFILT Reference operating filter voltage TEST CONDITIONS tc(XT1) UNIT
crystal-oscillator characteristics
PARAMETER VSB(XT1) IOH(XT2) IOL(XT2) Input self-bias voltage Output high-level current Output low-level current V(XT2) VSB(XT1) V(XT1) VSB(XT1) V(XT2) VSB(XT1) V(XT1) VSB(XT1) TEST CONDITIONS UNIT
timing parameters
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timing parameters signals TI380C30 shown following tables illustrated accompanying figures. purpose these figures tables quantify timing relationships among various signals. parameters numbered convenience. static signals following table lists signals that allowed change dynamically therefore have timing associated with them. They should strapped high, low, left unconnected required.
SIGNAL CLKDIV BTSTRP PRTYEN TEST0 TEST1 TEST2 TEST3 TEST4 Reserved Default-bootstrap mode (RAM ROM) Default-parity select (enabled disabled) Test indicates network type Test indicates network type Test manufacturing test Test manufacturing test FUNCTION Host-processor select (Intel Motorola)
TEST5 Test manufacturing test unit-in-place test
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timing parameter symbology Some timing parameter symbols have been created accordance with JEDEC Standard 100-A. shorten symbols, some signal names other related terminology have been abbreviated shown below:
DRVR DRVR OSCIN SBCLK SRESET VDDL,
Lower-case subscripts defined follows:
cycle time delay time hold time pulse duration (width) rise time skew setup time transition time
following additional letters phrases defined follows:
Valid Falling edge Rising edge longer high longer
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High
High impedance
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
PARAMETER MEASUREMENT INFORMATION
Outputs driven minimum high-logic level maximum low-logic level These levels compatible with devices. Output transition times specified follows: high-to-low transition either input output signal, level which signal said longer high level which signal said low-to-high transition, level which signal said longer level which signal said high shown below. rise fall times specified assumed those standard devices, which typically
(high) (low)
test measurement
test-load circuit shown Figure represents programmable load tester electronics that used verify timing parameters TI380C30 output signals.
Test Point VLOAD Test Point Test Point TTL-OUTPUT TEST LOAD XMT+ XMT- TEST LOAD IEQB VLOAD VEQW XMT- XMT+
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Output Under Test
Iref TEST CIRCUIT Where: VLOAD typical dc-level verification typical timing verification
EQUALIZER TEST CIRCUIT
Figure Test Load Circuits
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switching characteristics over recommended range supply voltage (unless otherwise noted)
transmitter-drive characteristics
PARAMETER TEST CONDITIONS 4.75 Figures 5.25 Figures 10.3 UNIT
VPP(XMT) XMT+ XMT- peak peak voltage (see Note peak-to-peak
NOTE VPP(XMT) determined VOH(XMT+) VOH(XMT-) VOL(XMT+) VOL(XMT-)
transmitter switching characteristics (see Figures
PARAMETER XMT+/XMT- XMT+/XMT skew (see Note XMT+/XMT asymmetry (see Note XMT+/XMT- TEST CONDITIONS tsk(DRV) tsk(DRV) tsk(DRV) tsk(DRV) td(XMT- td(XMT+ td(XMT- UNIT
NOTES: XMT+/XMT- skew determined td(XMT+ XMT+/XMT- asymmetry determined d(XMT d(XMT d(XMT- d(XMT-
DRVR+
0.45 0.45 tsk(DRV) tsk(DRV) VOH(XMT+) V50(XMT+) VOL(XMT+) td(XMT+L) td(XMT+H) VOH(XMT-) V50(XMT-) VOL(XMT-) td(XMT- td(XMT-
DRVR-
XMT+
XMT-
Figure Transmitter Timing
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timing requirements over recommended range supply voltage, tc(XT1) (see Figure
TEST CONDITIONS tc(XT1) tw(OSC32H) tw(OSC32L) tw(PXTALL) (PXTALL) tw(PXTALH) (PXTALH) tw(RCLKL) (RCLKL) tw(RCLKH) (RCLKH) tsu(RCVR) th(RCVR) Cycle time clock applied Pulse duration, OSC32 high Pulse duration, OSC32 Pulse duration, PXTAL duration Pulse duration, PXTAL high duration Pulse duration RCLK duration, Pulse duration, RCLK high duration Setup time, RCVR valid RCLK rising edge Hold time, RCVR valid after RCLK rising edge tw(PXTALH) tw(PXTALL) PXTAL 16-Mbps mode 4-Mbps mode 16-Mbps mode 4-Mbps mode 16-Mbps mode 4-Mbps mode 16-Mbps mode 4-Mbps mode 16-Mbps mode 16-Mbps mode UNIT
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tw(OSC32H) tw(OSC32L) OSC32
tw(RCLKH) tw(RCLKL) RCLK tsu(RCVR) th(RCVR) RCVR
Figure PXTAL, RCLK, RCVR Timing
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TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
power SBCLK, OSCIN, MBCLK1, MBCLK2, SYNCIN, SRESET timing
tr(VDD) td(VDDH-SCKV) td(VDDH-OSCV) tc(SCK) tw(SCKH) tw(SCKL) tt(SCK) tc(OSC) tw(OSCH) Rise time, minimum VDD-high level Delay time, minimum VDD-high level first valid SBCLK longer high Delay time, minimum VDD-high level first valid OSCIN high Cycle time, SBCLK (see Note Pulse duration, SBCLK high Pulse duration, SBCLK Transition time, SBCLK Cycle time, OSCIN (see Note OSCIN Pulse duration, OSCIN high (see Note OSCIN OSCIN OSCIN tw(OSCL) tt(OSC) td(OSCV-CKV) th(VDDH-RSL) tw(RSH) tw(RSL) tsu(RST) th(RST) Pulse duration, OSCIN (see Note Transition time, OSCIN Delay time, OSCIN valid MBCLK1 MBCLK2 valid Hold time, SRESET after reaches minimum high level Pulse duration, SRESET high Pulse duration, SRESET Setup time, size SRESET high (Intel mode only) Hold time, size from SRESET high (Intel mode only) CLKDIV One-eighth local-memory cycle CLKDIV 2tc(OSC) 2tc(OSC) OSCIN OSCIN OSCIN 30.3 UNIT
This specification provided board design. assured during manufacturing testing. parameter cannot met, parameter must extended larger difference: real value parameter minus value listed. NOTES: SBCLK value between MHz. This data sheet describes system interface timing parameters cases SBCLK MHz. value OSCIN ±1%, OSCIN used generate PXTALIN, OSCIN tolerance must 0.01%. This assure duty-cycle crystal, provided that OSCIN meets recommended operating conditions
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ADVANCE INFORMATION
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
Minimum VDD-High Level SBCLK
OSCIN
MBCLK1 MBCLK2
ADVANCE INFORMATION
SRESET SHALT
NOTE represent information illustration, nonactual phase timebase characteristics shown. Refer specified parameters precise information.
Figure Timing Power System Clocks, SYNCIN, SRESET
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TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
memory-bus timing: local-memory clocks, MAL, MROMEN, MBIAEN, NMI, MRESET, ADDRESS
cycle time one-eighth local-memory cycle (31.25 minimum 4-MHz local 20.83 minimum 6-MHz local bus).
Period MBCLK1 MBCLK2 Pulse duration, clock high Pulse duration, clock Hold time, MBCLK2 after MBCLK1 high Hold time, MBCLK1 high after MBCLK2 high Hold time, MBCLK2 high after MBCLK1 Hold time, MBCLK1 after MBCLK2 Setup time, address enable MAX0, MAX2, MROMEN before MBCLK1 longer high Setup time, address MADL0 MADL7, MAXPH, MAXPL before MBCLK1 longer high Setup time, address MADH0 MADH7 before MBCLK1 longer high Setup time, high before MBCLK1 longer high Setup time, address MAX0, MAX2, MROMEN before MBCLK1 longer Setup time, column address MADL0 MADL7, MAXPH, MAXPL before MBCLK1 longer Setup time, status MADH0 MADH7 before MBCLK1 longer Setup time, valid before MBCLK1 Hold time, valid after MBCLK1 Delay time, MBCLK1 longer MRESET valid Hold time, column address status after MBCLK1 longer Reference Periods Periods Periods 0.5tM 0.5tM 0.5tM Periods UNIT Periods
OSCIN (when CLKDIV OSCIN (when CLKDIV
OSCOUT
MBCLK1
MBCLK2 MBCLK1 MBCLK2 have timing relationship OSCOUT. MBCLK1 MBCLK2 start OSCIN rising edge, depending when memory cycle starts execution.
Figure Clock Waveforms After Clock Stabilization
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ADVANCE INFORMATION
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
MBCLK1 MBCLK2 MAX0, MAX2, MROMEN MAXPH, MAXPL, MADL0 MADL7 MADH0 MADH7 Valid MRESET Valid Address Status Address
ADVANCE INFORMATION
Figure Memory-Bus Timing: Local-Memory Clocks, MAL, MROMEN, MBIAEN, NMI, MRESET, ADDRESS
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TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
memory-bus timing: clocks, MRAS, MCAS, ADDRESS
cycle time one-eighth local-memory cycle (31.25 minimum 4-MHz local 20.83 minimum 6-MHz local bus).
Setup time, address MADL0 MADL7, MAXPH, MAXPL before MRAS longer high Hold time, address MADL0 MADL7, MAXPH, MAXPL after MRAS longer high Delay time, MRAS longer high MRAS longer high next memory cycle Pulse duration, MRAS Pulse duration, MRAS high Setup time, column address (MADL0 MADL7, MAXPH, MAXPL) status (MADH0 MADH7) before MCAS longer high Hold time, column address (MADL0 MADL7, MAXPH, MAXPL) status (MADH0 MADH7) after MCAS Hold time, column address (MADL0 MADL7, MAXPH, MAXPL) status (MADH0 MADH7) after MRAS longer high Pulse duration, MCAS Pulse duration, MCAS high, refresh cycle follows read write cycle Hold time, address MAXL0 MAXL7, MAXPH, MAXPL after Setup time, address MAXL0 MAXL7, MAXPH, MAXPL before longer high Pulse duration, high Setup time, address enable MAX0, MAX2, MROMEN before longer high Hold time, address enable MAX0, MAX2, MROMEN after Setup time, address MADH0 MADH7 before longer high Hold time, address MADH0 MADH7 after 1.5tM 11.5 4.5tM 3.5tM 0.5tM 2.5tM 1.5tM 1.5tM 1.5tM UNIT
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ADVANCE INFORMATION
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
MAXPH, MAXPL, MADL0 MADL7
Column
Column
MRAS
MCAS MAX0, MAX2, MROMEN MADH0 MADH7 Address Status Address Address
ADVANCE INFORMATION
Status
Figure Memory-Bus Timing: Clocks, MRAS, MCAS, ADDRESS
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TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
memory-bus timing: read cycle
cycle time one-eighth local-memory cycle (31.25 minimum 4-MHz local 20.83 minimum 6-MHz local bus).
Access time, address enable valid MAX0, MAX2, MROMEN valid data parity Access time, address valid MAXPH, MAXPL, MADH0 MADH7, MADL0 MADL7 valid data parity Access time, MRAS valid data parity Hold time, valid data parity after MRAS longer Hold time, address high-impedance state MAXPH, MAXPL, MADH0 MADH7 MADL0 MADL7 after MRAS high (see Note Access time, MCAS valid data parity Hold time, valid data parity after MCAS longer Hold time, address high-impedance state MAXPH, MAXPL, MADH0 MADH7, MADL0 MADL7 after MCAS high (see Note Delay time, MCAS longer high Setup time, address status high-impedance state MAXPH, MAXPL, MADL0 MADL7, MADH0 MADH7 before longer high Access time, valid data parity Pulse duration, Delay time, MCAS longer Hold time, valid data parity after longer Hold time, address high-impedance state MAXPH, MAXPL, MADH0 MADH7, MADL0 MADL7 after high (see Note Setup time, address status high-impedance state MAXPH, MAXPL, MADL0 MADL7, MADH0 MADH7, before MBEN longer high Setup time, address status high-impedance state MAXPH, MAXPL, MADL0 MADL7, MADH0 MADH7 before MBIAEN longer high Access time, MBEN valid data parity Access time, MBIAEN valid data parity Pulse duration, MBEN Pulse duration, MBIAEN Hold time, valid data parity after MBEN longer Hold time, valid data parity after MBIAEN longer Hold time, address high-impedance state MAXPH, MAXPL, MADH0 MADH7, MADL0 MADL7 after MBEN high (see Note Hold time, address high-impedance state MAXPH, MAXPL, MADH0 MADH7, MADL0 MADL7 after MBIAEN high Hold time, MDDIR high after MBEN high, read follows write cycle Setup time, MDDIR before MBEN longer high 1.5tM 10.5 4.5tM 21.5 UNIT
Hold time, MDDIR after MBEN high, write follows read cycle This specification been characterized meet stated value. assured during manufacturing testing. NOTE data parity that exists address lines will most likely reach high-impedance state sometime later than rising edge MRAS, MCAS, MOE, MBEN (between timing parameter will function memory being read. time given represents time from rising edge MRAS, MCAS, MOE, MBEN beginning next address, does represent actual high-impedance period address bus.
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ADVANCE INFORMATION
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
MAX0, MAX2, MROMEN
Address Enable
Address Data Parity Address
MAXPH, MAXPL, MADH0 MADH7, MADL0 MADL7
Address
Address Status
MRAS
MCAS
ADVANCE INFORMATION
MBIAEN MDDIR MBEN
Figure Memory-Bus Timing: Read Cycle
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TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
memory-bus timing: write cycle
cycle time one-eighth local-memory cycle (31.25 minimum 4-MHz local 20.83 minimum 6-MHz local bus).
Setup time, before MRAS longer Setup time, before MCAS longer Setup time, valid data parity before longer high Pulse duration, Hold time, data parity valid after high Setup time, address valid MAX0, MAX2, MROMEN before longer Hold time, MRAS longer Hold time, MCAS longer Setup time, MBEN before longer high Hold time, MBEN after high Setup time, MDDIR high before MBEN longer high Hold time, MDDIR high after MBEN high MAX0, MAX2, MROMEN MAXPH, MAXPL, MADH0 MADH7, MADL0 MADL7 1.5tM 2.5tM 0.5tM 10.5 -11.5 5.5tM -11.5 1.5tM 13.5 0.5tM 1.5tM UNIT
Address Enable
Address
Address
Data Parity
MRAS
MCAS MBEN MDDIR
Figure Memory-Bus Timing: Write Cycle
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TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
memory-bus timing: DRAM-refresh timing
cycle time one-eighth local-memory cycle (31.25 minimum 4-MHz local 20.83 minimum 6-MHz local bus).
Setup time, address MADL0 MADL7, MAXPH, MAXPL before MRAS longer high Hold time, address MADL0 MADL7, MAXPH, MAXPL after MRAS longer high Pulse duration, MRAS Pulse duration, MRAS high Setup time, MCAS before MRAS longer high Hold time, MCAS after MRAS Setup time, MREF high before MCAS longer high Hold time, MREF high after MCAS high 1.5tM 11.5 4.5tM 3.5tM 1.5tM -11.5 4.5tM UNIT
MADL0 MADL7
Refresh Address
Address
ADVANCE INFORMATION
MRAS MCAS MREF
Figure Memory-Bus Timing: DRAM-Refresh Cycle
XMATCH XFAIL timing
cycle time one-eighth local-memory cycle (31.25 minimum 4-MHz local 20.83 minimum 6-MHz local bus).
Delay time, status high XMATCH XFAIL recognized Pulse duration, XMATCH XFAIL high UNIT
MADH7
Status
XMATCH, XFAIL
Figure XMATCH XFAIL Timing
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TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
token ring: ring-interface timing
154L 154H 158L 158H Period RCLK (see Note Pulse duration RCLK duration, Pulse duration, RCLK high duration Mbps Mbps Mbps nominal: 62.5 Mbps nominal: 15.625 Mbps nominal: 62.5 Mbps nominal: 15.625 31.25 0.01 31.25 UNIT
Setup time, RCVR valid before rising edge (1.8 RCLK Mbps Hold time, RCVR valid after rising edge (1.8 RCLK Mbps Pulse duration, ring-baud clock duration ring baud Pulse duration, ring-baud clock high duration ring baud Period OSCOUT PXTALIN (see Note Tolerance PXTALIN input frequency (see Note Mbps Mbps Mbps Mbps Mbps Mbps (for PXTALIN only)
NOTE This parameter tested required IEEE 802.5 specification.
154H
RCLK 154L RCVR Valid
158H 158L OSCOUT, PXTALIN
Figure Ring-Interface Timing
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TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
token ring: transmitter timing
tsk(DR) td(DR)H td(DR)L td(DRN)H t(DRN)L DRVR DRVR asymmetry Delay time, DRVR rising edge (1.8 DRVR falling edge DRVR falling edge DRVR rising edge (1.8 Delay time, RCLK PXTALIN) falling edge DRVR rising edge (1.8 Delay time, RCLK PXTALIN) falling edge DRVR falling edge Delay time, RCLK PXTALIN) falling edge DRVR falling edge Delay time, RCLK PXTALIN) falling edge DRVR rising edge (1.8 d(DR)L Note Note Note Note ±1.5 UNIT
d(DRN)H
d(DR)H
d(DRN)L
When active-monitor mode, clock source PXTALIN; otherwise, clock-source either RCLK PXTALIN. NOTE This parameter tested minimum maximum measured used component required parameter 164.
RCLK PXTALIN
ADVANCE INFORMATION
DRVR
DRVR
Figure Skew Asymmetry From RCLK PXTALIN DRVR DRVR
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TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
80x8x read-cycle timing
261a 266a 272a 273a 282a 282R 283R Delay time, SRDY either high Pulse duration, SRAS high Hold time, high-impedance state after (see Note Setup time, SADH0 SADH7, SADL0 SADL7, SPH, valid before SRDY Delay time, high high-impedance state (see Note Hold time, output data valid after high (see Note Setup time, SRSX, SRS0 SRS2, SCS, SBHE valid SRAS longer high (see Note Hold time, SRSX, SRS0 SRS2, SCS, SBHE valid after SRAS Setup time, SRAS high longer high (see Note Setup time, SRSX, SRS0 SRS2 valid before longer high (see Note Hold time, SRSX, SRS0 SRS2 valid after longer (see Note Setup time, SRD, SWR, SIACK high from previous cycle longer high Hold time, SRD, SWR, SIACK high after high Delay time, SWR, high SRDY high (see Note Delay time, SWR, high SRDY high-impedance state Delay time, SDBEN SRDY read cycle Delay time, SDBEN (see TMS380 Second Generation Token-Ring User's Guide, SPWU005, subsection 3.4.1.1.1), provided previous cycle completed Delay time, high SDBEN high (see Note Pulse duration, high between accesses (see Note tc(SCK) tc(SCK) tc(SCK) tc(SCK) tc(SCK) tc(SCK) tc(SCK) 25-MHz OPERATION tc(SCK) tc(SCK) tc(SCK) tc(SCK) tc(SCK) tc(SCK) tc(SCK) 33-MHz OPERATION UNIT
This specification provided board design. assured during manufacturing testing. later that indicates start cycle. NOTES: inactive chip select SIACK DIO-read DIO-write cycles, inactive chip select interrupt-acknowledge cycles. 80x8x mode, SRAS used strobe values SBHE, SRSX, SRS0 SRS2, SCS. When used SRAS must meet parameter 266a, SBHE, SRS0 SRS2, must meet parameter 264. SRAS strapped high, parameters 266a irrelevant parameter must met.
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TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
SCS, SRSX, SRS0 SRS2, SBHE
Valid
Valid
SRAS 266a
SIACK
272a 273a
272a 272a High SDDIR 282R 283R SDBEN 261a Output Data Valid
273a
ADVANCE INFORMATION
273a
282a SRDY Hi-Z SADH0 SADH7, SADL0 SADL7, SPH, Hi-Z
Hi-Z
Hi-Z
80x8x mode, SRAS used strobe values SBHE, SRSX, SRS0 SRS2, SCS. When used SRAS must meet parameter 266a; SBHE, SRS0 SRS2, must meet parameter 264. SRAS strapped high, parameters 266a irrelevant parameter must met. When TMS380C25 begins drive SDBEN inactive, already latched write data internally. Parameter must input data buffers. 8-bit 80x8x mode reads, SADH0 SADH7 contain don't-care data.
Figure 80x8x Read-Cycle Timing
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TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
80x8x write-cycle timing
266a 272a 273a Delay time, SRDY either high Pulse duration, SRAS high Setup time, SADH0 SADH7, SADL0 SADL7, SPH, valid before longer Hold time, SADH0 SADH7, SADL0 SADL7, SPH, valid after high Setup time, SRSX, SRS0 SRS2, SCS, SBHE SRAS longer high (see Note Hold time, SRSX, SRS0 SRS2, SCS, SBHE after SRAS Setup time, SRAS high longer high (see Note Setup time, SRSX, SRS0 SRS2 before longer high (see Note Hold time, SRSX, SRS0 SRS2 valid after longer (see Note Setup time, SRD, SWR, SIACK high from previous cycle longer high Hold time, SRD, SWR, SIACK high after high Delay time, SRDY first access register SRDY immediately following access (see TMS380 Second-Generation Token-Ring User's Guide, SPWU005, subsection 3.4.1.1.1) Delay time, high SRDY high (see Note Delay time, high SRDY high-impedance state Delay time, SDDIR (see Note Delay time, SDBEN SRDY (see TMS380 Second Generation Token-Ring User's Guide, SPWU005, subsection 3.4.1.1.1) Delay time, SDDIR SDBEN Delay time, high SDBEN longer Pulse duration, high between accesses (see Note register ready waiting required) register ready (waiting required) 25-MHz OPERATION tc(SCK) tc(SCK) 4000 33-MHz OPERATION tc(SCK) tc(SCK) 4000 UNIT
tc(SCK) tc(SCK) tc(SCK)
tc(SCK) tc(SCK) tc(SCK)
282b
4000 tc(SCK) tc(SCK) 4000 tc(SCK) tc(SCK)
282W 283W
tc(SCK) tc(SCK) later that indicates start cycle. This specification been characterized meet stated value. assured during manufacturing testing. This specification provided board design. assured during manufacturing testing. NOTES: inactive chip select SIACK DIO-read DIO-write cycles; inactive chip select interrupt-acknowledge cycles. 80x8x mode, SRAS used strobe values SBHE, SRSX, SRS0 SRS2, SCS. When used SRAS must meet parameter 266a; SBHE, SRS0 SRS2, must meet parameter 264. SRAS strapped high, parameters 266a irrelevant parameter must met.
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TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
SCS, SRSX, SRS0 SRS2, SBHE
Valid
SRAS
SIACK
266a 272a 273a
272a
273a 273a
272a
ADVANCE INFORMATION
SDDIR 282W SDBEN 282b Hi-Z SADH0 SADH7, SADL0 SADL7, Hi-Z Hi-Z Data SPH, When TMS380C25 begins drive SDBEN inactive, already latched write data internally. Parameter must input data buffers. 8-bit 80x8x-mode writes, value placed SADH0 SADH7 don't care. Hi-Z 283W
SRDY
Figure 80x8x Write-Cycle Timing
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TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
80x8x interrupt-acknowledge-cycle timing: first SIACK pulse
Pulse duration, SIACK high between accesses (see Note Pulse duration, SIACK first pulse pulses 25-MHz OPERATION tc(SCK) tc(SCK) 33-MHz OPERATION tc(SCK) tc(SCK) UNIT
NOTE inactive chip select SIACK DIO-read DIO-write cycles, inactive chip select interrupt-acknowledge cycles. SRD, SWR, SIACK First Second
Figure 80x8x Interrupt-Acknowledge-Cycle Timing: First SIACK Pulse
80x8x interrupt-acknowledge-cycle timing: second SIACK pulse
261a 272a 273a 282a 282R Delay time, SRDY high Hold time, high-impedance state after SIACK (see Note Setup time, output data valid before SRDY Delay time, SIACK high high-impedance state (see Note Hold time, output data valid after SIACK high (see Note Setup time, inactive data strobe high SIACK longer high Hold time, inactive data strobe high after SIACK high Delay time, SIACK high SRDY high (see Note Delay time, SRDY first access register SRDY immediately following access Delay time, SIACK high SRDY high-impedance state Delay time, SDBEN SRDY read cycle Delay time, SIACK SDBEN (see TMS380 Second Generation Token-Ring User's Guide, SPWU005, subsection 3.4.1.1.1), provided previous cycle completed tc(SCK) tc(SCK) 4000 tc(SCK) tc(SCK) tc(SCK) 25-MHz OPERATION tc(SCK) tc(SCK) 4000 tc(SCK) tc(SCK) tc(SCK) 33-MHz OPERATION UNIT
283R Delay time, SIACK high SDBEN high (see Note tc(SCK) tc(SCK) This specification provided board design. assured during manufacturing. This specification been characterized meet stated value. assured during manufacturing. NOTE inactive chip select SIACK DIO-read DIO-write cycles; inactive chip select interrupt-acknowledge cycles.
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TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
SCS, SRSX, SRS0 SRS2, SBHE
Only needs inactive. others don't care.
SIACK 272a 272a 272a SDDIR High 282R 283R SDBEN SRDY 282a Hi-Z 261a Hi-Z Hi-Z 273a 273a 273a
ADVANCE INFORMATION
SADH0 SADH7, Output Data Valid Hi-Z SADL0 SADL7, SPH, SRDY active-low ready signal. must asserted before data output. 8-bit 80x8x-mode writes, value placed SADH0 SADH7 don't care.
Figure 80x8x Interrupt-Acknowledge-Cycle Timing: Second SIACK Pulse
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TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
80x8x-mode bus-arbitration timing, takes control
Setup time, asynchronous signal SBBSY SHLDA before SBCLK longer high assure recognition that cycle Hold time, asynchronous signal SBBSY SHLDA after SBCLK assure recognition that cycle Delay time, SBCLK SADH0 SADH7, SADL0 SADL7, SPH, valid Delay time, SBCLK cycle SOWN Delay time, SBCLK cycle SDDIR read Delay time, SBCLK high SHRQ high Delay time, SBCLK high cycle high, acquisition Hold time, high-impedance state after SOWN low, acquisition tc(SCK) 25-MHz OPERATION 208a 208b 224a 224c 241a tc(SCK) 33-MHz OPERATION UNIT
This specification been characterized meet stated value. assured during manufacturing testing.
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ADVANCE INFORMATION
User Master Inputs: SBCLK 208a SBBSY, SHLDA Outputs: SHRQ
SRD, 241a SBHE SADH0 SADH7, SADL0 SADL7, SPH, Address Valid 224c Write SDDIR Read 224a SOWN While system interface controls active (i.e., SOWN asserted), input disabled.
Figure 80x8x-Mode Bus-Arbitration Timing, Takes Control
ADVANCE INFORMATION
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL LAYER INTERFACE
Exchange
Master
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Template Release Date: 7-11-94
208b
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
80x8x-mode read-cycle timing
Setup time, SADL0 SADL7, SADH0 SADH7, SPH, valid before SBCLK cycle longer high Hold time, SADL0 SADL7, SADH0 SADH7, SPH, valid after SBCLK cycle parameters 207a 207b Hold time, SADL0 SADL7, SADH0 SADH7, SPH, valid after high Hold time, SADL0 SADL7, SADH0 SADH7, SPH, valid after SDBEN longer Setup time, asynchronous signal SRDY before SBCLK longer high assure recognition this cycle Hold time, asynchronous signal SRDY after SBCLK assure recognition this cycle Delay time, SBCLK address valid Delay time, SBCLK cycle SADH0 SADH7, SADL0 SADL7, SPH, high-impedance state Delay time, SBCLK high SALE SXAL high Hold time, SALE SXAL after high Delay time, SBCLK high SXAL cycle SALE cycle Hold time, SADH0 SADH7, SADL0 SADL7, SPH, valid after SALE SXAL Delay time, SBCLK cycle high (see Note Delay time, SBCLK cycle SDBEN high Delay time, SADH0 SADH7, SADL0 SADL7, SPH, high-impedance state Delay time, SBCLK cycle Hold time, SADH0 SADH7, SADL0 SADL7, SPH, high-impedance state after SBCLK cycle Pulse duration, Setup time, SADH0 SADH7, SADL0 SADL7, SPH, valid before SALE, SXAL longer high Delay time, SBCLK high cyle SDBEN Setup time, data valid before SRDY parameter 208a 2tc(SCK) tw(SCKH) tc(SCK) 2tc(SCK) 25-MHz OPERATION 33-MHz OPERATION UNIT
207a 207b
208a
216a 223R 225R 227R 237R
tw(SCKH)
tc(SCK)
This specification been characterized meet stated value. assured during manufacturing testing. NOTE While system-interface controls active (i.e., SOWN asserted), disabled.
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ADVANCE INFORMATION
208b
SBCLK
SRAS SBHE
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SXAL
SALE SADH0-SADH7, SADL0-SADL7, SPH, Address Extended Address 208a SRDY 208b 225R 207b Data 207a Address
SDBEN SDDIR
8-bit 80x8x mode, SBHE SRNW don't care input during inactive (high) output during DMA. Motorola-style slaves hold SDTACK active until master deasserts SAS. 8-bit 80x8x mode, most significant byte address maintained SADH address maintained according parameter 221; i.e., held after high. parameter 208A met, then valid data must present before SRDY goes low.
Figure 80x8x-Mode Read-Cycle Timing
ADVANCE INFORMATION
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL LAYER INTERFACE
TWAIT
Template Release Date: 7-11-94
Hi-Z
Valid High 227R 223R
216a
237R
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
80x8x-mode write-cycle timing
Setup time, asynchronous signal SRDY before SBCLK longer high assure recognition that cycle Hold time, asynchronous signal SRDY after SBCLK assure recognition that cycle Delay time, SBCLK SADH0 SADH7, SADL0 SADL7, SPH, valid Delay time, SBCLK high SALE SXAL high Hold time, SALE SXAL after high Delay time, SBCLK high SXAL cycle SALE cycle Hold time, address valid after SALE, SXAL Delay time, SBCLK cycle output data parity valid Hold time, SADH0 SADH7, SADL0 SADL7, SPH, valid after high Delay time, SBCLK high Delay time, SBCLK high cycle SDBEN high Hold time, SDBEN after SWR, SUDS, SLDS high Delay time, SBCLK cycle Setup time, SADH0 SADH7, SADL0 SADL7, SPH, valid before SALE, SXAL longer high Delay time, SBCLK high cycle SDBEN tc(SCK) tc(SCK) tc(SCK) tw(SCKH) tc(SCK) tc(SCK) 25-MHz OPERATION 33-MHz OPERATION UNIT
208a
208b 216a 223W 225W 225WH 227W 237W
tw(SCKH) tc(SCK)
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HOUSTON, TEXAS 77251-1443
ADVANCE INFORMATION
SBCLK
SBHE Valid
227W
POST OFFICE 1443 HOUSTON, TEXAS 77251-1443
SXAL 216a SALE SADL0 SADH7, SADH0 SADL7, SPH, SRDY 237W SDBEN 208b 225WH 225W Address Extended Address 208a Output Data
SDDIR
8-bit 80x8x mode, SBHE SRNW don't care input during inactive (high) output during DMA. 8-bit 80x8x mode, most significant byte address maintained SADH address maintained according parameter 221; i.e., held after high. cycle-steal mode, state present every system transfer. burst mode, state present first transfer whenever increment address register carries beyond least significant bits.
Figure 80x8x-Mode Write-Cycle Timing
ADVANCE INFORMATION
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL LAYER INTERFACE
TWAIT
Template Release Date: 7-11-94
High 223W
High
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
80x8x-mode bus-arbitration timing, returns control
Delay time, SBCLK cycle SADH0 SADH7, SADL0 SADL7, SPL, SPH, SRD, high-impedance state Delay time, SBCLK cycle SBHE high-impedance state Delay time, SBCLK cycle SOWN high Delay time, SBCLK cycle SDDIR high Delay time, SBCLK high cycle SHRQ Setup time, SRD, SWR, SBHE high-impedance state before SOWN longer 25-MHz OPERATION 223b 224b 224d 33-MHz OPERATION UNIT
This specification been characterized meet stated value. assured during manufacturing testing.
Master SBCLK
Exchange (T1)
User Master (T2)
SHLDA Outputs: SHRQ SRD, 223b SBHE SADH0 SADH7, SADL0 SADL7, SPH, SDDIR Read 224b SOWN 80x8x mode, system interface deasserts SHRQ rising edge SBCLK following state last system transfer controls. 68xxx mode, system interface deasserts SBRQ rising edge SBCLK state first system bus-transfer controls. While system-interface controls active (i.e., SOWN asserted), disabled. 224d Write Hi-Z Hi-Z Hi-Z
Figure 80x8x-Mode Bus-Arbitration Timing, Returns Control
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
ADVANCE INFORMATION
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
80x8x-mode bus-release timing
Setup time, asynchronous input SBRLS before SBCLK longer high assure recognition Hold time, asynchronous input SBRLS after SBCLK assure recognition Hold time, SBRLS after SOWN high 25-MHz OPERATION 208a 208b 208c 33-MHz OPERATION UNIT
SBCLK 208a SBRLS
208b
ADVANCE INFORMATION
SOWN 208c Unless otherwise specified, signals specified maximum delay from SBCLK transition signal valid, signal also specified hold previous value (including high impedance) until start that SBCLK transition. system interface ignores assertion SBRLS does system bus. does bus, when detects assertion SBRLS, completes internally started cycle relinquishes control bus. transfer started internally, system interface releases before starting another.
Figure 80x8x-Mode Bus-Release Timing
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
68xxx read-cycle timing
Delay time, SDTACK either SCS, SUDS, SLDS high Hold time, high-impedance state after SUDS SLDS (see Note Setup time, SADH0 SADH7, SADL0 SADL7, SPH, valid before SDTACK Delay time, SCS, SUDS, SLDS high SADH0 SADH7, SADL0 SADL7, SPH, high-impedance state (see Note Hold time, output data valid after SUDS SLDS longer (see Note Setup time, register address before SUDS SLDS longer high (see Note Hold time, register address valid after SUDS SLDS longer (see Note Setup time, SRNW before SUDS SLDS longer high (see Note Hold time, SRNW after SUDS SLDS high Hold time, SIACK high after SUDS SLDS high Delay time, SCS, SUDS, SLDS high SDTACK high (see Note Delay time, SDTACK first access register SDTACK immediately following access Delay time, SUDS SLDS high SDTACK high-impedance state Delay time, SDBEN SDTACK Delay time, SUDS SLDS SDBEN (see TMS380 Second Generation Token-Ring User's Guide, SPWU005, subsection 3.4.1.1.1), provided previous cycle completed Delay time, SUDS SLDS high SDBEN high (see Note Pulse duration, SUDS SLDS high between accesses (see Note tc(SCK) tc(SCK) 4000 tc(SCK) tc(SCK) tc(SCK) tc(SCK) tc(SCK) 25-MHz OPERATION 33-MHz OPERATION UNIT
261a 273a 282a 282R 283R
tc(SCK) 4000 tc(SCK) tc(SCK) tc(SCK) tc(SCK)
This specification provided board design. assured during manufacturing testing. This specification been characterized meet stated value. assured during manufacturing testing. NOTES: inactive chip select SIACK DIO-read DIO-write cycles, inactive chip select interrupt-acknowledge cycles. 80x8x mode, SRAS used strobe values SBHE, SRSX, SRS0 SRS2, SCS. When used SRAS must meet parameter 266a, SBHE, SRS0 SRS2, must meet parameter 264. SRAS strapped high, parameters 266a irrelevant parameter must met.
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
ADVANCE INFORMATION
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
SCS, SRSX, SRS0, SRS1 SIACK
Valid
273a SRNW SUDS, SLDS SDDIR High 282R 283R SDBEN SDTACK Hi-Z 282a 261a SADH0 SADH7, SADL0 SADL7, Output Data Valid Hi-Z SPH, SDTACK active-low bus-ready signal. must asserted before data output. Hi-Z Hi-Z
ADVANCE INFORMATION
Figure 68xxx Read-Cycle Timing
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
68xxx write-cycle timing
272a 273a Delay time, SDTACK either SCS, SUDS SLDS high Setup time, write data valid before SUDS SLDS longer Hold time, write data valid after SUDS SLDS high Setup time, register address before SUDS SLDS longer high (see Note Hold time, register address valid after SUDS SLDS longer (see Note Setup time, SRNW before SUDS SLDS longer high (see Note Setup time, inactive SUDS SLDS high active data strobe longer high Hold time, SRNW after SUDS SLDS high Hold time, inactive SUDS SLDS high after active data strobe high Delay time, SCS, SUDS SLDS high SDTACK high (see Note Delay time, SDTACK first access register SDTACK immediately following access Delay time, SUDS SLDS high SDTACK high-impedance state Delay time, SUDS SLDS SDDIR (see Note Delay time, SDBEN SDTACK (see TMS380 Second Generation TokenRing User's Guide, SPWU005, subsection 3.4.1.1.1) Delay time, SDDIR SDBEN Delay time, SUDS SLDS high SDBEN longer Pulse duration, SUDS SLDS high between accesses (see Note register ready waiting required) register ready (waiting required) 25-MHz OPERATION tc(SCK) tc(SCK) 4000 tc(SCK) tc(SCK) tc(SCK) 33-MHz OPERATION tc(SCK) tc(SCK) 4000 tc(SCK) tc(SCK) tc(SCK) tc(SCK) 4000 tc(SCK) tc(SCK) tc(SCK) 4000 tc(SCK) tc(SCK) UNIT
282b
282W 283W
later that indicates start cycle. This specification been characterized meet stated value. assured during manufacturing testing. This specification provided board design. assured during manufacturing testing. NOTES: inactive chip select SIACK DIO-read DIO-write cycles, inactive chip select interrupt-acknowledge cycles. 80x8x mode, SRAS used strobe values SBHE, SRSX, SRS0 SRS2, SCS. When used SRAS must meet parameter 266a, SBHE, SRS0 SRS2, must meet parameter 264. SRAS strapped high, parameters 266a irrelevant parameter must met.
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
ADVANCE INFORMATION
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
SRSX, SRS0, SRS1 SIACK SRNW 272a SUDS, SLDS
Valid
273a
273a SDDIR High 282W SDBEN SDTACK Hi-Z 282b Hi-Z 283W
ADVANCE INFORMATION
SADH0 SADH7, SADL0 SADL7, Hi-Z Data Hi-Z SPH, 68xxx mode, skew between SLDS SUDS must exceed Provided this limitation observed, events referenced data strobe edge later occurring edge. Events defined data strobes, edges, such parameter 286, measured between latest earlier edges. When TMS380C25 begins drive SDBEN inactive, already latched write data internally. Parameter must input data buffers. SDTACK active-low ready signal. must asserted before data output.
Figure 68xxx Write-Cycle Timing
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
68xxx interrupt-acknowledge-cycle timing
261a 272a 273a 282a 282R 283R Delay time, SDTACK either SUDS, SIACK high Hold time, high-impedance state after SIACK longer high (see Note Setup time, output data valid before SDTACK longer high Delay time, SIACK high high-impedance state (see Note Hold time, output data valid after SIACK longer (see Note Setup time, register address before SIACK longer high (see Note Setup time, inactive high SIACK active data strobe longer high Hold time, inactive SRNW high after active data strobe high Delay time, SRNW high SDTACK high (see Note Delay time, SDTACK first access register SDTACK immediately following access Delay time, SIACK high SDTACK high-impedance state Delay time, SDBEN SDTACK read cycle Delay time, SIACK SDBEN (see TMS380 Second Generation Token-Ring User's Guide, SPWU005, subsection 3.4.1.1.1), provided previous cycle completed Delay time, SIACK high SDBEN high (see Note Pulse duration, SIACK high between accesses (see Note tc(SCK) tc(SCK) 25-MHz OPERATION tc(SCK) tc(SCK) 33-MHz OPERATION UNIT 4000 tc(SCK) tc(SCK) tc(SCK)
4000 tc(SCK) tc(SCK) tc(SCK)
tc(SCK) tc(SCK) tc(SCK) tc(SCK) This specification provided board design. assured during manufacturing testing. This specification been characterized meet stated value. assured during manufacturing testing. later that indicates start cycle. NOTE inactive chip select SIACK DIO-read DIO-write cycles, inactive chip select interrupt-acknowledge cycles.
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
ADVANCE INFORMATION
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
SCS, SRSX, SRS0, SRS1, SBHE
Only needs Inactive. others don't care.
SIACK 272a SRNW 273a SLDS SDDIR High 282R 283R SDBEN 282a SDTACK SADH0 SADH7, SADL0 SADL7, SPH, Hi-Z 261a Hi-Z Output Data Valid Hi-Z Hi-Z
ADVANCE INFORMATION
SDTACK active-low ready signal. must asserted before data output. Internal logic drives SDTACK high verifies that reached valid-high level before making 3-state signal.
Figure 68xxx Interrupt-Acknowledge-Cycle Timing
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
68xxx-mode bus-arbitration timing, takes control
Setup time, asynchronous input SBGR before SBCLK longer high assure recognition this cycle Hold time, asynchronous input SBGR after SBCLK assure recognition this cycle Delay time, SBCLK address valid Delay time, SBCLK cycle SOWN (see Note Delay time, SBCLK cycle SDDIR read Delay time, SBCLK high either SHRQ SBRQ high Delay time, SBCLK high cycle SUDS SLDS high Hold time, SUDS, SLDS, SRNW, high-impedance state after SOWN low, aquisition tc(SCK-15) 25-MHz OPERATION 208a 208b 224a 224c 241a tc(SCK-15) 33-MHz OPERATION UNIT
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ADVANCE INFORMATION
This specification been characterized meet stated value. assured during manufacturing testing. NOTE Motorola-style slaves hold SDTACK active until master deasserts SAS.
User Master Inputs: SBCLK
SBGR
SBERR, SDTACK, SBBSY Outputs: SBRQ
POST OFFICE 1443 HOUSTON, TEXAS 77251-1443
208a SAS, SLDS, SUDS
SRNW Write SADH0 SADH7, SADL0 SADL7, SPH, SDDIR Read 224a SOWN 241a Hi-Z 224c Write
80x8x mode, system interface deasserts SHRQ rising edge SBCLK following state last system-bus transfer controls. 68xxx mode, system interface deasserts SBRQ rising edge SBCLK state first system-bus transfer controls. While system-interface controls active (i.e., SOWN asserted), input disabled.
Figure 68xxx-Mode Bus-Arbitration Timing, Takes Control
ADVANCE INFORMATION
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL LAYER INTERFACE
Exchange
Master
Template Release Date: 7-11-94
208b 208a
208b Input
Output Read
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
68xxx-mode read-cycle timing
207a 207b Setup time, input data valid before SBCLK cycle longer high Hold time, input data valid after SBCLK cycle parameters 207a 207b Hold time, input data valid after data strobe longer Hold time, input data valid after SDBEN longer Setup time, asynchronous input SDTACK before SBCLK longer high assure recognition this cycle Hold time, asynchronous input SDTACK after SBCLK assure recognition this cycle Pulse duration, SAS, SUDS, SLDS high Delay time, SBCLK high cycle SUDS SLDS active Delay time, SBCLK address valid Delay time, SBCLK cycle high impedance Delay time, SBCLK high SALE SXAL high Hold time, SALE SXAL after SUDS high Delay time, SBCLK high SXAL cycle SALE cycle Hold time, address valid after SALE, SXAL Delay time, SBCLK high Delay time, SBCLK cycle SUDS, SLDS, high (see Note Delay time, SBCLK cycle SDBEN high Hold time, high-impedance state after SBCLK cycle Setup time, address valid before SALE SXAL longer high Setup time, address valid before longer high Delay time, SBCLK high cycle SDBEN Setup time, data valid before SDTACK parameter 208a tw(SCKL) tw(SCKH) tc(SCK) tw(SCKL) 25-MHz OPERATION 33-MHz OPERATION UNIT
208a
208b 216a 223R 225R 233a 237R
tc(SCK)+ tw(SCKL)
tc(SCK)+ tw(SCKL) tw(SCKH) tc(SCK)
This specification been characterized meet stated value. assured during manufacturing testing. NOTE While system-interface controls active (i.e., SOWN asserted), disabled.
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
ADVANCE INFORMATION
SBCLK SUDS, SLDS High SRNW SXAL SALE SADL0 SADH7, SADH0 SADL7, SPH, SDTACK 208b SDDIR 237R SDBEN 225R Address Extended Address 208a 233a 207a Data Hi-Z 207b 216a
POST OFFICE 1443 HOUSTON, TEXAS 77251-1443
read cycle, read strobe remains active until internal sample incoming data completed. Input data removed when either read strobe SDBEN becomes longer active. parameter 208a met, then valid data must present before SDTACK goes low. Motorola-style slaves hold SDTACK active until master deasserts SAS. pins should routed minimize inductance system ground.
Figure 68xxx-Mode Read-Cycle Timing
ADVANCE INFORMATION
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL LAYER INTERFACE
TWAIT
Template Release Date: 7-11-94
223R
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
68xxx-mode write-cycle timing
Setup time, asynchronous input SDTACK before SBCLK longer high assure recognition this cycle Hold time, asynchronous input SDTACK after SBCLK assure recognition this cycle Pulse duration, SAS, SUDS, SLDS high Delay time, SBCLK high cycle SUDS SLDS active Delay time, output data valid SUDS SLDS longer high Delay time, SBCLK address valid Delay time, SBCLK high SALE SXAL high Hold time, SALE SXAL after SUDS high Delay time, SBCLK high SXAL cycle SALE cycle Hold time, address valid after SALE, SXAL Delay time, SBCLK cycle output data parity valid Hold time, output data, parity valid after SUDS SLDS high Delay time, SBCLK high Delay time, SBCLK SUDS, SLDS, high Delay time, SBCLK high cycle SDBEN high Hold time, SDBEN after SUDS SLDS high Setup time, address valid before SALE SXAL longer high Setup time, address valid before longer high Delay time, SBCLK high cycle SDBEN tc(SCK) tw(SCKL) tc(SCK) tc(SCK) tw(SCKL) tw(SCKH) tc(SCK) tc(SCK) tw(SCKL) tw(SCKH) tc(SCK) 25-MHz OPERATION 33-MHz OPERATION UNIT
208a
208b 211a 216a 223W 225W 225WH 233a 237W
tc(SCK)+ tw(SCKL)
tc(SCK)+ tw(SCKL) tw(SCKL)
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
ADVANCE INFORMATION
SBCLK
233a SUDS, SLDS SRNW SXAL SALE SADL0 SADH7, SADH0 SADL7, SPL, Extended Address SDTACK Address Output Data 208a
POST OFFICE 1443 HOUSTON, TEXAS 77251-1443
SDDIR SDBEN
terminals should routed minimize inductance system ground. read cycle, read strobe remains active until internal sample incoming data completed. Input data removed when either read strobe SDBEN becomes longer active. cycle-steal mode, state present every system transfer. burst mode, state present first transfer whenever increment address register carries beyond least significant bits.
Figure 68xxx-Mode Write-Cycle Timing
ADVANCE INFORMATION
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL LAYER INTERFACE
TWAIT
211a 208b 237W
Template Release Date: 7-11-94
223W
216a
225W 225WH
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
68xxx-mode bus-arbitration timing, returns control
Delay time, SBCLK cycle SAD, SPL, SPH, SUDS, SLDS high-impedance state, release Delay time, SBCLK cycle SBHE/SRNW high-impedance state Delay time, SBCLK cycle SOWN high Delay time, SBCLK cycle SDDIR high Delay time, SBCLK high either SHRQ SBRQ high Setup from, SUDS, SLDS, SRNW, control signals high-impedance state before SOWN longer 25-MHz OPERATION 223b 224b 224d 25-MHz OPERATION UNIT
This specification been characterized meet stated value. assured during manufacturing testing.
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
ADVANCE INFORMATION
Master Inputs: SBCLK
SBGR
SDTACK Outputs: SBRQ SAS, SUDS, SLDS 223b Read SRNW Write SADH0 SADH7, SADL0 SADL7, SPH, 224d Write SDDIR Read 224b SOWN 80x8x mode, system interface deasserts SHRQ rising edge SBCLK following state last system-bus transfer controls. 68xxx mode, system interface deasserts SBRQ rising edge SBCLK state first system-bus transfer controls. Hi-Z Hi-Z
POST OFFICE 1443 HOUSTON, TEXAS 77251-1443
Figure 68xxx-Mode Bus-Arbitration Timing, Returns Control
ADVANCE INFORMATION
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL LAYER INTERFACE
Exchange
User
Template Release Date: 7-11-94
TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
68xxx-mode bus-release error timing
208a 208b 208c Setup time, asynchronous input before SBCLK longer high assure recognition Hold time, asynchronous input SBRLS, SOWN, SBERR after SBCLK assure recognition Hold time, SBRLS after SOWN high Setup time, SBERR before SDTACK longer high parameter 208a SBCLK 208a SBRLS 208b 25-MHz OPERATION 33-MHz OPERATION UNIT
SOWN 208a SBERR
208b 208c
SDTACK Unless otherwise specified, signals specified maximum delay from SBCLK transition signal valid, signal also specified hold previous value (including high impedance) until start that SBCLK transition. system interface ignores assertion SBRLS does system bus. does bus, when detects assertion SBRLS, completes internally-started cycle relinquishes control bus. transfer started internally, system interface releases before starting another. SBERR asserted when system interface controls system bus, current transfer completed, regardless value SDTACK. BERETRY register nonzero, cycle retried. BERETRY register zero, system interface then releases control system bus. system interface ignores assertion SBERR performing DMA-bus cycle system bus. When SBERR properly asserted BERETRY zero, however, system interface releases upon completion current transfer halts further system side. error synchronized local stops local sides. value SDMAADR, SDMADDRX
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