NanoStar Package Supports Operation Inputs Accept Voltages Power Consu

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NanoStar Package Supports Operation Inputs Accept Voltages Power Consu

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SN74LVC2G125Q DUAL BUFFER GATE WITH STATE OUTPUTS
NanoStar Package Supports Operation Inputs Accept Voltages Power Consumption, 10-µA ±24-mA Output Drive Typical VOLP (Output Ground Bounce) <0.8 25°C Typical VOHV (Output Undershoot) 25°C Ioff Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds
JESD Class Protection Exceeds JESD 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
PACKAGE (BOTTOM VIEW)
description/ordering information
SN74LVC2G125 dual buffer gate, designed 1.65-V 5.5-V operation. This device features dual line drivers with 3-state outputs. outputs disabled when associated output-enable (OE) input high. NanoStar package technology major breakthrough packaging concepts, using package. ensure high-impedance state during power power down, should tied through pullup resistor; minimum value resistor determined current-sinking capability driver. This device fully specified partial-power-down applications using Ioff. Ioff circuitry disables outputs, preventing damaging current backflow through device when powered down. ORDERING INFORMATION
-40°C 125°C PACKAGE NanoStar WCSP (DSBGA) 0.23-mm Large Bump Reel 3000 ORDERABLE PART NUMBER 1P2G125QYEPR TOP-SIDE MARKING _CM_
Package drawings, standard packing quantities, thermal data, symbolization, design guidelines available www.ti.com/sc/package. YEP: actual top-side marking three preceding characters denote year, month, sequence code, following character designate assembly/test site. identifier indicates solder-bump composition SnPb, Pb-free). FUNCTION TABLE (each buffer) INPUTS OUTPUT
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. NanoStar trademark Texas Instruments.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2003, Texas Instruments Incorporated
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SN74LVC2G125Q DUAL BUFFER GATE WITH STATE OUTPUTS
logic diagram (positive logic)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, -0.5 Input voltage range, (see Note -0.5 Voltage range applied output high-impedance power-off state, (see Note -0.5 Voltage range applied output high state, (see Notes -0.5 Input clamp current, Output clamp current, Continuous output current, Continuous current through ±100 Package thermal impedance, (see Note 102°C/W Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input negative-voltage output voltage ratings exceeded input output current ratings observed. value provided recommended operating conditions table. package thermal impedance calculated accordance with JESD 51-7.
POST OFFICE 655303
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SN74LVC2G125Q DUAL BUFFER GATE WITH STATE OUTPUTS
recommended operating conditions (see Note
Operating Supply voltage Data retention only 1.65 1.95 1.65 1.95 High state Output voltage 3-state 1.65 High-level output current 1.65 Low-level output current 0.15 Input transition rise fall rate 1.65 0.65 0.35 ns/V UNIT
High-level input voltage
Low-level input voltage
Input voltage
Operating free-air temperature NOTE unused inputs device must held ensure proper device operation. Refer application report, Implications Slow Floating CMOS Inputs, literature number SCBA004.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN74LVC2G125Q DUAL BUFFER GATE WITH STATE OUTPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER -100 Ioff Data inputs Control inputs typical values 25°C. inputs GND, input -40°C 25°C 125°C Other inputs TEST CONDITIONS 1.65 1.65 1.65 1.65 1.65 VCC-0.1 0.45 0.55 0.55 UNIT
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure
PARAMETER tdis FROM (INPUT) (OUTPUT) UNIT
operating characteristics,
PARAMETER Outputs enabled Power dissipation capacitance Outputs disabled TEST CONDITIONS UNIT
POST OFFICE 655303
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SN74LVC2G125Q DUAL BUFFER GATE WITH STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
VLOAD Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD
From Output Under Test (see Note
LOAD CIRCUIT
INPUTS tr/tf VCC/2 VLOAD
Timing Input Input VOLTAGE WAVEFORMS PULSE DURATION Input tPLH Output tPHL tPHL tPLH Output VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING NONINVERTING OUTPUTS Output Waveform (see Note Output Control tPZL tPZH VOLTAGE WAVEFORMS SETUP HOLD TIMES tPLZ VLOAD/2 tPHZ Data Input
Output Waveform VLOAD (see Note
VOLTAGE WAVEFORMS ENABLE DISABLE TIMES LOW- HIGH-LEVEL ENABLING
NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with transition measurement. tPLZ tPHZ same tdis. tPZL tPZH same ten. tPLH tPHL same tpd. parameters waveforms applicable devices.
Figure Load Circuit Voltage Waveforms
POST OFFICE 655303
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Feb-2006
PACKAGING INFORMATION
Orderable Device 1P2G125QYEPR
Status ACTIVE
Package Type WCSP
Package Drawing
Pins Package Plan 3000
Lead/Ball Finish SNPB
Peak Temp Level-1-260C-UNLIM
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
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NanoStar Package Supports Operation Inputs Accept Voltages Power Consu

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