Output Ports Have Equivalent Series Resistors, External Resistors Requ

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Output Ports Have Equivalent Series Resistors, External Resistors Requ

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SN54ABT5402A, SN74ABT5402A 12-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS
Output Ports Have Equivalent Series Resistors, External Resistors Required State-of-the-Art EPIC-B BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) 25°C Typical VOLV (Output Undershoot) 25°C Package Options Include Plastic Small-Outline (DW) Package Ceramic Chip Carriers (FK) DIPs (JT)
SN54ABT5402A PACKAGE SN74ABT5402A PACKAGE (TOP VIEW)
description
These 12-bit buffers line drivers designed specifically improve both performance density 3-state memory address drivers, clock drivers, bus-oriented receivers transmitters. 3-state control gate 2-input gate with active-low inputs that either output-enable (OE1 OE2) input high, outputs high-impedance state. outputs, which designed source sink include equivalent series resistors reduce overshoot undershoot. ensure high-impedance state during power power down, should tied through pullup resistor; minimum value resistor determined current-sinking capability driver.
SN54ABT5402A PACKAGE (TOP VIEW)
SN54ABT5402A characterized operation over full military temperature range -55°C 125°C. SN74ABT5402A characterized operation from -40°C 85°C.
FUNCTION TABLE INPUTS OUTPUT
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. EPIC-B trademark Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters. POST OFFICE 655303
DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
SN54ABT5402A, SN74ABT5402A 12-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS
logic symbol
logic diagram (positive logic)
Eleven Other Channels
This symbol accordance with ANSI/IEEE 91-1984 Publication 617-12. numbers shown packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, -0.5 Input voltage range, (see Note -0.5 Voltage range applied output high power-off state, -0.5 Current into output state, Input clamp current, Output clamp current, Package thermal impedance, (see Note package 78°C/W Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output negative-voltage ratings exceeded input output clamp-current ratings observed. package thermal impedance calculated accordance with EIA/JEDEC JESD51.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT5402A, SN74ABT5402A 12-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS
recommended operating conditions (see Note
SN54ABT5402A Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise fall rate Outputs enabled SN74ABT5402A UNIT ns/V
Operating free-air temperature NOTE Unused inputs must held high prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS Vhys IOZH IOZL Ioff ICEX Outputs high Outputs high Outputs Outputs disabled ±100 -100 -200 0.05 -100 -200 0.05 ±100 -100 -200 0.05 3.35 3.85 25°C SN54ABT5402A -1.2 -1.2 3.35 3.85 0.65 SN74ABT5402A -1.2 UNIT
Data inputs Control inputs
Outputs enabled input Other inputs Outputs disabled input Other inputs
typical values more than output should tested time, duration test should exceed second. This increase supply current each input that specified voltage level rather than GND.
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT5402A, SN74ABT5402A 12-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS
switching characteristics over recommended ranges supply voltage operating free-air temperature, (unless otherwise noted) (see Figure
PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) (OUTPUT) 25°C SN54ABT5402A SN74ABT5402A UNIT
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT5402A, SN74ABT5402A 12-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
From Output Under Test (see Note Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Open
LOAD CIRCUIT Timing Input Data Input VOLTAGE WAVEFORMS SETUP HOLD TIMES
Input tPLH Output tPHL tPHL Output tPLH VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING NONINVERTING OUTPUTS
Output Control tPZL Output Waveform (see Note Output Waveform Open (see Note tPZH
tPLZ tPHZ VOLTAGE WAVEFORMS ENABLE DISABLE TIMES LOW- HIGH-LEVEL ENABLING
NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with transition measurement.
Figure Load Circuit Voltage Waveforms
POST OFFICE 655303
DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
6-Jun-2005
PACKAGING INFORMATION
Orderable Device SN74ABT5402ADW SN74ABT5402ADWE4 SN74ABT5402ADWR SN74ABT5402ADWRE4
Status ACTIVE ACTIVE ACTIVE ACTIVE
Package Type SOIC SOIC SOIC SOIC
Package Drawing
Pins Package Plan Green (RoHS Sb/Br) Green (RoHS Sb/Br)
Lead/Ball Finish NIPDAU NIPDAU NIPDAU NIPDAU
Peak Temp Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM
1000 Green (RoHS Sb/Br) 1000 Green (RoHS Sb/Br)
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS) Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
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Output Ports Have Equivalent Series Resistors, External Resistors Requ

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