PCM1720 Stereo Audio DIGITAL-TO-ANALOG CONVERTER MPEG2/AC-3 COMPA

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PCM1720 Stereo Audio DIGITAL-TO-ANALOG CONVERTER MPEG2/AC-3 COMPA

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PCM1720
Stereo Audio DIGITAL-TO-ANALOG CONVERTER MPEG2/AC-3 COMPATIBLE
FEATURES
ACCEPTS 16-, 20-, 24-BIT INPUT DATA COMPLETE STEREO DAC: Includes Digital Filter Output DYNAMIC RANGE: 96dB MULTIPLE SAMPLING FREQUENCIES: 16kHz 96kHz Oversampling Sampling Frequencies SYSTEM CLOCK: 256fS/384fS NORMAL DATA INPUT FORMATS SELECTABLE FUNCTIONS: Soft Mute Digital Attenuator (256 Steps) Digital De-emphasis OUTPUT MODE: Left, Right, Mono, Mute
DESCRIPTION
PCM1720 complete cost stereo audio digital-to-analog converter (DAC), operating 256fS 384fS system clock. contains 3rdorder modulator, digital interpolation filter, analog output amplifier. PCM1720 accept 16-, 20-, 24-bit input data either normal formats. digital filter performs interpolation function includes selectable features such soft mute, digital attenuation digital de-emphasis. PCM1720 accept standard digital audio sampling frequencies well one-half double sampling frequencies. PCM1720 ideal applications which combine compressed audio video data such DVD, DVDROM, set-top boxes MPEG sound cards.
BCKIN LRCIN Serial Input Oversampling Digital Filter with Function Controller
Multi-level Delta-Sigma Modulator
Low-pass Filter
VOUTL
Multi-level Delta-Sigma Modulator Low-pass Filter VOUTR
Mode Control
ZERO BPZ-Cont. Open Drain
RSTB 256fS/384fS Power Supply
SCKI
AGND DGND
International Airport Industrial Park Mailing Address: 11400, Tucson, 85734 Street Address: 6730 Tucson Blvd., Tucson, 85706 Tel: (520) 746-1111 Twx: 910-952-1111 Internet: http://www.burr-brown.com/ FAXLine: (800) 548-6133 (US/Canada Only) Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
1996 Burr-Brown Corporation
PDS-1333B
Printed U.S.A. August, 1996
SBAS052
SPECIFICATIONS
specifications +25°C, +VCC +VDD +5V, 44.1kHz, 16-bit input data, SYSCLK 384fS, unless otherwise noted. PCM1720 PARAMETER RESOLUTION DATA FORMAT Audio Data Format Data Length Sampling Frequency (fS) Standard One-half Double CONDITIONS Standard/I2S 16/20/24 Selectable 44.1 22.05 88.2 256fS/384fS 44.1kHz 96kHz 44.1kHz 96kHz 44.1kHz 96kHz 44.1kHz 96kHz 44.1kHz ±1.0 ±1.0 VOUT VCC/2 Full Scale (0dB) Load 0.445 0.555 ±0.17 11.125/fS -0.2 -0.16 +100 +0.55 0.62 VCC/2 Vp-p UNITS Bits
Internal System Clock Frequency DIGITAL INPUT/OUTPUT LOGIC LEVEL DYNAMIC PERFORMANCE(1) THD+N (0dB) THD+N -60dB Dynamic Range Signal-to-Noise Ratio(2) Channel Separation ACCURACY Gain Error Gain Mismatch, Channel-to-Channel Bipolar Zero Error ANALOG OUTPUT Output Voltage Center Voltage Load Impedance DIGITAL FILTER PERFORMANCE Passband Stopband Passband Ripple Stopband Attenuation Delay Time De-emphasis Error INTERNAL ANALOG FILTER -3dB Bandwidth Passband Response POWER SUPPLY REQUIREMENTS Voltage Range Supply Current: TEMPERATURE RANGE Operation Storage
±5.0 ±5.0
20kHz VDD, 44.1kHz 96kHz
NOTES: Dynamic performance specs tested with 20kHz pass filter THD+N specs tested with 30kHz LPF, 400Hz HPF, Average-Mode. tested with Infinite Zero Detection off.
information provided herein believed reliable; however, BURR-BROWN assumes responsibility inaccuracies omissions. BURR-BROWN assumes responsibility this information, such information shall entirely user's risk. Prices specifications subject change without notice. patent rights licenses circuits described herein implied granted third party. BURR-BROWN does authorize warrant BURR-BROWN product life support devices and/or systems.
PCM1720
CONFIGURATION
VIEW SSOP
ASSIGNMENTS
NAME SCKI TEST RSTB ZERO TYPE FUNCTION Connection. System Clock Input: 256fS 384fS. Reserved Factory Use. Latch Enable Serial Control Data. Clock Serial Control Data. Data Input Serial Control. Reset Input. When this low, digital filters modulators held reset. Zero Data Flag. This when data continuously zero more than 65,535 cycles BCKIN. Right Channel Analog Output. Analog Ground. Analog Power Supply (+5V). Left Channel Analog Output. Common Analog Output Amplifiers. Clock Clocking Audio Data. Serial Audio Data Input. Left/Right Word Clock. Frequency equal Ground. Connection. Digital Power Supply (+5V). Recommended connection analog power supply. Digital Ground. Recommended connection digital ground plane.
SCKI TEST RSTB ZERO VOUTR
DGND LRCIN BCKIN VOUTL
VOUTR AGND VOUTL BCKIN LRCIN DGND
AGND
PACKAGE INFORMATION
PRODUCT PCM1720 PACKAGE 20-Pin SSOP PACKAGE DRAWING NUMBER(1) 334-1
These pins include internal pull-up resistors.
NOTE: detailed drawing dimension table, please data sheet, Appendix Burr-Brown Data Book.
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage +6.5V +VCC +VDD Difference ±0.1V Input Logic Voltage -0.3V (VDD 0.3V) Power Dissipation 300mW Operating Temperature Range -25°C +85°C Storage Temperature -55°C +125°C Lead Temperature (soldering, +260°C Thermal Resistance, +70°C/W
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit damaged ESD. Burr-Brown recommends that integrated circuits handled with appropriate precautions. Failure observe proper handling installation procedures cause damage. damage range from subtle performance degradation complete device failure. Precision integrated circuits more susceptible damage because very small parametric changes could cause device meet published specifications.
PCM1720
TYPICAL PERFORMANCE CURVES
+25°C, +5V, 44.1kHz, 16-bit input data, unless otherwise noted. Measurement bandwidth 20kHz
DYNAMIC PERFORMANCE
THD+N VCC, 96kHz
THD+N TEMPERATURE 96kHz
THD+N -60dB (dB)
THD+N (dB)
THD+N (dB)
44.1kHz
44.1kHz
VCC,
Temperature (°C)
DYNAMIC RANGE VCC,
THD+N DYNAMIC RANGE
Dynamic Range
Dynamic Range
VCC,
44.1 88.2 Sampling Frequency, (kHz)
PCM1720
Dynamic Range (dB)
THD+N
THD+N (dB)
(dB)
TYPICAL PERFORMANCE CURVES
+25°C, +5V, 44.1kHz, fSYS 384fS, 16-bit input data, unless otherwise noted.
DIGITAL FILTER
OVERALL FREQUENCY CHARACTERISTIC
PASSBAND RIPPLE CHARACTERISTIC
-0.2
-0.4
-0.6
-0.8
-100 0.4536fS 1.3605fS 2.2675fS 3.1745fS 4.0815fS Frequency (Hz)
0.1134fS 0.2268fS Frequency (Hz) 0.3402fS 0.4535fS
DE-EMPHASIS FREQUENCY RESPONSE (3kHz) Frequency (Hz) DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz) Frequency (Hz) DE-EMPHASIS FREQUENCY RESPONSE (48kHz) Frequency (Hz) -0.2 -0.4 -0.6
Level (dB)
DE-EMPHASIS ERROR (3kHz) -0.2 -0.4 -0.6 3628 7256 Frequency (Hz) DE-EMPHASIS ERROR (44.1kHz) -0.2 -0.4 -0.6 4999.8375 9999.675 Frequency (Hz) DE-EMPHASIS ERROR (48kHz)
Error (dB) Error (dB) Error (dB)
Level (dB)
10884
14512
Level (dB)
14999.5125
19999.35
5442
10884 Frequency (Hz)
16326
21768
PCM1720
1/fs L_ch LRCIN (pin BCKIN (pin AUDIO DATA WORD 16-BIT (pin R_ch
AUDIO DATA WORD 20-BIT (pin
AUDIO DATA WORD 24-BIT (pin
FIGURE "Normal" Data Input Timing.
1/fs LRCIN (pin BCKIN (pin AUDIO DATA WORD 16-BIT (pin L_ch R_ch
AUDIO DATA WORD 20-BIT (pin
AUDIO DATA WORD 24-BIT (pin
FIGURE "I2S" Data Input Timing.
LRCKIN tBCH BCKIN tBCY tBCL
1.4V
1.4V
1.4V
BCKIN Pulse Cycle Time BCKIN Pulse Width High BCKIN Pulse Width
tBCY tBCH tBCL
100ns (min) 50ns (min) 50ns (min) 30ns (min) 30ns (min) 30ns (min) 30ns (min)
BCKIN Rising Edge LRCIN Edge LRCIN Edge BCKIN Rising Edge Set-up Time Hold Time
FIGURE Audio Data Input Timing.
PCM1720
TYPICAL CONNECTION DIAGRAM Figure illustrates typical connection diagram PCM1720 used stand-alone application. SYSTEM CLOCK system clock PCM1720 must either 256fS 384fS, where audio sampling frequency (LRCIN), typically 32kHz, 44.1kHz 48kHz. system clock used operate digital filter noise shaper. system clock input (SCKI) PCM1720 system clock detection circuit which automatically detects frequency, either 256fS 384fS. system clock should synchronized with LRCIN (pin 16), PCM1720 compensate phase differences. phase difference between LRCIN system clock greater than clocks (BCKIN), synchronization performed automatically. analog outputs forced bipolar zero state (VCC/2) during synchronization function. Table shows typical system clock frequency inputs PCM1720.
SAMPLING RATE (LRCIN) SYSTEM CLOCK FREQUENCY (MHz) 256fS 32kHz 44.1kHz 48kHz 8.192 11.2896 12.288 384fS 12.288 16.9340 18.432
SPECIAL FUNCTIONS PCM1720 includes several special functions, including digital attenuation, digital de-emphasis, soft mute, data format selection input word resolution. These functions controlled using three-wire interface. (pin used program data, (pin used clock program data, (pin used latch program data. Table lists selectable special functions.
FUNCTION Input Audio Data Format Selection Normal Format Format Input Audio Data Selection 16/20/24 Bits Input LRCIN Polarity Selection Lch/Rch High/Low Lch/Rch Low/High De-emphasis Control Soft Mute Control Attenuation Control Lch, Individually Lch, Common Infinite Zero Detection Circuit Control Operation Enable (OPE) Sample Rate Selection Internal System Clock Selection 256fS 384fS Sampling Frequency 44.1kHz Group 48kHz Group 32kHz Group Analog Output Mode Mono, Mute DEFAULT MODE Normal Format
Bits Lch/Rch High/Low Lch, Individually Fixed Enabled
384fS
44.1kHz
TABLE System Clock Frequencies Sampling Rate.
Stereo
TABLE Selectable Functions.
Analog DGND Audio Data Processor 256fS/384fS PCM1720 ZERO BCKIN LRCIN SCKI VOUTR VOUTL 10µF Post Analog Mute Analog Post Analog Mute
Analog
RSTB AGND
STRB SCKO System Controller
Analog
FIGURE Typical Connection Diagram.
PCM1720
MAPPING PROGRAM REGISTERS
REGISTER REGISTER REGISTER REGISTER
PROGRAM REGISTER MAPPING PCM1720's special functions controlled using four program registers which bits long. These registers loaded using After data bits clocked used latch data appropriate register. Table shows complete mapping four registers Figure illustrates data input timing.
REGISTER NAME Register NAME (7:0) (1:0) (7:0) (1:0) (1:0) (3:0) (1:0) (1:0) (1:0) DESCRIPTION Attenuation Data Attenuation Data Load Control Register Address Reserved Attentuation Data Attenuation Data Load Control Register Address Reserved Left Right DACs Soft Mute Control De-emphasis Control Left Right DACs Operation Control Input Audio Data Select Output Mode Select Register Address Reserved Audio Data Format Select Polarity LRCIN (pin Select Attenuator Control System Clock Select Sampling Rate Select Infinite Zero Detection Circuit Control Register Address Reserved
ATTENUATION DATA LOAD CONTROL, (LDL) used simultaneously analog outputs Rch. output level controlled AL[0:7] attenuation data when this When output level controlled remains previous attenuation level. Register equivalent function LDL. When output level left right channel simultaneously controlled. attenuation level given (y/256) (dB), where when when user-determined step number, integer value between 255. Example:
Register
Register
Register
068dB
-48.16dB
TABLE III. Internal Register Mapping. REGISTER
REGISTER
Register used control left channel attenuation. Bits (AL0 AL7) used determine attenuation level. level attenuation given log10 (ATT_DATA/255)]
Register used control right channel attenuation. Register bits (AR0 AR7) control level attenuation.
PCM1720
REGISTER
MUTE
Bits (PL0:3) used control output format. output PCM1720 programmed different states, shown Table VII.
OUTPUT MUTE MUTE MUTE MUTE R)/2 R)/2 R)/2 R)/2 OUTPUT MUTE R)/2 MUTE R)/2 MUTE R)/2 MUTE R)/2 MONO STEREO REVERSE NOTE MUTE
Register used control soft mute, de-emphasis, operation enable, input resolution, output format. used soft mute: "HIGH" level will cause output muted (this ramped down digital domain, "click" audible). used control de-emphasis. "LOW" level disables de-emphasis, while "HIGH" level enables de-emphasis. (OPE) used operational control. Table illustrates features controlled OPE.
DATA INPUT Zero Other Zero Other OUTPUT Forced BPZ(1) Forced BPZ(1) Controlled Normal SOFTWARE MODE INPUT Enabled Enabled Enabled Enabled
TABLE Output Enable (OPE) Function. controls operation DAC: when "LOW", will convert non-zero input data. input data continuously zero cycles BCKIN, output will forced zero only "HIGH". When "HIGH", output will forced bipolar zero, irrespective input data.
DATA INPUT Zero Other Zero Other OUTPUT Forced BPZ(1)
TABLE VII. Programmable Output Format. REGISTER
Normal Zero(2) Normal
Register used control input data format polarity, attenuation channel control, system clock frequency, sampling frequency infinite zero detection. Bits (I2S) (LRP) used control input data format. "LOW" sets format "Normal" (MSB-first, right-justified Japanese format) "HIGH" sets format (Philips serial data protocol). (LRP) used select polarity LRCIN (sample rate clock). When "LOW", left channel data assumed when LRCIN "HIGH" phase right channel data assumed when LRCIN "LOW" phase. When "HIGH", polarity assumption reversed. (ATC) used controlling attenuator. When "HIGH", attenuation data loaded program Register used both left right channels. When "LOW", attenuation data each register applied separately left right channels. Bits (SF0) (SF1) used select sampling frequency:
Sampling Frequency 44.1kHz group 48kHz group 32kHz group Reserved 22.05/44.1/88.2kHz 24/48/96kHz 16/32/64kHz Defined
TABLE Infinite Zero Detection (IZD) Function.
SOFTWARE MODE INPUT Enabled Enabled Disabled Disabled
DATA INPUT RSTB "HIGH" RSTB "LOW" Zero Other Zero Other
OUTPUT Controlled Controlled Forced BPZ(1) Forced BPZ(1)
TABLE Reset (RSTB) Function.
NOTE: disconnected from output amplifier. connected output amplifier.
Bits (IW0) (IW1) used determine input word resolution. PCM1720 input word resolutions bits:
(IW1) (IW0) Input Resolution 16-bit Data Word 20-bit Data Word 24-bit Data Word Reserved
used control infinite zero detection function (IZD).
PCM1720
When "LOW", zero detect circuit off. Under this condition, automatic muting will occur input continuously zero. When "HIGH", zero detect feature enabled. input data continuously zero cycles BCKIN, output will immediately forced bipolar zero state (VCC/2). zero detection
feature used avoid noise which occur when input When output forced bipolar zero, there audible click. PCM1720 allows zero detect feature disabled user implement external muting circuit.
(pin (pin (pin
FIGURE Serial Interface Timing.
tMLS tMCH tMCY tMCL tMLL
tMLH 1.4V
1.4V
tMDS tMDH
1.4V
Pulse Cycle Time Pulse Width Pulse Width HIGH Set-up Time Hold Time Level Time Set-up Time Hold Time
tMCY tMCL tMCH tMDS tMDH tMLL tMLS tMLH
100ns (min) 50ns (min) 50ns (min) 30ns (min) 30ns (min) 30ns 1SYSCLK (min) 30ns (min) 30ns (min)
FIGURE Program Register Input Timing.
PCM1720
APPLICATION CONSIDERATIONS
DELAY TIME There finite delay time delta-sigma converters. converters, this commonly referred latency. delta-sigma converter, delay time determined order number filter stage, chosen sampling rate. following equation expresses delay time PCM1720: 11.125 1/fS 44.1kHz, 11.125/44.1kHz 251.4µs Applications using data from disc tape source, such audio, CD-Interactive, Video DAT, Minidisc, etc., generally affected delay time. some professional applications such broadcast audio studios, important total delay time less than 2ms. OUTPUT FILTERING testing purposes dynamic tests done PCM1720 using 20kHz pass filter. This filter limits measured bandwidth THD+N, etc. 20kHz. Failure such filter will result higher THD+N lower Dynamic Range readings than found specifications. pass filter removes band noise. Although audible, affect dynamic specification numbers. performance internal pass filter from 24kHz shown Figure higher frequency rolloff filter shown Figure user's application PCM1720 driving wideband amplifier, recommended external pass filter. simple 3rdorder filter shown Figure some applications, passive filter 2nd-order filter adequate.
-1.0
INTERNAL ANALOG FILTER FREQUENCY RESPONSE (20Hz~24kHz, Expanded Scale)
-0.5
Frequency (Hz)
FIGURE Pass Filter Frequency Response.
INTERNAL ANALOG FILTER FREQUENCY RESPONSE (10Hz~10MHz) 100k Frequency (Hz)
FIGURE Pass Filter Wideband Frequency Response.
GAIN FREQUENCY Gain 1500pF VSIN -270
680pF
100pF
Phase
-180
Frequency (Hz) 100k
-360
FIGURE 3rd-Order LPF.
Phase
OPA604
Gain (dB)
PCM1720
POWER SUPPLY CONNECTIONS
PCM1720 power supply connections: digital (VDD) analog (VCC). Each connection also separate ground. power supplies turn different times, there possibility latch-up condition. avoid this condition, recommended have common connection between digital analog power supplies. separate supplies used without common connection, delta between supplies during ramp-up time must less than 0.6V. application circuit avoid latch-up condition shown Figure
THEORY OPERATION
delta-sigma section PCM1720 based 5-level amplitude quantizer 3rd-order noise shaper. This section converts oversampled input data 5-level deltasigma format. block diagram 5-level delta-sigma modulator shown Figure This 5-level delta-sigma modulator advantage stability clock jitter over typical one-bit (2-level) delta-sigma modulator. combined oversampling rate delta-sigma modulator internal interpolation filter 48fS 384fS system clock, 64fS 256fS system clock. theoretical quantization noise performance 5-level delta-sigma modulator shown Figure
Digital Power Supply
Analog Power Supply
ORDER MODULATOR
DGND
AGND
Gain (-dB)
-100 -120
FIGURE Latch-up Prevention Circuit. BYPASSING POWER SUPPLIES power supplies should bypassed close possible unit. Refer Figure optimal values bypass capacitors. also recommended include 0.1µF ceramic capacitor parallel with 10µF tantalum capacitor.
-140 -160 Frequency (kHz)
FIGURE Quantization Noise Spectrum.
18-Bit
5-level Quantizer 48fS (384fS) 64fS (256fS)
FIGURE 5-Level Modulator Block Diagram.
PCM1720
AC-3 APPLICATION Figure shows typical circuit diagram Dolby AC-3, channel system.
10µF SCKO AC-3 Audio Decoder LRCKO SERO_0 SERO_1 SERO_2 SYSCKI DGND BCKIN LRCIN SCKI PCM1720 VOUTR ZERO RSTB AGND 3.3µF 10µF Three-wire (Serial I/O) BCKIN LRCIN SCKI PCM1720 VOUTR ZERO RSTB AGND 3.3µF 10µF Post Pass Filter 10µF Analog Analog Mute Control 10µF DGND VOUTL Post Pass Filter Analog Mute Analog Mute Control 10µF VOUTL Post Pass Filter Analog Mute Analog Analog
Post Pass Filter
Analog Mute
Analog
Analog
STRB SCKO
Analog
Post Pass Filter
Analog Mute
Analog
Analog VOUTL Analog Mute
PGND DGND Master Clock Generator BCKIN LRCIN SCKO SCKI MCKI
PCM1721 VOUTR Post Pass Filter Analog Mute Analog
Reset
RSTB AGND 3.3µF Analog ZERO Mute Control
FIGURE Connection Diagram 6-Channel AC-3 Application.
PCM1720
PACKAGE OPTION ADDENDUM
www.ti.com
10-Feb-2006
PACKAGING INFORMATION
Orderable Device PCM1720E PCM1720E/2K PCM1720E/2KG4 PCM1720EG4
Status ACTIVE ACTIVE ACTIVE ACTIVE
Package Type SSOP SSOP SSOP SSOP
Package Drawing
Pins Package Plan Green (RoHS Sb/Br)
Lead/Ball Finish NIPDAU NIPDAU NIPDAU NIPDAU
Peak Temp Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM
2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) Green (RoHS Sb/Br)
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
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PCM1720 Stereo Audio DIGITAL-TO-ANALOG CONVERTER MPEG2/AC-3 COMPA

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