Octal Current Input 20-Bit Analog-To-Digital Converter SINGLE-CHI

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Octal Current Input 20-Bit Analog-To-Digital Converter SINGLE-CHI

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DDC118
Octal Current Input 20-Bit Analog-To-Digital Converter
SINGLE-CHIP SOLUTION DIRECTLY MEASURE EIGHT LOW-LEVEL CURRENTS HIGH PRECISION, TRUE INTEGRATING FUNCTION INTEGRAL LINEARITY: ±0.01% Reading ±0.5ppm VERY NOISE: 5.2ppm POWER: 13.5mW/channel ADJUSTABLE DATA RATE: 3.125kSPS PROGRAMMABLE FULL SCALE DAISY-CHAINABLE SERIAL INTERFACE
AVDD VREF DVDD
APPLICATIONS
SCANNER PHOTODIODE SENSORS INFRARED PYROMETER LIQUID/GAS CHROMATOGRAPHY
Protected Patent #5841310
DESCRIPTION
DDC118 20-bit octal channel, current-input analog-to-digital (A/D) converter. combines both current-to-voltage conversion that eight low-level current output devices, such photodiodes, directly connected inputs digitized. each eight inputs, DDC118 provides dual-switched integrator front-end. This design allows continuous current integration: while integrator being digitized onboard converter, other integrating input current. Adjustable full-scale ranges from 12pC 350pC adjustable integration times from 50µs allow currents from measured with outstanding precision. Low-level linearity ±0.5ppm full-scale range noise 5.2ppm full-scale range. modes operation provided. Low-Power mode, total power dissipation only 13.5mW channel with maximum data rate 2.5kSPS. High-Speed mode supports data rates 3.125kSPS with corresponding dissipation 18mW channel. DDC118 serial interface designed daisy-chaining multi-device systems. Simply connect output device input next create chain. Common clocking feeds devices chain that digital overhead multi-DDC118 system minimal. DDC118 single-supply device using analog supply supporting +2.7V +5.25V digital supply. Operating over industrial temperature range -40°C 85°C, DDC118 offered QFN-48 package.
Dual Switched Integrator Dual Switched Integrator Modulator CONV RANGE0 Digital Filter RANGE1 Control RANGE2 TEST CLK_4X HISPD/LOPWR RESET
Dual Switched Integrator Dual Switched Integrator DCLK Modulator
Digital Filter
FORMAT
DCLK
Dual Switched Integrator Dual Switched Integrator Modulator Digital Input/Output
DVALID Digital Filter
DOUT
DOUT
Dual Switched Integrator Dual Switched Integrator AGND DGND Modulator Digital Filter
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. trademarks property their respective owners.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2002-2005, Texas Instruments Incorporated
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DDC118
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ABSOLUTE MAXIMUM RATINGS(1)
Analog Input Current 750µA AVDD DVDD -0.3V AVDD AGND -0.3V DVDD DGND -0.3V AGND DGND ±0.2V VREF Input AGND 2.0V AVDD 0.3V Analog Input AGND -0.3V +0.7V Digital Input Voltage DGND -0.3V DVDD 0.3V Digital Output Voltage DGND -0.3V AVDD 0.3V Operating Temperature -40°C +85°C Storage Temperature -60°C +150°C Junction Temperature (TJ) +150°C Stresses above these ratings cause permanent damage. Exposure absolute maximum conditions extended periods degrade device reliability. These stress ratings only, functional operation device these other conditions beyond those specified implied.
This integrated circuit damaged ESD. Texas Instruments recommends that integrated circuits handled with appropriate precautions. Failure observe proper handling installation procedures cause damage. damage range from subtle performance degradation complete device failure. Precision integrated circuits more susceptible damage because very small parametric changes could cause device meet published specifications.
ORDERING INFORMATION
package ordering information, Package Option Addendum located this data sheet.
DDC118
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ELECTRICAL CHARACTERISTICS
+25°C, AVDD +5V, DVDD VREF +4.096V, Range (250pC), continuous mode operation, unless otherwise noted. Low-Power Mode: TINT 400µs 4MHz; High-Speed Mode: TINT 320µs 4.8MHz.
Low-Power Mode PARAMETER ANALOG INPUT RANGE Range Range Range Range Range Range Range Range Negative Full-Scale Range Input Current(2) DYNAMIC CHARACTERISTICS Data Rate Integration Time, TINT System Clock Input (CLK) CLK_4X CLK_4X Data Clock (DCLK) ACCURACY Noise, Low-Level Input(3) Integral Linearity Error(6) Resolution Input Bias Current Range Error Match(7) Range Sensitivity VREF Offset Error Offset Error Match(7) Bias Voltage(9) Power-Supply Rejection Ratio Internal Test Signal Internal Test Accuracy PERFORMANCE OVER TEMPERATURE Offset Drift Offset Drift Stability Bias Voltage Drift(9) Input Bias Current Drift Range Drift(10) REFERENCE Voltage Input Current(11) ±0.5 ±0.2 +25°C +45°C 0.01 4.000 Average Value 4.096 ±3(8) ±1(8) 1(8) FORMAT FORMAT Ranges VREF 4.096 0.1V Range (250pC) Low-Level Input FSR) CSENSOR(4) 50pF, Range (250pC) Continuous Mode Non-continuous Mode, Range TEST CONDITIONS High-Speed Mode UNITS
10.2 13.8 47.5 52.5 142.5 157.5 237.5 262.5 332.5 367.5 -0.4% Positive Full-Scale Range 1,000,000
3.125
kSPS FSR(5),
19.2
±0.01% Reading 0.5ppm FSR, ±0.025% Reading 1.0ppm FSR, ±400 ±1000 ±100 ±0.05 ±200
Bits Bits FSR/V FSR/°C FSR/ minute µV/°C pA/°C ppm/°C
4.200
indicates that specification same Low-Power Mode. Exceeding maximum input current specification damage device. Input less than full scale. SENSOR capacitance seen DDC118 inputs from wiring, photodiode, etc. Full-Scale Range. best-fit line used measuring nonlinearity. Matching between side side same input. Ensured design, production tested. Voltage produced DDC118 input which applied sensor. (10)Range drift does include external reference drift. (11)Input reference current decreases with increasing (see Voltage Reference section, page 11). (12)Data format Straight Binary with small offset. number bits output word controlled FORMAT (see text).
DDC118
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ELECTRICAL CHARACTERISTICS (continued)
+25°C, AVDD +5V, DVDD VREF +4.096V, Range (250pC), continuous mode operation, unless otherwise noted. Low-Power Mode: TINT 400µs 4MHz; High-Speed Mode: TINT 320µs 4.8MHz.
Low-Power Mode PARAMETER DIGITAL INPUT/OUTPUT Logic Levels Input Current (IIN) Data Format(12) POWER-SUPPLY REQUIREMENTS Analog Power-Supply Voltage (AVDD) Digital Power-Supply Voltage (DVDD) Supply Current Total Analog Current Total Digital Current Total Power Dissipation Total Power Dissipation Channel TEST CONDITIONS High-Speed Mode UNITS
-500µA 500µA DVDD
0.8DVDD DVDD
DVDD 0.2DVDD
Straight Binary
1.34
4.75 13.5
5.25 5.25
DVDD DVDD DVDD
18.75
indicates that specification same Low-Power Mode. Exceeding maximum input current specification damage device. Input less than full scale. SENSOR capacitance seen DDC118 inputs from wiring, photodiode, etc. Full-Scale Range. best-fit line used measuring nonlinearity. Matching between side side same input. Ensured design, production tested. Voltage produced DDC118 input which applied sensor. (10)Range drift does include external reference drift. (11)Input reference current decreases with increasing (see Voltage Reference section, page 11). (12)Data format Straight Binary with small offset. number bits output word controlled FORMAT (see text).
DDC118
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CONFIGURATION
DVALID DGND DGND DGND DGND DGND CONV DVDD DCLK DCLK View DGND
DOUT DOUT CLK_4X FORMAT HISPD/LOPWR RANGE0 RANGE1 RANGE2 AGND VREF AGND AGND AGND
RESET
DDC118
TEST DGND DGND AGND AVDD AGND AGND
AIN8 AIN4
AIN7
AIN3
AGND
AGND
AIN6
AIN2
AIN5
AIN1 AGND
DESCRIPTIONS
DOUT DOUT CLK_4X FORMAT HISPD/LOPWR RANGE0 RANGE1 RANGE2 AGND VREF AIN8 AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AVDD DGND TEST RESET DVDD DCLK DCLK DVALID CONV NUMBER 11-13, 24-26, FUNCTION Digital Output Digital Output Digital Input Digital Input Digital Input Digital Input Digital Input Digital Input Analog Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Digital Digital Input Digital Input Digital Input Digital Input Digital Digital Input Digital Input Digital Input Digital Output Digital Input DESCRIPTION Serial Data Output Serial Data Output: Complementary Signal (optional, text page Master Clock Divider Control: divide divide Digital Output Word Format: Bits, Bits Mode Control: Low-Power, High-Speed Range Control (least significant bit) Range Control Range Control (most significant bit) Analog Ground External Voltage Reference Input, 4.096V Nominal Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Power Supply, Nominal Digital Ground Test Mode Control Resets Digital Circuitry, Active connection. These pins must left unconnected. Serial Data Input: Complementary Signal (optional, text page Serial Data Input Digital Power Supply, Nominal Serial Data Clock Input: Complementary Signal (optional, text page Serial Data Clock Input Master Clock Input Data Valid Output, Active Conversion Control Input: Integrate Side Integrate Side
DDC118
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TYPICAL CHARACTERISTICS
+25°C, characterization done with Range (250pC), AVDD +5V, DVDD VREF +4.096V, Low-Power Mode: TINT 400µs 4MHz, unless otherwise noted.
NOISE CSENSOR Noise (ppm FSR, rms) Range CSENSOR (pF) Range Range
NOISE CSENSOR Noise (ppm FSR, rms)
CSENSOR Range Range Range Range Range Range Range Range (pF) 23.6 30.8 36.3 41.3 46.1 57.0 68.1 89.3 134.0 10.4 12.3 14.4 16.0 18.8 21.7 27.7 38.9 10.0 11.9 13.5 16.3 22.4 10.2 12.5 16.6 10.6 13.5 11.7 10.4
NOISE TINT CSENSOR 50pF
NOISE INPUT LEVEL Noise (ppm FSR, rms) Range CSENSOR CSENSOR 50pF
Noise (ppm FSR, rms)
CSENSOR Range TINT (ms) 1000
Input Level Full-Scale)
NOISE TEMPERATURE CSENSOR 50pF Noise (ppm FSR, rms) Range Range Range Range Drift (ppm) Range Temperature (_C) 1500 1000 -500 -1000 -1500 -2000 2000
RANGE DRIFT TEMPERATURE Ranges
Temperature
DDC118
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TYPICAL CHARACTERISTICS (continued)
+25°C, characterization done with Range (250pC), AVDD +5V, DVDD VREF +4.096V, Low-Power Mode: TINT 400µs 4MHz, unless otherwise noted.
TEMPERATURE Ranges Offset Drift (ppm FSR)
OFFSET DRIFT TEMPERATURE
(pA)
0.01 Temperature
-100 Temperature
ANALOG SUPPLY CURRENT TEMPERATURE Low-Power Mode
DIGITAL SUPPLY CURRENT TEMPERATURE Low-Power Mode DVDD Current (mA)
Current (mA)
DVDD
Temperature (_C) Temperature (_C)
POWER CONSUMPTION HISTOGRAM Occurences Occurences 12.00 12.25 12.50 12.75 13.00 13.25 13.50 13.75 14.00 14.25 14.50 14.75 15.00 15.25 15.50 15.75 16.00 Data collected from multiple lots. Low-Power Mode 1200 1000
OFFSET DRIFT HISTOGRAM ROOM TEMPERATURE Repeated measurement offset drift over minute interval. Range
-1.0
-0.6
-0.2
Offset Drift (ppm FSR/minute)
Power Channel (mW)
DDC118
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THEORY OPERATION
block diagram DDC118 shown Figure device contains eight identical input channels that perform function current-to-voltage integration followed multiplexed conversion. Each input integrators that current-to-voltage integration continuous time. output sixteen integrators switched four delta-sigma converters four four-input multiplexers. With
DDC118 continuous integration mode, output integrators from side inputs will digitized while other eight integrators integration mode, illustrated timing diagram Figure This integration conversion process controlled system clock, CLK. results from side side each signal input stored serial output shift register. DVALID output goes when shift register contains valid data.
AVDD
VREF
DVDD
CONV RANGE0 Dual Switched Integrator
odulato
Digital Filter
RANGE1
ontro
RANGE2 TEST
Dual Switched Integrator Dual Switched Integrator
odulato
CLK_4X HISPD/LOPWR RESET
Digital Filter
FORMAT
Dual Switched Integrator DCLK
DCLK
Dual Switched Integrator
ital odulato
DVALID Digital Filter
t/Output
DOUT
DOUT Dual Switched Integrator Dual Switched Integrator Dual Switched Integrator AGND DGND
odulato
Digital Filter
Figure DDC118 Block Diagram
DDC118
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digital interface DDC118 provides digital results synchronous serial interface consisting differential data clocks (DCLK DCLK), valid data (DVALID), differential serial data output pins (DOUT DOUT), differential serial data input pins (DIN DIN). DDC118 contains only four converters, conversion process interleaved (see Figure integration conversion process fundamentally independent data retrieval process. Consequently, frequency DCLK frequencies need same. only used when multiple converters cascaded should tied DGND DVDD otherwise.
implement integration cycle. timing relationships switches shown Figure illustrated Figure Figure used conceptualize operation integrator input stage DDC118 should used exact timing tool design. Figure block diagrams reset, integrate, wait convert states integrator section DDC118. This internal switching network controlled externally with convert (CONV), range selection pins (RANGE0-RANGE2), system clock (CLK). best noise performance, CONV must synchronized with rising edge CLK. recommended that CONV toggle within ±10ns rising edge CLK. noninverting inputs integrators connected ground. Consequently, DDC118 analog ground should clean possible. range switches, along with internal external capacitors (CF), shown parallel between inverting input output operational amplifier. beginning conversion, switches SA/D, SINTA, SINTB, SREF1, SREF2, SRESET (see Figure
DEVICE OPERATION
Basic Integration Cycle
topology front DDC118 analog integrator shown Figure this diagram, only Input shown. This representation input stage consists operational amplifier, selectable feedback capacitor network (CF), several switches that
IN1, IN2, IN5, IN6, Integrator IN1, IN2, IN5, IN6, Integrator IN3, IN4, IN7, IN8, Integrator IN3, IN4, IN7, IN8, Integrator Conversion Progress IN1B IN2B IN5B IN6B IN3B IN4B IN7B IN8B IN1A IN2A IN5A IN6A Integrate Integrate
Integrate Integrate
Integrate Integrate Integrate Integrate IN1B IN2B IN5B IN6B IN3B IN4B IN7B IN8B IN1A IN2A IN5A IN6A IN3A IN4A IN7A IN8A
IN3A IN4A IN7A IN8A
DVALID
Figure Basic Integration Conversion Timing DDC118 (continuous mode)
SREF1 VREF
50pF RANGE2 25pF RANGE1 12.5pF Input Current SINTA Protection Diodes SRESET SINTB Integrator Integrator (same SREF2 RANGE0 SA/D1A Converter
Photodiode
Figure Basic Integration Configuration Input shown with 250pC 62.5pF) Input Range
DDC118
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CONV
SINTA SINTB
SREF1 SREF2
SRESET
SA/D1A
Configuration Integrator VREF Integrator Voltage Output
Convert
Wait
Integrate
Convert
Wait
Figure Basic Integration Timing Diagram shown Figure
SREF1 VREF
SINT SRESET
SREF2 Converter SA/D SRESET SINT
SREF1 VREF SREF2 Converter SA/D
Reset Configuration
SREF1 VREF SINT SRESET Converter SA/D SRESET SINT SREF2
Wait Configuration
SREF1 VREF SREF2 Converter SA/D
Integrate Configuration
Convert Configuration
Figure Diagrams Four Configurations Front Integrators DDC118
DDC118
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completion conversion, charge integration capacitor (CF) reset with SREF1 SRESET (see Figure Figure 5a). this manner, selected capacitor charged reference voltage, VREF. Once integration capacitor charged, SREF1 SRESET switched that VREF longer connected amplifier circuit while waits begin integrating (see Figure 5b). With rising edge CONV, SINTA closes, which begins integration side This process puts integrator stage into integrate mode (see Figure 5c). Charge from input signal collected integration capacitor, causing voltage output amplifier decrease. falling edge CONV stops integration switching input signal from side side (SINTA SINTB). Prior falling edge CONV, signal side converted converter reset during time that side integrating. With falling edge CONV, side starts integrating input signal. output voltage side operational amplifier presented input converter (see Figure 5d).
Voltage Reference
external voltage reference used reset integration capacitors before integration cycle begins. also used converter while converter measuring voltage stored integrators after integration cycle ends. During this sampling, external reference must supply charge needed converter. integration time 400µs, this charge translates average VREF current approximately 150µA. amount charge needed converter independent integration time; therefore, increasing integration time lowers average current. example, integration time 800µs lowers average VREF current 75µA. critical that VREF stable during different modes operation (see Figure converter measures voltage integrator with respect VREF. Since integrator capacitors initially reset VREF, drop VREF from time capacitors reset time when converter measures integrator output will introduce offset. also important that VREF stable over longer periods time because changes VREF correspond directly changes full-scale range. Finally, VREF should introduce little additional noise possible. these reasons, strongly recommended that external reference source buffered with operational amplifier, shown Figure this circuit, voltage reference generated 4.096V reference. low-pass filter reduce noise connects reference operational amplifier configured buffer. This amplifier should have noise, input/output common-mode ranges that support VREF. Following buffer capacitors placed close DDC118 VREF pin. Even though circuit Figure might appear unstable because large output capacitors, works well most operational amplifiers. recommended that series resistance placed output lead improve stability since this cause drop VREF, which producing large offsets.
Integration Capacitors
There eight different capacitors available on-chip both sides every channel DDC118. These internal capacitors trimmed production achieve specified performance range error DDC118. range control pins (RANGE0-RANGE2) change capacitor value four integrators. Consequently, inputs both sides each input will always have same full-scale range. Table shows capacitor value selected each range selection.
Table Range Selection DDC118
RANGE2 RANGE1 RANGE0 (pF, typ) 12.5 37.5 62.5 87.5 INPUT RANGE (pC, typ) -0.048 -0.2 -0.4 -0.6 -0.8 -0.1 -1.2 -1.4
0.47µF
0.10µF
REF3140
10µF 0.10µF OPA350
VREF DDC118 10µF 0.1µF
Figure Recommended External Voltage Reference Circuit Best Low-Noise Operation with DDC118
DDC118
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DDC118 Frequency Response
frequency response DDC118 front integrators that traditional continuous time integrator, shown Figure adjusting TINT, user change bandwidth location notches response. frequency response converter that follows front integrator consequence because converter samples held signal from integrators. That input converter always signal. Since output front integrators sampled, aliasing occur. Whenever frequency input signal exceeds one-half sampling rate, signal will fold back down lower frequencies.
TINT TINT Frequency TINT TINT
Test Mode
When Test Mode used, inputs (IN1, IN2, IN3, IN4, IN5, IN6, IN7, IN8) disconnected from DDC118 integrators enable user measure zero input signal regardless current supplied inputs. addition, packets charge transferred integrators 11pC intervals measure non-zero values. test mode works with both continuous non-continuous modes. timing diagram test mode shown Figure with timing specifications given Table enter Test Mode, hold TEST high while CONV transitions. TEST held high during entire integration period, integrators measure zero value. This mode used help debug design perform diagnostic tests. apply packets charge during Test Mode, simply strobe TEST then high before next CONV transition. Each rising edge TEST causes approximately 11pC charge transferred integrators. This charge transfer independent integration time. Data retrieval during Test Mode identical normal operation. exit Test Mode, take TEST allow several cycles after exiting before using data.
(dB)
Figure Frequency Response DDC118
Test Mode Disabled
Test Mode Enabled: Inputs Disconnected
into 11pC into 22pC into 33pC into
Test Mode Disabled
Action Integrate Integrate Integrate Integrate
CONV TEST
Figure Timing Diagram Test Mode DDC118 Table Timing DDC118 Test Mode
SYMBOL DESCRIPTION Setup Time Test Mode Enable Setup Time Test Mode Disable Hold Time Test Mode Enable From Rising Edge TEST Edge CONV while Test Mode Enabled Falling Edge Rising Edge TEST Rising Edge Falling Edge TEST UNITS
DDC118
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DIGITAL INTERFACE
digital interface DDC118 provides digital results synchronous serial interface consisting differential data clocks (DCLK DCLK), valid data (DVALID), differential serial data output pins (DOUT DOUT), differential serial data input pins (DIN DIN). DDC118 contains only four converters, conversion process interleaved (see Figure page integration conversion processes independent data retrieval process. Consequently, frequency DCLK frequencies need same. used when multiple converters cascaded. Cascading daisy-chaining greatly simplifies interconnection routing digital outputs cases where large number converters needed. Refer Cascading Multiple Converters section this data sheet more detail.
High-Speed Low-Power Modes (HISPD/LOPWR)
HISPD/LOPWR input controls power dissipation turn, maximum allowable frequency data rate, shown Table With HISPD/LOPWR Low-Power Mode selected with typical 13.5mW/ channel maximum data rate 2.5kSPS. Setting HISPD/LOPWR selects High-Speed Mode, which supports maximum data rate 3.125kSPS with corresponding typical power 18.0mW/channel.
Table HISPD/LOPWR Operation
HISPD/ LOPWR MODE Low-Power High-Speed TYPICAL POWER/ CHANNEL 13.5mW/ch 18.0mW/ch MAXIMUM FREQUENCY (CLK_4X 4.0MHz 4.8MHz MAXIMUM DATA RATE 2.5kSPS 3.125kSPS
Data Valid (DVALID) Complementary Signals (DCLK, DIN, DOUT)
DDC118 provides optional complementary inputs (DCLK, DIN) help reduce digital coupling analog inputs. using these inputs, connect complementary signal each. these inputs connected DDC118, they should tied DGND. DOUT complementary output designed drive DIN. using DOUT, leave floating. DVALID signal indicates that data ready. Data retrieval begin after DVALID goes low. This signal generated using internal clock divided down from system clock CLK. phase relationship between this internal clock when power first applied random. Since user must synchronize CONV with CLK, DVALID signal will have random phase relationship with CONV. This uncertainty 1/fCLK. Polling DVALID eliminates concern about this relationship. data read back timed from CONV, wait maximum value insure data valid.
System Data Clocks (CLK CONV)
system clock supplied data clock supplied DCLK. Make sure clock signals clean-avoid overshoot ringing. best performance, generate both clocks from same clock source. DCLK should disabled taking after data been shifted while CONV transitioning. When using multiple DDC118s, close attention DCLK distribution printed circuit board (PCB). particular, make sure minimize skew DCLK signal this lead timing violations serial interface specifications. Cascading Multiple Converters section more details.
Reset (RESET)
DDC118 reset asynchronously taking RESET input low, shown Figure Make sure reset pulse least 50µs wide. After resetting DDC118, wait least four conversions before using data. very important make sure RESET glitch free avoid unintended resets. RESET used during power-up; Power-Up Sequence section more details.
System Clock Divider (CLK_4X)
CLK_4X input enables internal divider system clock shown Table When CLK_4X system clock divided four. This allows faster system clock, which turn provides finer quantization integration time CONV signal needs synchronized with system clock best performance.
RESET
50µs
Figure Reset Timing Convert (CONV)
CONV controls integration time (TINT). optimum analog performance, make sure CONV synchronized CLK. This recommendation implies that while SPEED low, TINT needs adjusted steps 250ns CLK_4X 4MHz. CLK_4X high 16MHz, this allows TINT adjusted steps 62.5ns.
Table CLK_4X Operation
CLK_4X DIVIDER VALUE TYPICAL FREQUENCY 4MHz 16MHz INTERNAL CLOCK FREQUENCY 4MHz 4MHz
DDC118
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Conversion Rate
conversion rate DDC118 combination integration time (determined user) speed conversion process. conversion time primarily function system clock (CLK) speed. conversion cycle encompasses conversion signals (one side each dual integrator feeding modulator) reset time each integrators involved conversions. most situations, conversion time shorter than integration time. this condition exists, DDC118 will operate continuous mode. When DDC118 continuous mode, sensor output continuously integrated sides each input. event that conversion takes longer than integration time, DDC118 will switch into non-continuous mode. non-continuous mode, converter able keep pace with speed integration process. Consequently, integration process periodically halted until digitizing process catches These basic modes operation DDC118-continuous non-continuous modes-are described below.
CONV|mbsy
Ncont
CONV mbsy
Ncont
CONV mbsy
CONV
Cont CONV
B/Meas Cont
CONV mbsy CONV mbsy
A/Meas Cont
Cont CONV
CONV
CONV mbsy
Ncont CONV mbsy CONV|mbsy
Ncont
Continuous Non-Continuous Operational Modes
Figure shows state diagram DDC118. all, there eight states. Table provides brief explanation each state.
Figure Integrate/Measure State Diagram
During cont mode, mbsy active when CONV toggles. non-integrating side always ready begin integrating when other side finishes integration. Consequently, monitoring current status CONV that needed know current state. Cont mode operation corresponds states 3-6. states, only perform integration m/r/az cycle). mbsy becomes important when operating ncont mode, states Whenever CONV toggled while mbsy active, DDC118 will enter remain either ncont state After mbsy goes inactive, state entered. This state prepares appropriate side integration. ncont states, inputs DDC118 grounded. interesting observation from state diagram that integrations always alternate between sides This relationship holds CONV pattern independent mode. States insure this relationship during ncont mode. When power first applied DDC118, beginning state either depending initial level CONV. CONV held high power-up, beginning state Conversely, CONV held power-up, beginning state general, there symmetry state diagram between states 1-8, 2-7, 3-6, 4-5. Inverting CONV results states progressing through their symmetrical match.
Table State Descriptions
STATE MODE Ncont DESCRIPTION Complete m/r/az side then side previous state state Initial power-up state when CONV initially held HIGH. Prepare side integration. Integrate side Integrate side m/r/az side Integrate side m/r/az side Integrate side Prepare side integration. Complete m/r/az side then side previous state state Initial power-up state when CONV initially held LOW.
Ncont Cont Cont Cont Cont Ncont Ncont
Four signals used control progression around state diagram: CONV, mbsy, their complements. state machine uses level opposed edges CONV control progression. mbsy internallygenerated signal available user. active whenever measurement/reset/auto-zero (m/r/az) cycle progress.
DDC118
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TIMING EXAMPLES
Cont Mode
timing diagrams help illustrate operation state machine. These diagrams shown Figure through Figure Table gives generalized timing specifications units periods CLK_4X CLK_4X these values increase factor four because internal clock divider. Values Table easily found given CLK. example, 4MHz, then period 0.25µs. Table would then 367.50 0.125µs.
measurement cycles underway. internal signal mbsy shown next. Finally, DVALID given. DVALID goes active when data ready retrieved from DDC118. stays until DCLK taken high then back user. text below DVALID pulse indicates side data available read, arrows help match data corresponding integration. signals illustrated Figure through Figure drawn approximately same scale. Figure first state ncont state DDC118 always powers ncont mode. this case, first state because CONV initially low. After first states, cont mode operation reached states begin toggling between From input being continuously integrated, either side side time needed m/r/az cycle, same time that determines boundary between cont ncont modes described earlier Overview section. DVALID goes after CONV toggles time indicating that data ready retrieved. shown Figure there values reason this discussed Special Considerations section. Figure timing diagram internal operations occurring during continuous mode operation. Table gives timing specifications continuous mode.
Table Timing Specifications Generalized Periods
SYMBOL DESCRIPTION Cont mode m/r/az cycle Cont mode data ready ncont mode data ready ncont mode data ready Ncont mode m/r/az cycle VALUE (CLK periods with CLK_4X 1470 1380 1379 1450 2901
Figure shows integration cycles beginning with initial power-up cont mode example. signal CONV supplied user. next line indicates current state state diagram. following traces show when integrations
CONV
State
Integration Status m/r/az Status
Integrate
Integrate
Integrate
Integrate
m/r/az
m/r/az
m/r/az
mbsy
DVALID Power-Up SYMBOL DESCRIPTION Cont Mode m/r/az Cycle Cont Mode Data Ready
Side Data VALUE (CLK 4MHz, CLK_4X 367.50 0.125µs 345.00 0.125µs Side Data Side Data
VALUE (CLK 4.8MHz, CLK_4X 306.25 0.104µs 287.5 0.104µs
Figure Continuous Mode Timing
DDC118
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Integration Side Start Integration Side
Integration Side Start Integration Side
Integration Side Start Integration Side
CONV
TINT
TINT
Side Conversion Inputs (Internal) Side Conversion Inputs (Internal) DVALID Side Data Ready
Side
Side
Side
Side Data Ready
Figure Timing Diagram Internal Operation Continuous Mode DDC118 Table Timing Internal Operation Continuous Mode
4MHz, CLK_4X SYMBOL TINT DESCRIPTION Integration Period (continuous mode) Conversion Time (internally controlled) Conversion Reset Time (internally controlled) Integrator Conversion Reset Time (internally controlled) 169.5 1,000,000 4.8MHz, CLK_4X 141.25 3.333 19.167 1,000,000 UNITS
DDC118
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Ncont Mode
Non-continuous mode operation intended Ranges recommended Range when operating non-continuous mode. Figure illustrates operation ncont mode. integrations come pairs (that sides sides B/A) followed time during which integrations occur. During that time, previous integrations being measured, reset auto-zeroed. Before DDC118 advance states both sides must finished with m/r/az cycle which takes time t10. When m/r/az cycles completed, time needed prepare next side integration. This time required ncont mode because m/r/az cycle ncont mode slightly different from that cont mode. After first
integration ends, DVALID goes time This time same cont mode. second data will ready time after first data ready. result naming convention used this data sheet that when DDC118 operating ncont mode, passes through both ncont mode states cont mode states. example, Figure state pattern where cont mode states. Ncont mode, definition, means that some portion time, neither side integrating. States that perform integration labeled cont mode states, while those that called ncont mode states. Since integrations performed ncont mode, just continuously, some cont mode states must used ncont mode state pattern.
CONV
State
Integration Status
m/r/az Status
m/r/az
m/r/az
m/r/az
m/r/az
mbsy DVALID Side Data Side Data Side Data Side Data
SYMBOL
DESCRIPTION ncont Mode Data Ready ncont Mode Data Ready ncont Mode m/r/az Cycle Prepare Side Integration
VALUE (CLK 4MHz, CLK_4X 344.75 0.25µs 362.5µs 725.25 0.25µs 18µs
VALUE (CLK 4.8MHz, CLK_4X 287.292 0.208µs 302.083µs 604.375 0.208µs 15µs
Figure Non-Continuous Mode Timing
DDC118
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Start Integration Side Integration Side Start Integration Side Integration Side Wait State
Start Integration Side
Release State
TINT CONV TINT Conversion Inputs Conversion Inputs DVALID Side Data Ready Side Data Ready
Figure Conversion Detail Internal Operation Non-Continuous Mode with Side Integrated First Table Internal Timing DDC118 Non-Continuous Mode
4MHz, CLK_4X SYMBOL TINT DESCRIPTION Integration Time (non-continuous mode) Conversion Time (internally controlled) Conversion Reset Time (internally controlled) Integrator Conversion Reset Time (internally controlled) Total Conversion Reset Time (internally controlled) Release Time 169.5 19.5 725.25 0.25 1,000,000 4.8MHz, CLK_4X 141.25 3.333 16.25 604.375 0.208 1,000,000 UNITS
Start Integration Side Integration Side Start Integration Side Integration Side Wait State
Start Integration Side
Release State
TINT CONV TINT Conversion Inputs Conversion Inputs DVALID Side Data Ready Side Data Ready
Figure Internal Operation Timing Diagram Non-Continuous Mode with Side Integrated First
DDC118
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Looking state diagram, that CONV pattern needed generate given state progression unique. Upon entering states DDC118 remains those states until mbsy goes low, independent CONV. long m/r/az cycle underway, state machine ignores CONV (see Figure page 14). signals Figure different CONV patterns that produce same state. This feature allows flexibility generating ncont mode CONV patterns. example, DDC118 Evaluation Fixture operates ncont mode generating square wave with pulse width Figure illustrates operation ncont mode using duty
cycle CONV signal with TINT periods. Care must exercised when using square wave generate CONV. There certain integration times that must avoided since they produce very short intervals state state CONV inverted). seen state diagram, state progresses from soon CONV high. state machine does insure that duration state long enough properly prepare next side integration (t11). This must done user with proper timing CONV. example, CONV square wave with TINT periods, state will only periods long; therefore, will met.
CONV1
CONV2
mbsy
State
Figure Equivalent CONV Signals Non-Continuous Mode
CONV
State
Integration Status
mbsy
DVALID Side Data Side Data Side Data
Figure Non-Continuous Mode Timing with Duty Cycle CONV Signal
DDC118
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Changing Between Modes
Changing from cont ncont mode occurs whenever TINT Figure shows example this transition. this figure, cont mode entered when integration side completed before m/r/az cycle side complete. DDC118 completes measurement sides during states with input signal shorted ground. Ncont integration begins with state
Changing from ncont cont mode occurs when TINT increased that TINT always shown Figure (see also Figure Table page 18). With longer TINT, m/r/az cycle enough time finish before next integration begins continuous integration input signal possible. special case very first integration when changing cont mode, TINT This allowed because there simultaneous m/r/az cycle side during state 3-there need wait finish before ending integration side
CONV
State
Continuous
Non-Continuous
Integration Status
Integrate
Integrate
m/r/az Status
m/r/az
m/r/az
m/r/az
m/r/az
m/r/az
mbsy
Figure Changing from Continuous Mode Non-Continuous Mode
CONV
State
Non-Continuous
Continuous Integrate
Integration Status m/r/az Status
Integrate
m/r/az
m/r/az
m/r/az
mbsy
Figure Changing from Non-Continuous Mode Continuous Mode
DDC118
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DATA FORMAT (FORMAT)
serial output data provided offset binary code shown Table digital input FORMAT selects many bits used output word. When FORMAT high (1), bits used. When FORMAT (0), lower bits truncated that only bits used. Note that size times bigger when FORMAT offset included output allow slightly negative inputs, from board leakages example, from clipping reading. This offset approximately 0.4% positive full-scale.
DATA RETRIEVAL
both continuous non-continuous modes operation, data from last conversion available retrieval falling edge DVALID (see Figure Table 10). Data shifted falling edge data clock, DCLK. Make sure retrieve data while CONV changes this introduce noise. Stop activity DCLK least 10µs before after CONV transition. Setting FORMAT (16-bit output word) reduces time needed retrieve data 20%, since there fewer bits shift out. This time reduction useful multichannel systems requiring only bits resolution.
Table Ideal Output Code(1) Input Signal
INPUT SIGNAL
100% 0.001531% 0.001436% 0.000191% 0.000096% -0.3955% IDEAL OUTPUT CODE FORMAT HIGH 1111 1111 1111 1111 1111 0000 0001 0000 0001 0000 0000 0001 0000 0000 1111 0000 0001 0000 0000 0010 0000 0001 0000 0000 0001 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 IDEAL OUTPUT CODE FORMAT 1111 1111 1111 1111 0000 0001 0000 0001 0000 0001 0000 0000 0000 0001 0000 0000 0000 0001 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000
Excludes effects noise, INL, offset, gain errors.
DVALID
DCLK
DOUT Input Input Input Input Input Input Input Input Input
Figure Digital Interface Timing Diagram Data Retrieval From Single DDC118 Table Timing DDC118 Data Retrieval
4MHz, CLK_4X SYMBOL t21A(1) DESCRIPTION Propagation Delay from Falling Edge DVALID Propagation Delay from Falling Edge DCLK DVALID HIGH Hold Time that DOUT Valid Before Falling Edge DVALID Hold Time that DOUT Valid After Falling Edge DCLK Propagation Delay from Falling Edge DCLK Valid DOUT 1.75 4.8MHz, CLK_4X 1.458 UNITS
With maximum load DDC118 (4pF typical) with additional load (5pF).
DDC118
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SPECIAL CONSIDERATIONS
Cascading Multiple Converters
Multiple DDC118 units connected serial configuration, illustrated Figure DOUT used with daisy-chain several
DDC118 devices together minimize wiring. this mode operation, serial data output shifted through multiple DDC118s, illustrated Figure Figure timing diagram when input used daisy-chain several devices. Table gives timing specification data retrieval using DIN.
Data Clock
DCLK
DCLK
DCLK
DCLK
DCLK
DVALID
DVALID
Data Retrieval Outputs
DOUT DOUT
DDC118
DOUT DOUT
DDC118
DOUT DOUT
DVALID
DCLK
DDC118
Sensor
Figure Daisy-Chained DDC118s
DVALID
DCLK
DOUT
Input
Input
Input
Input
Input
Input
Input
Input
Input
Figure Timing Diagram When Using Function DDC118 Table Timing DDC118 Data Retrieval Using
SYMBOL DESCRIPTION Set-Up Time From Falling Edge DCLK Hold Time After Falling Edge DCLK UNITS
DDC118
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RETRIEVAL BEFORE CONV TOGGLES (CONTINUOUS MODE)
Date retrieval before CONV toggles most straightforward method. Data retrieval begins soon after DVALID goes finishes before CONV toggles, shown Figure best performance, data retrieval must stop before CONV toggles. This method most appropriate longer integration times. maximum time available readback TINT t28. DCLK 10MHz 4MHz, maximum number DDC118s that daisy-chained together (FORMAT high) calculated Equation
NOTE: 128DCLK used FORMAT low. where DCLK period data clock. example, TINT 1000µs DCLK 10MHz, maximum number DDC118s (FORMAT high) shown Equation
1000ms 355.125ms 40.30 40DDC118s (160)(100ns)
FORMAT low).
355.125ms 160t DCLK
CONV
TINT
TINT
DVALID
DCLK
Side Data
Side Data
DOUT
4MHz, CLK_4X SYMBOL DESCRIPTION Cont Mode Data Ready Data Retrieval Shutdown Before Edge CONV 345.00 0.125
4.8MHz, CLK_4X UNITS 287.5 0.104
Figure Readback Before CONV Toggles
DDC118
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RETRIEVAL AFTER CONV TOGGLES (CONTINUOUS MODE)
shorter integration times, more time available data retrieval begins after CONV toggles ends before data ready. Data retrieval must wait after CONV toggles before beginning. Figure example this. maximum time available retrieval (344.875µs 10µs 1.75µs 4MHz), regardless TINT. maximum number
DDC118s that daisy-chained together (FORMAT high) calculated Equation
333.125ms 160t DCLK
NOTE: 128DCLK used FORMAT low.
DCLK 10MHz, maximum number DDC118s FORMAT low).
CONV
TINT
TINT
TINT
DVALID DCLK
Side Data
Side Data
DOUT
Side Data
4MHz, CLK_4X SYMBOL DESCRIPTION Hold Time that DOUT Valid Before Falling Edge DVALID Cont Mode Data Ready Data Retrieval Start-Up After Edge CONV 1.75 345.00 0.125
4.8MHz, CLK_4X 1.458 287.5 0.104 UNITS
Figure Readback After CONV Toggles
DDC118
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RETRIEVAL BEFORE AFTER CONV TOGGLES (CONTINUOUS MODE)
absolute maximum time data retrieval, data retrieved before after CONV toggles. Nearly TINT available data retrieval. Figure illustrates this done combining previous methods. Retrieval during CONV toggling prevent digital noise, discussed previously, finished before next data ready. maximum number DDC118s that daisy-chained together (FORMAT high)
RETRIEVAL: NONCONTINUOUS MODE
Retrieving noncontinuous mode slightly different, compared continuous mode. illustrated Figure DVALID goes time after first integration completes. TINT shorter than this time, available retrieve data before other side data ready. TINT t30, first integration data ready before second integration completes. Data retrieval must delayed until second integration completes, leaving less time available retrieval. time available (TINT t30). second integration's data must retrieved before next round integration begins. This time highly dependent pattern used generate CONV. with continuous mode, data retrieval must halt before after CONV toggles (t28, t29) completed before data ready (t26).
20ms 1.75ms 160t DCLK
NOTE: 128DCLK used FORMAT low. TINT 400µs DCLK 10MHz, maximum number DDC118s FORMAT low).
CONV
TINT
TINT
TINT
DVALID DCLK
Side Data
Side Data 4MHZ, CLK_4X 1.75
DOUT
SYMBOL
DESCRIPTION Hold Time that DOUT Valid Before Falling Edge DVALID Data Retrieval Shutdown Before Edge CONV Data Retrieval Start-Up After Edge CONV
4.8MHZ, CLK_4X 1.458
UNITS
Figure Readback Before After CONV Toggles
CONV
DVALID DCLK
Side Data
Side Data
SYMBOL
DESCRIPTION ncont Mode Data Ready ncont Mode Data Ready
4MHz, CLK_4X 344.75 0.25 362.500
4.8MHz, CLK_4X 287.292 0.208 302.083
UNITS
Figure Readback Non-Continuous Mode
DDC118
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POWER-UP SEQUENCING
Prior power-up, digital analog inputs must low. After power supplies have settled, release RESET after time t32. (See Figure Table 12.) Wait time begin applying digital signals CONV CLK. first CONV pulse will complete release state begin integration.
AVDD 10µF 0.1µF DDC118 DVDD 10µF 0.1µF DGND AGND
LAYOUT
POWER SUPPLIES GROUNDING
Both AVDD DVDD should quiet possible. particularly important eliminate noise from AVDD that non-synchronous with DDC118 operation. Figure illustrates acceptable ways supply power DDC118. first case shows separate supplies AVDD DVDD. this case, each supply DDC118 should bypassed with 10µF solid tantalum capacitors 0.1µF ceramic capacitors. second case shows DVDD power supply derived from AVDD supply with isolation resistor. both cases, 0.1µF capacitors should placed close DDC118 package possible. recommended that both analog digital grounds (AGND DGND) connected single ground plane printed circuit board (PCB).
Separate Supplies
AVDD 10µF 0.1µF DDC118 AGND
DVDD 0.1µF
DGND
Supply
Figure Power-Supply Connection Options
THERMAL
strongly recommended that thermal DDC118 connected ground PCB. traces should routed underneath thermal pad.
AVDD DVDD RESET CONV Integrate Side Release State Start Integration
Figure Timing Diagram Power-Up DDC118 Table Timing DDC118 Power-Up Sequence
SYMBOL DESCRIPTION Power Supplies Settled RESET Release RESET Release CONV, Begin First CONV Pulse Width UNITS
DDC118
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Shielding Analog Signal Paths
with precision circuit, careful layout ensures best performance. essential make short, direct interconnections avoid stray wiring capacitance-particularly analog input pins. Digital signals should kept from analog input signals possible PCB. Input shielding practices should taken into consideration when designing circuit layout DDC118. inputs DDC118 high impedance extremely sensitive extraneous noise. Leakage
currents between traces exceed input bias current DDC118 shielding implemented. Figure illustrates acceptable approach this problem. ground plane placed around inputs DDC118. This shield helps minimize coupled noise into input pins. This approach reduces leakage effects surrounding these sensitive pins with impedance analog ground. Leakage currents from other portions circuit will flow harmlessly impedance analog ground rather than into analog input stage DDC118.
Digital Digital Power
DDC118
Analog Ground Analog Ground Analog Power
Analog Ground
Figure Recommended Shield DDC118 Layout Design
PACKAGE OPTION ADDENDUM
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30-Nov-2005
PACKAGING INFORMATION
Orderable Device DDC118IRTCR DDC118IRTCRG4 DDC118IRTCT DDC118IRTCTG4
Status ACTIVE ACTIVE ACTIVE ACTIVE
Package Type
Package Drawing
Pins Package Plan 2500 Green (RoHS Sb/Br) 2500 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
Lead/Ball Finish NIPDAU NIPDAU NIPDAU NIPDAU
Peak Temp Level-3-260C-168 Level-3-260C-168 Level-3-260C-168 Level-3-260C-168
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS) Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
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Octal Current Input 20-Bit Analog-To-Digital Converter SINGLE-CHI

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