November 1997 Revised 2003 High-Speed CMOS Logic Octal-Bus Transc

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November 1997 Revised 2003 High-Speed CMOS Logic Octal-Bus Transc

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CD54HC245, CD74HC245, CD54HCT245, CD74HCT245
November 1997 Revised 2003
High-Speed CMOS Logic Octal-Bus Transceiver, Three-State, Non-Inverting
Description
CD54HC245, CD54HCT245, CD74HC245, CD74HCT245 high-speed octal three-state bidirectional transceivers intended two-way asynchronous communication between data buses. They have high drive current outputs which enable high-speed operation while driving large capacitances. They provide power consumption standard CMOS circuits with speeds drive capabilities comparable that LSTTL circuits. CD54HC245, CD54HCT245, CD74HC245 CD74HCT245 allow data transmission from bus. logic level direction input (DIR) determines direction. output enable input (OE), when high, puts ports high-impedance state. HC/HCT245 similar operation HC/HCT640 HC/HCT643.
Features
Buffered Inputs
/Title (CD54 HC245 CD54 HCT24 CD74 HC245 CD74 HCT24 /Subject (High Speed
Three-State Outputs Line Driving Capability Typical Propagation Delay 15pF, 25oC Fanout (Over Temperature Range) Standard Outputs LSTTL Loads Driver Outputs LSTTL Loads Wide Operating Temperature Range -55oC 125oC Balanced Propagation Delay Transition Times Significant Power Reduction Compared LSTTL Logic Types Operation High Noise Immunity: 30%, Types 4.5V 5.5V Operation Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), (Min) CMOS Input Compatibility, VOL,
Ordering Information
PART NUMBER CD54HC245F3A CD54HCT245F3A CD74HC245E CD74HC245M TEMP. RANGE (oC) PACKAGE CERDIP CERDIP PDIP SOIC SOIC PDIP SOIC SOIC
Pinout
CD54HC245, CD54HCT245 (CERDIP) CD74HC245, CD74HCT245 (PDIP, SOIC) VIEW
CD74HC245M96 CD74HCT245E CD74HCT245M CD74HCT245M96
NOTE: When ordering, entire part number. suffix denotes tape reel.
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. Copyright
2003, Texas Instruments Incorporated
CD54HC245, CD74HC245, CD54HCT245, CD74HCT245 Functional Diagram
TRUTH TABLE CONTROL INPUTS OPERATION Data Data Isolation
High Level, Level, Irrelevant prevent excess currents High-Z (Isolation) modes terminals should terminated with resistors.
CD54HC245, CD74HC245, CD54HCT245, CD74HCT245
Absolute Maximum Ratings
Supply Voltage, -0.5V Input Diode Current, -0.5V 0.5V .±20mA Output Diode Current, -0.5V 0.5V .±20mA Drain Current, Output, -0.5V 0.5V. .±35mA Output Source Sink Current Output Pin, -0.5V 0.5V .±25mA Ground Current, .±50mA
Thermal Information
Thermal Resistance (Typical, Note (oC/W) (PDIP) Package (SOIC) Package. Maximum Junction Temperature 150oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (SOIC Lead Tips Only)
Operating Conditions
Temperature Range, -55oC 125oC Supply Voltage Range, Types Types .4.5V 5.5V Input Output Voltage, Input Rise Fall Time 1000ns (Max) 4.5V. 500ns (Max) 400ns (Max)
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
package thermal impedance calculated accordance with JESD 51-7.
Electrical Specifications
TEST CONDITIONS PARAMETER TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage CMOS Loads Level Output Voltage Loads Input Leakage Current Quiescent Device Current -0.02 -0.02 -0.02 -5.2 0.02 0.02 0.02 3.15 3.98 5.48 1.35 0.26 0.26 ±0.1 3.15 3.84 5.34 1.35 0.33 0.33 3.15 1.35 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
CD54HC245, CD74HC245, CD54HCT245, CD74HCT245
Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Three-State Leakage Current TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage CMOS Loads Level Output Voltage Loads Input Leakage Current Quiescent Device Current Three-State Leakage Current Additional Quiescent Device Current Input Pin: Unit Load NOTE: dual-supply systems theoretical worst case 2.4V, 5.5V) specification 1.8mA. -0.02 SYMBOL (mA) 25oC ±0.5 -40oC 85oC -55oC 125oC UNITS
3.98
3.84
0.02
0.26
0.33
±0.1 ±0.5
(Note
-2.1
Input Loading Table
INPUT UNIT LOADS
NOTE: Unit Load limit specified Electrical Table, e.g., 360µA 25oC.
CD54HC245, CD74HC245, CD54HCT245, CD74HCT245
Switching Specifications
50pF, Input 25oC -40oC 85oC -55oC 125oC UNITS
PARAMETER TYPES Propagation Delay Data Output
SYMBOL
TEST CONDITIONS
tPHL, tPLH
50pF 15pF 50pF 15pF 50pF 15pF 50pF
Output Disable Output
tPHL, tPLH
50pF
Output Enable Output
tPHL, tPLH
50pF
Output Transition Time
tTHL, tTLH
50pF
Input Capacitance Three-State Output Capacitance Power Dissipation Capacitance (Notes TYPES Propagation Delay Data Output
50pF
tPHL, tPLH
50pF 15pF
Output Disable Output
tPHL, tPLH
50pF 15pF
Output Enable Output
tPHL, tPLH
50pF 15pF
Output Transition Time Input Capacitance Three-State Output Capacitance Power Dissipation Capacitance (Notes NOTES:
tTHL, tTLH
50pF 50pF
used determine dynamic power consumption, channel. VCC2 (CPD where Input Frequency, Output Load Capacitance, Supply Voltage.
CD54HC245, CD74HC245, CD54HCT245, CD74HCT245 Test Circuits Waveforms
INPUT tTLH tPHL tPLH INPUT tTHL 2.7V 1.3V 0.3V tTLH INVERTING OUTPUT tPHL tPLH 1.3V
tTHL
INVERTING OUTPUT
FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC
FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC
OUTPUT DISABLE
tPZL tPHZ tPZH OUTPUTS DISABLED OUTPUTS ENABLED
OUTPUT DISABLE
tPZL
tPLZ OUTPUT
tPLZ OUTPUT tPHZ OUTPUT HIGH OUTPUTS ENABLED
tPZH
1.3V
OUTPUT HIGH OUTPUTS ENABLED
1.3V OUTPUTS DISABLED OUTPUTS ENABLED
FIGURE THREE-STATE PROPAGATION DELAY WAVEFORM
FIGURE THREE-STATE PROPAGATION DELAY WAVEFORM
OTHER INPUTS TIED HIGH OUTPUT DISABLE
WITH THREESTATE OUTPUT
OUTPUT 50pF
tPLZ tPZL tPHZ tPZH
NOTE: Open drain waveforms tPLZ tPZL same those three-state shown left. test circuit Output VCC, 50pF. FIGURE THREE-STATE PROPAGATION DELAY TEST CIRCUIT
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2006
PACKAGING INFORMATION
Orderable Device CD54HC245F CD54HC245F3A CD54HCT245F CD54HCT245F3A CD74HC245E CD74HC245EE4 CD74HC245M CD74HC245M96 CD74HC245M96E4 CD74HC245ME4 CD74HCT245E CD74HCT245EE4 CD74HCT245M CD74HCT245M96 CD74HCT245M96E4 CD74HCT245ME4
Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type CDIP CDIP CDIP CDIP PDIP PDIP SOIC SOIC SOIC SOIC PDIP PDIP SOIC SOIC SOIC SOIC
Package Drawing
Pins Package Plan Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS Sb/Br)
Lead/Ball Finish Call Call Call Call NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU
Peak Temp Type Type Type Type Type Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Type Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM
2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS Sb/Br)
2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) Green (RoHS Sb/Br)
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature.
Addendum-Page
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2006
Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
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November 1997 Revised 2003 High-Speed CMOS Logic Octal-Bus Transc

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