BiCMOS Interface Logic, Octal Transceivers/Registers, Three-State

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BiCMOS Interface Logic, Octal Transceivers/Registers, Three-State

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CD74FCT651, CD74FCT652
BiCMOS Interface Logic, Octal Transceivers/Registers, Three-State
CD74FCT651 CD74FCT652 three-state, octal transceivers/registers small geometry BiCMOS technology. output stage combination bipolar CMOS transistors that limits output HIGH level diode drops below VCC. This resultant lowering output swing 3.7V) reduces power ringing source EMI) minimizes bounce ground bounce their effects during simultaneous output switching. output configuration also enhances switching speed capable sinking milliamperes. These devices consist transceiver circuits, D-Type flipflops, control circuitry arranged multiplexed transmission data directly from data from internal storage registers. Output Enables OEAB OEBA provided control transceiver functions. control pins provided select whether real-time stored data transferred. circuitry used select control will eliminate typical decoding glitch that occurs multiplexer during transition between stored real-time data. input level selects real-time data HIGH selects stored data. following examples demonstrate four fundamental management functions that performed with octal transceivers registers. Data data bus, both, stored internal flip-flops high transitions appropriate clock pins (CAB CBA) regardless select enable control pins. When real-time transfer mode, also possible store data without using internal D-Type flip-flops simultaneously enabling OEAB OEBA. this configuration, each output reinforces input. Thus, when other data sources sets lines high impedance, each lines will remain last state.
January 1997
Features
ENDE IGNS ology Techn
Buffered Inputs Typical Propagation Delay: 6.8ns 25oC, 50pF CD75FCT651 Inverting CD74FCT652 Noninverting Family Features Latchup Resistant BiCMOS Process Circuit Design Speed Bipolar FASTTM/AS/S 64mA Output Sink Current Output Voltage Swing Limited 3.7V Controlled Output Edge Rates Input/Output Isolation BiCMOS Technology with Quiescent Power
Ordering Information
PART NUMBER CD74FCT651EN CD74FCT652EN CD74FCT651M CD74FCT652M TEMP. RANGE (oC) PACKAGE PDIP PDIP SOIC SOIC PKG. E24.3 E24.3 M24.3 M24.3
NOTE: When ordering suffix packages, entire part number. suffix obtain variant tape reel.
Pinouts
CD74FCT651 (PDIP, SOIC) VIEW
OEAB OEBA
CD74FCT652 (PDIP, SOIC) VIEW
OEAB OEBA
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. FASTis trademark Fairchild Semiconductor. Copyright Harris Corporation 1997
File Number
2394.2
CD74FCT651, CD74FCT652 Functional Diagram
DATA PORT OEBA OEAB CLOCK CLOCK DATA PORT DATA SOURCE SELECTION INPUTS
SOURCE SOURCE
FLIP-FLOP CLOCKS
TRUTH TABLE INPUTS OEAB OEBA NOTES: prevent excess currents High-Z (isolation) modes, terminals should terminated with resistors. data output functions enabled disabled various signals OEAB OEBA inputs. Data input functions always enabled, i.e., data pins will stored every low-to-high transition clock inputs. Select control clocks occur simultaneously. Select control clocks must staggered order load both registers. Input Input Input Input DATA THRU THRU Input Input OPERATION FUNCTION CD74FCT651 Isolation (Note Store Data CD74FCT652 Isolation (Note Store Data Store Hold Store both registers Hold Store Store both registers
Unspecified Store Hold Output Store both registers Hold Store Store both registers
Unspecified Input Output Input Output Output Input Input Output Input Input Output Output Output
Real-Time Data Real-Time Data Stored Data Stored Data Real-Time Data Real-Time Data Stored Data Stored Data Stored Data Stored Data Stored Data Stored Data
CD74FCT651, CD74FCT652 Logic Symbol
CD74FCT651
3EN1 3EN2
CD74FCT652
3EN1 3EN2
CD74FCT651, CD74FCT652
Absolute Maximum Ratings
Supply Voltage (VCC) -0.5V Input Diode Current, (For -0.5V) -20mA Output Diode Current, (for -0.5V) -50mA Output Sink Current Output Pin, 70mA Output Source Current Output Pin, -30mA Current (ICC) 140mA Ground Current (IGND). 528mA
Thermal Information
Thermal Resistance (Typical, Note (oC/W) PDIP Package SOIC Package Maximum Junction Temperature 150oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (SOIC-Lead Tips Only)
Operating Conditions
Operating Temperature Range (TA) .0oC 70oC Supply Voltage Range, .4.75V 5.25V Input Voltage, Output Voltage, Input Rise Fall Slew Rate, dt/dv. 10ns/V
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted evaluation board free air.
Electrical Specifications Commercial Temperature Range 70oC, 5.25V, 4.75V
AMBIENT TEMPERATURE (TA) TEST CONDITIONS PARAMETER High Level Input Voltage Level Input Voltage High Level Output Voltage Level Output Voltage High Level Input Current Level Input Current Three-State Leakage Current SYMBOL IOZH IOZL Input Clamp Voltage Short Circuit Output Current (Note Quiescent Supply Current, Additional Quiescent Supply Current Input Inputs High, Unit Load NOTES: more than output should shorted time. Test duration should exceed 100ms. Inputs that measured GND. Input Loading: inputs unit load. Unit load limit specified Electrical Specifications table, e.g., 1.6mA Max. 70oC. 3.4V (Note (mA) 4.75 5.25 4.75 5.25 25oC 0.55 -0.1 -0.5 -1.2 70oC 0.55 -1.2 UNITS
CD74FCT651, CD74FCT652
Switching Specifications Over Operating Range Series 2.5ns, 50pF, (Figure
25oC PARAMETER Propagation Delays Stored Stored Stored Stored Select Data Three-State Enabling Time, Output Register Output Three-State Disabling Time, Output Register Output Power Dissipation Capacitance Minimum (Valley) VOHV During Switching Other Outputs (Output Under Test Switching) Maximum (Peak) VOLP During Switching Other Outputs (Output Under Test Switching) Input Capacitance Input/Output Capacitance NOTE: CPD, measured flip-flop, used determine dynamic power consumption. (per package) (VCC2 where: supply voltage flow through current unit load output load capacitance duty cycle input high output frequency input frequency CD74FCT651 CD74FCT652 CD74FCT651 CD74FCT652 CD74FCT651 CD74FCT652 CD74FCT651 CD74FCT652 CD74FCT651, CD74FCT652 CD74FCT651, CD74FCT652 CD74FCT651, CD74FCT652 tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPZL, tPZH tPLZ, tPHZ (Note VOHV VOLP CI/O Typical 25oC Typical 25oC SYMBOL 70oC UNITS
Prerequisite Switching
25oC PARAMETER Maximum Frequency Data Clock Setup Time Data Clock Hold Time Clock Pulse Width NOTE: Minimum 4.75V 70oC, Typical SYMBOL fMAX (Note 70oC UNITS
Test Circuits Waveforms
2.5ns (NOTE PULSE 50pF
SWITCH POSITION TEST tPLZ, tPZL, Open Drain tPHZ, tPZH, tPLH, tPHL SWITCH Closed Open
NOTE: Pulse Generator Pulses: Rate 1.0MHz; ZOUT 2.5ns. FIGURE TEST CIRCUIT
DEFINITIONS: Load capacitance, includes probe capacitance. Termination resistance, should equal ZOUT Pulse Generator. Input: 2.5ns (10% 90%), unless otherwise specified
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL tREM
1.5V 1.5V 1.5V
LOW-HIGH-LOW PULSE
1.5V
SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. 1.5V HIGH-LOW-HIGH PULSE
1.5V
FIGURE SETUP, HOLD, RELEASE TIMING
FIGURE PULSE WIDTH
ENABLE CONTROL INPUT tPZL 3.5V OUTPUT NORMALLY SWITCH CLOSED tPZH OUTPUT NORMALLY HIGH SWITCH OPEN 1.5V 1.5V
DISABLE 1.5V tPLZ 3.5V OUTPUT 0.3V tPHZ 0.3V OPPOSITE PHASE INPUT TRANSITION tPLH tPHL SAME PHASE INPUT TRANSITION tPLH tPHL
1.5V 1.5V 1.5V
FIGURE ENABLE DISABLE TIMING
FIGURE PROPAGATION DELAY
Test Circuits Waveforms
(Continued)
OTHER OUTPUTS OUTPUT UNDER TEST VOHV VOLP
NOTES: VOLP measured with respect ground reference near output under test. VOHV measured with respect VOH. Input pulses have following characteristics: 1MHz, 2.5ns, 2.5ns, skew 1ns. R.F. fixture with 700MHz design rules required. should soldered into test board bypassed with 0.1µF capacitor. Scope probes require 700MHz bandwidth. FIGURE SIMULTANEOUS SWITCHING TRANSIENT WAVEFORMS
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device CD74FCT651EN CD74FCT651M CD74FCT652EN CD74FCT652M
Status OBSOLETE OBSOLETE OBSOLETE OBSOLETE
Package Type PDIP SOIC PDIP SOIC
Package Drawing
Pins Package Plan
Lead/Ball Finish Call Call Call Call
Peak Temp Call Call Call Call
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS) Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
MECHANICAL DATA
MPDI004 OCTOBER 1994
(R-PDIP-T**)
PINS SHOWN
PLASTIC DUAL-IN-LINE PACKAGE
PINS
1.260 (32,04) 1.230 (31,24) 0.310 (7,87) 0.290 (7,37)
1.425 (36,20) 1.385 (35,18) 0.315 (8,00) 0.295 (7,49)
0.280 (7,11) 0.250 (6,35)
0.070 (1,78)
0.020 (0,51)
0.200 (5,08) Seating Plane 0.125 (3,18)
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) 0.010 (0,25)
4040050 04/95 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice.
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BiCMOS Interface Logic, Octal Transceivers/Registers, Three-State

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