8-Input Multiplexer, Three-State CD74AC251 CD74ACT251 8-input mul
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CD74AC251, CD74ACT251
8-Input Multiplexer, Three-State
CD74AC251 CD74ACT251 8-input multiplexers that utilize Harris Advanced CMOS Logic technology. This multiplexer features both true complement outputs well Output Enable (OE) input. must logic level enable this device. When input HIGH, both outputs high-impedance state. When enabled, address information data select inputs determines which data input routed outputs.
August 1998
Features
Buffered Inputs Typical Propagation Delay 25oC, 50pF Exceeds Protection MIL-STD-883, Method 3015 SCR-Latchup-Resistant CMOS Process Circuit Design Speed Bipolar FASTTM/AS/S with Significantly Reduced Power Consumption Balanced Propagation Delays Types Feature 1.5V 5.5V Operation Balanced Noise Immunity Supply ±24mA Output Drive Current Fanout FASTICs Drives Transmission Lines
Ordering Information
PART NUMBER CD74AC251E CD74ACT251E CD74AC251M CD74ACT251M TEMP. RANGE (oC) PACKAGE PKG. E16.3 E16.3 M16.15 M16.15
70oC, PDIP 70oC, PDIP 70oC, SOIC 70oC, SOIC
Pinout
CD74AC251, CD74ACT251 (PDIP, SOIC) VIEW
NOTES: When ordering, entire part number. suffix obtain variant tape reel. Wafer this part number available which meets electrical specifications. Please contact your local sales office Harris customer service ordering information.
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. FASTis Trademark Fairchild Semiconductor. Copyright Harris Corporation 1998
File Number
1981.1
CD74AC251, CD74ACT251 Functional Diagram
THREE-STATE DISABLE CHANNEL INPUTS DATA SELECT OUTPUTS
TRUTH TABLE INPUTS SELECT OUTPUT ENABLE OUTPUTS
High logic level, logic level, High impedance (off), Irrelevant, I1.I7 level respective input
CD74AC251, CD74ACT251
Absolute Maximum Ratings
Supply Voltage, -0.5V Input Diode Current, -0.5V 0.5V .±20mA Output Diode Current, -0.5V 0.5V .±50mA Output Source Sink Current Output Pin, -0.5V 0.5V .±50mA Ground Current, IGND (Note .±100mA
Thermal Information
Thermal Resistance (Typical, Note (oC/W) PDIP Package SOIC Package Maximum Junction Temperature (Plastic Package) 150oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC
Operating Conditions
Temperature Range, -55oC 125oC Supply Voltage Range, (Note Types. .1.5V 5.5V Types .4.5V 5.5V Input Output Voltage, Input Rise Fall Slew Rate, dt/dv Types, 1.5V 50ns (Max) Types, 3.6V 5.5V 20ns (Max) Types, 4.5V 5.5V. 10ns (Max)
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTES: outputs device, ±25mA each additional output. Unless otherwise specified, voltages referenced ground. measured with component mounted evaluation board free air.
Electrical Specifications
TEST CONDITIONS PARAMETER TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage -0.05 -0.05 -0.05 (Note (Note 3.85 2.58 3.94 1.65 3.85 2.48 3.85 1.65 3.85 3.85 1.65 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
CD74AC251, CD74ACT251
Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Level Output Voltage SYMBOL (mA) 0.05 0.05 0.05 (Note (Note Input Leakage Current Three-State Leakage Current Quiescent Supply Current TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage -0.05 (Note (Note Level Output Voltage 0.05 (Note (Note Input Leakage Current Three-State Leakage Current Quiescent Supply Current Additional Supply Current Input Inputs High Unit Load NOTES: Test output time 1-second maximum duration. Measurement made forcing current measuring voltage minimize power dissipation. Test verifies minimum transmission-line-drive capability 85oC, 125oC. -2.1 3.94 0.36 ±0.1 ±0.5 3.85 0.44 1.65 3.85 1.65 25oC 0.36 0.36 ±0.1 ±0.5 -40oC 85oC 0.44 0.44 1.65 -55oC 125oC 1.65 UNITS
CD74AC251, CD74ACT251
Input Load Table
INPUT UNIT LOAD
NOTE: Unit load limit specified Electrical Specifications Table, e.g., 2.4mA 25oC.
Switching Specifications Input 3ns, 50pF (Worst Case)
-40oC 85oC PARAMETER TYPES Propagation Delay, Data Output tPLH, tPHL (Note (Note Propagation Delay, Data Output tPLH, tPHL Propagation Delay, Select Output tPLH, tPHL Propagation Delay, Select Output tPLH, tPHL Propagation Delay, Output Enable Output Disable Output tPZH, tPZL, tPHZ, tPLZ Three-State Output Capacitance Input Capacitance Power Dissipation Capacitance TYPES Propagation Delay, Data Output Propagation Delay, Data Output Propagation Delay, Select Output Propagation Delay, Select Output Propagation Delay, Output Enable Output Disable Output tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPZH, tPZL, tPHZ, tPLZ (Note 12.3 13.5 16.5 17.8 12.3 13.5 14.9 18.2 19.6 13.5 (Note 17.2 12.3 13.5 23.2 16.5 24.9 17.8 18.7 12.3 18.9 13.5 20.9 14.9 25.5 18.2 27.4 19.6 20.3 13.5 SYMBOL -55oC 125oC UNITS
CD74AC251, CD74ACT251
Switching Specifications Input 3ns, 50pF (Worst Case)
PARAMETER Three-State Output Capacitance Input Capacitance Power Dissipation Capacitance NOTES: Limits tested 100%. 3.3V 3.6V, 5.5V, 4.5V. used determine dynamic power consumption device. VCC2 (CPD where input frequency, output load capacitance, supply voltage. SYMBOL (Note (Continued) -55oC 125oC UNITS
-40oC 85oC
OUTPUT DISABLE
INPUT LEVEL
tPLZ OUTPUT: tPHZ OUTPUT: HIGH HIGH OUTPUTS ENABLED
tPZL 0.2VCC tPZH
GND)
VCC) OUTPUTS ENABLED (tPHZ, tPZH) OPEN (tPHL, tPLH) (tPLZ, tPZL) (OPEN DRAIN)
OUTPUTS DISABLED
OTHER INPUTS (TIED HIGH LOW) OUTPUT DISABLE
WITH THREESTATE OUTPUT
50pF
SERIES ONLY: WHEN 1.5V,
FIGURE THREE-STATE PROPAGATION DELAY WAVEFORMS TEST CIRCUIT
INPUT LEVEL
INVERTING OUTPUT tPHL NON-INVERTING OUTPUT tPLH
tPLH
tPHL
FIGURE PROPAGATION DELAY TIMES
CD74AC251, CD74ACT251
OUTPUT (NOTE) OUTPUT LOAD 50pF
NOTE: Series Only: When 1.5V, CD74AC Input Level Input Switching Voltage, Output Switching Voltage, CD74ACT 1.5V
FIGURE PROPAGATION DELAY TIMES
PACKAGE OPTION ADDENDUM
www.ti.com
1-Jul-2005
PACKAGING INFORMATION
Orderable Device CD74AC251M CD74AC251M96 CD74AC251M96E4 CD74AC251ME4
Status ACTIVE ACTIVE ACTIVE ACTIVE
Package Type SOIC SOIC SOIC SOIC
Package Drawing
Pins Package Plan Green (RoHS Sb/Br)
Lead/Ball Finish NIPDAU NIPDAU NIPDAU NIPDAU
Peak Temp Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM
2500 Green (RoHS Sb/Br) 2500 Green (RoHS Sb/Br) Green (RoHS Sb/Br)
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS) Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
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