High-Speed CMOS Logic 4-Bit Binary Full Adder with Fast Carry Des

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High-Speed CMOS Logic 4-Bit Binary Full Adder with Fast Carry Des

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CD54HC283, CD74HC283, CD54HCT283, CD74HCT283
High-Speed CMOS Logic 4-Bit Binary Full Adder with Fast Carry
Description
'HC283 'HCT283 binary full adders 4-bit binary numbers generate carry-out exceeds Because symmetry function, this device used with either active-high operands (positive logic) with active-low operands (negative logic). When using positive logic carry-in input must tied there carry-in.
Features
Adds Binary Numbers
/Title (CD74 HC283 CD74 HCT28 /Subject (High Speed CMOS Logic 4-Bit Binary Full Adder
Full Internal Lookahead Fast Ripple Carry Economical Expansion Operates with Both Positive Negative Logic Fanout (Over Temperature Range) Standard Outputs LSTTL Loads Driver Outputs LSTTL Loads Wide Operating Temperature Range -55oC 125oC Balanced Propagation Delay Transition Times Significant Power Reduction Compared LSTTL Logic Types Operation High Noise Immunity: 30%, Types 4.5V 5.5V Operation Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), (Min) CMOS Input Compatibility, VOL,
Ordering Information
PART NUMBER CD54HC283F3A CD54HCT283F3A CD74HC283E CD74HC283M CD74HC283MT CD74HC283M96 CD74HCT283E CD74HCT283M CD74HCT283MT CD74HCT283M96 TEMP. RANGE (oC) PACKAGE CERDIP CERDIP PDIP SOIC SOIC SOIC PDIP SOIC SOIC SOIC
NOTE: When ordering, entire part number. suffix denotes tape reel. suffix denotes small-quantity reel 250.
Pinout
CD54HC283, CD54HCT283 (CERDIP) CD74HC283, CD74HCT283 (PDIP, SOIC) VIEW
COUT
Functional Diagram
COUT
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. Copyright
2003, Texas Instruments Incorporated
CD54HC283, CD74HC283, CD54HCT283, CD74HCT283
Absolute Maximum Ratings
Supply Voltage, -0.5V Input Diode Current, -0.5V 0.5V .±20mA Output Diode Current, -0.5V 0.5V .±20mA Drain Current, Output, -0.5V 0.5V. .±25mA Output Source Sink Current Output Pin, -0.5V 0.5V .±25mA Ground Current, .±50mA
Thermal Information
Thermal Resistance (Typical, Note (oC/W) (PDIP) Package (SOIC) Package. Maximum Junction Temperature 150oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (SOIC Lead Tips Only)
Operating Conditions
Temperature Range, -55oC 125oC Supply Voltage Range, Types Input Output Voltage, Input Rise Fall Time 1000ns (Max) 4.5V. 500ns (Max) 400ns (Max)
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: package thermal impedance calculated accordance with JESD 51-7.
Electrical Specifications
TEST CONDITIONS PARAMETER TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage CMOS Loads Level Output Voltage Loads Input Leakage Current Quiescent Device Current -0.02 -0.02 -0.02 -5.2 0.02 0.02 0.02 3.15 3.98 5.48 1.35 0.26 0.26 ±0.1 3.15 3.84 5.34 1.35 0.33 0.33 3.15 1.35 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
CD54HC283, CD74HC283, CD54HCT283, CD74HCT283
Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Types High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage CMOS Loads Level Output Voltage Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Input Pin: Unit Load NOTE: dual-supply systems theoretical worst case 2.4V, 5.5V) specification 1.8mA. -0.02 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
3.98
3.84
0.02
0.26
0.33
(Note
±0.1
Input Loading Table
INPUT UNIT LOADS
NOTE: Unit Load limit specified Electrical Specifications table, e.g., 360µA 25oC.
Switching Specifications Input
TEST CONDITIONS 50pF 25oC 15pF 50pF -40oC 85oC -55oC 125oC UNITS
PARAMETER TYPES Propagation Delay
SYMBOL tPLH, tPHL
CD54HC283, CD74HC283, CD54HCT283, CD74HCT283
Switching Specifications Input
(Continued) 25oC 15pF 50pF COUT tPLH, tPHL 50pF 15pF 50pF tPLH, tPHL 50pF 15pF 50pF COUT tPLH, tPHL 50pF 15pF 50pF tPLH, tPHL 50pF 15pF 50pF Output Transition Time tTLH, tTHL 50pF Input Capacitance Power Dissipation Capacitance, (Notes TYPES Propagation Delay tPLH, tPHL 15pF 50pF tPLH, tPHL 15pF 50pF COUT tPLH, tPHL 15pF 50pF tPLH, tPHL 15pF 50pF COUT tPLH, tPHL 15pF 50pF tPLH, tPHL 15pF 50pF Output Transition Time tTLH, tTHL 50pF 50pF -40oC 85oC -55oC 125oC UNITS
PARAMETER
SYMBOL tPLH, tPHL
TEST CONDITIONS 50pF
CD54HC283, CD74HC283, CD54HCT283, CD74HCT283
Switching Specifications Input
(Continued) 25oC -40oC 85oC -55oC 125oC UNITS
PARAMETER Input Capacitance Power Dissipation Capacitance, (Notes NOTES:
SYMBOL
TEST CONDITIONS
used determine dynamic power consumption, package. VCC2 (CPD where: Input Frequency, Output Load Capacitance, Supply Voltage.
Test Circuits Waveforms
INPUT tTLH tPHL tPLH INPUT tTHL 2.7V 1.3V 0.3V tTLH INVERTING OUTPUT tPHL tPLH 1.3V
tTHL
INVERTING OUTPUT
FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC
FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2006
PACKAGING INFORMATION
Orderable Device 5962-8976501EA CD54HC283F3A CD54HCT283F3A CD74HC283E CD74HC283EE4 CD74HC283M CD74HC283M96 CD74HC283M96E4 CD74HC283ME4 CD74HC283MT CD74HC283MTE4 CD74HCT283E CD74HCT283EE4 CD74HCT283M CD74HCT283M96 CD74HCT283M96E4 CD74HCT283ME4 CD74HCT283MT CD74HCT283MTE4
Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type CDIP CDIP CDIP PDIP PDIP SOIC SOIC SOIC SOIC SOIC SOIC PDIP PDIP SOIC SOIC SOIC SOIC SOIC SOIC
Package Drawing
Pins Package Plan Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS Sb/Br)
Lead/Ball Finish Call Call Call NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU
Peak Temp Type Type Type Type Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Type Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM
2500 Green (RoHS Sb/Br) 2500 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS Sb/Br)
2500 Green (RoHS Sb/Br) 2500 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS
Addendum-Page
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2006
compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
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High-Speed CMOS Logic 4-Bit Binary Full Adder with Fast Carry Des

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