August 1998 Revised October 2003 Wide Range Digital Analog Signal

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August 1998 Revised October 2003 Wide Range Digital Analog Signal

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CD4051B, CD4052B, CD4053B
August 1998 Revised October 2003
Wide Range Digital Analog Signal Levels Digital Analog 20VP-P
CD4051B single 8-Channel multiplexer having three binary control inputs, inhibit input. three binary signals select channels turned connect inputs output. CD4052B differential 4-Channel multiplexer having binary control inputs, inhibit input. binary input signals select pairs channels turned connect analog inputs outputs. CD4053B triple 2-Channel multiplexer having three separate digital control inputs, inhibit input. Each control input selects pair channels which connected single-pole, double-throw configuration. When these devices used demultiplexers, "CHANNEL IN/OUT" terminals outputs "COMMON OUT/IN" terminals inputs.
/Title Resistance, (Typ) Over 15VP-P Signal Input Range -VEE (CD405 High Resistance, Channel Leakage ±100pA (Typ) CD4052 -VEE Logic-Level Conversion Digital Addressing Signals (VDD CD4053 -VSS 20V) Switch Analog Signals (VDD -VEE 20V) Matched Switch Characteristics, (Typ) /SubVDD -VEE ject (CMOS Very Quiescent Power Dissipation Under DigitalControl Input Supply Conditions, 0.2µW (Typ) Analog -VSS -VEE Binary Address Decoding Chip plexers/Dem 10V, Parametric Ratings ultiplex- 100% Tested Quiescent Current with Maximum Input Current Over Full Package Temperature Range, 100nA 25oC Logic Level Break-Before-Make Switching Eliminates Channel Overlap Conversion) /Author Applications Analog Digital Multiplexing Demultiplexing Conversion words Signal Gating (Harris CMOS Analog Multiplexers/Demultiplexers Semiconduc- with Logic Level Conversion tor, CD4051B, CD4052B, CD4053B analog multiplexers CD4000 digitally-controlled analog switches having
impedance very leakage current. Control analog signals 20VP-P achieved digital signal amplitudes 4.5V -VSS -VEE controlled; -VEE level differences above 13V, -VSS least 4.5V required). example, +4.5V, -13.5V, analog signals from -13.5V +4.5V controlled digital inputs These multiplexer circuits dissipate extremely quiescent power over full -VSS -VEE supply-voltage ranges, independent logic state control signals. When logic present inhibit input terminal, channels off.
Ordering Information
PART NUMBER CD4051BF3A, CD4052BF3A, CD4053BF3A CD4051BE, CD4052BE, CD4053BE CD4051BM, CD4051BMT, CD4051BM96 CD4052BM, CD4052BMT, CD4052BM96 CD4053BM, CD4053BMT, CD4053BM96 CD4051BNSR, CD4052BNSR, CD4053BNSR CD4051BPW, CD4051BPWR, CD4052BPW, CD4052BPWR CD4053BPW, CD4053BPWR TEMP. RANGE (oC) PACKAGE CERAMIC PDIP SOIC
TSSOP
NOTE: When ordering, entire part number. suffixes denote tape reel. suffix denotes small-quantity reel 250.
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. Copyright 2003, Texas Instruments Incorporated
CD4051B, CD4052B, CD4053B Pinouts
CD4051B (PDIP, CDIP, SOIC, SOP, TSSOP) VIEW
CHANNELS IN/OUT CHANNELS IN/OUT CHANNELS IN/OUT COMMON OUT/IN CHANNELS IN/OUT
CD4052B (PDIP, CDIP, SOP, TSSOP) VIEW
CHANNELS IN/OUT
CHANNELS IN/OUT
CHANNELS IN/OUT
OUT/IN
COMMON OUT/IN
CD4053B (PDIP, CDIP, SOP, TSSOP) VIEW
IN/OUT OUT/IN IN/OUT OUT/IN OUT/IN IN/OUT
Functional Block Diagrams
CD4051B
CHANNEL IN/OUT
COMMON OUT/IN
LOGIC LEVEL CONVERSION
BINARY DECODER WITH INHIBIT
inputs protected standard CMOS protection network.
CD4051B, CD4052B, CD4053B Functional Block Diagrams
(Continued) CD4052B
CHANNELS IN/OUT
COMMON OUT/IN COMMON OUT/IN
LOGIC LEVEL CONVERSION
BINARY DECODER WITH INHIBIT
CHANNELS IN/OUT
CD4053B
BINARY DECODERS WITH INHIBIT
LOGIC LEVEL CONVERSION
IN/OUT COMMON OUT/IN
COMMON OUT/IN
COMMON OUT/IN
inputs protected standard CMOS protection network.
CD4051B, CD4052B, CD4053B
TRUTH TABLES INPUT STATES INHIBIT CD4051B CD4052B INHIBIT CD4053B INHIBIT Don't Care None None None "ON" CHANNEL(S)
CD4051B, CD4052B, CD4053B
Absolute Maximum Ratings Supply Voltage Voltages Referenced Terminal -0.5V Input Voltage Range -0.5V +0.5V Input Current, Input. ±10mA
Thermal Information
Package Thermal Impedance, (see Note (PDIP) package. 67oC/W (SOIC) package 73oC/W (SOP) package. 64oC/W (TSSOP) package 108oC/W Maximum Junction Temperature (Ceramic Package) .175oC Maximum Junction Temperature (Plastic Package) .150oC Maximum Storage Temperature Range -65oC 150oC Maximum Lead Temperature (Soldering 10s) .265oC (SOIC Lead Tips Only)
Operating Conditions
Temperature Range -55oC 125oC
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: package thermal impedance calculated accordance with JESD 51-7.
Electrical Specifications
Common Conditions Here: Whole Table Full Temp. Range, VSUPPLY ±5V, 100, Unless Otherwise Specified (Note CONDITIONS LIMITS INDICATED TEMPERATURES (oC)
PARAMETER
UNITS
SIGNAL INPUTS (VIS) OUTPUTS (VOS) Quiescent Device Current, Drain Source Resistance Change Resistance (Between Channels), Channel Leakage Current: Channel (Max) Channels (Common OUT/IN) (Max) Capacitance: Input, Output, CD4051 CD4052 CD4053 Feedthrough CIOS Propagation Delay Time (Signal Input Output 200k, 50pF, 20ns 3000 1200 3000 1300 0.04 0.04 0.04 0.08 ±0.01 1050 ±100 (Note
±100 (Note
±1000 (Note
CD4051B, CD4052B, CD4053B
Electrical Specifications
Common Conditions Here: Whole Table Full Temp. Range, VSUPPLY ±5V, 100, Unless Otherwise Specified (Continued) (Note CONDITIONS LIMITS INDICATED TEMPERATURES (oC) PARAMETER UNITS
CONTROL (ADDRESS INHIBIT), through through Input High Voltage, Input Voltage, Channels Input Current, (Max) Propagation Delay Time: Address-to-Signal 20ns, (Channels 50pF, OFF) Figures Propagation Delay Time: Inhibit-to-Signal 20ns, (Channel Turning 50pF, Figure Propagation Delay Time: Inhibit-to-Signal (Channel Turning OFF) Figure 20ns, 50pF, Input Capacitance, (Any Address Inhibit Input) NOTE: Determined minimum feasible leakage measurement automatic testing. ±0.1 ±0.1 ±10-5 ±0.1
Electrical Specifications
TEST CONDITIONS PARAMETER Cutoff (-3dB) Frequency Channel (Sine Wave Input) (Note 20Log Common OUT/IN CD4053 CD4052 CD4051 Channel LIMITS UNITS
CD4051B, CD4052B, CD4053B
Electrical Specifications
TEST CONDITIONS PARAMETER Total Harmonic Distortion, (Note (Note (Note LIMITS 0.12 UNITS Common OUT/IN CD4053 CD4052 CD4051 Channel Between Channels Between Sections, CD4052 Only Measured Common Measured Channel mVPEAK mVPEAK
VSS, 1kHz Sine Wave -40dB Feedthrough Frequency (All Channels OFF) (Note 20Log 40dB -40dB Signal Crosstalk Frequency (Note 20Log 40dB
Between Sections, CD4053 Only Address-or-Inhibit-to-Signal Crosstalk (Note
20ns, (Square Wave) NOTES: Peak-to-Peak voltage symmetrical about Both ends channel.
Typical Performance Curves
CHANNEL RESISTANCE CHANNEL RESISTANCE 125oC
125oC 25oC -55oC
25oC -55oC
INPUT SIGNAL VOLTAGE
-7.5
-2.5 INPUT SIGNAL VOLTAGE
FIGURE CHANNEL RESISTANCE INPUT SIGNAL VOLTAGE (ALL TYPES)
FIGURE CHANNEL RESISTANCE INPUT SIGNAL VOLTAGE (ALL TYPES)
CD4051B, CD4052B, CD4053B Typical Performance Curves
CHANNEL RESISTANCE CHANNEL RESISTANCE 25oC
(Continued)
125oC
25oC -55oC
-7.5
-2.5
-7.5
-2.5
INPUT SIGNAL VOLTAGE
INPUT SIGNAL VOLTAGE
FIGURE CHANNEL RESISTANCE INPUT SIGNAL VOLTAGE (ALL TYPES)
OUTPUT SIGNAL VOLTAGE 25oC 100k,
FIGURE CHANNEL RESISTANCE INPUT SIGNAL VOLTAGE (ALL TYPES)
POWER DISSIPATION PACKAGE (µW)
25oC ALTERNATING PATTERN 50pF
TEST CIRCUIT CD4029
15pF
CD4051
INPUT SIGNAL VOLTAGE
SWITCHING FREQUENCY (kHz)
FIGURE CHARACTERISTICS CHANNELS (CD4051B)
FIGURE DYNAMIC POWER DISSIPATION SWITCHING FREQUENCY (CD4051B)
POWER DISSIPATION PACKAGE (µW)
POWER DISSIPATION PACKAGE (µW)
25oC ALTERNATING PATTERN 50pF
15pF
CD4029 CD4052
TEST CIRCUIT
25oC ALTERNATING PATTERN 50pF
TEST CIRCUIT CD4053
15pF
SWITCHING FREQUENCY (kHz)
SWITCHING FREQUENCY (kHz)
FIGURE DYNAMIC POWER DISSIPATION SWITCHING FREQUENCY (CD4052B)
FIGURE DYNAMIC POWER DISSIPATION SWITCHING FREQUENCY (CD4053B)
CD4051B, CD4052B, CD4053B Test Circuits Waveforms
7.5V
7.5V
-7.5V
-10V
NOTE: ADDRESS (digital-control inputs) INHIBIT logic levels are: VDD. analog signal (through swing from VDD. FIGURE TYPICAL BIAS VOLTAGES
20ns TURN-ON TIME TURN-OFF TIME
20ns
20ns
20ns
TURN-OFF TIME tPHZ TURN-ON TIME
FIGURE WAVEFORMS, CHANNEL BEING TURNED
FIGURE WAVEFORMS, CHANNEL BEING TURNED
CD4051
CD4052
CD4053
FIGURE CHANNEL LEAKAGE CURRENT CHANNEL
CD4051B, CD4052B, CD4053B Test Circuits Waveforms (Continued)
CD4051
CD4052
CD4053
FIGURE CHANNEL LEAKAGE CURRENT CHANNELS
OUTPUT
OUTPUT CD4052 CD4053
OUTPUT
CD4051
CLOCK
CLOCK
CLOCK
FIGURE PROPAGATION DELAY ADDRESS INPUT SIGNAL OUTPUT
OUTPUT 50pF CLOCK
OUTPUT 50pF CLOCK
OUTPUT 50pF
CLOCK
tPHL tPLH CD4051
tPHL tPLH CD4052
tPHL tPLH CD4053
FIGURE PROPAGATION DELAY INHIBIT INPUT SIGNAL OUTPUT
MEASURE "OFF" CHANNELS (e.g., CHANNEL MEASURE "OFF" CHANNELS (e.g., CHANNEL
CD4051B
CD4052B
CD4053B
MEASURE "OFF" CHANNELS (e.g., CHANNEL
FIGURE INPUT VOLTAGE TEST CIRCUITS (NOISE IMMUNITY)
CD4051B, CD4052B, CD4053B Test Circuits Waveforms (Continued)
KEITHLEY DIGITAL MULTIMETER "ON" RANGE
PLOTTER
CD4051 CD4053
CD4052
H.P. MOSELEY 7030A
FIGURE QUIESCENT DEVICE CURRENT
FIGURE CHANNEL RESISTANCE MEASUREMENT CIRCUIT
CD4051 CD4053 CD4052
NOTE: Measure inputs sequentially, both connect unused inputs either
NOTE: Measure inputs sequentially, both connect unused inputs either
FIGURE INPUT CURRENT
CHANNEL 5VP-P CHANNEL CHANNEL COMMON
5VP-P
CHANNEL
CHANNEL
FIGURE FEEDTHROUGH (ALL TYPES)
FIGURE CROSSTALK BETWEEN CHANNELS (ALL TYPES)
5VP-P
CHANNEL
CHANNEL
FIGURE CROSSTALK BETWEEN DUALS TRIPLETS (CD4052B, CD4053B)
CD4051B, CD4052B, CD4053B Test Circuits Waveforms (Continued)
DIFFERENTIAL SIGNALS CD4052 CD4052
COMMUNICATIONS LINK
DIFF. AMPLIFIER/ LINE DRIVER
DIFF. RECEIVER
DIFF. MULTIPLEXING
DEMULTIPLEXING
FIGURE TYPICAL TIME-DIVISION APPLICATION CD4052B
Special Considerations
applications where separate power sources used drive signal inputs, current capability should exceed VDD/RL effective external load). This provision avoids permanent current flow clamp action supply when power applied removed from CD4051B, CD4052B CD4053B.
CD4051B CD4556 COMMON OUTPUT
CD4051B
CD4051B
FIGURE 24-TO-1 ADDRESSING
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2006
PACKAGING INFORMATION
Orderable Device 7901502EA 8101801EA CD4051BE CD4051BEE4 CD4051BF CD4051BF3A CD4051BM CD4051BM96 CD4051BM96E4 CD4051BM96G4 CD4051BME4 CD4051BMG4 CD4051BMT CD4051BMTE4 CD4051BNSR CD4051BNSRE4 CD4051BPW CD4051BPWE4 CD4051BPWR CD4051BPWRE4 CD4052BE CD4052BEE4 CD4052BF CD4052BF3A CD4052BM CD4052BM96 CD4052BM96E4 Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type CDIP CDIP PDIP PDIP CDIP CDIP SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC TSSOP TSSOP TSSOP TSSOP PDIP PDIP CDIP CDIP SOIC SOIC SOIC Package Drawing Pins Package Plan Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS Sb/Br) Lead/Ball Finish Call Call NIPDAU NIPDAU Call Call NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU Call Call NIPDAU NIPDAU NIPDAU Peak Temp Type Type Type Type Type Type Level-2-260C-1YEAR Level-2-260C-1YEAR Level-2-260C-1YEAR Level-1-260C-UNLIM Level-2-260C-1YEAR Level-1-260C-UNLIM Level-2-260C-1YEAR Level-2-260C-1YEAR Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Type Type Type Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM
2500 Green (RoHS Sb/Br) 2500 Green (RoHS Sb/Br) 2500 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS Sb/Br)
2500 Green (RoHS Sb/Br) 2500 Green (RoHS Sb/Br)
Addendum-Page
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2006
Orderable Device CD4052BME4 CD4052BMT CD4052BMTE4 CD4052BNSR CD4052BNSRE4 CD4052BNSRG4 CD4052BPW CD4052BPWE4 CD4052BPWG4 CD4052BPWR CD4052BPWRE4 CD4052BPWRG4 CD4053BE CD4053BEE4 CD4053BF CD4053BF3A CD4053BM CD4053BM96 CD4053BM96E4 CD4053BME4 CD4053BMT CD4053BMTE4 CD4053BNSR CD4053BNSRE4 CD4053BNSRG4 CD4053BPW CD4053BPWE4
Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type SOIC SOIC SOIC TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP PDIP PDIP CDIP CDIP SOIC SOIC SOIC SOIC SOIC SOIC TSSOP TSSOP
Package Drawing
Pins Package Plan Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
Lead/Ball Finish NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU Call Call NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU
Peak Temp Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Type Type Type Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM
2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS Sb/Br)
2500 Green (RoHS Sb/Br) 2500 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS
Addendum-Page
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2006
Orderable Device
Status
Package Type TSSOP TSSOP TSSOP TSSOP
Package Drawing
Pins Package Plan Sb/Br) Green (RoHS Sb/Br)
Lead/Ball Finish
Peak Temp
CD4053BPWG4 CD4053BPWR CD4053BPWRE4 CD4053BPWRG4
ACTIVE ACTIVE ACTIVE ACTIVE
NIPDAU NIPDAU NIPDAU NIPDAU
Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM
2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br)
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
(R-PDSO-G**)
PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,30 0,19
0,10
0,15 4,50 4,30 6,60 6,20 Gage Plane 0,25 0,75 0,50
Seating Plane 1,20 0,15 0,05 0,10
PINS
3,10
5,10
5,10
6,60
7,90
9,80
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0,15. Falls within JEDEC MO-153
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DALLAS, TEXAS 75265
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August 1998 Revised October 2003 Wide Range Digital Analog Signal

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